arch/mips/au1000/common/pci.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Alchemy/AMD Au1x00 pci support.
   4  *
   5  * Copyright 2001,2002,2003 MontaVista Software Inc.
   6  * Author: MontaVista Software, Inc.
   7  *              ppopov@mvista.com or source@mvista.com
   8  *
   9  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
  10  *
  11  *  Support for all devices (greater than 16) added by David Gathright.
  12  *
  13  *  This program is free software; you can redistribute  it and/or modify it
  14  *  under  the terms of  the GNU General  Public License as published by the
  15  *  Free Software Foundation;  either version 2 of the  License, or (at your
  16  *  option) any later version.
  17  *
  18  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  19  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  20  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  21  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  22  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  24  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  25  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  26  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  *  You should have received a copy of the  GNU General Public License along
  30  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  31  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32  */
  33 #include <linux/config.h>
  34 #include <linux/types.h>
  35 #include <linux/pci.h>
  36 #include <linux/kernel.h>
  37 #include <linux/init.h>
  38
  39 #include <asm/mach-au1x00/au1000.h>
  40
  41 /* TBD */
  42 static struct resource pci_io_resource = {
  43         "pci IO space",
  44         (u32)PCI_IO_START,
  45         (u32)PCI_IO_END,
  46         IORESOURCE_IO
  47 };
  48
  49 static struct resource pci_mem_resource = {
  50         "pci memory space",
  51         (u32)PCI_MEM_START,
  52         (u32)PCI_MEM_END,
  53         IORESOURCE_MEM
  54 };
  55
  56 extern struct pci_ops au1x_pci_ops;
  57
  58 static struct pci_controller au1x_controller = {
  59         .pci_ops        = &au1x_pci_ops,
  60         .io_resource    = &pci_io_resource,
  61         .mem_resource   = &pci_mem_resource,
  62 };
  63
  64 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
  65 static unsigned long virt_io_addr;
  66 #endif
  67
  68 static int __init au1x_pci_setup(void)
  69 {
  70 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
  71         virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
  72                         Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
  73
  74         if (!virt_io_addr) {
  75                 printk(KERN_ERR "Unable to ioremap pci space\n");
  76                 return 1;
  77         }
  78
  79 #ifdef CONFIG_DMA_NONCOHERENT
  80         /*
  81          *  Set the NC bit in controller for Au1500 pre-AC silicon
  82          */
  83         u32 prid = read_c0_prid();
  84         if ( (prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
  85                au_writel( 1<<16 | au_readl(Au1500_PCI_CFG), Au1500_PCI_CFG);
  86                printk("Non-coherent PCI accesses enabled\n");
  87         }
  88 #endif
  89
  90         set_io_port_base(virt_io_addr);
  91 #endif
  92
  93         register_pci_controller(&au1x_controller);
  94         return 0;
  95 }
  96
  97 arch_initcall(au1x_pci_setup);