arch/m68k/kernel/bios32.c

   1 /*
   2  * bios32.c - PCI BIOS functions for m68k systems.
   3  *
   4  * Written by Wout Klaren.
   5  *
   6  * Based on the DEC Alpha bios32.c by Dave Rusling and David Mosberger.
   7  */
   8
   9 #include <linux/config.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12
  13 #if 0
  14 # define DBG_DEVS(args)         printk args
  15 #else
  16 # define DBG_DEVS(args)
  17 #endif
  18
  19 #ifdef CONFIG_PCI
  20
  21 /*
  22  * PCI support for Linux/m68k. Currently only the Hades is supported.
  23  *
  24  * The support for PCI bridges in the DEC Alpha version has
  25  * been removed in this version.
  26  */
  27
  28 #include <linux/pci.h>
  29 #include <linux/slab.h>
  30 #include <linux/mm.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/pci.h>
  34 #include <asm/uaccess.h>
  35
  36 #define KB              1024
  37 #define MB              (1024*KB)
  38 #define GB              (1024*MB)
  39
  40 #define MAJOR_REV       0
  41 #define MINOR_REV       5
  42
  43 /*
  44  * Align VAL to ALIGN, which must be a power of two.
  45  */
  46
  47 #define ALIGN(val,align)        (((val) + ((align) - 1)) & ~((align) - 1))
  48
  49 /*
  50  * Offsets relative to the I/O and memory base addresses from where resources
  51  * are allocated.
  52  */
  53
  54 #define IO_ALLOC_OFFSET         0x00004000
  55 #define MEM_ALLOC_OFFSET        0x04000000
  56
  57 /*
  58  * Declarations of hardware specific initialisation functions.
  59  */
  60
  61 extern struct pci_bus_info *init_hades_pci(void);
  62
  63 /*
  64  * Bus info structure of the PCI bus. A pointer to this structure is
  65  * put in the sysdata member of the pci_bus structure.
  66  */
  67
  68 static struct pci_bus_info *bus_info;
  69
  70 static int pci_modify = 1;              /* If set, layout the PCI bus ourself. */
  71 static int skip_vga;                    /* If set do not modify base addresses
  72                                            of vga cards.*/
  73 static int disable_pci_burst;           /* If set do not allow PCI bursts. */
  74
  75 static unsigned int io_base;
  76 static unsigned int mem_base;
  77
  78 /*
  79  * static void disable_dev(struct pci_dev *dev)
  80  *
  81  * Disable PCI device DEV so that it does not respond to I/O or memory
  82  * accesses.
  83  *
  84  * Parameters:
  85  *
  86  * dev  - device to disable.
  87  */
  88
  89 static void __init disable_dev(struct pci_dev *dev)
  90 {
  91         unsigned short cmd;
  92
  93         if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) ||
  94              (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) ||
  95              (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga)
  96                 return;
  97
  98         pci_read_config_word(dev, PCI_COMMAND, &cmd);
  99
 100         cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER);
 101         pci_write_config_word(dev, PCI_COMMAND, cmd);
 102 }
 103
 104 /*
 105  * static void layout_dev(struct pci_dev *dev)
 106  *
 107  * Layout memory and I/O for a device.
 108  *
 109  * Parameters:
 110  *
 111  * device       - device to layout memory and I/O for.
 112  */
 113
 114 static void __init layout_dev(struct pci_dev *dev)
 115 {
 116         unsigned short cmd;
 117         unsigned int base, mask, size, reg;
 118         unsigned int alignto;
 119         int i;
 120
 121         /*
 122          * Skip video cards if requested.
 123          */
 124
 125         if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) ||
 126              (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) ||
 127              (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga)
 128                 return;
 129
 130         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 131
 132         for (reg = PCI_BASE_ADDRESS_0, i = 0; reg <= PCI_BASE_ADDRESS_5; reg += 4, i++)
 133         {
 134                 /*
 135                  * Figure out how much space and of what type this
 136                  * device wants.
 137                  */
 138
 139                 pci_write_config_dword(dev, reg, 0xffffffff);
 140                 pci_read_config_dword(dev, reg, &base);
 141
 142                 if (!base)
 143                 {
 144                         /* this base-address register is unused */
 145                         dev->resource[i].start = 0;
 146                         dev->resource[i].end = 0;
 147                         dev->resource[i].flags = 0;
 148                         continue;
 149                 }
 150
 151                 /*
 152                  * We've read the base address register back after
 153                  * writing all ones and so now we must decode it.
 154                  */
 155
 156                 if (base & PCI_BASE_ADDRESS_SPACE_IO)
 157                 {
 158                         /*
 159                          * I/O space base address register.
 160                          */
 161
 162                         cmd |= PCI_COMMAND_IO;
 163
 164                         base &= PCI_BASE_ADDRESS_IO_MASK;
 165                         mask = (~base << 1) | 0x1;
 166                         size = (mask & base) & 0xffffffff;
 167
 168                         /*
 169                          * Align to multiple of size of minimum base.
 170                          */
 171
 172                         alignto = max_t(unsigned int, 0x040, size);
 173                         base = ALIGN(io_base, alignto);
 174                         io_base = base + size;
 175                         pci_write_config_dword(dev, reg, base | PCI_BASE_ADDRESS_SPACE_IO);
 176
 177                         dev->resource[i].start = base;
 178                         dev->resource[i].end = dev->resource[i].start + size - 1;
 179                         dev->resource[i].flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
 180
 181                         DBG_DEVS(("layout_dev: IO address: %lX\n", base));
 182                 }
 183                 else
 184                 {
 185                         unsigned int type;
 186
 187                         /*
 188                          * Memory space base address register.
 189                          */
 190
 191                         cmd |= PCI_COMMAND_MEMORY;
 192                         type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
 193                         base &= PCI_BASE_ADDRESS_MEM_MASK;
 194                         mask = (~base << 1) | 0x1;
 195                         size = (mask & base) & 0xffffffff;
 196                         switch (type)
 197                         {
 198                         case PCI_BASE_ADDRESS_MEM_TYPE_32:
 199                         case PCI_BASE_ADDRESS_MEM_TYPE_64:
 200                                 break;
 201
 202                         case PCI_BASE_ADDRESS_MEM_TYPE_1M:
 203                                 printk("bios32 WARNING: slot %d, function %d "
 204                                        "requests memory below 1MB---don't "
 205                                        "know how to do that.\n",
 206                                        PCI_SLOT(dev->devfn),
 207                                        PCI_FUNC(dev->devfn));
 208                                 continue;
 209                         }
 210
 211                         /*
 212                          * Align to multiple of size of minimum base.
 213                          */
 214
 215                         alignto = max_t(unsigned int, 0x1000, size);
 216                         base = ALIGN(mem_base, alignto);
 217                         mem_base = base + size;
 218                         pci_write_config_dword(dev, reg, base);
 219
 220                         dev->resource[i].start = base;
 221                         dev->resource[i].end = dev->resource[i].start + size - 1;
 222                         dev->resource[i].flags = IORESOURCE_MEM;
 223
 224                         if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
 225                         {
 226                                 /*
 227                                  * 64-bit address, set the highest 32 bits
 228                                  * to zero.
 229                                  */
 230
 231                                 reg += 4;
 232                                 pci_write_config_dword(dev, reg, 0);
 233
 234                                 i++;
 235                                 dev->resource[i].start = 0;
 236                                 dev->resource[i].end = 0;
 237                                 dev->resource[i].flags = 0;
 238                         }
 239                 }
 240         }
 241
 242         /*
 243          * Enable device:
 244          */
 245
 246         if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
 247             dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
 248             dev->class >> 8 == PCI_CLASS_DISPLAY_VGA ||
 249             dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)
 250         {
 251                 /*
 252                  * All of these (may) have I/O scattered all around
 253                  * and may not use i/o-base address registers at all.
 254                  * So we just have to always enable I/O to these
 255                  * devices.
 256                  */
 257                 cmd |= PCI_COMMAND_IO;
 258         }
 259
 260         pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
 261
 262         pci_write_config_byte(dev, PCI_LATENCY_TIMER, (disable_pci_burst) ? 0 : 32);
 263
 264         if (bus_info != NULL)
 265                 bus_info->conf_device(dev);     /* Machine dependent configuration. */
 266
 267         DBG_DEVS(("layout_dev: bus %d  slot 0x%x  VID 0x%x  DID 0x%x  class 0x%x\n",
 268                   dev->bus->number, PCI_SLOT(dev->devfn), dev->vendor, dev->device, dev->class));
 269 }
 270
 271 /*
 272  * static void layout_bus(struct pci_bus *bus)
 273  *
 274  * Layout memory and I/O for all devices on the given bus.
 275  *
 276  * Parameters:
 277  *
 278  * bus  - bus.
 279  */
 280
 281 static void __init layout_bus(struct pci_bus *bus)
 282 {
 283         unsigned int bio, bmem;
 284         struct pci_dev *dev;
 285
 286         DBG_DEVS(("layout_bus: starting bus %d\n", bus->number));
 287
 288         if (!bus->devices && !bus->children)
 289                 return;
 290
 291         /*
 292          * Align the current bases on appropriate boundaries (4K for
 293          * IO and 1MB for memory).
 294          */
 295
 296         bio = io_base = ALIGN(io_base, 4*KB);
 297         bmem = mem_base = ALIGN(mem_base, 1*MB);
 298
 299         /*
 300          * PCI devices might have been setup by a PCI BIOS emulation
 301          * running under TOS. In these cases there is a
 302          * window during which two devices may have an overlapping
 303          * address range. To avoid this causing trouble, we first
 304          * turn off the I/O and memory address decoders for all PCI
 305          * devices.  They'll be re-enabled only once all address
 306          * decoders are programmed consistently.
 307          */
 308
 309         DBG_DEVS(("layout_bus: disable_dev for bus %d\n", bus->number));
 310
 311         for (dev = bus->devices; dev; dev = dev->sibling)
 312         {
 313                 if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) ||
 314                     (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA))
 315                         disable_dev(dev);
 316         }
 317
 318         /*
 319          * Allocate space to each device:
 320          */
 321
 322         DBG_DEVS(("layout_bus: starting bus %d devices\n", bus->number));
 323
 324         for (dev = bus->devices; dev; dev = dev->sibling)
 325         {
 326                 if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) ||
 327                     (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA))
 328                         layout_dev(dev);
 329         }
 330
 331         DBG_DEVS(("layout_bus: bus %d finished\n", bus->number));
 332 }
 333
 334 /*
 335  * static void pcibios_fixup(void)
 336  *
 337  * Layout memory and I/O of all devices on the PCI bus if 'pci_modify' is
 338  * true. This might be necessary because not every m68k machine with a PCI
 339  * bus has a PCI BIOS. This function should be called right after
 340  * pci_scan_bus() in pcibios_init().
 341  */
 342
 343 static void __init pcibios_fixup(void)
 344 {
 345         if (pci_modify)
 346         {
 347                 /*
 348                  * Set base addresses for allocation of I/O and memory space.
 349                  */
 350
 351                 io_base = bus_info->io_space.start + IO_ALLOC_OFFSET;
 352                 mem_base = bus_info->mem_space.start + MEM_ALLOC_OFFSET;
 353
 354                 /*
 355                  * Scan the tree, allocating PCI memory and I/O space.
 356                  */
 357
 358                 layout_bus(pci_bus_b(pci_root.next));
 359         }
 360
 361         /*
 362          * Fix interrupt assignments, etc.
 363          */
 364
 365         bus_info->fixup(pci_modify);
 366 }
 367
 368 /*
 369  * static void pcibios_claim_resources(struct pci_bus *bus)
 370  *
 371  * Claim all resources that are assigned to devices on the given bus.
 372  *
 373  * Parameters:
 374  *
 375  * bus  - bus.
 376  */
 377
 378 static void __init pcibios_claim_resources(struct pci_bus *bus)
 379 {
 380         struct pci_dev *dev;
 381         int i;
 382
 383         while (bus)
 384         {
 385                 for (dev = bus->devices; (dev != NULL); dev = dev->sibling)
 386                 {
 387                         for (i = 0; i < PCI_NUM_RESOURCES; i++)
 388                         {
 389                                 struct resource *r = &dev->resource[i];
 390                                 struct resource *pr;
 391                                 struct pci_bus_info *bus_info = (struct pci_bus_info *) dev->sysdata;
 392
 393                                 if ((r->start == 0) || (r->parent != NULL))
 394                                         continue;
 395 #if 1
 396                                 if (r->flags & IORESOURCE_IO)
 397                                         pr = &bus_info->io_space;
 398                                 else
 399                                         pr = &bus_info->mem_space;
 400 #else
 401                                 if (r->flags & IORESOURCE_IO)
 402                                         pr = &ioport_resource;
 403                                 else
 404                                         pr = &iomem_resource;
 405 #endif
 406                                 if (request_resource(pr, r) < 0)
 407                                 {
 408                                         printk(KERN_ERR "PCI: Address space collision on region %d of device %s\n", i, dev->name);
 409                                 }
 410                         }
 411                 }
 412
 413                 if (bus->children)
 414                         pcibios_claim_resources(bus->children);
 415
 416                 bus = bus->next;
 417         }
 418 }
 419
 420 /*
 421  * int pcibios_assign_resource(struct pci_dev *dev, int i)
 422  *
 423  * Assign a new address to a PCI resource.
 424  *
 425  * Parameters:
 426  *
 427  * dev  - device.
 428  * i    - resource.
 429  *
 430  * Result: 0 if successful.
 431  */
 432
 433 int __init pcibios_assign_resource(struct pci_dev *dev, int i)
 434 {
 435         struct resource *r = &dev->resource[i];
 436         struct resource *pr = pci_find_parent_resource(dev, r);
 437         unsigned long size = r->end + 1;
 438
 439         if (!pr)
 440                 return -EINVAL;
 441
 442         if (r->flags & IORESOURCE_IO)
 443         {
 444                 if (size > 0x100)
 445                         return -EFBIG;
 446
 447                 if (allocate_resource(pr, r, size, bus_info->io_space.start +
 448                                       IO_ALLOC_OFFSET,  bus_info->io_space.end, 1024))
 449                         return -EBUSY;
 450         }
 451         else
 452         {
 453                 if (allocate_resource(pr, r, size, bus_info->mem_space.start +
 454                                       MEM_ALLOC_OFFSET, bus_info->mem_space.end, size))
 455                         return -EBUSY;
 456         }
 457
 458         if (i < 6)
 459                 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, r->start);
 460
 461         return 0;
 462 }
 463
 464 void __init pcibios_fixup_bus(struct pci_bus *bus)
 465 {
 466         struct pci_dev *dev;
 467         void *sysdata;
 468
 469         sysdata = (bus->parent) ? bus->parent->sysdata : bus->sysdata;
 470
 471         for (dev = bus->devices; (dev != NULL); dev = dev->sibling)
 472                 dev->sysdata = sysdata;
 473 }
 474
 475 void __init pcibios_init(void)
 476 {
 477         printk("Linux/m68k PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
 478
 479         bus_info = NULL;
 480 #ifdef CONFIG_HADES
 481         if (MACH_IS_HADES)
 482                 bus_info = init_hades_pci();
 483 #endif
 484         if (bus_info != NULL)
 485         {
 486                 printk("PCI: Probing PCI hardware\n");
 487                 pci_scan_bus(0, bus_info->m68k_pci_ops, bus_info);
 488                 pcibios_fixup();
 489                 pcibios_claim_resources(pci_root);
 490         }
 491         else
 492                 printk("PCI: No PCI bus detected\n");
 493 }
 494
 495 char * __init pcibios_setup(char *str)
 496 {
 497         if (!strcmp(str, "nomodify"))
 498         {
 499                 pci_modify = 0;
 500                 return NULL;
 501         }
 502         else if (!strcmp(str, "skipvga"))
 503         {
 504                 skip_vga = 1;
 505                 return NULL;
 506         }
 507         else if (!strcmp(str, "noburst"))
 508         {
 509                 disable_pci_burst = 1;
 510                 return NULL;
 511         }
 512
 513         return str;
 514 }
 515 #endif /* CONFIG_PCI */