arch/i386/kernel/cpu/cpufreq/powernow-k8.h

   1 /*
   2  *  (c) 2003, 2004 Advanced Micro Devices, Inc.
   3  *  Your use of this code is subject to the terms and conditions of the
   4  *  GNU general public license version 2. See "COPYING" or
   5  *  http://www.gnu.org/licenses/gpl.html
   6  */
   7
   8 struct powernow_k8_data {
   9         unsigned int cpu;
  10
  11         u32 numps;  /* number of p-states */
  12         u32 batps;  /* number of p-states supported on battery */
  13
  14         /* these values are constant when the PSB is used to determine
  15          * vid/fid pairings, but are modified during the ->target() call
  16          * when ACPI is used */
  17         u32 rvo;     /* ramp voltage offset */
  18         u32 irt;     /* isochronous relief time */
  19         u32 vidmvs;  /* usable value calculated from mvs */
  20         u32 vstable; /* voltage stabilization time, units 20 us */
  21         u32 plllock; /* pll lock time, units 1 us */
  22
  23         /* keep track of the current fid / vid */
  24         u32 currvid, currfid;
  25
  26         /* the powernow_table includes all frequency and vid/fid pairings:
  27          * fid are the lower 8 bits of the index, vid are the upper 8 bits.
  28          * frequency is in kHz */
  29         struct cpufreq_frequency_table  *powernow_table;
  30
  31 #ifdef CONFIG_X86_POWERNOW_K8_ACPI
  32         /* the acpi table needs to be kept. it's only available if ACPI was
  33          * used to determine valid frequency/vid/fid states */
  34         struct acpi_processor_performance acpi_data;
  35 #endif
  36 };
  37
  38
  39 /* processor's cpuid instruction support */
  40 #define CPUID_PROCESSOR_SIGNATURE       1       /* function 1 */
  41 #define CPUID_XFAM                      0x0ff00000      /* extended family */
  42 #define CPUID_XFAM_K8                   0
  43 #define CPUID_XMOD                      0x000f0000      /* extended model */
  44 #define CPUID_XMOD_REV_E                0x00020000
  45 #define CPUID_USE_XFAM_XMOD             0x00000f00
  46 #define CPUID_GET_MAX_CAPABILITIES      0x80000000
  47 #define CPUID_FREQ_VOLT_CAPABILITIES    0x80000007
  48 #define P_STATE_TRANSITION_CAPABLE      6
  49
  50 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For     */
  51 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and   */
  52 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
  53 /* the register number is placed in ecx, and the data is returned in edx:eax. */
  54
  55 #define MSR_FIDVID_CTL      0xc0010041
  56 #define MSR_FIDVID_STATUS   0xc0010042
  57
  58 /* Field definitions within the FID VID Low Control MSR : */
  59 #define MSR_C_LO_INIT_FID_VID     0x00010000
  60 #define MSR_C_LO_NEW_VID          0x00001f00
  61 #define MSR_C_LO_NEW_FID          0x0000002f
  62 #define MSR_C_LO_VID_SHIFT        8
  63
  64 /* Field definitions within the FID VID High Control MSR : */
  65 #define MSR_C_HI_STP_GNT_TO       0x000fffff
  66
  67 /* Field definitions within the FID VID Low Status MSR : */
  68 #define MSR_S_LO_CHANGE_PENDING   0x80000000    /* cleared when completed */
  69 #define MSR_S_LO_MAX_RAMP_VID     0x1f000000
  70 #define MSR_S_LO_MAX_FID          0x003f0000
  71 #define MSR_S_LO_START_FID        0x00003f00
  72 #define MSR_S_LO_CURRENT_FID      0x0000003f
  73
  74 /* Field definitions within the FID VID High Status MSR : */
  75 #define MSR_S_HI_MAX_WORKING_VID  0x001f0000
  76 #define MSR_S_HI_START_VID        0x00001f00
  77 #define MSR_S_HI_CURRENT_VID      0x0000001f
  78 #define MSR_C_HI_STP_GNT_BENIGN   0x00000001
  79
  80 /*
  81  * There are restrictions frequencies have to follow:
  82  * - only 1 entry in the low fid table ( <=1.4GHz )
  83  * - lowest entry in the high fid table must be >= 2 * the entry in the
  84  *   low fid table
  85  * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
  86  *   in the low fid table
  87  * - the parts can only step at 200 MHz intervals, so 1.9 GHz is never valid
  88  * - lowest frequency must be >= interprocessor hypertransport link speed
  89  *   (only applies to MP systems obviously)
  90  */
  91
  92 /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
  93 #define LO_FID_TABLE_TOP     6  /* fid values marking the boundary    */
  94 #define HI_FID_TABLE_BOTTOM  8  /* between the low and high tables    */
  95
  96 #define LO_VCOFREQ_TABLE_TOP    1400    /* corresponding vco frequency values */
  97 #define HI_VCOFREQ_TABLE_BOTTOM 1600
  98
  99 #define MIN_FREQ_RESOLUTION  200 /* fids jump by 2 matching freq jumps by 200 */
 100
 101 #define MAX_FID 0x2a    /* Spec only gives FID values as far as 5 GHz */
 102 #define LEAST_VID 0x1e  /* Lowest (numerically highest) useful vid value */
 103
 104 #define MIN_FREQ 800    /* Min and max freqs, per spec */
 105 #define MAX_FREQ 5000
 106
 107 #define INVALID_FID_MASK 0xffffffc1  /* not a valid fid if these bits are set */
 108 #define INVALID_VID_MASK 0xffffffe0  /* not a valid vid if these bits are set */
 109
 110 #define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */
 111
 112 #define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */
 113
 114 #define MAXIMUM_VID_STEPS 1  /* Current cpus only allow a single step of 25mV */
 115 #define VST_UNITS_20US 20   /* Voltage Stabalization Time is in units of 20us */
 116
 117 /*
 118  * Most values of interest are enocoded in a single field of the _PSS
 119  * entries: the "control" value.
 120  */
 121
 122 #define IRT_SHIFT      30
 123 #define RVO_SHIFT      28
 124 #define PLL_L_SHIFT    20
 125 #define MVS_SHIFT      18
 126 #define VST_SHIFT      11
 127 #define VID_SHIFT       6
 128 #define IRT_MASK        3
 129 #define RVO_MASK        3
 130 #define PLL_L_MASK   0x7f
 131 #define MVS_MASK        3
 132 #define VST_MASK     0x7f
 133 #define VID_MASK     0x1f
 134 #define FID_MASK     0x3f
 135
 136
 137 /*
 138  * Version 1.4 of the PSB table. This table is constructed by BIOS and is
 139  * to tell the OS's power management driver which VIDs and FIDs are
 140  * supported by this particular processor.
 141  * If the data in the PSB / PST is wrong, then this driver will program the
 142  * wrong values into hardware, which is very likely to lead to a crash.
 143  */
 144
 145 #define PSB_ID_STRING      "AMDK7PNOW!"
 146 #define PSB_ID_STRING_LEN  10
 147
 148 #define PSB_VERSION_1_4  0x14
 149
 150 struct psb_s {
 151         u8 signature[10];
 152         u8 tableversion;
 153         u8 flags1;
 154         u16 vstable;
 155         u8 flags2;
 156         u8 num_tables;
 157         u32 cpuid;
 158         u8 plllocktime;
 159         u8 maxfid;
 160         u8 maxvid;
 161         u8 numps;
 162 };
 163
 164 /* Pairs of fid/vid values are appended to the version 1.4 PSB table. */
 165 struct pst_s {
 166         u8 fid;
 167         u8 vid;
 168 };
 169
 170 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "powernow-k8", msg)
 171
 172 static int core_voltage_pre_transition(struct powernow_k8_data *data, u32 reqvid);
 173 static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid);
 174 static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid);
 175
 176 static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index);