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jme: Fix unmap error (Causing system freeze)
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / jme.c
blob0d0aafd2444d3b3afbbd849f2375557cdabda621
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/mii.h>
31 #include <linux/crc32.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/ipv6.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/if_vlan.h>
40 #include <linux/slab.h>
41 #include <net/ip6_checksum.h>
42 #include "jme.h"
43
44 static int force_pseudohp = -1;
45 static int no_pseudohp = -1;
46 static int no_extplug = -1;
47 module_param(force_pseudohp, int, 0);
48 MODULE_PARM_DESC(force_pseudohp,
49 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
50 module_param(no_pseudohp, int, 0);
51 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
52 module_param(no_extplug, int, 0);
53 MODULE_PARM_DESC(no_extplug,
54 "Do not use external plug signal for pseudo hot-plug.");
55
56 static int
57 jme_mdio_read(struct net_device *netdev, int phy, int reg)
58 {
59 struct jme_adapter *jme = netdev_priv(netdev);
60 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
61
62 read_again:
63 jwrite32(jme, JME_SMI, SMI_OP_REQ |
64 smi_phy_addr(phy) |
65 smi_reg_addr(reg));
66
67 wmb();
68 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
69 udelay(20);
70 val = jread32(jme, JME_SMI);
71 if ((val & SMI_OP_REQ) == 0)
72 break;
73 }
74
75 if (i == 0) {
76 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
77 return 0;
78 }
79
80 if (again--)
81 goto read_again;
82
83 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
84 }
85
86 static void
87 jme_mdio_write(struct net_device *netdev,
88 int phy, int reg, int val)
89 {
90 struct jme_adapter *jme = netdev_priv(netdev);
91 int i;
92
93 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
94 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
95 smi_phy_addr(phy) | smi_reg_addr(reg));
96
97 wmb();
98 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
99 udelay(20);
100 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
101 break;
102 }
103
104 if (i == 0)
105 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
106 }
107
108 static inline void
109 jme_reset_phy_processor(struct jme_adapter *jme)
110 {
111 u32 val;
112
113 jme_mdio_write(jme->dev,
114 jme->mii_if.phy_id,
115 MII_ADVERTISE, ADVERTISE_ALL |
116 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
117
118 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
119 jme_mdio_write(jme->dev,
120 jme->mii_if.phy_id,
121 MII_CTRL1000,
122 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
123
124 val = jme_mdio_read(jme->dev,
125 jme->mii_if.phy_id,
126 MII_BMCR);
127
128 jme_mdio_write(jme->dev,
129 jme->mii_if.phy_id,
130 MII_BMCR, val | BMCR_RESET);
131 }
132
133 static void
134 jme_setup_wakeup_frame(struct jme_adapter *jme,
135 u32 *mask, u32 crc, int fnr)
136 {
137 int i;
138
139 /*
140 * Setup CRC pattern
141 */
142 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
143 wmb();
144 jwrite32(jme, JME_WFODP, crc);
145 wmb();
146
147 /*
148 * Setup Mask
149 */
150 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
151 jwrite32(jme, JME_WFOI,
152 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
153 (fnr & WFOI_FRAME_SEL));
154 wmb();
155 jwrite32(jme, JME_WFODP, mask[i]);
156 wmb();
157 }
158 }
159
160 static inline void
161 jme_reset_mac_processor(struct jme_adapter *jme)
162 {
163 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
164 u32 crc = 0xCDCDCDCD;
165 u32 gpreg0;
166 int i;
167
168 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
169 udelay(2);
170 jwrite32(jme, JME_GHC, jme->reg_ghc);
171
172 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
173 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
174 jwrite32(jme, JME_RXQDC, 0x00000000);
175 jwrite32(jme, JME_RXNDA, 0x00000000);
176 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
177 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
178 jwrite32(jme, JME_TXQDC, 0x00000000);
179 jwrite32(jme, JME_TXNDA, 0x00000000);
180
181 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
182 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
183 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
184 jme_setup_wakeup_frame(jme, mask, crc, i);
185 if (jme->fpgaver)
186 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
187 else
188 gpreg0 = GPREG0_DEFAULT;
189 jwrite32(jme, JME_GPREG0, gpreg0);
190 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
191 }
192
193 static inline void
194 jme_reset_ghc_speed(struct jme_adapter *jme)
195 {
196 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
197 jwrite32(jme, JME_GHC, jme->reg_ghc);
198 }
199
200 static inline void
201 jme_clear_pm(struct jme_adapter *jme)
202 {
203 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
204 pci_set_power_state(jme->pdev, PCI_D0);
205 pci_enable_wake(jme->pdev, PCI_D0, false);
206 }
207
208 static int
209 jme_reload_eeprom(struct jme_adapter *jme)
210 {
211 u32 val;
212 int i;
213
214 val = jread32(jme, JME_SMBCSR);
215
216 if (val & SMBCSR_EEPROMD) {
217 val |= SMBCSR_CNACK;
218 jwrite32(jme, JME_SMBCSR, val);
219 val |= SMBCSR_RELOAD;
220 jwrite32(jme, JME_SMBCSR, val);
221 mdelay(12);
222
223 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
224 mdelay(1);
225 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
226 break;
227 }
228
229 if (i == 0) {
230 jeprintk(jme->pdev, "eeprom reload timeout\n");
231 return -EIO;
232 }
233 }
234
235 return 0;
236 }
237
238 static void
239 jme_load_macaddr(struct net_device *netdev)
240 {
241 struct jme_adapter *jme = netdev_priv(netdev);
242 unsigned char macaddr[6];
243 u32 val;
244
245 spin_lock_bh(&jme->macaddr_lock);
246 val = jread32(jme, JME_RXUMA_LO);
247 macaddr[0] = (val >> 0) & 0xFF;
248 macaddr[1] = (val >> 8) & 0xFF;
249 macaddr[2] = (val >> 16) & 0xFF;
250 macaddr[3] = (val >> 24) & 0xFF;
251 val = jread32(jme, JME_RXUMA_HI);
252 macaddr[4] = (val >> 0) & 0xFF;
253 macaddr[5] = (val >> 8) & 0xFF;
254 memcpy(netdev->dev_addr, macaddr, 6);
255 spin_unlock_bh(&jme->macaddr_lock);
256 }
257
258 static inline void
259 jme_set_rx_pcc(struct jme_adapter *jme, int p)
260 {
261 switch (p) {
262 case PCC_OFF:
263 jwrite32(jme, JME_PCCRX0,
264 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
265 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
266 break;
267 case PCC_P1:
268 jwrite32(jme, JME_PCCRX0,
269 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
270 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
271 break;
272 case PCC_P2:
273 jwrite32(jme, JME_PCCRX0,
274 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
275 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
276 break;
277 case PCC_P3:
278 jwrite32(jme, JME_PCCRX0,
279 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
280 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
281 break;
282 default:
283 break;
284 }
285 wmb();
286
287 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
288 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
289 }
290
291 static void
292 jme_start_irq(struct jme_adapter *jme)
293 {
294 register struct dynpcc_info *dpi = &(jme->dpi);
295
296 jme_set_rx_pcc(jme, PCC_P1);
297 dpi->cur = PCC_P1;
298 dpi->attempt = PCC_P1;
299 dpi->cnt = 0;
300
301 jwrite32(jme, JME_PCCTX,
302 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
303 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
304 PCCTXQ0_EN
305 );
306
307 /*
308 * Enable Interrupts
309 */
310 jwrite32(jme, JME_IENS, INTR_ENABLE);
311 }
312
313 static inline void
314 jme_stop_irq(struct jme_adapter *jme)
315 {
316 /*
317 * Disable Interrupts
318 */
319 jwrite32f(jme, JME_IENC, INTR_ENABLE);
320 }
321
322 static u32
323 jme_linkstat_from_phy(struct jme_adapter *jme)
324 {
325 u32 phylink, bmsr;
326
327 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
328 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
329 if (bmsr & BMSR_ANCOMP)
330 phylink |= PHY_LINK_AUTONEG_COMPLETE;
331
332 return phylink;
333 }
334
335 static inline void
336 jme_set_phyfifoa(struct jme_adapter *jme)
337 {
338 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
339 }
340
341 static inline void
342 jme_set_phyfifob(struct jme_adapter *jme)
343 {
344 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
345 }
346
347 static int
348 jme_check_link(struct net_device *netdev, int testonly)
349 {
350 struct jme_adapter *jme = netdev_priv(netdev);
351 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
352 char linkmsg[64];
353 int rc = 0;
354
355 linkmsg[0] = '\0';
356
357 if (jme->fpgaver)
358 phylink = jme_linkstat_from_phy(jme);
359 else
360 phylink = jread32(jme, JME_PHY_LINK);
361
362 if (phylink & PHY_LINK_UP) {
363 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
364 /*
365 * If we did not enable AN
366 * Speed/Duplex Info should be obtained from SMI
367 */
368 phylink = PHY_LINK_UP;
369
370 bmcr = jme_mdio_read(jme->dev,
371 jme->mii_if.phy_id,
372 MII_BMCR);
373
374 phylink |= ((bmcr & BMCR_SPEED1000) &&
375 (bmcr & BMCR_SPEED100) == 0) ?
376 PHY_LINK_SPEED_1000M :
377 (bmcr & BMCR_SPEED100) ?
378 PHY_LINK_SPEED_100M :
379 PHY_LINK_SPEED_10M;
380
381 phylink |= (bmcr & BMCR_FULLDPLX) ?
382 PHY_LINK_DUPLEX : 0;
383
384 strcat(linkmsg, "Forced: ");
385 } else {
386 /*
387 * Keep polling for speed/duplex resolve complete
388 */
389 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
390 --cnt) {
391
392 udelay(1);
393
394 if (jme->fpgaver)
395 phylink = jme_linkstat_from_phy(jme);
396 else
397 phylink = jread32(jme, JME_PHY_LINK);
398 }
399 if (!cnt)
400 jeprintk(jme->pdev,
401 "Waiting speed resolve timeout.\n");
402
403 strcat(linkmsg, "ANed: ");
404 }
405
406 if (jme->phylink == phylink) {
407 rc = 1;
408 goto out;
409 }
410 if (testonly)
411 goto out;
412
413 jme->phylink = phylink;
414
415 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
416 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
417 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
418 switch (phylink & PHY_LINK_SPEED_MASK) {
419 case PHY_LINK_SPEED_10M:
420 ghc |= GHC_SPEED_10M |
421 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
422 strcat(linkmsg, "10 Mbps, ");
423 break;
424 case PHY_LINK_SPEED_100M:
425 ghc |= GHC_SPEED_100M |
426 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
427 strcat(linkmsg, "100 Mbps, ");
428 break;
429 case PHY_LINK_SPEED_1000M:
430 ghc |= GHC_SPEED_1000M |
431 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
432 strcat(linkmsg, "1000 Mbps, ");
433 break;
434 default:
435 break;
436 }
437
438 if (phylink & PHY_LINK_DUPLEX) {
439 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
440 ghc |= GHC_DPX;
441 } else {
442 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
443 TXMCS_BACKOFF |
444 TXMCS_CARRIERSENSE |
445 TXMCS_COLLISION);
446 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
447 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
448 TXTRHD_TXREN |
449 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
450 }
451
452 gpreg1 = GPREG1_DEFAULT;
453 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
454 if (!(phylink & PHY_LINK_DUPLEX))
455 gpreg1 |= GPREG1_HALFMODEPATCH;
456 switch (phylink & PHY_LINK_SPEED_MASK) {
457 case PHY_LINK_SPEED_10M:
458 jme_set_phyfifoa(jme);
459 gpreg1 |= GPREG1_RSSPATCH;
460 break;
461 case PHY_LINK_SPEED_100M:
462 jme_set_phyfifob(jme);
463 gpreg1 |= GPREG1_RSSPATCH;
464 break;
465 case PHY_LINK_SPEED_1000M:
466 jme_set_phyfifoa(jme);
467 break;
468 default:
469 break;
470 }
471 }
472
473 jwrite32(jme, JME_GPREG1, gpreg1);
474 jwrite32(jme, JME_GHC, ghc);
475 jme->reg_ghc = ghc;
476
477 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
478 "Full-Duplex, " :
479 "Half-Duplex, ");
480 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
481 "MDI-X" :
482 "MDI");
483 netif_info(jme, link, jme->dev, "Link is up at %s.\n", linkmsg);
484 netif_carrier_on(netdev);
485 } else {
486 if (testonly)
487 goto out;
488
489 netif_info(jme, link, jme->dev, "Link is down.\n");
490 jme->phylink = 0;
491 netif_carrier_off(netdev);
492 }
493
494 out:
495 return rc;
496 }
497
498 static int
499 jme_setup_tx_resources(struct jme_adapter *jme)
500 {
501 struct jme_ring *txring = &(jme->txring[0]);
502
503 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
504 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
505 &(txring->dmaalloc),
506 GFP_ATOMIC);
507
508 if (!txring->alloc)
509 goto err_set_null;
510
511 /*
512 * 16 Bytes align
513 */
514 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
515 RING_DESC_ALIGN);
516 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
517 txring->next_to_use = 0;
518 atomic_set(&txring->next_to_clean, 0);
519 atomic_set(&txring->nr_free, jme->tx_ring_size);
520
521 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
522 jme->tx_ring_size, GFP_ATOMIC);
523 if (unlikely(!(txring->bufinf)))
524 goto err_free_txring;
525
526 /*
527 * Initialize Transmit Descriptors
528 */
529 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
530 memset(txring->bufinf, 0,
531 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
532
533 return 0;
534
535 err_free_txring:
536 dma_free_coherent(&(jme->pdev->dev),
537 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
538 txring->alloc,
539 txring->dmaalloc);
540
541 err_set_null:
542 txring->desc = NULL;
543 txring->dmaalloc = 0;
544 txring->dma = 0;
545 txring->bufinf = NULL;
546
547 return -ENOMEM;
548 }
549
550 static void
551 jme_free_tx_resources(struct jme_adapter *jme)
552 {
553 int i;
554 struct jme_ring *txring = &(jme->txring[0]);
555 struct jme_buffer_info *txbi;
556
557 if (txring->alloc) {
558 if (txring->bufinf) {
559 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
560 txbi = txring->bufinf + i;
561 if (txbi->skb) {
562 dev_kfree_skb(txbi->skb);
563 txbi->skb = NULL;
564 }
565 txbi->mapping = 0;
566 txbi->len = 0;
567 txbi->nr_desc = 0;
568 txbi->start_xmit = 0;
569 }
570 kfree(txring->bufinf);
571 }
572
573 dma_free_coherent(&(jme->pdev->dev),
574 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
575 txring->alloc,
576 txring->dmaalloc);
577
578 txring->alloc = NULL;
579 txring->desc = NULL;
580 txring->dmaalloc = 0;
581 txring->dma = 0;
582 txring->bufinf = NULL;
583 }
584 txring->next_to_use = 0;
585 atomic_set(&txring->next_to_clean, 0);
586 atomic_set(&txring->nr_free, 0);
587 }
588
589 static inline void
590 jme_enable_tx_engine(struct jme_adapter *jme)
591 {
592 /*
593 * Select Queue 0
594 */
595 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
596 wmb();
597
598 /*
599 * Setup TX Queue 0 DMA Bass Address
600 */
601 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
602 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
603 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
604
605 /*
606 * Setup TX Descptor Count
607 */
608 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
609
610 /*
611 * Enable TX Engine
612 */
613 wmb();
614 jwrite32(jme, JME_TXCS, jme->reg_txcs |
615 TXCS_SELECT_QUEUE0 |
616 TXCS_ENABLE);
617
618 }
619
620 static inline void
621 jme_restart_tx_engine(struct jme_adapter *jme)
622 {
623 /*
624 * Restart TX Engine
625 */
626 jwrite32(jme, JME_TXCS, jme->reg_txcs |
627 TXCS_SELECT_QUEUE0 |
628 TXCS_ENABLE);
629 }
630
631 static inline void
632 jme_disable_tx_engine(struct jme_adapter *jme)
633 {
634 int i;
635 u32 val;
636
637 /*
638 * Disable TX Engine
639 */
640 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
641 wmb();
642
643 val = jread32(jme, JME_TXCS);
644 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
645 mdelay(1);
646 val = jread32(jme, JME_TXCS);
647 rmb();
648 }
649
650 if (!i)
651 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
652 }
653
654 static void
655 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
656 {
657 struct jme_ring *rxring = &(jme->rxring[0]);
658 register struct rxdesc *rxdesc = rxring->desc;
659 struct jme_buffer_info *rxbi = rxring->bufinf;
660 rxdesc += i;
661 rxbi += i;
662
663 rxdesc->dw[0] = 0;
664 rxdesc->dw[1] = 0;
665 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
666 rxdesc->desc1.bufaddrl = cpu_to_le32(
667 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
668 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
669 if (jme->dev->features & NETIF_F_HIGHDMA)
670 rxdesc->desc1.flags = RXFLAG_64BIT;
671 wmb();
672 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
673 }
674
675 static int
676 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
677 {
678 struct jme_ring *rxring = &(jme->rxring[0]);
679 struct jme_buffer_info *rxbi = rxring->bufinf + i;
680 struct sk_buff *skb;
681 dma_addr_t mapping;
682
683 skb = netdev_alloc_skb(jme->dev,
684 jme->dev->mtu + RX_EXTRA_LEN);
685 if (unlikely(!skb))
686 return -ENOMEM;
687
688 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
689 offset_in_page(skb->data), skb_tailroom(skb),
690 PCI_DMA_FROMDEVICE);
691 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
692 dev_kfree_skb(skb);
693 return -ENOMEM;
694 }
695
696 if (likely(rxbi->mapping))
697 pci_unmap_page(jme->pdev, rxbi->mapping,
698 rxbi->len, PCI_DMA_FROMDEVICE);
699
700 rxbi->skb = skb;
701 rxbi->len = skb_tailroom(skb);
702 rxbi->mapping = mapping;
703 return 0;
704 }
705
706 static void
707 jme_free_rx_buf(struct jme_adapter *jme, int i)
708 {
709 struct jme_ring *rxring = &(jme->rxring[0]);
710 struct jme_buffer_info *rxbi = rxring->bufinf;
711 rxbi += i;
712
713 if (rxbi->skb) {
714 pci_unmap_page(jme->pdev,
715 rxbi->mapping,
716 rxbi->len,
717 PCI_DMA_FROMDEVICE);
718 dev_kfree_skb(rxbi->skb);
719 rxbi->skb = NULL;
720 rxbi->mapping = 0;
721 rxbi->len = 0;
722 }
723 }
724
725 static void
726 jme_free_rx_resources(struct jme_adapter *jme)
727 {
728 int i;
729 struct jme_ring *rxring = &(jme->rxring[0]);
730
731 if (rxring->alloc) {
732 if (rxring->bufinf) {
733 for (i = 0 ; i < jme->rx_ring_size ; ++i)
734 jme_free_rx_buf(jme, i);
735 kfree(rxring->bufinf);
736 }
737
738 dma_free_coherent(&(jme->pdev->dev),
739 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
740 rxring->alloc,
741 rxring->dmaalloc);
742 rxring->alloc = NULL;
743 rxring->desc = NULL;
744 rxring->dmaalloc = 0;
745 rxring->dma = 0;
746 rxring->bufinf = NULL;
747 }
748 rxring->next_to_use = 0;
749 atomic_set(&rxring->next_to_clean, 0);
750 }
751
752 static int
753 jme_setup_rx_resources(struct jme_adapter *jme)
754 {
755 int i;
756 struct jme_ring *rxring = &(jme->rxring[0]);
757
758 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
759 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
760 &(rxring->dmaalloc),
761 GFP_ATOMIC);
762 if (!rxring->alloc)
763 goto err_set_null;
764
765 /*
766 * 16 Bytes align
767 */
768 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
769 RING_DESC_ALIGN);
770 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
771 rxring->next_to_use = 0;
772 atomic_set(&rxring->next_to_clean, 0);
773
774 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
775 jme->rx_ring_size, GFP_ATOMIC);
776 if (unlikely(!(rxring->bufinf)))
777 goto err_free_rxring;
778
779 /*
780 * Initiallize Receive Descriptors
781 */
782 memset(rxring->bufinf, 0,
783 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
784 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
785 if (unlikely(jme_make_new_rx_buf(jme, i))) {
786 jme_free_rx_resources(jme);
787 return -ENOMEM;
788 }
789
790 jme_set_clean_rxdesc(jme, i);
791 }
792
793 return 0;
794
795 err_free_rxring:
796 dma_free_coherent(&(jme->pdev->dev),
797 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
798 rxring->alloc,
799 rxring->dmaalloc);
800 err_set_null:
801 rxring->desc = NULL;
802 rxring->dmaalloc = 0;
803 rxring->dma = 0;
804 rxring->bufinf = NULL;
805
806 return -ENOMEM;
807 }
808
809 static inline void
810 jme_enable_rx_engine(struct jme_adapter *jme)
811 {
812 /*
813 * Select Queue 0
814 */
815 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
816 RXCS_QUEUESEL_Q0);
817 wmb();
818
819 /*
820 * Setup RX DMA Bass Address
821 */
822 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
823 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
824 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
825
826 /*
827 * Setup RX Descriptor Count
828 */
829 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
830
831 /*
832 * Setup Unicast Filter
833 */
834 jme_set_multi(jme->dev);
835
836 /*
837 * Enable RX Engine
838 */
839 wmb();
840 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
841 RXCS_QUEUESEL_Q0 |
842 RXCS_ENABLE |
843 RXCS_QST);
844 }
845
846 static inline void
847 jme_restart_rx_engine(struct jme_adapter *jme)
848 {
849 /*
850 * Start RX Engine
851 */
852 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
853 RXCS_QUEUESEL_Q0 |
854 RXCS_ENABLE |
855 RXCS_QST);
856 }
857
858 static inline void
859 jme_disable_rx_engine(struct jme_adapter *jme)
860 {
861 int i;
862 u32 val;
863
864 /*
865 * Disable RX Engine
866 */
867 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
868 wmb();
869
870 val = jread32(jme, JME_RXCS);
871 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
872 mdelay(1);
873 val = jread32(jme, JME_RXCS);
874 rmb();
875 }
876
877 if (!i)
878 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
879
880 }
881
882 static int
883 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
884 {
885 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
886 return false;
887
888 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
889 == RXWBFLAG_TCPON)) {
890 if (flags & RXWBFLAG_IPV4)
891 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
892 return false;
893 }
894
895 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
896 == RXWBFLAG_UDPON)) {
897 if (flags & RXWBFLAG_IPV4)
898 netif_err(jme, rx_err, jme->dev, "UDP Checksum error.\n");
899 return false;
900 }
901
902 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
903 == RXWBFLAG_IPV4)) {
904 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error.\n");
905 return false;
906 }
907
908 return true;
909 }
910
911 static void
912 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
913 {
914 struct jme_ring *rxring = &(jme->rxring[0]);
915 struct rxdesc *rxdesc = rxring->desc;
916 struct jme_buffer_info *rxbi = rxring->bufinf;
917 struct sk_buff *skb;
918 int framesize;
919
920 rxdesc += idx;
921 rxbi += idx;
922
923 skb = rxbi->skb;
924 pci_dma_sync_single_for_cpu(jme->pdev,
925 rxbi->mapping,
926 rxbi->len,
927 PCI_DMA_FROMDEVICE);
928
929 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
930 pci_dma_sync_single_for_device(jme->pdev,
931 rxbi->mapping,
932 rxbi->len,
933 PCI_DMA_FROMDEVICE);
934
935 ++(NET_STAT(jme).rx_dropped);
936 } else {
937 framesize = le16_to_cpu(rxdesc->descwb.framesize)
938 - RX_PREPAD_SIZE;
939
940 skb_reserve(skb, RX_PREPAD_SIZE);
941 skb_put(skb, framesize);
942 skb->protocol = eth_type_trans(skb, jme->dev);
943
944 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
945 skb->ip_summed = CHECKSUM_UNNECESSARY;
946 else
947 skb->ip_summed = CHECKSUM_NONE;
948
949 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
950 if (jme->vlgrp) {
951 jme->jme_vlan_rx(skb, jme->vlgrp,
952 le16_to_cpu(rxdesc->descwb.vlan));
953 NET_STAT(jme).rx_bytes += 4;
954 } else {
955 dev_kfree_skb(skb);
956 }
957 } else {
958 jme->jme_rx(skb);
959 }
960
961 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
962 cpu_to_le16(RXWBFLAG_DEST_MUL))
963 ++(NET_STAT(jme).multicast);
964
965 NET_STAT(jme).rx_bytes += framesize;
966 ++(NET_STAT(jme).rx_packets);
967 }
968
969 jme_set_clean_rxdesc(jme, idx);
970
971 }
972
973 static int
974 jme_process_receive(struct jme_adapter *jme, int limit)
975 {
976 struct jme_ring *rxring = &(jme->rxring[0]);
977 struct rxdesc *rxdesc = rxring->desc;
978 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
979
980 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
981 goto out_inc;
982
983 if (unlikely(atomic_read(&jme->link_changing) != 1))
984 goto out_inc;
985
986 if (unlikely(!netif_carrier_ok(jme->dev)))
987 goto out_inc;
988
989 i = atomic_read(&rxring->next_to_clean);
990 while (limit > 0) {
991 rxdesc = rxring->desc;
992 rxdesc += i;
993
994 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
995 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
996 goto out;
997 --limit;
998
999 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1000
1001 if (unlikely(desccnt > 1 ||
1002 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1003
1004 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1005 ++(NET_STAT(jme).rx_crc_errors);
1006 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1007 ++(NET_STAT(jme).rx_fifo_errors);
1008 else
1009 ++(NET_STAT(jme).rx_errors);
1010
1011 if (desccnt > 1)
1012 limit -= desccnt - 1;
1013
1014 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1015 jme_set_clean_rxdesc(jme, j);
1016 j = (j + 1) & (mask);
1017 }
1018
1019 } else {
1020 jme_alloc_and_feed_skb(jme, i);
1021 }
1022
1023 i = (i + desccnt) & (mask);
1024 }
1025
1026 out:
1027 atomic_set(&rxring->next_to_clean, i);
1028
1029 out_inc:
1030 atomic_inc(&jme->rx_cleaning);
1031
1032 return limit > 0 ? limit : 0;
1033
1034 }
1035
1036 static void
1037 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1038 {
1039 if (likely(atmp == dpi->cur)) {
1040 dpi->cnt = 0;
1041 return;
1042 }
1043
1044 if (dpi->attempt == atmp) {
1045 ++(dpi->cnt);
1046 } else {
1047 dpi->attempt = atmp;
1048 dpi->cnt = 0;
1049 }
1050
1051 }
1052
1053 static void
1054 jme_dynamic_pcc(struct jme_adapter *jme)
1055 {
1056 register struct dynpcc_info *dpi = &(jme->dpi);
1057
1058 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1059 jme_attempt_pcc(dpi, PCC_P3);
1060 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1061 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1062 jme_attempt_pcc(dpi, PCC_P2);
1063 else
1064 jme_attempt_pcc(dpi, PCC_P1);
1065
1066 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1067 if (dpi->attempt < dpi->cur)
1068 tasklet_schedule(&jme->rxclean_task);
1069 jme_set_rx_pcc(jme, dpi->attempt);
1070 dpi->cur = dpi->attempt;
1071 dpi->cnt = 0;
1072 }
1073 }
1074
1075 static void
1076 jme_start_pcc_timer(struct jme_adapter *jme)
1077 {
1078 struct dynpcc_info *dpi = &(jme->dpi);
1079 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1080 dpi->last_pkts = NET_STAT(jme).rx_packets;
1081 dpi->intr_cnt = 0;
1082 jwrite32(jme, JME_TMCSR,
1083 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1084 }
1085
1086 static inline void
1087 jme_stop_pcc_timer(struct jme_adapter *jme)
1088 {
1089 jwrite32(jme, JME_TMCSR, 0);
1090 }
1091
1092 static void
1093 jme_shutdown_nic(struct jme_adapter *jme)
1094 {
1095 u32 phylink;
1096
1097 phylink = jme_linkstat_from_phy(jme);
1098
1099 if (!(phylink & PHY_LINK_UP)) {
1100 /*
1101 * Disable all interrupt before issue timer
1102 */
1103 jme_stop_irq(jme);
1104 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1105 }
1106 }
1107
1108 static void
1109 jme_pcc_tasklet(unsigned long arg)
1110 {
1111 struct jme_adapter *jme = (struct jme_adapter *)arg;
1112 struct net_device *netdev = jme->dev;
1113
1114 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1115 jme_shutdown_nic(jme);
1116 return;
1117 }
1118
1119 if (unlikely(!netif_carrier_ok(netdev) ||
1120 (atomic_read(&jme->link_changing) != 1)
1121 )) {
1122 jme_stop_pcc_timer(jme);
1123 return;
1124 }
1125
1126 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1127 jme_dynamic_pcc(jme);
1128
1129 jme_start_pcc_timer(jme);
1130 }
1131
1132 static inline void
1133 jme_polling_mode(struct jme_adapter *jme)
1134 {
1135 jme_set_rx_pcc(jme, PCC_OFF);
1136 }
1137
1138 static inline void
1139 jme_interrupt_mode(struct jme_adapter *jme)
1140 {
1141 jme_set_rx_pcc(jme, PCC_P1);
1142 }
1143
1144 static inline int
1145 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1146 {
1147 u32 apmc;
1148 apmc = jread32(jme, JME_APMC);
1149 return apmc & JME_APMC_PSEUDO_HP_EN;
1150 }
1151
1152 static void
1153 jme_start_shutdown_timer(struct jme_adapter *jme)
1154 {
1155 u32 apmc;
1156
1157 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1158 apmc &= ~JME_APMC_EPIEN_CTRL;
1159 if (!no_extplug) {
1160 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1161 wmb();
1162 }
1163 jwrite32f(jme, JME_APMC, apmc);
1164
1165 jwrite32f(jme, JME_TIMER2, 0);
1166 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1167 jwrite32(jme, JME_TMCSR,
1168 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1169 }
1170
1171 static void
1172 jme_stop_shutdown_timer(struct jme_adapter *jme)
1173 {
1174 u32 apmc;
1175
1176 jwrite32f(jme, JME_TMCSR, 0);
1177 jwrite32f(jme, JME_TIMER2, 0);
1178 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1179
1180 apmc = jread32(jme, JME_APMC);
1181 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1182 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1183 wmb();
1184 jwrite32f(jme, JME_APMC, apmc);
1185 }
1186
1187 static void
1188 jme_link_change_tasklet(unsigned long arg)
1189 {
1190 struct jme_adapter *jme = (struct jme_adapter *)arg;
1191 struct net_device *netdev = jme->dev;
1192 int rc;
1193
1194 while (!atomic_dec_and_test(&jme->link_changing)) {
1195 atomic_inc(&jme->link_changing);
1196 netif_info(jme, intr, jme->dev, "Get link change lock failed.\n");
1197 while (atomic_read(&jme->link_changing) != 1)
1198 netif_info(jme, intr, jme->dev, "Waiting link change lock.\n");
1199 }
1200
1201 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1202 goto out;
1203
1204 jme->old_mtu = netdev->mtu;
1205 netif_stop_queue(netdev);
1206 if (jme_pseudo_hotplug_enabled(jme))
1207 jme_stop_shutdown_timer(jme);
1208
1209 jme_stop_pcc_timer(jme);
1210 tasklet_disable(&jme->txclean_task);
1211 tasklet_disable(&jme->rxclean_task);
1212 tasklet_disable(&jme->rxempty_task);
1213
1214 if (netif_carrier_ok(netdev)) {
1215 jme_reset_ghc_speed(jme);
1216 jme_disable_rx_engine(jme);
1217 jme_disable_tx_engine(jme);
1218 jme_reset_mac_processor(jme);
1219 jme_free_rx_resources(jme);
1220 jme_free_tx_resources(jme);
1221
1222 if (test_bit(JME_FLAG_POLL, &jme->flags))
1223 jme_polling_mode(jme);
1224
1225 netif_carrier_off(netdev);
1226 }
1227
1228 jme_check_link(netdev, 0);
1229 if (netif_carrier_ok(netdev)) {
1230 rc = jme_setup_rx_resources(jme);
1231 if (rc) {
1232 jeprintk(jme->pdev, "Allocating resources for RX error"
1233 ", Device STOPPED!\n");
1234 goto out_enable_tasklet;
1235 }
1236
1237 rc = jme_setup_tx_resources(jme);
1238 if (rc) {
1239 jeprintk(jme->pdev, "Allocating resources for TX error"
1240 ", Device STOPPED!\n");
1241 goto err_out_free_rx_resources;
1242 }
1243
1244 jme_enable_rx_engine(jme);
1245 jme_enable_tx_engine(jme);
1246
1247 netif_start_queue(netdev);
1248
1249 if (test_bit(JME_FLAG_POLL, &jme->flags))
1250 jme_interrupt_mode(jme);
1251
1252 jme_start_pcc_timer(jme);
1253 } else if (jme_pseudo_hotplug_enabled(jme)) {
1254 jme_start_shutdown_timer(jme);
1255 }
1256
1257 goto out_enable_tasklet;
1258
1259 err_out_free_rx_resources:
1260 jme_free_rx_resources(jme);
1261 out_enable_tasklet:
1262 tasklet_enable(&jme->txclean_task);
1263 tasklet_hi_enable(&jme->rxclean_task);
1264 tasklet_hi_enable(&jme->rxempty_task);
1265 out:
1266 atomic_inc(&jme->link_changing);
1267 }
1268
1269 static void
1270 jme_rx_clean_tasklet(unsigned long arg)
1271 {
1272 struct jme_adapter *jme = (struct jme_adapter *)arg;
1273 struct dynpcc_info *dpi = &(jme->dpi);
1274
1275 jme_process_receive(jme, jme->rx_ring_size);
1276 ++(dpi->intr_cnt);
1277
1278 }
1279
1280 static int
1281 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1282 {
1283 struct jme_adapter *jme = jme_napi_priv(holder);
1284 int rest;
1285
1286 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1287
1288 while (atomic_read(&jme->rx_empty) > 0) {
1289 atomic_dec(&jme->rx_empty);
1290 ++(NET_STAT(jme).rx_dropped);
1291 jme_restart_rx_engine(jme);
1292 }
1293 atomic_inc(&jme->rx_empty);
1294
1295 if (rest) {
1296 JME_RX_COMPLETE(netdev, holder);
1297 jme_interrupt_mode(jme);
1298 }
1299
1300 JME_NAPI_WEIGHT_SET(budget, rest);
1301 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1302 }
1303
1304 static void
1305 jme_rx_empty_tasklet(unsigned long arg)
1306 {
1307 struct jme_adapter *jme = (struct jme_adapter *)arg;
1308
1309 if (unlikely(atomic_read(&jme->link_changing) != 1))
1310 return;
1311
1312 if (unlikely(!netif_carrier_ok(jme->dev)))
1313 return;
1314
1315 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1316
1317 jme_rx_clean_tasklet(arg);
1318
1319 while (atomic_read(&jme->rx_empty) > 0) {
1320 atomic_dec(&jme->rx_empty);
1321 ++(NET_STAT(jme).rx_dropped);
1322 jme_restart_rx_engine(jme);
1323 }
1324 atomic_inc(&jme->rx_empty);
1325 }
1326
1327 static void
1328 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1329 {
1330 struct jme_ring *txring = &(jme->txring[0]);
1331
1332 smp_wmb();
1333 if (unlikely(netif_queue_stopped(jme->dev) &&
1334 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1335 netif_info(jme, tx_done, jme->dev, "TX Queue Waked.\n");
1336 netif_wake_queue(jme->dev);
1337 }
1338
1339 }
1340
1341 static void
1342 jme_tx_clean_tasklet(unsigned long arg)
1343 {
1344 struct jme_adapter *jme = (struct jme_adapter *)arg;
1345 struct jme_ring *txring = &(jme->txring[0]);
1346 struct txdesc *txdesc = txring->desc;
1347 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1348 int i, j, cnt = 0, max, err, mask;
1349
1350 tx_dbg(jme, "Into txclean.\n");
1351
1352 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1353 goto out;
1354
1355 if (unlikely(atomic_read(&jme->link_changing) != 1))
1356 goto out;
1357
1358 if (unlikely(!netif_carrier_ok(jme->dev)))
1359 goto out;
1360
1361 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1362 mask = jme->tx_ring_mask;
1363
1364 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1365
1366 ctxbi = txbi + i;
1367
1368 if (likely(ctxbi->skb &&
1369 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1370
1371 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1372 i, ctxbi->nr_desc, jiffies);
1373
1374 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1375
1376 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1377 ttxbi = txbi + ((i + j) & (mask));
1378 txdesc[(i + j) & (mask)].dw[0] = 0;
1379
1380 pci_unmap_page(jme->pdev,
1381 ttxbi->mapping,
1382 ttxbi->len,
1383 PCI_DMA_TODEVICE);
1384
1385 ttxbi->mapping = 0;
1386 ttxbi->len = 0;
1387 }
1388
1389 dev_kfree_skb(ctxbi->skb);
1390
1391 cnt += ctxbi->nr_desc;
1392
1393 if (unlikely(err)) {
1394 ++(NET_STAT(jme).tx_carrier_errors);
1395 } else {
1396 ++(NET_STAT(jme).tx_packets);
1397 NET_STAT(jme).tx_bytes += ctxbi->len;
1398 }
1399
1400 ctxbi->skb = NULL;
1401 ctxbi->len = 0;
1402 ctxbi->start_xmit = 0;
1403
1404 } else {
1405 break;
1406 }
1407
1408 i = (i + ctxbi->nr_desc) & mask;
1409
1410 ctxbi->nr_desc = 0;
1411 }
1412
1413 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1414 atomic_set(&txring->next_to_clean, i);
1415 atomic_add(cnt, &txring->nr_free);
1416
1417 jme_wake_queue_if_stopped(jme);
1418
1419 out:
1420 atomic_inc(&jme->tx_cleaning);
1421 }
1422
1423 static void
1424 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1425 {
1426 /*
1427 * Disable interrupt
1428 */
1429 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1430
1431 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1432 /*
1433 * Link change event is critical
1434 * all other events are ignored
1435 */
1436 jwrite32(jme, JME_IEVE, intrstat);
1437 tasklet_schedule(&jme->linkch_task);
1438 goto out_reenable;
1439 }
1440
1441 if (intrstat & INTR_TMINTR) {
1442 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1443 tasklet_schedule(&jme->pcc_task);
1444 }
1445
1446 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1447 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1448 tasklet_schedule(&jme->txclean_task);
1449 }
1450
1451 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1452 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1453 INTR_PCCRX0 |
1454 INTR_RX0EMP)) |
1455 INTR_RX0);
1456 }
1457
1458 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1459 if (intrstat & INTR_RX0EMP)
1460 atomic_inc(&jme->rx_empty);
1461
1462 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1463 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1464 jme_polling_mode(jme);
1465 JME_RX_SCHEDULE(jme);
1466 }
1467 }
1468 } else {
1469 if (intrstat & INTR_RX0EMP) {
1470 atomic_inc(&jme->rx_empty);
1471 tasklet_hi_schedule(&jme->rxempty_task);
1472 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1473 tasklet_hi_schedule(&jme->rxclean_task);
1474 }
1475 }
1476
1477 out_reenable:
1478 /*
1479 * Re-enable interrupt
1480 */
1481 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1482 }
1483
1484 static irqreturn_t
1485 jme_intr(int irq, void *dev_id)
1486 {
1487 struct net_device *netdev = dev_id;
1488 struct jme_adapter *jme = netdev_priv(netdev);
1489 u32 intrstat;
1490
1491 intrstat = jread32(jme, JME_IEVE);
1492
1493 /*
1494 * Check if it's really an interrupt for us
1495 */
1496 if (unlikely((intrstat & INTR_ENABLE) == 0))
1497 return IRQ_NONE;
1498
1499 /*
1500 * Check if the device still exist
1501 */
1502 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1503 return IRQ_NONE;
1504
1505 jme_intr_msi(jme, intrstat);
1506
1507 return IRQ_HANDLED;
1508 }
1509
1510 static irqreturn_t
1511 jme_msi(int irq, void *dev_id)
1512 {
1513 struct net_device *netdev = dev_id;
1514 struct jme_adapter *jme = netdev_priv(netdev);
1515 u32 intrstat;
1516
1517 intrstat = jread32(jme, JME_IEVE);
1518
1519 jme_intr_msi(jme, intrstat);
1520
1521 return IRQ_HANDLED;
1522 }
1523
1524 static void
1525 jme_reset_link(struct jme_adapter *jme)
1526 {
1527 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1528 }
1529
1530 static void
1531 jme_restart_an(struct jme_adapter *jme)
1532 {
1533 u32 bmcr;
1534
1535 spin_lock_bh(&jme->phy_lock);
1536 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1537 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1538 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1539 spin_unlock_bh(&jme->phy_lock);
1540 }
1541
1542 static int
1543 jme_request_irq(struct jme_adapter *jme)
1544 {
1545 int rc;
1546 struct net_device *netdev = jme->dev;
1547 irq_handler_t handler = jme_intr;
1548 int irq_flags = IRQF_SHARED;
1549
1550 if (!pci_enable_msi(jme->pdev)) {
1551 set_bit(JME_FLAG_MSI, &jme->flags);
1552 handler = jme_msi;
1553 irq_flags = 0;
1554 }
1555
1556 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1557 netdev);
1558 if (rc) {
1559 jeprintk(jme->pdev,
1560 "Unable to request %s interrupt (return: %d)\n",
1561 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1562 rc);
1563
1564 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1565 pci_disable_msi(jme->pdev);
1566 clear_bit(JME_FLAG_MSI, &jme->flags);
1567 }
1568 } else {
1569 netdev->irq = jme->pdev->irq;
1570 }
1571
1572 return rc;
1573 }
1574
1575 static void
1576 jme_free_irq(struct jme_adapter *jme)
1577 {
1578 free_irq(jme->pdev->irq, jme->dev);
1579 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1580 pci_disable_msi(jme->pdev);
1581 clear_bit(JME_FLAG_MSI, &jme->flags);
1582 jme->dev->irq = jme->pdev->irq;
1583 }
1584 }
1585
1586 static inline void
1587 jme_phy_on(struct jme_adapter *jme)
1588 {
1589 u32 bmcr;
1590
1591 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1592 bmcr &= ~BMCR_PDOWN;
1593 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1594 }
1595
1596 static int
1597 jme_open(struct net_device *netdev)
1598 {
1599 struct jme_adapter *jme = netdev_priv(netdev);
1600 int rc;
1601
1602 jme_clear_pm(jme);
1603 JME_NAPI_ENABLE(jme);
1604
1605 tasklet_enable(&jme->linkch_task);
1606 tasklet_enable(&jme->txclean_task);
1607 tasklet_hi_enable(&jme->rxclean_task);
1608 tasklet_hi_enable(&jme->rxempty_task);
1609
1610 rc = jme_request_irq(jme);
1611 if (rc)
1612 goto err_out;
1613
1614 jme_start_irq(jme);
1615
1616 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1617 jme_phy_on(jme);
1618 jme_set_settings(netdev, &jme->old_ecmd);
1619 } else {
1620 jme_reset_phy_processor(jme);
1621 }
1622
1623 jme_reset_link(jme);
1624
1625 return 0;
1626
1627 err_out:
1628 netif_stop_queue(netdev);
1629 netif_carrier_off(netdev);
1630 return rc;
1631 }
1632
1633 #ifdef CONFIG_PM
1634 static void
1635 jme_set_100m_half(struct jme_adapter *jme)
1636 {
1637 u32 bmcr, tmp;
1638
1639 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1640 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1641 BMCR_SPEED1000 | BMCR_FULLDPLX);
1642 tmp |= BMCR_SPEED100;
1643
1644 if (bmcr != tmp)
1645 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1646
1647 if (jme->fpgaver)
1648 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1649 else
1650 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1651 }
1652
1653 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1654 static void
1655 jme_wait_link(struct jme_adapter *jme)
1656 {
1657 u32 phylink, to = JME_WAIT_LINK_TIME;
1658
1659 mdelay(1000);
1660 phylink = jme_linkstat_from_phy(jme);
1661 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1662 mdelay(10);
1663 phylink = jme_linkstat_from_phy(jme);
1664 }
1665 }
1666 #endif
1667
1668 static inline void
1669 jme_phy_off(struct jme_adapter *jme)
1670 {
1671 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1672 }
1673
1674 static int
1675 jme_close(struct net_device *netdev)
1676 {
1677 struct jme_adapter *jme = netdev_priv(netdev);
1678
1679 netif_stop_queue(netdev);
1680 netif_carrier_off(netdev);
1681
1682 jme_stop_irq(jme);
1683 jme_free_irq(jme);
1684
1685 JME_NAPI_DISABLE(jme);
1686
1687 tasklet_disable(&jme->linkch_task);
1688 tasklet_disable(&jme->txclean_task);
1689 tasklet_disable(&jme->rxclean_task);
1690 tasklet_disable(&jme->rxempty_task);
1691
1692 jme_reset_ghc_speed(jme);
1693 jme_disable_rx_engine(jme);
1694 jme_disable_tx_engine(jme);
1695 jme_reset_mac_processor(jme);
1696 jme_free_rx_resources(jme);
1697 jme_free_tx_resources(jme);
1698 jme->phylink = 0;
1699 jme_phy_off(jme);
1700
1701 return 0;
1702 }
1703
1704 static int
1705 jme_alloc_txdesc(struct jme_adapter *jme,
1706 struct sk_buff *skb)
1707 {
1708 struct jme_ring *txring = &(jme->txring[0]);
1709 int idx, nr_alloc, mask = jme->tx_ring_mask;
1710
1711 idx = txring->next_to_use;
1712 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1713
1714 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1715 return -1;
1716
1717 atomic_sub(nr_alloc, &txring->nr_free);
1718
1719 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1720
1721 return idx;
1722 }
1723
1724 static void
1725 jme_fill_tx_map(struct pci_dev *pdev,
1726 struct txdesc *txdesc,
1727 struct jme_buffer_info *txbi,
1728 struct page *page,
1729 u32 page_offset,
1730 u32 len,
1731 u8 hidma)
1732 {
1733 dma_addr_t dmaaddr;
1734
1735 dmaaddr = pci_map_page(pdev,
1736 page,
1737 page_offset,
1738 len,
1739 PCI_DMA_TODEVICE);
1740
1741 pci_dma_sync_single_for_device(pdev,
1742 dmaaddr,
1743 len,
1744 PCI_DMA_TODEVICE);
1745
1746 txdesc->dw[0] = 0;
1747 txdesc->dw[1] = 0;
1748 txdesc->desc2.flags = TXFLAG_OWN;
1749 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1750 txdesc->desc2.datalen = cpu_to_le16(len);
1751 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1752 txdesc->desc2.bufaddrl = cpu_to_le32(
1753 (__u64)dmaaddr & 0xFFFFFFFFUL);
1754
1755 txbi->mapping = dmaaddr;
1756 txbi->len = len;
1757 }
1758
1759 static void
1760 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1761 {
1762 struct jme_ring *txring = &(jme->txring[0]);
1763 struct txdesc *txdesc = txring->desc, *ctxdesc;
1764 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1765 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1766 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1767 int mask = jme->tx_ring_mask;
1768 struct skb_frag_struct *frag;
1769 u32 len;
1770
1771 for (i = 0 ; i < nr_frags ; ++i) {
1772 frag = &skb_shinfo(skb)->frags[i];
1773 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1774 ctxbi = txbi + ((idx + i + 2) & (mask));
1775
1776 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1777 frag->page_offset, frag->size, hidma);
1778 }
1779
1780 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1781 ctxdesc = txdesc + ((idx + 1) & (mask));
1782 ctxbi = txbi + ((idx + 1) & (mask));
1783 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1784 offset_in_page(skb->data), len, hidma);
1785
1786 }
1787
1788 static int
1789 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1790 {
1791 if (unlikely(skb_shinfo(skb)->gso_size &&
1792 skb_header_cloned(skb) &&
1793 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1794 dev_kfree_skb(skb);
1795 return -1;
1796 }
1797
1798 return 0;
1799 }
1800
1801 static int
1802 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1803 {
1804 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1805 if (*mss) {
1806 *flags |= TXFLAG_LSEN;
1807
1808 if (skb->protocol == htons(ETH_P_IP)) {
1809 struct iphdr *iph = ip_hdr(skb);
1810
1811 iph->check = 0;
1812 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1813 iph->daddr, 0,
1814 IPPROTO_TCP,
1815 0);
1816 } else {
1817 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1818
1819 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1820 &ip6h->daddr, 0,
1821 IPPROTO_TCP,
1822 0);
1823 }
1824
1825 return 0;
1826 }
1827
1828 return 1;
1829 }
1830
1831 static void
1832 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1833 {
1834 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1835 u8 ip_proto;
1836
1837 switch (skb->protocol) {
1838 case htons(ETH_P_IP):
1839 ip_proto = ip_hdr(skb)->protocol;
1840 break;
1841 case htons(ETH_P_IPV6):
1842 ip_proto = ipv6_hdr(skb)->nexthdr;
1843 break;
1844 default:
1845 ip_proto = 0;
1846 break;
1847 }
1848
1849 switch (ip_proto) {
1850 case IPPROTO_TCP:
1851 *flags |= TXFLAG_TCPCS;
1852 break;
1853 case IPPROTO_UDP:
1854 *flags |= TXFLAG_UDPCS;
1855 break;
1856 default:
1857 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol.\n");
1858 break;
1859 }
1860 }
1861 }
1862
1863 static inline void
1864 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1865 {
1866 if (vlan_tx_tag_present(skb)) {
1867 *flags |= TXFLAG_TAGON;
1868 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1869 }
1870 }
1871
1872 static int
1873 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1874 {
1875 struct jme_ring *txring = &(jme->txring[0]);
1876 struct txdesc *txdesc;
1877 struct jme_buffer_info *txbi;
1878 u8 flags;
1879
1880 txdesc = (struct txdesc *)txring->desc + idx;
1881 txbi = txring->bufinf + idx;
1882
1883 txdesc->dw[0] = 0;
1884 txdesc->dw[1] = 0;
1885 txdesc->dw[2] = 0;
1886 txdesc->dw[3] = 0;
1887 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1888 /*
1889 * Set OWN bit at final.
1890 * When kernel transmit faster than NIC.
1891 * And NIC trying to send this descriptor before we tell
1892 * it to start sending this TX queue.
1893 * Other fields are already filled correctly.
1894 */
1895 wmb();
1896 flags = TXFLAG_OWN | TXFLAG_INT;
1897 /*
1898 * Set checksum flags while not tso
1899 */
1900 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1901 jme_tx_csum(jme, skb, &flags);
1902 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1903 jme_map_tx_skb(jme, skb, idx);
1904 txdesc->desc1.flags = flags;
1905 /*
1906 * Set tx buffer info after telling NIC to send
1907 * For better tx_clean timing
1908 */
1909 wmb();
1910 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1911 txbi->skb = skb;
1912 txbi->len = skb->len;
1913 txbi->start_xmit = jiffies;
1914 if (!txbi->start_xmit)
1915 txbi->start_xmit = (0UL-1);
1916
1917 return 0;
1918 }
1919
1920 static void
1921 jme_stop_queue_if_full(struct jme_adapter *jme)
1922 {
1923 struct jme_ring *txring = &(jme->txring[0]);
1924 struct jme_buffer_info *txbi = txring->bufinf;
1925 int idx = atomic_read(&txring->next_to_clean);
1926
1927 txbi += idx;
1928
1929 smp_wmb();
1930 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1931 netif_stop_queue(jme->dev);
1932 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused.\n");
1933 smp_wmb();
1934 if (atomic_read(&txring->nr_free)
1935 >= (jme->tx_wake_threshold)) {
1936 netif_wake_queue(jme->dev);
1937 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked.\n");
1938 }
1939 }
1940
1941 if (unlikely(txbi->start_xmit &&
1942 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1943 txbi->skb)) {
1944 netif_stop_queue(jme->dev);
1945 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1946 }
1947 }
1948
1949 /*
1950 * This function is already protected by netif_tx_lock()
1951 */
1952
1953 static netdev_tx_t
1954 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1955 {
1956 struct jme_adapter *jme = netdev_priv(netdev);
1957 int idx;
1958
1959 if (unlikely(jme_expand_header(jme, skb))) {
1960 ++(NET_STAT(jme).tx_dropped);
1961 return NETDEV_TX_OK;
1962 }
1963
1964 idx = jme_alloc_txdesc(jme, skb);
1965
1966 if (unlikely(idx < 0)) {
1967 netif_stop_queue(netdev);
1968 netif_err(jme, tx_err, jme->dev, "BUG! Tx ring full when queue awake!\n");
1969
1970 return NETDEV_TX_BUSY;
1971 }
1972
1973 jme_fill_tx_desc(jme, skb, idx);
1974
1975 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1976 TXCS_SELECT_QUEUE0 |
1977 TXCS_QUEUE0S |
1978 TXCS_ENABLE);
1979
1980 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1981 skb_shinfo(skb)->nr_frags + 2,
1982 jiffies);
1983 jme_stop_queue_if_full(jme);
1984
1985 return NETDEV_TX_OK;
1986 }
1987
1988 static int
1989 jme_set_macaddr(struct net_device *netdev, void *p)
1990 {
1991 struct jme_adapter *jme = netdev_priv(netdev);
1992 struct sockaddr *addr = p;
1993 u32 val;
1994
1995 if (netif_running(netdev))
1996 return -EBUSY;
1997
1998 spin_lock_bh(&jme->macaddr_lock);
1999 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2000
2001 val = (addr->sa_data[3] & 0xff) << 24 |
2002 (addr->sa_data[2] & 0xff) << 16 |
2003 (addr->sa_data[1] & 0xff) << 8 |
2004 (addr->sa_data[0] & 0xff);
2005 jwrite32(jme, JME_RXUMA_LO, val);
2006 val = (addr->sa_data[5] & 0xff) << 8 |
2007 (addr->sa_data[4] & 0xff);
2008 jwrite32(jme, JME_RXUMA_HI, val);
2009 spin_unlock_bh(&jme->macaddr_lock);
2010
2011 return 0;
2012 }
2013
2014 static void
2015 jme_set_multi(struct net_device *netdev)
2016 {
2017 struct jme_adapter *jme = netdev_priv(netdev);
2018 u32 mc_hash[2] = {};
2019
2020 spin_lock_bh(&jme->rxmcs_lock);
2021
2022 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2023
2024 if (netdev->flags & IFF_PROMISC) {
2025 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2026 } else if (netdev->flags & IFF_ALLMULTI) {
2027 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2028 } else if (netdev->flags & IFF_MULTICAST) {
2029 struct netdev_hw_addr *ha;
2030 int bit_nr;
2031
2032 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2033 netdev_for_each_mc_addr(ha, netdev) {
2034 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2035 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2036 }
2037
2038 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2039 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2040 }
2041
2042 wmb();
2043 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2044
2045 spin_unlock_bh(&jme->rxmcs_lock);
2046 }
2047
2048 static int
2049 jme_change_mtu(struct net_device *netdev, int new_mtu)
2050 {
2051 struct jme_adapter *jme = netdev_priv(netdev);
2052
2053 if (new_mtu == jme->old_mtu)
2054 return 0;
2055
2056 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2057 ((new_mtu) < IPV6_MIN_MTU))
2058 return -EINVAL;
2059
2060 if (new_mtu > 4000) {
2061 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2062 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2063 jme_restart_rx_engine(jme);
2064 } else {
2065 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2066 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2067 jme_restart_rx_engine(jme);
2068 }
2069
2070 if (new_mtu > 1900) {
2071 netdev->features &= ~(NETIF_F_HW_CSUM |
2072 NETIF_F_TSO |
2073 NETIF_F_TSO6);
2074 } else {
2075 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2076 netdev->features |= NETIF_F_HW_CSUM;
2077 if (test_bit(JME_FLAG_TSO, &jme->flags))
2078 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2079 }
2080
2081 netdev->mtu = new_mtu;
2082 jme_reset_link(jme);
2083
2084 return 0;
2085 }
2086
2087 static void
2088 jme_tx_timeout(struct net_device *netdev)
2089 {
2090 struct jme_adapter *jme = netdev_priv(netdev);
2091
2092 jme->phylink = 0;
2093 jme_reset_phy_processor(jme);
2094 if (test_bit(JME_FLAG_SSET, &jme->flags))
2095 jme_set_settings(netdev, &jme->old_ecmd);
2096
2097 /*
2098 * Force to Reset the link again
2099 */
2100 jme_reset_link(jme);
2101 }
2102
2103 static inline void jme_pause_rx(struct jme_adapter *jme)
2104 {
2105 atomic_dec(&jme->link_changing);
2106
2107 jme_set_rx_pcc(jme, PCC_OFF);
2108 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2109 JME_NAPI_DISABLE(jme);
2110 } else {
2111 tasklet_disable(&jme->rxclean_task);
2112 tasklet_disable(&jme->rxempty_task);
2113 }
2114 }
2115
2116 static inline void jme_resume_rx(struct jme_adapter *jme)
2117 {
2118 struct dynpcc_info *dpi = &(jme->dpi);
2119
2120 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2121 JME_NAPI_ENABLE(jme);
2122 } else {
2123 tasklet_hi_enable(&jme->rxclean_task);
2124 tasklet_hi_enable(&jme->rxempty_task);
2125 }
2126 dpi->cur = PCC_P1;
2127 dpi->attempt = PCC_P1;
2128 dpi->cnt = 0;
2129 jme_set_rx_pcc(jme, PCC_P1);
2130
2131 atomic_inc(&jme->link_changing);
2132 }
2133
2134 static void
2135 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2136 {
2137 struct jme_adapter *jme = netdev_priv(netdev);
2138
2139 jme_pause_rx(jme);
2140 jme->vlgrp = grp;
2141 jme_resume_rx(jme);
2142 }
2143
2144 static void
2145 jme_get_drvinfo(struct net_device *netdev,
2146 struct ethtool_drvinfo *info)
2147 {
2148 struct jme_adapter *jme = netdev_priv(netdev);
2149
2150 strcpy(info->driver, DRV_NAME);
2151 strcpy(info->version, DRV_VERSION);
2152 strcpy(info->bus_info, pci_name(jme->pdev));
2153 }
2154
2155 static int
2156 jme_get_regs_len(struct net_device *netdev)
2157 {
2158 return JME_REG_LEN;
2159 }
2160
2161 static void
2162 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2163 {
2164 int i;
2165
2166 for (i = 0 ; i < len ; i += 4)
2167 p[i >> 2] = jread32(jme, reg + i);
2168 }
2169
2170 static void
2171 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2172 {
2173 int i;
2174 u16 *p16 = (u16 *)p;
2175
2176 for (i = 0 ; i < reg_nr ; ++i)
2177 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2178 }
2179
2180 static void
2181 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2182 {
2183 struct jme_adapter *jme = netdev_priv(netdev);
2184 u32 *p32 = (u32 *)p;
2185
2186 memset(p, 0xFF, JME_REG_LEN);
2187
2188 regs->version = 1;
2189 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2190
2191 p32 += 0x100 >> 2;
2192 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2193
2194 p32 += 0x100 >> 2;
2195 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2196
2197 p32 += 0x100 >> 2;
2198 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2199
2200 p32 += 0x100 >> 2;
2201 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2202 }
2203
2204 static int
2205 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2206 {
2207 struct jme_adapter *jme = netdev_priv(netdev);
2208
2209 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2210 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2211
2212 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2213 ecmd->use_adaptive_rx_coalesce = false;
2214 ecmd->rx_coalesce_usecs = 0;
2215 ecmd->rx_max_coalesced_frames = 0;
2216 return 0;
2217 }
2218
2219 ecmd->use_adaptive_rx_coalesce = true;
2220
2221 switch (jme->dpi.cur) {
2222 case PCC_P1:
2223 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2224 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2225 break;
2226 case PCC_P2:
2227 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2228 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2229 break;
2230 case PCC_P3:
2231 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2232 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2233 break;
2234 default:
2235 break;
2236 }
2237
2238 return 0;
2239 }
2240
2241 static int
2242 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2243 {
2244 struct jme_adapter *jme = netdev_priv(netdev);
2245 struct dynpcc_info *dpi = &(jme->dpi);
2246
2247 if (netif_running(netdev))
2248 return -EBUSY;
2249
2250 if (ecmd->use_adaptive_rx_coalesce &&
2251 test_bit(JME_FLAG_POLL, &jme->flags)) {
2252 clear_bit(JME_FLAG_POLL, &jme->flags);
2253 jme->jme_rx = netif_rx;
2254 jme->jme_vlan_rx = vlan_hwaccel_rx;
2255 dpi->cur = PCC_P1;
2256 dpi->attempt = PCC_P1;
2257 dpi->cnt = 0;
2258 jme_set_rx_pcc(jme, PCC_P1);
2259 jme_interrupt_mode(jme);
2260 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2261 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2262 set_bit(JME_FLAG_POLL, &jme->flags);
2263 jme->jme_rx = netif_receive_skb;
2264 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2265 jme_interrupt_mode(jme);
2266 }
2267
2268 return 0;
2269 }
2270
2271 static void
2272 jme_get_pauseparam(struct net_device *netdev,
2273 struct ethtool_pauseparam *ecmd)
2274 {
2275 struct jme_adapter *jme = netdev_priv(netdev);
2276 u32 val;
2277
2278 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2279 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2280
2281 spin_lock_bh(&jme->phy_lock);
2282 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2283 spin_unlock_bh(&jme->phy_lock);
2284
2285 ecmd->autoneg =
2286 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2287 }
2288
2289 static int
2290 jme_set_pauseparam(struct net_device *netdev,
2291 struct ethtool_pauseparam *ecmd)
2292 {
2293 struct jme_adapter *jme = netdev_priv(netdev);
2294 u32 val;
2295
2296 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2297 (ecmd->tx_pause != 0)) {
2298
2299 if (ecmd->tx_pause)
2300 jme->reg_txpfc |= TXPFC_PF_EN;
2301 else
2302 jme->reg_txpfc &= ~TXPFC_PF_EN;
2303
2304 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2305 }
2306
2307 spin_lock_bh(&jme->rxmcs_lock);
2308 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2309 (ecmd->rx_pause != 0)) {
2310
2311 if (ecmd->rx_pause)
2312 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2313 else
2314 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2315
2316 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2317 }
2318 spin_unlock_bh(&jme->rxmcs_lock);
2319
2320 spin_lock_bh(&jme->phy_lock);
2321 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2322 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2323 (ecmd->autoneg != 0)) {
2324
2325 if (ecmd->autoneg)
2326 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2327 else
2328 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2329
2330 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2331 MII_ADVERTISE, val);
2332 }
2333 spin_unlock_bh(&jme->phy_lock);
2334
2335 return 0;
2336 }
2337
2338 static void
2339 jme_get_wol(struct net_device *netdev,
2340 struct ethtool_wolinfo *wol)
2341 {
2342 struct jme_adapter *jme = netdev_priv(netdev);
2343
2344 wol->supported = WAKE_MAGIC | WAKE_PHY;
2345
2346 wol->wolopts = 0;
2347
2348 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2349 wol->wolopts |= WAKE_PHY;
2350
2351 if (jme->reg_pmcs & PMCS_MFEN)
2352 wol->wolopts |= WAKE_MAGIC;
2353
2354 }
2355
2356 static int
2357 jme_set_wol(struct net_device *netdev,
2358 struct ethtool_wolinfo *wol)
2359 {
2360 struct jme_adapter *jme = netdev_priv(netdev);
2361
2362 if (wol->wolopts & (WAKE_MAGICSECURE |
2363 WAKE_UCAST |
2364 WAKE_MCAST |
2365 WAKE_BCAST |
2366 WAKE_ARP))
2367 return -EOPNOTSUPP;
2368
2369 jme->reg_pmcs = 0;
2370
2371 if (wol->wolopts & WAKE_PHY)
2372 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2373
2374 if (wol->wolopts & WAKE_MAGIC)
2375 jme->reg_pmcs |= PMCS_MFEN;
2376
2377 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2378
2379 return 0;
2380 }
2381
2382 static int
2383 jme_get_settings(struct net_device *netdev,
2384 struct ethtool_cmd *ecmd)
2385 {
2386 struct jme_adapter *jme = netdev_priv(netdev);
2387 int rc;
2388
2389 spin_lock_bh(&jme->phy_lock);
2390 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2391 spin_unlock_bh(&jme->phy_lock);
2392 return rc;
2393 }
2394
2395 static int
2396 jme_set_settings(struct net_device *netdev,
2397 struct ethtool_cmd *ecmd)
2398 {
2399 struct jme_adapter *jme = netdev_priv(netdev);
2400 int rc, fdc = 0;
2401
2402 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2403 return -EINVAL;
2404
2405 if (jme->mii_if.force_media &&
2406 ecmd->autoneg != AUTONEG_ENABLE &&
2407 (jme->mii_if.full_duplex != ecmd->duplex))
2408 fdc = 1;
2409
2410 spin_lock_bh(&jme->phy_lock);
2411 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2412 spin_unlock_bh(&jme->phy_lock);
2413
2414 if (!rc && fdc)
2415 jme_reset_link(jme);
2416
2417 if (!rc) {
2418 set_bit(JME_FLAG_SSET, &jme->flags);
2419 jme->old_ecmd = *ecmd;
2420 }
2421
2422 return rc;
2423 }
2424
2425 static u32
2426 jme_get_link(struct net_device *netdev)
2427 {
2428 struct jme_adapter *jme = netdev_priv(netdev);
2429 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2430 }
2431
2432 static u32
2433 jme_get_msglevel(struct net_device *netdev)
2434 {
2435 struct jme_adapter *jme = netdev_priv(netdev);
2436 return jme->msg_enable;
2437 }
2438
2439 static void
2440 jme_set_msglevel(struct net_device *netdev, u32 value)
2441 {
2442 struct jme_adapter *jme = netdev_priv(netdev);
2443 jme->msg_enable = value;
2444 }
2445
2446 static u32
2447 jme_get_rx_csum(struct net_device *netdev)
2448 {
2449 struct jme_adapter *jme = netdev_priv(netdev);
2450 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2451 }
2452
2453 static int
2454 jme_set_rx_csum(struct net_device *netdev, u32 on)
2455 {
2456 struct jme_adapter *jme = netdev_priv(netdev);
2457
2458 spin_lock_bh(&jme->rxmcs_lock);
2459 if (on)
2460 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2461 else
2462 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2463 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2464 spin_unlock_bh(&jme->rxmcs_lock);
2465
2466 return 0;
2467 }
2468
2469 static int
2470 jme_set_tx_csum(struct net_device *netdev, u32 on)
2471 {
2472 struct jme_adapter *jme = netdev_priv(netdev);
2473
2474 if (on) {
2475 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2476 if (netdev->mtu <= 1900)
2477 netdev->features |= NETIF_F_HW_CSUM;
2478 } else {
2479 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2480 netdev->features &= ~NETIF_F_HW_CSUM;
2481 }
2482
2483 return 0;
2484 }
2485
2486 static int
2487 jme_set_tso(struct net_device *netdev, u32 on)
2488 {
2489 struct jme_adapter *jme = netdev_priv(netdev);
2490
2491 if (on) {
2492 set_bit(JME_FLAG_TSO, &jme->flags);
2493 if (netdev->mtu <= 1900)
2494 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2495 } else {
2496 clear_bit(JME_FLAG_TSO, &jme->flags);
2497 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2498 }
2499
2500 return 0;
2501 }
2502
2503 static int
2504 jme_nway_reset(struct net_device *netdev)
2505 {
2506 struct jme_adapter *jme = netdev_priv(netdev);
2507 jme_restart_an(jme);
2508 return 0;
2509 }
2510
2511 static u8
2512 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2513 {
2514 u32 val;
2515 int to;
2516
2517 val = jread32(jme, JME_SMBCSR);
2518 to = JME_SMB_BUSY_TIMEOUT;
2519 while ((val & SMBCSR_BUSY) && --to) {
2520 msleep(1);
2521 val = jread32(jme, JME_SMBCSR);
2522 }
2523 if (!to) {
2524 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2525 return 0xFF;
2526 }
2527
2528 jwrite32(jme, JME_SMBINTF,
2529 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2530 SMBINTF_HWRWN_READ |
2531 SMBINTF_HWCMD);
2532
2533 val = jread32(jme, JME_SMBINTF);
2534 to = JME_SMB_BUSY_TIMEOUT;
2535 while ((val & SMBINTF_HWCMD) && --to) {
2536 msleep(1);
2537 val = jread32(jme, JME_SMBINTF);
2538 }
2539 if (!to) {
2540 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2541 return 0xFF;
2542 }
2543
2544 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2545 }
2546
2547 static void
2548 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2549 {
2550 u32 val;
2551 int to;
2552
2553 val = jread32(jme, JME_SMBCSR);
2554 to = JME_SMB_BUSY_TIMEOUT;
2555 while ((val & SMBCSR_BUSY) && --to) {
2556 msleep(1);
2557 val = jread32(jme, JME_SMBCSR);
2558 }
2559 if (!to) {
2560 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2561 return;
2562 }
2563
2564 jwrite32(jme, JME_SMBINTF,
2565 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2566 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2567 SMBINTF_HWRWN_WRITE |
2568 SMBINTF_HWCMD);
2569
2570 val = jread32(jme, JME_SMBINTF);
2571 to = JME_SMB_BUSY_TIMEOUT;
2572 while ((val & SMBINTF_HWCMD) && --to) {
2573 msleep(1);
2574 val = jread32(jme, JME_SMBINTF);
2575 }
2576 if (!to) {
2577 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2578 return;
2579 }
2580
2581 mdelay(2);
2582 }
2583
2584 static int
2585 jme_get_eeprom_len(struct net_device *netdev)
2586 {
2587 struct jme_adapter *jme = netdev_priv(netdev);
2588 u32 val;
2589 val = jread32(jme, JME_SMBCSR);
2590 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2591 }
2592
2593 static int
2594 jme_get_eeprom(struct net_device *netdev,
2595 struct ethtool_eeprom *eeprom, u8 *data)
2596 {
2597 struct jme_adapter *jme = netdev_priv(netdev);
2598 int i, offset = eeprom->offset, len = eeprom->len;
2599
2600 /*
2601 * ethtool will check the boundary for us
2602 */
2603 eeprom->magic = JME_EEPROM_MAGIC;
2604 for (i = 0 ; i < len ; ++i)
2605 data[i] = jme_smb_read(jme, i + offset);
2606
2607 return 0;
2608 }
2609
2610 static int
2611 jme_set_eeprom(struct net_device *netdev,
2612 struct ethtool_eeprom *eeprom, u8 *data)
2613 {
2614 struct jme_adapter *jme = netdev_priv(netdev);
2615 int i, offset = eeprom->offset, len = eeprom->len;
2616
2617 if (eeprom->magic != JME_EEPROM_MAGIC)
2618 return -EINVAL;
2619
2620 /*
2621 * ethtool will check the boundary for us
2622 */
2623 for (i = 0 ; i < len ; ++i)
2624 jme_smb_write(jme, i + offset, data[i]);
2625
2626 return 0;
2627 }
2628
2629 static const struct ethtool_ops jme_ethtool_ops = {
2630 .get_drvinfo = jme_get_drvinfo,
2631 .get_regs_len = jme_get_regs_len,
2632 .get_regs = jme_get_regs,
2633 .get_coalesce = jme_get_coalesce,
2634 .set_coalesce = jme_set_coalesce,
2635 .get_pauseparam = jme_get_pauseparam,
2636 .set_pauseparam = jme_set_pauseparam,
2637 .get_wol = jme_get_wol,
2638 .set_wol = jme_set_wol,
2639 .get_settings = jme_get_settings,
2640 .set_settings = jme_set_settings,
2641 .get_link = jme_get_link,
2642 .get_msglevel = jme_get_msglevel,
2643 .set_msglevel = jme_set_msglevel,
2644 .get_rx_csum = jme_get_rx_csum,
2645 .set_rx_csum = jme_set_rx_csum,
2646 .set_tx_csum = jme_set_tx_csum,
2647 .set_tso = jme_set_tso,
2648 .set_sg = ethtool_op_set_sg,
2649 .nway_reset = jme_nway_reset,
2650 .get_eeprom_len = jme_get_eeprom_len,
2651 .get_eeprom = jme_get_eeprom,
2652 .set_eeprom = jme_set_eeprom,
2653 };
2654
2655 static int
2656 jme_pci_dma64(struct pci_dev *pdev)
2657 {
2658 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2659 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2660 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2661 return 1;
2662
2663 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2664 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2665 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2666 return 1;
2667
2668 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2669 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2670 return 0;
2671
2672 return -1;
2673 }
2674
2675 static inline void
2676 jme_phy_init(struct jme_adapter *jme)
2677 {
2678 u16 reg26;
2679
2680 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2681 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2682 }
2683
2684 static inline void
2685 jme_check_hw_ver(struct jme_adapter *jme)
2686 {
2687 u32 chipmode;
2688
2689 chipmode = jread32(jme, JME_CHIPMODE);
2690
2691 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2692 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2693 }
2694
2695 static const struct net_device_ops jme_netdev_ops = {
2696 .ndo_open = jme_open,
2697 .ndo_stop = jme_close,
2698 .ndo_validate_addr = eth_validate_addr,
2699 .ndo_start_xmit = jme_start_xmit,
2700 .ndo_set_mac_address = jme_set_macaddr,
2701 .ndo_set_multicast_list = jme_set_multi,
2702 .ndo_change_mtu = jme_change_mtu,
2703 .ndo_tx_timeout = jme_tx_timeout,
2704 .ndo_vlan_rx_register = jme_vlan_rx_register,
2705 };
2706
2707 static int __devinit
2708 jme_init_one(struct pci_dev *pdev,
2709 const struct pci_device_id *ent)
2710 {
2711 int rc = 0, using_dac, i;
2712 struct net_device *netdev;
2713 struct jme_adapter *jme;
2714 u16 bmcr, bmsr;
2715 u32 apmc;
2716
2717 /*
2718 * set up PCI device basics
2719 */
2720 rc = pci_enable_device(pdev);
2721 if (rc) {
2722 jeprintk(pdev, "Cannot enable PCI device.\n");
2723 goto err_out;
2724 }
2725
2726 using_dac = jme_pci_dma64(pdev);
2727 if (using_dac < 0) {
2728 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2729 rc = -EIO;
2730 goto err_out_disable_pdev;
2731 }
2732
2733 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2734 jeprintk(pdev, "No PCI resource region found.\n");
2735 rc = -ENOMEM;
2736 goto err_out_disable_pdev;
2737 }
2738
2739 rc = pci_request_regions(pdev, DRV_NAME);
2740 if (rc) {
2741 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2742 goto err_out_disable_pdev;
2743 }
2744
2745 pci_set_master(pdev);
2746
2747 /*
2748 * alloc and init net device
2749 */
2750 netdev = alloc_etherdev(sizeof(*jme));
2751 if (!netdev) {
2752 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2753 rc = -ENOMEM;
2754 goto err_out_release_regions;
2755 }
2756 netdev->netdev_ops = &jme_netdev_ops;
2757 netdev->ethtool_ops = &jme_ethtool_ops;
2758 netdev->watchdog_timeo = TX_TIMEOUT;
2759 netdev->features = NETIF_F_HW_CSUM |
2760 NETIF_F_SG |
2761 NETIF_F_TSO |
2762 NETIF_F_TSO6 |
2763 NETIF_F_HW_VLAN_TX |
2764 NETIF_F_HW_VLAN_RX;
2765 if (using_dac)
2766 netdev->features |= NETIF_F_HIGHDMA;
2767
2768 SET_NETDEV_DEV(netdev, &pdev->dev);
2769 pci_set_drvdata(pdev, netdev);
2770
2771 /*
2772 * init adapter info
2773 */
2774 jme = netdev_priv(netdev);
2775 jme->pdev = pdev;
2776 jme->dev = netdev;
2777 jme->jme_rx = netif_rx;
2778 jme->jme_vlan_rx = vlan_hwaccel_rx;
2779 jme->old_mtu = netdev->mtu = 1500;
2780 jme->phylink = 0;
2781 jme->tx_ring_size = 1 << 10;
2782 jme->tx_ring_mask = jme->tx_ring_size - 1;
2783 jme->tx_wake_threshold = 1 << 9;
2784 jme->rx_ring_size = 1 << 9;
2785 jme->rx_ring_mask = jme->rx_ring_size - 1;
2786 jme->msg_enable = JME_DEF_MSG_ENABLE;
2787 jme->regs = ioremap(pci_resource_start(pdev, 0),
2788 pci_resource_len(pdev, 0));
2789 if (!(jme->regs)) {
2790 jeprintk(pdev, "Mapping PCI resource region error.\n");
2791 rc = -ENOMEM;
2792 goto err_out_free_netdev;
2793 }
2794
2795 if (no_pseudohp) {
2796 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2797 jwrite32(jme, JME_APMC, apmc);
2798 } else if (force_pseudohp) {
2799 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2800 jwrite32(jme, JME_APMC, apmc);
2801 }
2802
2803 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2804
2805 spin_lock_init(&jme->phy_lock);
2806 spin_lock_init(&jme->macaddr_lock);
2807 spin_lock_init(&jme->rxmcs_lock);
2808
2809 atomic_set(&jme->link_changing, 1);
2810 atomic_set(&jme->rx_cleaning, 1);
2811 atomic_set(&jme->tx_cleaning, 1);
2812 atomic_set(&jme->rx_empty, 1);
2813
2814 tasklet_init(&jme->pcc_task,
2815 jme_pcc_tasklet,
2816 (unsigned long) jme);
2817 tasklet_init(&jme->linkch_task,
2818 jme_link_change_tasklet,
2819 (unsigned long) jme);
2820 tasklet_init(&jme->txclean_task,
2821 jme_tx_clean_tasklet,
2822 (unsigned long) jme);
2823 tasklet_init(&jme->rxclean_task,
2824 jme_rx_clean_tasklet,
2825 (unsigned long) jme);
2826 tasklet_init(&jme->rxempty_task,
2827 jme_rx_empty_tasklet,
2828 (unsigned long) jme);
2829 tasklet_disable_nosync(&jme->linkch_task);
2830 tasklet_disable_nosync(&jme->txclean_task);
2831 tasklet_disable_nosync(&jme->rxclean_task);
2832 tasklet_disable_nosync(&jme->rxempty_task);
2833 jme->dpi.cur = PCC_P1;
2834
2835 jme->reg_ghc = 0;
2836 jme->reg_rxcs = RXCS_DEFAULT;
2837 jme->reg_rxmcs = RXMCS_DEFAULT;
2838 jme->reg_txpfc = 0;
2839 jme->reg_pmcs = PMCS_MFEN;
2840 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2841 set_bit(JME_FLAG_TSO, &jme->flags);
2842
2843 /*
2844 * Get Max Read Req Size from PCI Config Space
2845 */
2846 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2847 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2848 switch (jme->mrrs) {
2849 case MRRS_128B:
2850 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2851 break;
2852 case MRRS_256B:
2853 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2854 break;
2855 default:
2856 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2857 break;
2858 }
2859
2860 /*
2861 * Must check before reset_mac_processor
2862 */
2863 jme_check_hw_ver(jme);
2864 jme->mii_if.dev = netdev;
2865 if (jme->fpgaver) {
2866 jme->mii_if.phy_id = 0;
2867 for (i = 1 ; i < 32 ; ++i) {
2868 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2869 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2870 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2871 jme->mii_if.phy_id = i;
2872 break;
2873 }
2874 }
2875
2876 if (!jme->mii_if.phy_id) {
2877 rc = -EIO;
2878 jeprintk(pdev, "Can not find phy_id.\n");
2879 goto err_out_unmap;
2880 }
2881
2882 jme->reg_ghc |= GHC_LINK_POLL;
2883 } else {
2884 jme->mii_if.phy_id = 1;
2885 }
2886 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2887 jme->mii_if.supports_gmii = true;
2888 else
2889 jme->mii_if.supports_gmii = false;
2890 jme->mii_if.mdio_read = jme_mdio_read;
2891 jme->mii_if.mdio_write = jme_mdio_write;
2892
2893 jme_clear_pm(jme);
2894 jme_set_phyfifoa(jme);
2895 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2896 if (!jme->fpgaver)
2897 jme_phy_init(jme);
2898 jme_phy_off(jme);
2899
2900 /*
2901 * Reset MAC processor and reload EEPROM for MAC Address
2902 */
2903 jme_reset_mac_processor(jme);
2904 rc = jme_reload_eeprom(jme);
2905 if (rc) {
2906 jeprintk(pdev,
2907 "Reload eeprom for reading MAC Address error.\n");
2908 goto err_out_unmap;
2909 }
2910 jme_load_macaddr(netdev);
2911
2912 /*
2913 * Tell stack that we are not ready to work until open()
2914 */
2915 netif_carrier_off(netdev);
2916 netif_stop_queue(netdev);
2917
2918 /*
2919 * Register netdev
2920 */
2921 rc = register_netdev(netdev);
2922 if (rc) {
2923 jeprintk(pdev, "Cannot register net device.\n");
2924 goto err_out_unmap;
2925 }
2926
2927 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2928 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2929 "JMC250 Gigabit Ethernet" :
2930 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2931 "JMC260 Fast Ethernet" : "Unknown",
2932 (jme->fpgaver != 0) ? " (FPGA)" : "",
2933 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2934 jme->rev, netdev->dev_addr);
2935
2936 return 0;
2937
2938 err_out_unmap:
2939 iounmap(jme->regs);
2940 err_out_free_netdev:
2941 pci_set_drvdata(pdev, NULL);
2942 free_netdev(netdev);
2943 err_out_release_regions:
2944 pci_release_regions(pdev);
2945 err_out_disable_pdev:
2946 pci_disable_device(pdev);
2947 err_out:
2948 return rc;
2949 }
2950
2951 static void __devexit
2952 jme_remove_one(struct pci_dev *pdev)
2953 {
2954 struct net_device *netdev = pci_get_drvdata(pdev);
2955 struct jme_adapter *jme = netdev_priv(netdev);
2956
2957 unregister_netdev(netdev);
2958 iounmap(jme->regs);
2959 pci_set_drvdata(pdev, NULL);
2960 free_netdev(netdev);
2961 pci_release_regions(pdev);
2962 pci_disable_device(pdev);
2963
2964 }
2965
2966 #ifdef CONFIG_PM
2967 static int
2968 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2969 {
2970 struct net_device *netdev = pci_get_drvdata(pdev);
2971 struct jme_adapter *jme = netdev_priv(netdev);
2972
2973 atomic_dec(&jme->link_changing);
2974
2975 netif_device_detach(netdev);
2976 netif_stop_queue(netdev);
2977 jme_stop_irq(jme);
2978
2979 tasklet_disable(&jme->txclean_task);
2980 tasklet_disable(&jme->rxclean_task);
2981 tasklet_disable(&jme->rxempty_task);
2982
2983 if (netif_carrier_ok(netdev)) {
2984 if (test_bit(JME_FLAG_POLL, &jme->flags))
2985 jme_polling_mode(jme);
2986
2987 jme_stop_pcc_timer(jme);
2988 jme_reset_ghc_speed(jme);
2989 jme_disable_rx_engine(jme);
2990 jme_disable_tx_engine(jme);
2991 jme_reset_mac_processor(jme);
2992 jme_free_rx_resources(jme);
2993 jme_free_tx_resources(jme);
2994 netif_carrier_off(netdev);
2995 jme->phylink = 0;
2996 }
2997
2998 tasklet_enable(&jme->txclean_task);
2999 tasklet_hi_enable(&jme->rxclean_task);
3000 tasklet_hi_enable(&jme->rxempty_task);
3001
3002 pci_save_state(pdev);
3003 if (jme->reg_pmcs) {
3004 jme_set_100m_half(jme);
3005
3006 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
3007 jme_wait_link(jme);
3008
3009 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3010
3011 pci_enable_wake(pdev, PCI_D3cold, true);
3012 } else {
3013 jme_phy_off(jme);
3014 }
3015 pci_set_power_state(pdev, PCI_D3cold);
3016
3017 return 0;
3018 }
3019
3020 static int
3021 jme_resume(struct pci_dev *pdev)
3022 {
3023 struct net_device *netdev = pci_get_drvdata(pdev);
3024 struct jme_adapter *jme = netdev_priv(netdev);
3025
3026 jme_clear_pm(jme);
3027 pci_restore_state(pdev);
3028
3029 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3030 jme_phy_on(jme);
3031 jme_set_settings(netdev, &jme->old_ecmd);
3032 } else {
3033 jme_reset_phy_processor(jme);
3034 }
3035
3036 jme_start_irq(jme);
3037 netif_device_attach(netdev);
3038
3039 atomic_inc(&jme->link_changing);
3040
3041 jme_reset_link(jme);
3042
3043 return 0;
3044 }
3045 #endif
3046
3047 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3048 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3049 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3050 { }
3051 };
3052
3053 static struct pci_driver jme_driver = {
3054 .name = DRV_NAME,
3055 .id_table = jme_pci_tbl,
3056 .probe = jme_init_one,
3057 .remove = __devexit_p(jme_remove_one),
3058 #ifdef CONFIG_PM
3059 .suspend = jme_suspend,
3060 .resume = jme_resume,
3061 #endif /* CONFIG_PM */
3062 };
3063
3064 static int __init
3065 jme_init_module(void)
3066 {
3067 printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
3068 "driver version %s\n", DRV_VERSION);
3069 return pci_register_driver(&jme_driver);
3070 }
3071
3072 static void __exit
3073 jme_cleanup_module(void)
3074 {
3075 pci_unregister_driver(&jme_driver);
3076 }
3077
3078 module_init(jme_init_module);
3079 module_exit(jme_cleanup_module);
3080
3081 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3082 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3083 MODULE_LICENSE("GPL");
3084 MODULE_VERSION(DRV_VERSION);
3085 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3086
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree