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davinci: DA850/OMAP-L138: avoid using separate initcall for initializing regulator
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-davinci / da850.c
blob717806c6cef942c3fdc5f65172d1643b2d706cfc
1 /*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14 #include <linux/init.h>
15 #include <linux/clk.h>
16 #include <linux/platform_device.h>
17 #include <linux/cpufreq.h>
18 #include <linux/regulator/consumer.h>
19
20 #include <asm/mach/map.h>
21
22 #include <mach/psc.h>
23 #include <mach/irqs.h>
24 #include <mach/cputype.h>
25 #include <mach/common.h>
26 #include <mach/time.h>
27 #include <mach/da8xx.h>
28 #include <mach/cpufreq.h>
29
30 #include "clock.h"
31 #include "mux.h"
32
33 /* SoC specific clock flags */
34 #define DA850_CLK_ASYNC3 BIT(16)
35
36 #define DA850_PLL1_BASE 0x01e1a000
37 #define DA850_TIMER64P2_BASE 0x01f0c000
38 #define DA850_TIMER64P3_BASE 0x01f0d000
39
40 #define DA850_REF_FREQ 24000000
41
42 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
43 #define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
44
45 static int da850_set_armrate(struct clk *clk, unsigned long rate);
46 static int da850_round_armrate(struct clk *clk, unsigned long rate);
47 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
48
49 static struct pll_data pll0_data = {
50 .num = 1,
51 .phys_base = DA8XX_PLL0_BASE,
52 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
53 };
54
55 static struct clk ref_clk = {
56 .name = "ref_clk",
57 .rate = DA850_REF_FREQ,
58 };
59
60 static struct clk pll0_clk = {
61 .name = "pll0",
62 .parent = &ref_clk,
63 .pll_data = &pll0_data,
64 .flags = CLK_PLL,
65 .set_rate = da850_set_pll0rate,
66 };
67
68 static struct clk pll0_aux_clk = {
69 .name = "pll0_aux_clk",
70 .parent = &pll0_clk,
71 .flags = CLK_PLL | PRE_PLL,
72 };
73
74 static struct clk pll0_sysclk2 = {
75 .name = "pll0_sysclk2",
76 .parent = &pll0_clk,
77 .flags = CLK_PLL,
78 .div_reg = PLLDIV2,
79 };
80
81 static struct clk pll0_sysclk3 = {
82 .name = "pll0_sysclk3",
83 .parent = &pll0_clk,
84 .flags = CLK_PLL,
85 .div_reg = PLLDIV3,
86 };
87
88 static struct clk pll0_sysclk4 = {
89 .name = "pll0_sysclk4",
90 .parent = &pll0_clk,
91 .flags = CLK_PLL,
92 .div_reg = PLLDIV4,
93 };
94
95 static struct clk pll0_sysclk5 = {
96 .name = "pll0_sysclk5",
97 .parent = &pll0_clk,
98 .flags = CLK_PLL,
99 .div_reg = PLLDIV5,
100 };
101
102 static struct clk pll0_sysclk6 = {
103 .name = "pll0_sysclk6",
104 .parent = &pll0_clk,
105 .flags = CLK_PLL,
106 .div_reg = PLLDIV6,
107 };
108
109 static struct clk pll0_sysclk7 = {
110 .name = "pll0_sysclk7",
111 .parent = &pll0_clk,
112 .flags = CLK_PLL,
113 .div_reg = PLLDIV7,
114 };
115
116 static struct pll_data pll1_data = {
117 .num = 2,
118 .phys_base = DA850_PLL1_BASE,
119 .flags = PLL_HAS_POSTDIV,
120 };
121
122 static struct clk pll1_clk = {
123 .name = "pll1",
124 .parent = &ref_clk,
125 .pll_data = &pll1_data,
126 .flags = CLK_PLL,
127 };
128
129 static struct clk pll1_aux_clk = {
130 .name = "pll1_aux_clk",
131 .parent = &pll1_clk,
132 .flags = CLK_PLL | PRE_PLL,
133 };
134
135 static struct clk pll1_sysclk2 = {
136 .name = "pll1_sysclk2",
137 .parent = &pll1_clk,
138 .flags = CLK_PLL,
139 .div_reg = PLLDIV2,
140 };
141
142 static struct clk pll1_sysclk3 = {
143 .name = "pll1_sysclk3",
144 .parent = &pll1_clk,
145 .flags = CLK_PLL,
146 .div_reg = PLLDIV3,
147 };
148
149 static struct clk pll1_sysclk4 = {
150 .name = "pll1_sysclk4",
151 .parent = &pll1_clk,
152 .flags = CLK_PLL,
153 .div_reg = PLLDIV4,
154 };
155
156 static struct clk pll1_sysclk5 = {
157 .name = "pll1_sysclk5",
158 .parent = &pll1_clk,
159 .flags = CLK_PLL,
160 .div_reg = PLLDIV5,
161 };
162
163 static struct clk pll1_sysclk6 = {
164 .name = "pll0_sysclk6",
165 .parent = &pll0_clk,
166 .flags = CLK_PLL,
167 .div_reg = PLLDIV6,
168 };
169
170 static struct clk pll1_sysclk7 = {
171 .name = "pll1_sysclk7",
172 .parent = &pll1_clk,
173 .flags = CLK_PLL,
174 .div_reg = PLLDIV7,
175 };
176
177 static struct clk i2c0_clk = {
178 .name = "i2c0",
179 .parent = &pll0_aux_clk,
180 };
181
182 static struct clk timerp64_0_clk = {
183 .name = "timer0",
184 .parent = &pll0_aux_clk,
185 };
186
187 static struct clk timerp64_1_clk = {
188 .name = "timer1",
189 .parent = &pll0_aux_clk,
190 };
191
192 static struct clk arm_rom_clk = {
193 .name = "arm_rom",
194 .parent = &pll0_sysclk2,
195 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
196 .flags = ALWAYS_ENABLED,
197 };
198
199 static struct clk tpcc0_clk = {
200 .name = "tpcc0",
201 .parent = &pll0_sysclk2,
202 .lpsc = DA8XX_LPSC0_TPCC,
203 .flags = ALWAYS_ENABLED | CLK_PSC,
204 };
205
206 static struct clk tptc0_clk = {
207 .name = "tptc0",
208 .parent = &pll0_sysclk2,
209 .lpsc = DA8XX_LPSC0_TPTC0,
210 .flags = ALWAYS_ENABLED,
211 };
212
213 static struct clk tptc1_clk = {
214 .name = "tptc1",
215 .parent = &pll0_sysclk2,
216 .lpsc = DA8XX_LPSC0_TPTC1,
217 .flags = ALWAYS_ENABLED,
218 };
219
220 static struct clk tpcc1_clk = {
221 .name = "tpcc1",
222 .parent = &pll0_sysclk2,
223 .lpsc = DA850_LPSC1_TPCC1,
224 .gpsc = 1,
225 .flags = CLK_PSC | ALWAYS_ENABLED,
226 };
227
228 static struct clk tptc2_clk = {
229 .name = "tptc2",
230 .parent = &pll0_sysclk2,
231 .lpsc = DA850_LPSC1_TPTC2,
232 .gpsc = 1,
233 .flags = ALWAYS_ENABLED,
234 };
235
236 static struct clk uart0_clk = {
237 .name = "uart0",
238 .parent = &pll0_sysclk2,
239 .lpsc = DA8XX_LPSC0_UART0,
240 };
241
242 static struct clk uart1_clk = {
243 .name = "uart1",
244 .parent = &pll0_sysclk2,
245 .lpsc = DA8XX_LPSC1_UART1,
246 .gpsc = 1,
247 .flags = DA850_CLK_ASYNC3,
248 };
249
250 static struct clk uart2_clk = {
251 .name = "uart2",
252 .parent = &pll0_sysclk2,
253 .lpsc = DA8XX_LPSC1_UART2,
254 .gpsc = 1,
255 .flags = DA850_CLK_ASYNC3,
256 };
257
258 static struct clk aintc_clk = {
259 .name = "aintc",
260 .parent = &pll0_sysclk4,
261 .lpsc = DA8XX_LPSC0_AINTC,
262 .flags = ALWAYS_ENABLED,
263 };
264
265 static struct clk gpio_clk = {
266 .name = "gpio",
267 .parent = &pll0_sysclk4,
268 .lpsc = DA8XX_LPSC1_GPIO,
269 .gpsc = 1,
270 };
271
272 static struct clk i2c1_clk = {
273 .name = "i2c1",
274 .parent = &pll0_sysclk4,
275 .lpsc = DA8XX_LPSC1_I2C,
276 .gpsc = 1,
277 };
278
279 static struct clk emif3_clk = {
280 .name = "emif3",
281 .parent = &pll0_sysclk5,
282 .lpsc = DA8XX_LPSC1_EMIF3C,
283 .gpsc = 1,
284 .flags = ALWAYS_ENABLED,
285 };
286
287 static struct clk arm_clk = {
288 .name = "arm",
289 .parent = &pll0_sysclk6,
290 .lpsc = DA8XX_LPSC0_ARM,
291 .flags = ALWAYS_ENABLED,
292 .set_rate = da850_set_armrate,
293 .round_rate = da850_round_armrate,
294 };
295
296 static struct clk rmii_clk = {
297 .name = "rmii",
298 .parent = &pll0_sysclk7,
299 };
300
301 static struct clk emac_clk = {
302 .name = "emac",
303 .parent = &pll0_sysclk4,
304 .lpsc = DA8XX_LPSC1_CPGMAC,
305 .gpsc = 1,
306 };
307
308 static struct clk mcasp_clk = {
309 .name = "mcasp",
310 .parent = &pll0_sysclk2,
311 .lpsc = DA8XX_LPSC1_McASP0,
312 .gpsc = 1,
313 .flags = DA850_CLK_ASYNC3,
314 };
315
316 static struct clk lcdc_clk = {
317 .name = "lcdc",
318 .parent = &pll0_sysclk2,
319 .lpsc = DA8XX_LPSC1_LCDC,
320 .gpsc = 1,
321 };
322
323 static struct clk mmcsd_clk = {
324 .name = "mmcsd",
325 .parent = &pll0_sysclk2,
326 .lpsc = DA8XX_LPSC0_MMC_SD,
327 };
328
329 static struct clk aemif_clk = {
330 .name = "aemif",
331 .parent = &pll0_sysclk3,
332 .lpsc = DA8XX_LPSC0_EMIF25,
333 .flags = ALWAYS_ENABLED,
334 };
335
336 static struct davinci_clk da850_clks[] = {
337 CLK(NULL, "ref", &ref_clk),
338 CLK(NULL, "pll0", &pll0_clk),
339 CLK(NULL, "pll0_aux", &pll0_aux_clk),
340 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
341 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
342 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
343 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
344 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
345 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
346 CLK(NULL, "pll1", &pll1_clk),
347 CLK(NULL, "pll1_aux", &pll1_aux_clk),
348 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
349 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
350 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
351 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
352 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
353 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
354 CLK("i2c_davinci.1", NULL, &i2c0_clk),
355 CLK(NULL, "timer0", &timerp64_0_clk),
356 CLK("watchdog", NULL, &timerp64_1_clk),
357 CLK(NULL, "arm_rom", &arm_rom_clk),
358 CLK(NULL, "tpcc0", &tpcc0_clk),
359 CLK(NULL, "tptc0", &tptc0_clk),
360 CLK(NULL, "tptc1", &tptc1_clk),
361 CLK(NULL, "tpcc1", &tpcc1_clk),
362 CLK(NULL, "tptc2", &tptc2_clk),
363 CLK(NULL, "uart0", &uart0_clk),
364 CLK(NULL, "uart1", &uart1_clk),
365 CLK(NULL, "uart2", &uart2_clk),
366 CLK(NULL, "aintc", &aintc_clk),
367 CLK(NULL, "gpio", &gpio_clk),
368 CLK("i2c_davinci.2", NULL, &i2c1_clk),
369 CLK(NULL, "emif3", &emif3_clk),
370 CLK(NULL, "arm", &arm_clk),
371 CLK(NULL, "rmii", &rmii_clk),
372 CLK("davinci_emac.1", NULL, &emac_clk),
373 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
374 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
375 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
376 CLK(NULL, "aemif", &aemif_clk),
377 CLK(NULL, NULL, NULL),
378 };
379
380 /*
381 * Device specific mux setup
382 *
383 * soc description mux mode mode mux dbg
384 * reg offset mask mode
385 */
386 static const struct mux_config da850_pins[] = {
387 #ifdef CONFIG_DAVINCI_MUX
388 /* UART0 function */
389 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
390 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
391 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
392 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
393 /* UART1 function */
394 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
395 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
396 /* UART2 function */
397 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
398 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
399 /* I2C1 function */
400 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
401 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
402 /* I2C0 function */
403 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
404 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
405 /* EMAC function */
406 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
407 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
408 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
409 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
410 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
411 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
412 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
413 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
414 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
415 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
416 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
417 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
418 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
419 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
420 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
421 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
422 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
423 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
424 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
425 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
426 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
427 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
428 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
429 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
430 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
431 /* McASP function */
432 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
433 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
434 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
435 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
436 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
437 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
438 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
439 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
440 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
441 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
442 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
443 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
444 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
445 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
446 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
447 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
448 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
449 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
450 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
451 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
452 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
453 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
454 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
455 /* LCD function */
456 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
457 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
458 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
459 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
460 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
461 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
462 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
463 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
464 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
465 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
466 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
467 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
468 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
469 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
470 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
471 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
472 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
473 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
474 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
475 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
476 /* MMC/SD0 function */
477 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
478 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
479 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
480 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
481 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
482 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
483 /* EMIF2.5/EMIFA function */
484 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
485 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
486 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
487 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
488 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
489 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
490 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
491 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
492 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
493 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
494 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
495 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
496 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
497 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
498 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
499 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
500 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
501 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
502 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
503 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
504 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
505 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
506 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
507 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
508 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
509 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
510 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
511 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
512 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
513 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
514 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
515 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
516 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
517 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
518 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
519 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
520 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
521 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
522 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
523 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
524 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
525 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
526 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
527 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
528 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
529 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
530 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
531 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
532 /* GPIO function */
533 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
534 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
535 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
536 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
537 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
538 #endif
539 };
540
541 const short da850_uart0_pins[] __initdata = {
542 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
543 -1
544 };
545
546 const short da850_uart1_pins[] __initdata = {
547 DA850_UART1_RXD, DA850_UART1_TXD,
548 -1
549 };
550
551 const short da850_uart2_pins[] __initdata = {
552 DA850_UART2_RXD, DA850_UART2_TXD,
553 -1
554 };
555
556 const short da850_i2c0_pins[] __initdata = {
557 DA850_I2C0_SDA, DA850_I2C0_SCL,
558 -1
559 };
560
561 const short da850_i2c1_pins[] __initdata = {
562 DA850_I2C1_SCL, DA850_I2C1_SDA,
563 -1
564 };
565
566 const short da850_cpgmac_pins[] __initdata = {
567 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
568 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
569 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
570 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
571 DA850_MDIO_D,
572 -1
573 };
574
575 const short da850_rmii_pins[] __initdata = {
576 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
577 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
578 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
579 DA850_MDIO_D,
580 -1
581 };
582
583 const short da850_mcasp_pins[] __initdata = {
584 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
585 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
586 DA850_AXR_11, DA850_AXR_12,
587 -1
588 };
589
590 const short da850_lcdcntl_pins[] __initdata = {
591 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
592 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
593 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
594 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
595 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
596 -1
597 };
598
599 const short da850_mmcsd0_pins[] __initdata = {
600 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
601 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
602 DA850_GPIO4_0, DA850_GPIO4_1,
603 -1
604 };
605
606 const short da850_nand_pins[] __initdata = {
607 DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
608 DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
609 DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
610 DA850_NEMA_WE, DA850_NEMA_OE,
611 -1
612 };
613
614 const short da850_nor_pins[] __initdata = {
615 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
616 DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
617 DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
618 DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
619 DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
620 DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
621 DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
622 DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
623 DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
624 DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
625 DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
626 DA850_EMA_A_22, DA850_EMA_A_23,
627 -1
628 };
629
630 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
631 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
632 [IRQ_DA8XX_COMMTX] = 7,
633 [IRQ_DA8XX_COMMRX] = 7,
634 [IRQ_DA8XX_NINT] = 7,
635 [IRQ_DA8XX_EVTOUT0] = 7,
636 [IRQ_DA8XX_EVTOUT1] = 7,
637 [IRQ_DA8XX_EVTOUT2] = 7,
638 [IRQ_DA8XX_EVTOUT3] = 7,
639 [IRQ_DA8XX_EVTOUT4] = 7,
640 [IRQ_DA8XX_EVTOUT5] = 7,
641 [IRQ_DA8XX_EVTOUT6] = 7,
642 [IRQ_DA8XX_EVTOUT6] = 7,
643 [IRQ_DA8XX_EVTOUT7] = 7,
644 [IRQ_DA8XX_CCINT0] = 7,
645 [IRQ_DA8XX_CCERRINT] = 7,
646 [IRQ_DA8XX_TCERRINT0] = 7,
647 [IRQ_DA8XX_AEMIFINT] = 7,
648 [IRQ_DA8XX_I2CINT0] = 7,
649 [IRQ_DA8XX_MMCSDINT0] = 7,
650 [IRQ_DA8XX_MMCSDINT1] = 7,
651 [IRQ_DA8XX_ALLINT0] = 7,
652 [IRQ_DA8XX_RTC] = 7,
653 [IRQ_DA8XX_SPINT0] = 7,
654 [IRQ_DA8XX_TINT12_0] = 7,
655 [IRQ_DA8XX_TINT34_0] = 7,
656 [IRQ_DA8XX_TINT12_1] = 7,
657 [IRQ_DA8XX_TINT34_1] = 7,
658 [IRQ_DA8XX_UARTINT0] = 7,
659 [IRQ_DA8XX_KEYMGRINT] = 7,
660 [IRQ_DA8XX_SECINT] = 7,
661 [IRQ_DA8XX_SECKEYERR] = 7,
662 [IRQ_DA850_MPUADDRERR0] = 7,
663 [IRQ_DA850_MPUPROTERR0] = 7,
664 [IRQ_DA850_IOPUADDRERR0] = 7,
665 [IRQ_DA850_IOPUPROTERR0] = 7,
666 [IRQ_DA850_IOPUADDRERR1] = 7,
667 [IRQ_DA850_IOPUPROTERR1] = 7,
668 [IRQ_DA850_IOPUADDRERR2] = 7,
669 [IRQ_DA850_IOPUPROTERR2] = 7,
670 [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7,
671 [IRQ_DA850_BOOTCFG_PROT_ERR] = 7,
672 [IRQ_DA850_MPUADDRERR1] = 7,
673 [IRQ_DA850_MPUPROTERR1] = 7,
674 [IRQ_DA850_IOPUADDRERR3] = 7,
675 [IRQ_DA850_IOPUPROTERR3] = 7,
676 [IRQ_DA850_IOPUADDRERR4] = 7,
677 [IRQ_DA850_IOPUPROTERR4] = 7,
678 [IRQ_DA850_IOPUADDRERR5] = 7,
679 [IRQ_DA850_IOPUPROTERR5] = 7,
680 [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7,
681 [IRQ_DA8XX_CHIPINT0] = 7,
682 [IRQ_DA8XX_CHIPINT1] = 7,
683 [IRQ_DA8XX_CHIPINT2] = 7,
684 [IRQ_DA8XX_CHIPINT3] = 7,
685 [IRQ_DA8XX_TCERRINT1] = 7,
686 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
687 [IRQ_DA8XX_C0_RX_PULSE] = 7,
688 [IRQ_DA8XX_C0_TX_PULSE] = 7,
689 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
690 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
691 [IRQ_DA8XX_C1_RX_PULSE] = 7,
692 [IRQ_DA8XX_C1_TX_PULSE] = 7,
693 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
694 [IRQ_DA8XX_MEMERR] = 7,
695 [IRQ_DA8XX_GPIO0] = 7,
696 [IRQ_DA8XX_GPIO1] = 7,
697 [IRQ_DA8XX_GPIO2] = 7,
698 [IRQ_DA8XX_GPIO3] = 7,
699 [IRQ_DA8XX_GPIO4] = 7,
700 [IRQ_DA8XX_GPIO5] = 7,
701 [IRQ_DA8XX_GPIO6] = 7,
702 [IRQ_DA8XX_GPIO7] = 7,
703 [IRQ_DA8XX_GPIO8] = 7,
704 [IRQ_DA8XX_I2CINT1] = 7,
705 [IRQ_DA8XX_LCDINT] = 7,
706 [IRQ_DA8XX_UARTINT1] = 7,
707 [IRQ_DA8XX_MCASPINT] = 7,
708 [IRQ_DA8XX_ALLINT1] = 7,
709 [IRQ_DA8XX_SPINT1] = 7,
710 [IRQ_DA8XX_UHPI_INT1] = 7,
711 [IRQ_DA8XX_USB_INT] = 7,
712 [IRQ_DA8XX_IRQN] = 7,
713 [IRQ_DA8XX_RWAKEUP] = 7,
714 [IRQ_DA8XX_UARTINT2] = 7,
715 [IRQ_DA8XX_DFTSSINT] = 7,
716 [IRQ_DA8XX_EHRPWM0] = 7,
717 [IRQ_DA8XX_EHRPWM0TZ] = 7,
718 [IRQ_DA8XX_EHRPWM1] = 7,
719 [IRQ_DA8XX_EHRPWM1TZ] = 7,
720 [IRQ_DA850_SATAINT] = 7,
721 [IRQ_DA850_TINT12_2] = 7,
722 [IRQ_DA850_TINT34_2] = 7,
723 [IRQ_DA850_TINTALL_2] = 7,
724 [IRQ_DA8XX_ECAP0] = 7,
725 [IRQ_DA8XX_ECAP1] = 7,
726 [IRQ_DA8XX_ECAP2] = 7,
727 [IRQ_DA850_MMCSDINT0_1] = 7,
728 [IRQ_DA850_MMCSDINT1_1] = 7,
729 [IRQ_DA850_T12CMPINT0_2] = 7,
730 [IRQ_DA850_T12CMPINT1_2] = 7,
731 [IRQ_DA850_T12CMPINT2_2] = 7,
732 [IRQ_DA850_T12CMPINT3_2] = 7,
733 [IRQ_DA850_T12CMPINT4_2] = 7,
734 [IRQ_DA850_T12CMPINT5_2] = 7,
735 [IRQ_DA850_T12CMPINT6_2] = 7,
736 [IRQ_DA850_T12CMPINT7_2] = 7,
737 [IRQ_DA850_T12CMPINT0_3] = 7,
738 [IRQ_DA850_T12CMPINT1_3] = 7,
739 [IRQ_DA850_T12CMPINT2_3] = 7,
740 [IRQ_DA850_T12CMPINT3_3] = 7,
741 [IRQ_DA850_T12CMPINT4_3] = 7,
742 [IRQ_DA850_T12CMPINT5_3] = 7,
743 [IRQ_DA850_T12CMPINT6_3] = 7,
744 [IRQ_DA850_T12CMPINT7_3] = 7,
745 [IRQ_DA850_RPIINT] = 7,
746 [IRQ_DA850_VPIFINT] = 7,
747 [IRQ_DA850_CCINT1] = 7,
748 [IRQ_DA850_CCERRINT1] = 7,
749 [IRQ_DA850_TCERRINT2] = 7,
750 [IRQ_DA850_TINT12_3] = 7,
751 [IRQ_DA850_TINT34_3] = 7,
752 [IRQ_DA850_TINTALL_3] = 7,
753 [IRQ_DA850_MCBSP0RINT] = 7,
754 [IRQ_DA850_MCBSP0XINT] = 7,
755 [IRQ_DA850_MCBSP1RINT] = 7,
756 [IRQ_DA850_MCBSP1XINT] = 7,
757 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
758 };
759
760 static struct map_desc da850_io_desc[] = {
761 {
762 .virtual = IO_VIRT,
763 .pfn = __phys_to_pfn(IO_PHYS),
764 .length = IO_SIZE,
765 .type = MT_DEVICE
766 },
767 {
768 .virtual = DA8XX_CP_INTC_VIRT,
769 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
770 .length = DA8XX_CP_INTC_SIZE,
771 .type = MT_DEVICE
772 },
773 };
774
775 static void __iomem *da850_psc_bases[] = {
776 IO_ADDRESS(DA8XX_PSC0_BASE),
777 IO_ADDRESS(DA8XX_PSC1_BASE),
778 };
779
780 /* Contents of JTAG ID register used to identify exact cpu type */
781 static struct davinci_id da850_ids[] = {
782 {
783 .variant = 0x0,
784 .part_no = 0xb7d1,
785 .manufacturer = 0x017, /* 0x02f >> 1 */
786 .cpu_id = DAVINCI_CPU_ID_DA850,
787 .name = "da850/omap-l138",
788 },
789 };
790
791 static struct davinci_timer_instance da850_timer_instance[4] = {
792 {
793 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
794 .bottom_irq = IRQ_DA8XX_TINT12_0,
795 .top_irq = IRQ_DA8XX_TINT34_0,
796 },
797 {
798 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
799 .bottom_irq = IRQ_DA8XX_TINT12_1,
800 .top_irq = IRQ_DA8XX_TINT34_1,
801 },
802 {
803 .base = IO_ADDRESS(DA850_TIMER64P2_BASE),
804 .bottom_irq = IRQ_DA850_TINT12_2,
805 .top_irq = IRQ_DA850_TINT34_2,
806 },
807 {
808 .base = IO_ADDRESS(DA850_TIMER64P3_BASE),
809 .bottom_irq = IRQ_DA850_TINT12_3,
810 .top_irq = IRQ_DA850_TINT34_3,
811 },
812 };
813
814 /*
815 * T0_BOT: Timer 0, bottom : Used for clock_event
816 * T0_TOP: Timer 0, top : Used for clocksource
817 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
818 */
819 static struct davinci_timer_info da850_timer_info = {
820 .timers = da850_timer_instance,
821 .clockevent_id = T0_BOT,
822 .clocksource_id = T0_TOP,
823 };
824
825 static void da850_set_async3_src(int pllnum)
826 {
827 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
828 struct davinci_clk *c;
829 unsigned int v;
830 int ret;
831
832 for (c = da850_clks; c->lk.clk; c++) {
833 clk = c->lk.clk;
834 if (clk->flags & DA850_CLK_ASYNC3) {
835 ret = clk_set_parent(clk, newparent);
836 WARN(ret, "DA850: unable to re-parent clock %s",
837 clk->name);
838 }
839 }
840
841 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
842 if (pllnum)
843 v |= CFGCHIP3_ASYNC3_CLKSRC;
844 else
845 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
846 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
847 }
848
849 #ifdef CONFIG_CPU_FREQ
850 /*
851 * Notes:
852 * According to the TRM, minimum PLLM results in maximum power savings.
853 * The OPP definitions below should keep the PLLM as low as possible.
854 *
855 * The output of the PLLM must be between 400 to 600 MHz.
856 * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
857 */
858 struct da850_opp {
859 unsigned int freq; /* in KHz */
860 unsigned int prediv;
861 unsigned int mult;
862 unsigned int postdiv;
863 unsigned int cvdd_min; /* in uV */
864 unsigned int cvdd_max; /* in uV */
865 };
866
867 static const struct da850_opp da850_opp_300 = {
868 .freq = 300000,
869 .prediv = 1,
870 .mult = 25,
871 .postdiv = 2,
872 .cvdd_min = 1140000,
873 .cvdd_max = 1320000,
874 };
875
876 static const struct da850_opp da850_opp_200 = {
877 .freq = 200000,
878 .prediv = 1,
879 .mult = 25,
880 .postdiv = 3,
881 .cvdd_min = 1050000,
882 .cvdd_max = 1160000,
883 };
884
885 static const struct da850_opp da850_opp_96 = {
886 .freq = 96000,
887 .prediv = 1,
888 .mult = 20,
889 .postdiv = 5,
890 .cvdd_min = 950000,
891 .cvdd_max = 1050000,
892 };
893
894 #define OPP(freq) \
895 { \
896 .index = (unsigned int) &da850_opp_##freq, \
897 .frequency = freq * 1000, \
898 }
899
900 static struct cpufreq_frequency_table da850_freq_table[] = {
901 OPP(300),
902 OPP(200),
903 OPP(96),
904 {
905 .index = 0,
906 .frequency = CPUFREQ_TABLE_END,
907 },
908 };
909
910 #ifdef CONFIG_REGULATOR
911 static struct regulator *cvdd;
912
913 static int da850_set_voltage(unsigned int index)
914 {
915 struct da850_opp *opp;
916
917 if (!cvdd)
918 return -ENODEV;
919
920 opp = (struct da850_opp *) da850_freq_table[index].index;
921
922 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
923 }
924
925 static int da850_regulator_init(void)
926 {
927 cvdd = regulator_get(NULL, "cvdd");
928 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
929 " voltage scaling unsupported\n")) {
930 return PTR_ERR(cvdd);
931 }
932
933 return 0;
934 }
935 #endif
936
937 static struct davinci_cpufreq_config cpufreq_info = {
938 .freq_table = &da850_freq_table[0],
939 #ifdef CONFIG_REGULATOR
940 .init = da850_regulator_init,
941 .set_voltage = da850_set_voltage,
942 #endif
943 };
944
945 static struct platform_device da850_cpufreq_device = {
946 .name = "cpufreq-davinci",
947 .dev = {
948 .platform_data = &cpufreq_info,
949 },
950 };
951
952 int __init da850_register_cpufreq(void)
953 {
954 return platform_device_register(&da850_cpufreq_device);
955 }
956
957 static int da850_round_armrate(struct clk *clk, unsigned long rate)
958 {
959 int i, ret = 0, diff;
960 unsigned int best = (unsigned int) -1;
961
962 rate /= 1000; /* convert to kHz */
963
964 for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
965 diff = da850_freq_table[i].frequency - rate;
966 if (diff < 0)
967 diff = -diff;
968
969 if (diff < best) {
970 best = diff;
971 ret = da850_freq_table[i].frequency;
972 }
973 }
974
975 return ret * 1000;
976 }
977
978 static int da850_set_armrate(struct clk *clk, unsigned long index)
979 {
980 struct clk *pllclk = &pll0_clk;
981
982 return clk_set_rate(pllclk, index);
983 }
984
985 static int da850_set_pll0rate(struct clk *clk, unsigned long index)
986 {
987 unsigned int prediv, mult, postdiv;
988 struct da850_opp *opp;
989 struct pll_data *pll = clk->pll_data;
990 unsigned int v;
991 int ret;
992
993 opp = (struct da850_opp *) da850_freq_table[index].index;
994 prediv = opp->prediv;
995 mult = opp->mult;
996 postdiv = opp->postdiv;
997
998 /* Unlock writing to PLL registers */
999 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
1000 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1001 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
1002
1003 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1004 if (WARN_ON(ret))
1005 return ret;
1006
1007 return 0;
1008 }
1009 #else
1010 int __init da850_register_cpufreq(void)
1011 {
1012 return 0;
1013 }
1014
1015 static int da850_set_armrate(struct clk *clk, unsigned long rate)
1016 {
1017 return -EINVAL;
1018 }
1019
1020 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1021 {
1022 return -EINVAL;
1023 }
1024
1025 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1026 {
1027 return clk->rate;
1028 }
1029 #endif
1030
1031
1032 static struct davinci_soc_info davinci_soc_info_da850 = {
1033 .io_desc = da850_io_desc,
1034 .io_desc_num = ARRAY_SIZE(da850_io_desc),
1035 .ids = da850_ids,
1036 .ids_num = ARRAY_SIZE(da850_ids),
1037 .cpu_clks = da850_clks,
1038 .psc_bases = da850_psc_bases,
1039 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
1040 .pinmux_pins = da850_pins,
1041 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
1042 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
1043 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1044 .intc_irq_prios = da850_default_priorities,
1045 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1046 .timer_info = &da850_timer_info,
1047 .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
1048 .gpio_num = 144,
1049 .gpio_irq = IRQ_DA8XX_GPIO0,
1050 .serial_dev = &da8xx_serial_device,
1051 .emac_pdata = &da8xx_emac_pdata,
1052 };
1053
1054 void __init da850_init(void)
1055 {
1056 da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K);
1057 if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module"))
1058 return;
1059
1060 davinci_soc_info_da850.jtag_id_base =
1061 DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG);
1062 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG_VIRT(0x120);
1063
1064 davinci_common_init(&davinci_soc_info_da850);
1065
1066 /*
1067 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1068 * This helps keeping the peripherals on this domain insulated
1069 * from CPU frequency changes caused by DVFS. The firmware sets
1070 * both PLL0 and PLL1 to the same frequency so, there should not
1071 * be any noticible change even in non-DVFS use cases.
1072 */
1073 da850_set_async3_src(1);
1074 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree