arch/arm/mach-at91/at91sam9260.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9260.c
   3  *
   4  *  Copyright (C) 2006 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/pm.h>
  15
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <mach/cpu.h>
  20 #include <mach/at91sam9260.h>
  21 #include <mach/at91_pmc.h>
  22 #include <mach/at91_rstc.h>
  23 #include <mach/at91_shdwc.h>
  24
  25 #include "generic.h"
  26 #include "clock.h"
  27
  28 extern void at91sam9_alt_reset(void);
  29
  30 static struct map_desc at91sam9260_io_desc[] __initdata = {
  31         {
  32                 .virtual        = AT91_VA_BASE_SYS,
  33                 .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  34                 .length         = SZ_16K,
  35                 .type           = MT_DEVICE,
  36         }
  37 };
  38
  39 static struct map_desc at91sam9260_sram_desc[] __initdata = {
  40         {
  41                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
  42                 .pfn            = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
  43                 .length         = AT91SAM9260_SRAM0_SIZE,
  44                 .type           = MT_DEVICE,
  45         }, {
  46                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
  47                 .pfn            = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
  48                 .length         = AT91SAM9260_SRAM1_SIZE,
  49                 .type           = MT_DEVICE,
  50         }
  51 };
  52
  53 static struct map_desc at91sam9g20_sram_desc[] __initdata = {
  54         {
  55                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE,
  56                 .pfn            = __phys_to_pfn(AT91SAM9G20_SRAM0_BASE),
  57                 .length         = AT91SAM9G20_SRAM0_SIZE,
  58                 .type           = MT_DEVICE,
  59         }, {
  60                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE - AT91SAM9G20_SRAM1_SIZE,
  61                 .pfn            = __phys_to_pfn(AT91SAM9G20_SRAM1_BASE),
  62                 .length         = AT91SAM9G20_SRAM1_SIZE,
  63                 .type           = MT_DEVICE,
  64         }
  65 };
  66
  67 static struct map_desc at91sam9xe_sram_desc[] __initdata = {
  68         {
  69                 .pfn            = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
  70                 .type           = MT_DEVICE,
  71         }
  72 };
  73
  74 /* --------------------------------------------------------------------
  75  *  Clocks
  76  * -------------------------------------------------------------------- */
  77
  78 /*
  79  * The peripheral clocks.
  80  */
  81 static struct clk pioA_clk = {
  82         .name           = "pioA_clk",
  83         .pmc_mask       = 1 << AT91SAM9260_ID_PIOA,
  84         .type           = CLK_TYPE_PERIPHERAL,
  85 };
  86 static struct clk pioB_clk = {
  87         .name           = "pioB_clk",
  88         .pmc_mask       = 1 << AT91SAM9260_ID_PIOB,
  89         .type           = CLK_TYPE_PERIPHERAL,
  90 };
  91 static struct clk pioC_clk = {
  92         .name           = "pioC_clk",
  93         .pmc_mask       = 1 << AT91SAM9260_ID_PIOC,
  94         .type           = CLK_TYPE_PERIPHERAL,
  95 };
  96 static struct clk adc_clk = {
  97         .name           = "adc_clk",
  98         .pmc_mask       = 1 << AT91SAM9260_ID_ADC,
  99         .type           = CLK_TYPE_PERIPHERAL,
 100 };
 101 static struct clk usart0_clk = {
 102         .name           = "usart0_clk",
 103         .pmc_mask       = 1 << AT91SAM9260_ID_US0,
 104         .type           = CLK_TYPE_PERIPHERAL,
 105 };
 106 static struct clk usart1_clk = {
 107         .name           = "usart1_clk",
 108         .pmc_mask       = 1 << AT91SAM9260_ID_US1,
 109         .type           = CLK_TYPE_PERIPHERAL,
 110 };
 111 static struct clk usart2_clk = {
 112         .name           = "usart2_clk",
 113         .pmc_mask       = 1 << AT91SAM9260_ID_US2,
 114         .type           = CLK_TYPE_PERIPHERAL,
 115 };
 116 static struct clk mmc_clk = {
 117         .name           = "mci_clk",
 118         .pmc_mask       = 1 << AT91SAM9260_ID_MCI,
 119         .type           = CLK_TYPE_PERIPHERAL,
 120 };
 121 static struct clk udc_clk = {
 122         .name           = "udc_clk",
 123         .pmc_mask       = 1 << AT91SAM9260_ID_UDP,
 124         .type           = CLK_TYPE_PERIPHERAL,
 125 };
 126 static struct clk twi_clk = {
 127         .name           = "twi_clk",
 128         .pmc_mask       = 1 << AT91SAM9260_ID_TWI,
 129         .type           = CLK_TYPE_PERIPHERAL,
 130 };
 131 static struct clk spi0_clk = {
 132         .name           = "spi0_clk",
 133         .pmc_mask       = 1 << AT91SAM9260_ID_SPI0,
 134         .type           = CLK_TYPE_PERIPHERAL,
 135 };
 136 static struct clk spi1_clk = {
 137         .name           = "spi1_clk",
 138         .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
 139         .type           = CLK_TYPE_PERIPHERAL,
 140 };
 141 static struct clk ssc_clk = {
 142         .name           = "ssc_clk",
 143         .pmc_mask       = 1 << AT91SAM9260_ID_SSC,
 144         .type           = CLK_TYPE_PERIPHERAL,
 145 };
 146 static struct clk tc0_clk = {
 147         .name           = "tc0_clk",
 148         .pmc_mask       = 1 << AT91SAM9260_ID_TC0,
 149         .type           = CLK_TYPE_PERIPHERAL,
 150 };
 151 static struct clk tc1_clk = {
 152         .name           = "tc1_clk",
 153         .pmc_mask       = 1 << AT91SAM9260_ID_TC1,
 154         .type           = CLK_TYPE_PERIPHERAL,
 155 };
 156 static struct clk tc2_clk = {
 157         .name           = "tc2_clk",
 158         .pmc_mask       = 1 << AT91SAM9260_ID_TC2,
 159         .type           = CLK_TYPE_PERIPHERAL,
 160 };
 161 static struct clk ohci_clk = {
 162         .name           = "ohci_clk",
 163         .pmc_mask       = 1 << AT91SAM9260_ID_UHP,
 164         .type           = CLK_TYPE_PERIPHERAL,
 165 };
 166 static struct clk macb_clk = {
 167         .name           = "macb_clk",
 168         .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
 169         .type           = CLK_TYPE_PERIPHERAL,
 170 };
 171 static struct clk isi_clk = {
 172         .name           = "isi_clk",
 173         .pmc_mask       = 1 << AT91SAM9260_ID_ISI,
 174         .type           = CLK_TYPE_PERIPHERAL,
 175 };
 176 static struct clk usart3_clk = {
 177         .name           = "usart3_clk",
 178         .pmc_mask       = 1 << AT91SAM9260_ID_US3,
 179         .type           = CLK_TYPE_PERIPHERAL,
 180 };
 181 static struct clk usart4_clk = {
 182         .name           = "usart4_clk",
 183         .pmc_mask       = 1 << AT91SAM9260_ID_US4,
 184         .type           = CLK_TYPE_PERIPHERAL,
 185 };
 186 static struct clk usart5_clk = {
 187         .name           = "usart5_clk",
 188         .pmc_mask       = 1 << AT91SAM9260_ID_US5,
 189         .type           = CLK_TYPE_PERIPHERAL,
 190 };
 191 static struct clk tc3_clk = {
 192         .name           = "tc3_clk",
 193         .pmc_mask       = 1 << AT91SAM9260_ID_TC3,
 194         .type           = CLK_TYPE_PERIPHERAL,
 195 };
 196 static struct clk tc4_clk = {
 197         .name           = "tc4_clk",
 198         .pmc_mask       = 1 << AT91SAM9260_ID_TC4,
 199         .type           = CLK_TYPE_PERIPHERAL,
 200 };
 201 static struct clk tc5_clk = {
 202         .name           = "tc5_clk",
 203         .pmc_mask       = 1 << AT91SAM9260_ID_TC5,
 204         .type           = CLK_TYPE_PERIPHERAL,
 205 };
 206
 207 static struct clk *periph_clocks[] __initdata = {
 208         &pioA_clk,
 209         &pioB_clk,
 210         &pioC_clk,
 211         &adc_clk,
 212         &usart0_clk,
 213         &usart1_clk,
 214         &usart2_clk,
 215         &mmc_clk,
 216         &udc_clk,
 217         &twi_clk,
 218         &spi0_clk,
 219         &spi1_clk,
 220         &ssc_clk,
 221         &tc0_clk,
 222         &tc1_clk,
 223         &tc2_clk,
 224         &ohci_clk,
 225         &macb_clk,
 226         &isi_clk,
 227         &usart3_clk,
 228         &usart4_clk,
 229         &usart5_clk,
 230         &tc3_clk,
 231         &tc4_clk,
 232         &tc5_clk,
 233         // irq0 .. irq2
 234 };
 235
 236 /*
 237  * The two programmable clocks.
 238  * You must configure pin multiplexing to bring these signals out.
 239  */
 240 static struct clk pck0 = {
 241         .name           = "pck0",
 242         .pmc_mask       = AT91_PMC_PCK0,
 243         .type           = CLK_TYPE_PROGRAMMABLE,
 244         .id             = 0,
 245 };
 246 static struct clk pck1 = {
 247         .name           = "pck1",
 248         .pmc_mask       = AT91_PMC_PCK1,
 249         .type           = CLK_TYPE_PROGRAMMABLE,
 250         .id             = 1,
 251 };
 252
 253 static void __init at91sam9260_register_clocks(void)
 254 {
 255         int i;
 256
 257         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 258                 clk_register(periph_clocks[i]);
 259
 260         clk_register(&pck0);
 261         clk_register(&pck1);
 262 }
 263
 264 /* --------------------------------------------------------------------
 265  *  GPIO
 266  * -------------------------------------------------------------------- */
 267
 268 static struct at91_gpio_bank at91sam9260_gpio[] = {
 269         {
 270                 .id             = AT91SAM9260_ID_PIOA,
 271                 .offset         = AT91_PIOA,
 272                 .clock          = &pioA_clk,
 273         }, {
 274                 .id             = AT91SAM9260_ID_PIOB,
 275                 .offset         = AT91_PIOB,
 276                 .clock          = &pioB_clk,
 277         }, {
 278                 .id             = AT91SAM9260_ID_PIOC,
 279                 .offset         = AT91_PIOC,
 280                 .clock          = &pioC_clk,
 281         }
 282 };
 283
 284 static void at91sam9260_reset(void)
 285 {
 286         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 287 }
 288
 289 static void at91sam9260_poweroff(void)
 290 {
 291         at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 292 }
 293
 294
 295 /* --------------------------------------------------------------------
 296  *  AT91SAM9260 processor initialization
 297  * -------------------------------------------------------------------- */
 298
 299 static void __init at91sam9xe_initialize(void)
 300 {
 301         unsigned long cidr, sram_size;
 302
 303         cidr = at91_sys_read(AT91_DBGU_CIDR);
 304
 305         switch (cidr & AT91_CIDR_SRAMSIZ) {
 306                 case AT91_CIDR_SRAMSIZ_32K:
 307                         sram_size = 2 * SZ_16K;
 308                         break;
 309                 case AT91_CIDR_SRAMSIZ_16K:
 310                 default:
 311                         sram_size = SZ_16K;
 312         }
 313
 314         at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
 315         at91sam9xe_sram_desc->length = sram_size;
 316
 317         iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
 318 }
 319
 320 void __init at91sam9260_initialize(unsigned long main_clock)
 321 {
 322         /* Map peripherals */
 323         iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
 324
 325         if (cpu_is_at91sam9xe())
 326                 at91sam9xe_initialize();
 327         else if (cpu_is_at91sam9g20())
 328                 iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc));
 329         else
 330                 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
 331
 332         if (cpu_is_at91sam9g20())
 333                 at91_arch_reset = at91sam9_alt_reset;
 334         else
 335                 at91_arch_reset = at91sam9260_reset;
 336
 337         pm_power_off = at91sam9260_poweroff;
 338         at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
 339                         | (1 << AT91SAM9260_ID_IRQ2);
 340
 341         /* Init clock subsystem */
 342         at91_clock_init(main_clock);
 343
 344         /* Register the processor-specific clocks */
 345         at91sam9260_register_clocks();
 346
 347         /* Register GPIO subsystem */
 348         at91_gpio_init(at91sam9260_gpio, 3);
 349 }
 350
 351 /* --------------------------------------------------------------------
 352  *  Interrupt initialization
 353  * -------------------------------------------------------------------- */
 354
 355 /*
 356  * The default interrupt priority levels (0 = lowest, 7 = highest).
 357  */
 358 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
 359         7,      /* Advanced Interrupt Controller */
 360         7,      /* System Peripherals */
 361         1,      /* Parallel IO Controller A */
 362         1,      /* Parallel IO Controller B */
 363         1,      /* Parallel IO Controller C */
 364         0,      /* Analog-to-Digital Converter */
 365         5,      /* USART 0 */
 366         5,      /* USART 1 */
 367         5,      /* USART 2 */
 368         0,      /* Multimedia Card Interface */
 369         2,      /* USB Device Port */
 370         6,      /* Two-Wire Interface */
 371         5,      /* Serial Peripheral Interface 0 */
 372         5,      /* Serial Peripheral Interface 1 */
 373         5,      /* Serial Synchronous Controller */
 374         0,
 375         0,
 376         0,      /* Timer Counter 0 */
 377         0,      /* Timer Counter 1 */
 378         0,      /* Timer Counter 2 */
 379         2,      /* USB Host port */
 380         3,      /* Ethernet */
 381         0,      /* Image Sensor Interface */
 382         5,      /* USART 3 */
 383         5,      /* USART 4 */
 384         5,      /* USART 5 */
 385         0,      /* Timer Counter 3 */
 386         0,      /* Timer Counter 4 */
 387         0,      /* Timer Counter 5 */
 388         0,      /* Advanced Interrupt Controller */
 389         0,      /* Advanced Interrupt Controller */
 390         0,      /* Advanced Interrupt Controller */
 391 };
 392
 393 void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])
 394 {
 395         if (!priority)
 396                 priority = at91sam9260_default_irq_priority;
 397
 398         /* Initialize the AIC interrupt controller */
 399         at91_aic_init(priority);
 400
 401         /* Enable GPIO interrupts */
 402         at91_gpio_irq_setup();
 403 }