2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitmap.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list
);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock
);
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
49 static struct protection_domain
*pt_domain
;
51 static struct iommu_ops amd_iommu_ops
;
54 * general struct to manage commands send to an IOMMU
60 static void reset_iommu_command_buffer(struct amd_iommu
*iommu
);
61 static void update_domain(struct protection_domain
*domain
);
63 /****************************************************************************
67 ****************************************************************************/
69 static inline u16
get_device_id(struct device
*dev
)
71 struct pci_dev
*pdev
= to_pci_dev(dev
);
73 return calc_devid(pdev
->bus
->number
, pdev
->devfn
);
76 static struct iommu_dev_data
*get_dev_data(struct device
*dev
)
78 return dev
->archdata
.iommu
;
82 * In this function the list of preallocated protection domains is traversed to
83 * find the domain for a specific device
85 static struct dma_ops_domain
*find_protection_domain(u16 devid
)
87 struct dma_ops_domain
*entry
, *ret
= NULL
;
89 u16 alias
= amd_iommu_alias_table
[devid
];
91 if (list_empty(&iommu_pd_list
))
94 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
96 list_for_each_entry(entry
, &iommu_pd_list
, list
) {
97 if (entry
->target_dev
== devid
||
98 entry
->target_dev
== alias
) {
104 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
110 * This function checks if the driver got a valid device from the caller to
111 * avoid dereferencing invalid pointers.
113 static bool check_device(struct device
*dev
)
117 if (!dev
|| !dev
->dma_mask
)
120 /* No device or no PCI device */
121 if (!dev
|| dev
->bus
!= &pci_bus_type
)
124 devid
= get_device_id(dev
);
126 /* Out of our scope? */
127 if (devid
> amd_iommu_last_bdf
)
130 if (amd_iommu_rlookup_table
[devid
] == NULL
)
136 static int iommu_init_device(struct device
*dev
)
138 struct iommu_dev_data
*dev_data
;
139 struct pci_dev
*pdev
;
142 if (dev
->archdata
.iommu
)
145 dev_data
= kzalloc(sizeof(*dev_data
), GFP_KERNEL
);
151 devid
= get_device_id(dev
);
152 alias
= amd_iommu_alias_table
[devid
];
153 pdev
= pci_get_bus_and_slot(PCI_BUS(alias
), alias
& 0xff);
155 dev_data
->alias
= &pdev
->dev
;
157 atomic_set(&dev_data
->bind
, 0);
159 dev
->archdata
.iommu
= dev_data
;
165 static void iommu_uninit_device(struct device
*dev
)
167 kfree(dev
->archdata
.iommu
);
170 void __init
amd_iommu_uninit_devices(void)
172 struct pci_dev
*pdev
= NULL
;
174 for_each_pci_dev(pdev
) {
176 if (!check_device(&pdev
->dev
))
179 iommu_uninit_device(&pdev
->dev
);
183 int __init
amd_iommu_init_devices(void)
185 struct pci_dev
*pdev
= NULL
;
188 for_each_pci_dev(pdev
) {
190 if (!check_device(&pdev
->dev
))
193 ret
= iommu_init_device(&pdev
->dev
);
202 amd_iommu_uninit_devices();
206 #ifdef CONFIG_AMD_IOMMU_STATS
209 * Initialization code for statistics collection
212 DECLARE_STATS_COUNTER(compl_wait
);
213 DECLARE_STATS_COUNTER(cnt_map_single
);
214 DECLARE_STATS_COUNTER(cnt_unmap_single
);
215 DECLARE_STATS_COUNTER(cnt_map_sg
);
216 DECLARE_STATS_COUNTER(cnt_unmap_sg
);
217 DECLARE_STATS_COUNTER(cnt_alloc_coherent
);
218 DECLARE_STATS_COUNTER(cnt_free_coherent
);
219 DECLARE_STATS_COUNTER(cross_page
);
220 DECLARE_STATS_COUNTER(domain_flush_single
);
221 DECLARE_STATS_COUNTER(domain_flush_all
);
222 DECLARE_STATS_COUNTER(alloced_io_mem
);
223 DECLARE_STATS_COUNTER(total_map_requests
);
225 static struct dentry
*stats_dir
;
226 static struct dentry
*de_fflush
;
228 static void amd_iommu_stats_add(struct __iommu_counter
*cnt
)
230 if (stats_dir
== NULL
)
233 cnt
->dent
= debugfs_create_u64(cnt
->name
, 0444, stats_dir
,
237 static void amd_iommu_stats_init(void)
239 stats_dir
= debugfs_create_dir("amd-iommu", NULL
);
240 if (stats_dir
== NULL
)
243 de_fflush
= debugfs_create_bool("fullflush", 0444, stats_dir
,
244 (u32
*)&amd_iommu_unmap_flush
);
246 amd_iommu_stats_add(&compl_wait
);
247 amd_iommu_stats_add(&cnt_map_single
);
248 amd_iommu_stats_add(&cnt_unmap_single
);
249 amd_iommu_stats_add(&cnt_map_sg
);
250 amd_iommu_stats_add(&cnt_unmap_sg
);
251 amd_iommu_stats_add(&cnt_alloc_coherent
);
252 amd_iommu_stats_add(&cnt_free_coherent
);
253 amd_iommu_stats_add(&cross_page
);
254 amd_iommu_stats_add(&domain_flush_single
);
255 amd_iommu_stats_add(&domain_flush_all
);
256 amd_iommu_stats_add(&alloced_io_mem
);
257 amd_iommu_stats_add(&total_map_requests
);
262 /****************************************************************************
264 * Interrupt handling functions
266 ****************************************************************************/
268 static void dump_dte_entry(u16 devid
)
272 for (i
= 0; i
< 8; ++i
)
273 pr_err("AMD-Vi: DTE[%d]: %08x\n", i
,
274 amd_iommu_dev_table
[devid
].data
[i
]);
277 static void dump_command(unsigned long phys_addr
)
279 struct iommu_cmd
*cmd
= phys_to_virt(phys_addr
);
282 for (i
= 0; i
< 4; ++i
)
283 pr_err("AMD-Vi: CMD[%d]: %08x\n", i
, cmd
->data
[i
]);
286 static void iommu_print_event(struct amd_iommu
*iommu
, void *__evt
)
289 int type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
290 int devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
291 int domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
292 int flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
293 u64 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
295 printk(KERN_ERR
"AMD-Vi: Event logged [");
298 case EVENT_TYPE_ILL_DEV
:
299 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
300 "address=0x%016llx flags=0x%04x]\n",
301 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
303 dump_dte_entry(devid
);
305 case EVENT_TYPE_IO_FAULT
:
306 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
307 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
308 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
309 domid
, address
, flags
);
311 case EVENT_TYPE_DEV_TAB_ERR
:
312 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
313 "address=0x%016llx flags=0x%04x]\n",
314 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
317 case EVENT_TYPE_PAGE_TAB_ERR
:
318 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
319 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
320 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
321 domid
, address
, flags
);
323 case EVENT_TYPE_ILL_CMD
:
324 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
325 iommu
->reset_in_progress
= true;
326 reset_iommu_command_buffer(iommu
);
327 dump_command(address
);
329 case EVENT_TYPE_CMD_HARD_ERR
:
330 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
331 "flags=0x%04x]\n", address
, flags
);
333 case EVENT_TYPE_IOTLB_INV_TO
:
334 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
335 "address=0x%016llx]\n",
336 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
339 case EVENT_TYPE_INV_DEV_REQ
:
340 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
341 "address=0x%016llx flags=0x%04x]\n",
342 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
346 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
350 static void iommu_poll_events(struct amd_iommu
*iommu
)
355 spin_lock_irqsave(&iommu
->lock
, flags
);
357 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
358 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
360 while (head
!= tail
) {
361 iommu_print_event(iommu
, iommu
->evt_buf
+ head
);
362 head
= (head
+ EVENT_ENTRY_SIZE
) % iommu
->evt_buf_size
;
365 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
367 spin_unlock_irqrestore(&iommu
->lock
, flags
);
370 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
372 struct amd_iommu
*iommu
;
374 for_each_iommu(iommu
)
375 iommu_poll_events(iommu
);
380 /****************************************************************************
382 * IOMMU command queuing functions
384 ****************************************************************************/
387 * Writes the command to the IOMMUs command buffer and informs the
388 * hardware about the new command. Must be called with iommu->lock held.
390 static int __iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
395 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
396 target
= iommu
->cmd_buf
+ tail
;
397 memcpy_toio(target
, cmd
, sizeof(*cmd
));
398 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
399 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
402 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
408 * General queuing function for commands. Takes iommu->lock and calls
409 * __iommu_queue_command().
411 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
416 spin_lock_irqsave(&iommu
->lock
, flags
);
417 ret
= __iommu_queue_command(iommu
, cmd
);
419 iommu
->need_sync
= true;
420 spin_unlock_irqrestore(&iommu
->lock
, flags
);
426 * This function waits until an IOMMU has completed a completion
429 static void __iommu_wait_for_completion(struct amd_iommu
*iommu
)
435 INC_STATS_COUNTER(compl_wait
);
437 while (!ready
&& (i
< EXIT_LOOP_COUNT
)) {
439 /* wait for the bit to become one */
440 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
441 ready
= status
& MMIO_STATUS_COM_WAIT_INT_MASK
;
444 /* set bit back to zero */
445 status
&= ~MMIO_STATUS_COM_WAIT_INT_MASK
;
446 writel(status
, iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
448 if (unlikely(i
== EXIT_LOOP_COUNT
))
449 iommu
->reset_in_progress
= true;
453 * This function queues a completion wait command into the command
456 static int __iommu_completion_wait(struct amd_iommu
*iommu
)
458 struct iommu_cmd cmd
;
460 memset(&cmd
, 0, sizeof(cmd
));
461 cmd
.data
[0] = CMD_COMPL_WAIT_INT_MASK
;
462 CMD_SET_TYPE(&cmd
, CMD_COMPL_WAIT
);
464 return __iommu_queue_command(iommu
, &cmd
);
468 * This function is called whenever we need to ensure that the IOMMU has
469 * completed execution of all commands we sent. It sends a
470 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
471 * us about that by writing a value to a physical address we pass with
474 static int iommu_completion_wait(struct amd_iommu
*iommu
)
479 spin_lock_irqsave(&iommu
->lock
, flags
);
481 if (!iommu
->need_sync
)
484 ret
= __iommu_completion_wait(iommu
);
486 iommu
->need_sync
= false;
491 __iommu_wait_for_completion(iommu
);
494 spin_unlock_irqrestore(&iommu
->lock
, flags
);
496 if (iommu
->reset_in_progress
)
497 reset_iommu_command_buffer(iommu
);
502 static void iommu_flush_complete(struct protection_domain
*domain
)
506 for (i
= 0; i
< amd_iommus_present
; ++i
) {
507 if (!domain
->dev_iommu
[i
])
511 * Devices of this domain are behind this IOMMU
512 * We need to wait for completion of all commands.
514 iommu_completion_wait(amd_iommus
[i
]);
519 * Command send function for invalidating a device table entry
521 static int iommu_flush_device(struct device
*dev
)
523 struct amd_iommu
*iommu
;
524 struct iommu_cmd cmd
;
527 devid
= get_device_id(dev
);
528 iommu
= amd_iommu_rlookup_table
[devid
];
531 memset(&cmd
, 0, sizeof(cmd
));
532 CMD_SET_TYPE(&cmd
, CMD_INV_DEV_ENTRY
);
535 return iommu_queue_command(iommu
, &cmd
);
538 static void __iommu_build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
539 u16 domid
, int pde
, int s
)
541 memset(cmd
, 0, sizeof(*cmd
));
542 address
&= PAGE_MASK
;
543 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
544 cmd
->data
[1] |= domid
;
545 cmd
->data
[2] = lower_32_bits(address
);
546 cmd
->data
[3] = upper_32_bits(address
);
547 if (s
) /* size bit - we flush more than one 4kb page */
548 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
549 if (pde
) /* PDE bit - we wan't flush everything not only the PTEs */
550 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
554 * Generic command send function for invalidaing TLB entries
556 static int iommu_queue_inv_iommu_pages(struct amd_iommu
*iommu
,
557 u64 address
, u16 domid
, int pde
, int s
)
559 struct iommu_cmd cmd
;
562 __iommu_build_inv_iommu_pages(&cmd
, address
, domid
, pde
, s
);
564 ret
= iommu_queue_command(iommu
, &cmd
);
570 * TLB invalidation function which is called from the mapping functions.
571 * It invalidates a single PTE if the range to flush is within a single
572 * page. Otherwise it flushes the whole TLB of the IOMMU.
574 static void __iommu_flush_pages(struct protection_domain
*domain
,
575 u64 address
, size_t size
, int pde
)
578 unsigned long pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
580 address
&= PAGE_MASK
;
584 * If we have to flush more than one page, flush all
585 * TLB entries for this domain
587 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
592 for (i
= 0; i
< amd_iommus_present
; ++i
) {
593 if (!domain
->dev_iommu
[i
])
597 * Devices of this domain are behind this IOMMU
598 * We need a TLB flush
600 iommu_queue_inv_iommu_pages(amd_iommus
[i
], address
,
607 static void iommu_flush_pages(struct protection_domain
*domain
,
608 u64 address
, size_t size
)
610 __iommu_flush_pages(domain
, address
, size
, 0);
613 /* Flush the whole IO/TLB for a given protection domain */
614 static void iommu_flush_tlb(struct protection_domain
*domain
)
616 __iommu_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 0);
619 /* Flush the whole IO/TLB for a given protection domain - including PDE */
620 static void iommu_flush_tlb_pde(struct protection_domain
*domain
)
622 __iommu_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 1);
627 * This function flushes the DTEs for all devices in domain
629 static void iommu_flush_domain_devices(struct protection_domain
*domain
)
631 struct iommu_dev_data
*dev_data
;
634 spin_lock_irqsave(&domain
->lock
, flags
);
636 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
637 iommu_flush_device(dev_data
->dev
);
639 spin_unlock_irqrestore(&domain
->lock
, flags
);
642 static void iommu_flush_all_domain_devices(void)
644 struct protection_domain
*domain
;
647 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
649 list_for_each_entry(domain
, &amd_iommu_pd_list
, list
) {
650 iommu_flush_domain_devices(domain
);
651 iommu_flush_complete(domain
);
654 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
657 void amd_iommu_flush_all_devices(void)
659 iommu_flush_all_domain_devices();
663 * This function uses heavy locking and may disable irqs for some time. But
664 * this is no issue because it is only called during resume.
666 void amd_iommu_flush_all_domains(void)
668 struct protection_domain
*domain
;
671 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
673 list_for_each_entry(domain
, &amd_iommu_pd_list
, list
) {
674 spin_lock(&domain
->lock
);
675 iommu_flush_tlb_pde(domain
);
676 iommu_flush_complete(domain
);
677 spin_unlock(&domain
->lock
);
680 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
683 static void reset_iommu_command_buffer(struct amd_iommu
*iommu
)
685 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
687 if (iommu
->reset_in_progress
)
688 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
690 amd_iommu_reset_cmd_buffer(iommu
);
691 amd_iommu_flush_all_devices();
692 amd_iommu_flush_all_domains();
694 iommu
->reset_in_progress
= false;
697 /****************************************************************************
699 * The functions below are used the create the page table mappings for
700 * unity mapped regions.
702 ****************************************************************************/
705 * This function is used to add another level to an IO page table. Adding
706 * another level increases the size of the address space by 9 bits to a size up
709 static bool increase_address_space(struct protection_domain
*domain
,
714 if (domain
->mode
== PAGE_MODE_6_LEVEL
)
715 /* address space already 64 bit large */
718 pte
= (void *)get_zeroed_page(gfp
);
722 *pte
= PM_LEVEL_PDE(domain
->mode
,
723 virt_to_phys(domain
->pt_root
));
724 domain
->pt_root
= pte
;
726 domain
->updated
= true;
731 static u64
*alloc_pte(struct protection_domain
*domain
,
732 unsigned long address
,
733 unsigned long page_size
,
740 BUG_ON(!is_power_of_2(page_size
));
742 while (address
> PM_LEVEL_SIZE(domain
->mode
))
743 increase_address_space(domain
, gfp
);
745 level
= domain
->mode
- 1;
746 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
747 address
= PAGE_SIZE_ALIGN(address
, page_size
);
748 end_lvl
= PAGE_SIZE_LEVEL(page_size
);
750 while (level
> end_lvl
) {
751 if (!IOMMU_PTE_PRESENT(*pte
)) {
752 page
= (u64
*)get_zeroed_page(gfp
);
755 *pte
= PM_LEVEL_PDE(level
, virt_to_phys(page
));
758 /* No level skipping support yet */
759 if (PM_PTE_LEVEL(*pte
) != level
)
764 pte
= IOMMU_PTE_PAGE(*pte
);
766 if (pte_page
&& level
== end_lvl
)
769 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
776 * This function checks if there is a PTE for a given dma address. If
777 * there is one, it returns the pointer to it.
779 static u64
*fetch_pte(struct protection_domain
*domain
, unsigned long address
)
784 if (address
> PM_LEVEL_SIZE(domain
->mode
))
787 level
= domain
->mode
- 1;
788 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
793 if (!IOMMU_PTE_PRESENT(*pte
))
797 if (PM_PTE_LEVEL(*pte
) == 0x07) {
798 unsigned long pte_mask
, __pte
;
801 * If we have a series of large PTEs, make
802 * sure to return a pointer to the first one.
804 pte_mask
= PTE_PAGE_SIZE(*pte
);
805 pte_mask
= ~((PAGE_SIZE_PTE_COUNT(pte_mask
) << 3) - 1);
806 __pte
= ((unsigned long)pte
) & pte_mask
;
811 /* No level skipping support yet */
812 if (PM_PTE_LEVEL(*pte
) != level
)
817 /* Walk to the next level */
818 pte
= IOMMU_PTE_PAGE(*pte
);
819 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
826 * Generic mapping functions. It maps a physical address into a DMA
827 * address space. It allocates the page table pages if necessary.
828 * In the future it can be extended to a generic mapping function
829 * supporting all features of AMD IOMMU page tables like level skipping
830 * and full 64 bit address spaces.
832 static int iommu_map_page(struct protection_domain
*dom
,
833 unsigned long bus_addr
,
834 unsigned long phys_addr
,
836 unsigned long page_size
)
841 if (!(prot
& IOMMU_PROT_MASK
))
844 bus_addr
= PAGE_ALIGN(bus_addr
);
845 phys_addr
= PAGE_ALIGN(phys_addr
);
846 count
= PAGE_SIZE_PTE_COUNT(page_size
);
847 pte
= alloc_pte(dom
, bus_addr
, page_size
, NULL
, GFP_KERNEL
);
849 for (i
= 0; i
< count
; ++i
)
850 if (IOMMU_PTE_PRESENT(pte
[i
]))
853 if (page_size
> PAGE_SIZE
) {
854 __pte
= PAGE_SIZE_PTE(phys_addr
, page_size
);
855 __pte
|= PM_LEVEL_ENC(7) | IOMMU_PTE_P
| IOMMU_PTE_FC
;
857 __pte
= phys_addr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
859 if (prot
& IOMMU_PROT_IR
)
860 __pte
|= IOMMU_PTE_IR
;
861 if (prot
& IOMMU_PROT_IW
)
862 __pte
|= IOMMU_PTE_IW
;
864 for (i
= 0; i
< count
; ++i
)
872 static unsigned long iommu_unmap_page(struct protection_domain
*dom
,
873 unsigned long bus_addr
,
874 unsigned long page_size
)
876 unsigned long long unmap_size
, unmapped
;
879 BUG_ON(!is_power_of_2(page_size
));
883 while (unmapped
< page_size
) {
885 pte
= fetch_pte(dom
, bus_addr
);
889 * No PTE for this address
890 * move forward in 4kb steps
892 unmap_size
= PAGE_SIZE
;
893 } else if (PM_PTE_LEVEL(*pte
) == 0) {
894 /* 4kb PTE found for this address */
895 unmap_size
= PAGE_SIZE
;
900 /* Large PTE found which maps this address */
901 unmap_size
= PTE_PAGE_SIZE(*pte
);
902 count
= PAGE_SIZE_PTE_COUNT(unmap_size
);
903 for (i
= 0; i
< count
; i
++)
907 bus_addr
= (bus_addr
& ~(unmap_size
- 1)) + unmap_size
;
908 unmapped
+= unmap_size
;
911 BUG_ON(!is_power_of_2(unmapped
));
917 * This function checks if a specific unity mapping entry is needed for
918 * this specific IOMMU.
920 static int iommu_for_unity_map(struct amd_iommu
*iommu
,
921 struct unity_map_entry
*entry
)
925 for (i
= entry
->devid_start
; i
<= entry
->devid_end
; ++i
) {
926 bdf
= amd_iommu_alias_table
[i
];
927 if (amd_iommu_rlookup_table
[bdf
] == iommu
)
935 * This function actually applies the mapping to the page table of the
938 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
939 struct unity_map_entry
*e
)
944 for (addr
= e
->address_start
; addr
< e
->address_end
;
946 ret
= iommu_map_page(&dma_dom
->domain
, addr
, addr
, e
->prot
,
951 * if unity mapping is in aperture range mark the page
952 * as allocated in the aperture
954 if (addr
< dma_dom
->aperture_size
)
955 __set_bit(addr
>> PAGE_SHIFT
,
956 dma_dom
->aperture
[0]->bitmap
);
963 * Init the unity mappings for a specific IOMMU in the system
965 * Basically iterates over all unity mapping entries and applies them to
966 * the default domain DMA of that IOMMU if necessary.
968 static int iommu_init_unity_mappings(struct amd_iommu
*iommu
)
970 struct unity_map_entry
*entry
;
973 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
974 if (!iommu_for_unity_map(iommu
, entry
))
976 ret
= dma_ops_unity_map(iommu
->default_dom
, entry
);
985 * Inits the unity mappings required for a specific device
987 static int init_unity_mappings_for_device(struct dma_ops_domain
*dma_dom
,
990 struct unity_map_entry
*e
;
993 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
994 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
996 ret
= dma_ops_unity_map(dma_dom
, e
);
1004 /****************************************************************************
1006 * The next functions belong to the address allocator for the dma_ops
1007 * interface functions. They work like the allocators in the other IOMMU
1008 * drivers. Its basically a bitmap which marks the allocated pages in
1009 * the aperture. Maybe it could be enhanced in the future to a more
1010 * efficient allocator.
1012 ****************************************************************************/
1015 * The address allocator core functions.
1017 * called with domain->lock held
1021 * Used to reserve address ranges in the aperture (e.g. for exclusion
1024 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
1025 unsigned long start_page
,
1028 unsigned int i
, last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
1030 if (start_page
+ pages
> last_page
)
1031 pages
= last_page
- start_page
;
1033 for (i
= start_page
; i
< start_page
+ pages
; ++i
) {
1034 int index
= i
/ APERTURE_RANGE_PAGES
;
1035 int page
= i
% APERTURE_RANGE_PAGES
;
1036 __set_bit(page
, dom
->aperture
[index
]->bitmap
);
1041 * This function is used to add a new aperture range to an existing
1042 * aperture in case of dma_ops domain allocation or address allocation
1045 static int alloc_new_range(struct dma_ops_domain
*dma_dom
,
1046 bool populate
, gfp_t gfp
)
1048 int index
= dma_dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1049 struct amd_iommu
*iommu
;
1052 #ifdef CONFIG_IOMMU_STRESS
1056 if (index
>= APERTURE_MAX_RANGES
)
1059 dma_dom
->aperture
[index
] = kzalloc(sizeof(struct aperture_range
), gfp
);
1060 if (!dma_dom
->aperture
[index
])
1063 dma_dom
->aperture
[index
]->bitmap
= (void *)get_zeroed_page(gfp
);
1064 if (!dma_dom
->aperture
[index
]->bitmap
)
1067 dma_dom
->aperture
[index
]->offset
= dma_dom
->aperture_size
;
1070 unsigned long address
= dma_dom
->aperture_size
;
1071 int i
, num_ptes
= APERTURE_RANGE_PAGES
/ 512;
1072 u64
*pte
, *pte_page
;
1074 for (i
= 0; i
< num_ptes
; ++i
) {
1075 pte
= alloc_pte(&dma_dom
->domain
, address
, PAGE_SIZE
,
1080 dma_dom
->aperture
[index
]->pte_pages
[i
] = pte_page
;
1082 address
+= APERTURE_RANGE_SIZE
/ 64;
1086 dma_dom
->aperture_size
+= APERTURE_RANGE_SIZE
;
1088 /* Intialize the exclusion range if necessary */
1089 for_each_iommu(iommu
) {
1090 if (iommu
->exclusion_start
&&
1091 iommu
->exclusion_start
>= dma_dom
->aperture
[index
]->offset
1092 && iommu
->exclusion_start
< dma_dom
->aperture_size
) {
1093 unsigned long startpage
;
1094 int pages
= iommu_num_pages(iommu
->exclusion_start
,
1095 iommu
->exclusion_length
,
1097 startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
1098 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
1103 * Check for areas already mapped as present in the new aperture
1104 * range and mark those pages as reserved in the allocator. Such
1105 * mappings may already exist as a result of requested unity
1106 * mappings for devices.
1108 for (i
= dma_dom
->aperture
[index
]->offset
;
1109 i
< dma_dom
->aperture_size
;
1111 u64
*pte
= fetch_pte(&dma_dom
->domain
, i
);
1112 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
1115 dma_ops_reserve_addresses(dma_dom
, i
<< PAGE_SHIFT
, 1);
1118 update_domain(&dma_dom
->domain
);
1123 update_domain(&dma_dom
->domain
);
1125 free_page((unsigned long)dma_dom
->aperture
[index
]->bitmap
);
1127 kfree(dma_dom
->aperture
[index
]);
1128 dma_dom
->aperture
[index
] = NULL
;
1133 static unsigned long dma_ops_area_alloc(struct device
*dev
,
1134 struct dma_ops_domain
*dom
,
1136 unsigned long align_mask
,
1138 unsigned long start
)
1140 unsigned long next_bit
= dom
->next_address
% APERTURE_RANGE_SIZE
;
1141 int max_index
= dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1142 int i
= start
>> APERTURE_RANGE_SHIFT
;
1143 unsigned long boundary_size
;
1144 unsigned long address
= -1;
1145 unsigned long limit
;
1147 next_bit
>>= PAGE_SHIFT
;
1149 boundary_size
= ALIGN(dma_get_seg_boundary(dev
) + 1,
1150 PAGE_SIZE
) >> PAGE_SHIFT
;
1152 for (;i
< max_index
; ++i
) {
1153 unsigned long offset
= dom
->aperture
[i
]->offset
>> PAGE_SHIFT
;
1155 if (dom
->aperture
[i
]->offset
>= dma_mask
)
1158 limit
= iommu_device_max_index(APERTURE_RANGE_PAGES
, offset
,
1159 dma_mask
>> PAGE_SHIFT
);
1161 address
= iommu_area_alloc(dom
->aperture
[i
]->bitmap
,
1162 limit
, next_bit
, pages
, 0,
1163 boundary_size
, align_mask
);
1164 if (address
!= -1) {
1165 address
= dom
->aperture
[i
]->offset
+
1166 (address
<< PAGE_SHIFT
);
1167 dom
->next_address
= address
+ (pages
<< PAGE_SHIFT
);
1177 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
1178 struct dma_ops_domain
*dom
,
1180 unsigned long align_mask
,
1183 unsigned long address
;
1185 #ifdef CONFIG_IOMMU_STRESS
1186 dom
->next_address
= 0;
1187 dom
->need_flush
= true;
1190 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1191 dma_mask
, dom
->next_address
);
1193 if (address
== -1) {
1194 dom
->next_address
= 0;
1195 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1197 dom
->need_flush
= true;
1200 if (unlikely(address
== -1))
1201 address
= DMA_ERROR_CODE
;
1203 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
1209 * The address free function.
1211 * called with domain->lock held
1213 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
1214 unsigned long address
,
1217 unsigned i
= address
>> APERTURE_RANGE_SHIFT
;
1218 struct aperture_range
*range
= dom
->aperture
[i
];
1220 BUG_ON(i
>= APERTURE_MAX_RANGES
|| range
== NULL
);
1222 #ifdef CONFIG_IOMMU_STRESS
1227 if (address
>= dom
->next_address
)
1228 dom
->need_flush
= true;
1230 address
= (address
% APERTURE_RANGE_SIZE
) >> PAGE_SHIFT
;
1232 bitmap_clear(range
->bitmap
, address
, pages
);
1236 /****************************************************************************
1238 * The next functions belong to the domain allocation. A domain is
1239 * allocated for every IOMMU as the default domain. If device isolation
1240 * is enabled, every device get its own domain. The most important thing
1241 * about domains is the page table mapping the DMA address space they
1244 ****************************************************************************/
1247 * This function adds a protection domain to the global protection domain list
1249 static void add_domain_to_list(struct protection_domain
*domain
)
1251 unsigned long flags
;
1253 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1254 list_add(&domain
->list
, &amd_iommu_pd_list
);
1255 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1259 * This function removes a protection domain to the global
1260 * protection domain list
1262 static void del_domain_from_list(struct protection_domain
*domain
)
1264 unsigned long flags
;
1266 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1267 list_del(&domain
->list
);
1268 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1271 static u16
domain_id_alloc(void)
1273 unsigned long flags
;
1276 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1277 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
1279 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1280 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
1283 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1288 static void domain_id_free(int id
)
1290 unsigned long flags
;
1292 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1293 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1294 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
1295 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1298 static void free_pagetable(struct protection_domain
*domain
)
1303 p1
= domain
->pt_root
;
1308 for (i
= 0; i
< 512; ++i
) {
1309 if (!IOMMU_PTE_PRESENT(p1
[i
]))
1312 p2
= IOMMU_PTE_PAGE(p1
[i
]);
1313 for (j
= 0; j
< 512; ++j
) {
1314 if (!IOMMU_PTE_PRESENT(p2
[j
]))
1316 p3
= IOMMU_PTE_PAGE(p2
[j
]);
1317 free_page((unsigned long)p3
);
1320 free_page((unsigned long)p2
);
1323 free_page((unsigned long)p1
);
1325 domain
->pt_root
= NULL
;
1329 * Free a domain, only used if something went wrong in the
1330 * allocation path and we need to free an already allocated page table
1332 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
1339 del_domain_from_list(&dom
->domain
);
1341 free_pagetable(&dom
->domain
);
1343 for (i
= 0; i
< APERTURE_MAX_RANGES
; ++i
) {
1344 if (!dom
->aperture
[i
])
1346 free_page((unsigned long)dom
->aperture
[i
]->bitmap
);
1347 kfree(dom
->aperture
[i
]);
1354 * Allocates a new protection domain usable for the dma_ops functions.
1355 * It also intializes the page table and the address allocator data
1356 * structures required for the dma_ops interface
1358 static struct dma_ops_domain
*dma_ops_domain_alloc(void)
1360 struct dma_ops_domain
*dma_dom
;
1362 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
1366 spin_lock_init(&dma_dom
->domain
.lock
);
1368 dma_dom
->domain
.id
= domain_id_alloc();
1369 if (dma_dom
->domain
.id
== 0)
1371 INIT_LIST_HEAD(&dma_dom
->domain
.dev_list
);
1372 dma_dom
->domain
.mode
= PAGE_MODE_2_LEVEL
;
1373 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
1374 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
1375 dma_dom
->domain
.priv
= dma_dom
;
1376 if (!dma_dom
->domain
.pt_root
)
1379 dma_dom
->need_flush
= false;
1380 dma_dom
->target_dev
= 0xffff;
1382 add_domain_to_list(&dma_dom
->domain
);
1384 if (alloc_new_range(dma_dom
, true, GFP_KERNEL
))
1388 * mark the first page as allocated so we never return 0 as
1389 * a valid dma-address. So we can use 0 as error value
1391 dma_dom
->aperture
[0]->bitmap
[0] = 1;
1392 dma_dom
->next_address
= 0;
1398 dma_ops_domain_free(dma_dom
);
1404 * little helper function to check whether a given protection domain is a
1407 static bool dma_ops_domain(struct protection_domain
*domain
)
1409 return domain
->flags
& PD_DMA_OPS_MASK
;
1412 static void set_dte_entry(u16 devid
, struct protection_domain
*domain
)
1414 u64 pte_root
= virt_to_phys(domain
->pt_root
);
1416 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
1417 << DEV_ENTRY_MODE_SHIFT
;
1418 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
1420 amd_iommu_dev_table
[devid
].data
[2] = domain
->id
;
1421 amd_iommu_dev_table
[devid
].data
[1] = upper_32_bits(pte_root
);
1422 amd_iommu_dev_table
[devid
].data
[0] = lower_32_bits(pte_root
);
1425 static void clear_dte_entry(u16 devid
)
1427 /* remove entry from the device table seen by the hardware */
1428 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
1429 amd_iommu_dev_table
[devid
].data
[1] = 0;
1430 amd_iommu_dev_table
[devid
].data
[2] = 0;
1432 amd_iommu_apply_erratum_63(devid
);
1435 static void do_attach(struct device
*dev
, struct protection_domain
*domain
)
1437 struct iommu_dev_data
*dev_data
;
1438 struct amd_iommu
*iommu
;
1441 devid
= get_device_id(dev
);
1442 iommu
= amd_iommu_rlookup_table
[devid
];
1443 dev_data
= get_dev_data(dev
);
1445 /* Update data structures */
1446 dev_data
->domain
= domain
;
1447 list_add(&dev_data
->list
, &domain
->dev_list
);
1448 set_dte_entry(devid
, domain
);
1450 /* Do reference counting */
1451 domain
->dev_iommu
[iommu
->index
] += 1;
1452 domain
->dev_cnt
+= 1;
1454 /* Flush the DTE entry */
1455 iommu_flush_device(dev
);
1458 static void do_detach(struct device
*dev
)
1460 struct iommu_dev_data
*dev_data
;
1461 struct amd_iommu
*iommu
;
1464 devid
= get_device_id(dev
);
1465 iommu
= amd_iommu_rlookup_table
[devid
];
1466 dev_data
= get_dev_data(dev
);
1468 /* decrease reference counters */
1469 dev_data
->domain
->dev_iommu
[iommu
->index
] -= 1;
1470 dev_data
->domain
->dev_cnt
-= 1;
1472 /* Update data structures */
1473 dev_data
->domain
= NULL
;
1474 list_del(&dev_data
->list
);
1475 clear_dte_entry(devid
);
1477 /* Flush the DTE entry */
1478 iommu_flush_device(dev
);
1482 * If a device is not yet associated with a domain, this function does
1483 * assigns it visible for the hardware
1485 static int __attach_device(struct device
*dev
,
1486 struct protection_domain
*domain
)
1488 struct iommu_dev_data
*dev_data
, *alias_data
;
1490 dev_data
= get_dev_data(dev
);
1491 alias_data
= get_dev_data(dev_data
->alias
);
1497 spin_lock(&domain
->lock
);
1499 /* Some sanity checks */
1500 if (alias_data
->domain
!= NULL
&&
1501 alias_data
->domain
!= domain
)
1504 if (dev_data
->domain
!= NULL
&&
1505 dev_data
->domain
!= domain
)
1508 /* Do real assignment */
1509 if (dev_data
->alias
!= dev
) {
1510 alias_data
= get_dev_data(dev_data
->alias
);
1511 if (alias_data
->domain
== NULL
)
1512 do_attach(dev_data
->alias
, domain
);
1514 atomic_inc(&alias_data
->bind
);
1517 if (dev_data
->domain
== NULL
)
1518 do_attach(dev
, domain
);
1520 atomic_inc(&dev_data
->bind
);
1523 spin_unlock(&domain
->lock
);
1529 * If a device is not yet associated with a domain, this function does
1530 * assigns it visible for the hardware
1532 static int attach_device(struct device
*dev
,
1533 struct protection_domain
*domain
)
1535 unsigned long flags
;
1538 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1539 ret
= __attach_device(dev
, domain
);
1540 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1543 * We might boot into a crash-kernel here. The crashed kernel
1544 * left the caches in the IOMMU dirty. So we have to flush
1545 * here to evict all dirty stuff.
1547 iommu_flush_tlb_pde(domain
);
1553 * Removes a device from a protection domain (unlocked)
1555 static void __detach_device(struct device
*dev
)
1557 struct iommu_dev_data
*dev_data
= get_dev_data(dev
);
1558 struct iommu_dev_data
*alias_data
;
1559 struct protection_domain
*domain
;
1560 unsigned long flags
;
1562 BUG_ON(!dev_data
->domain
);
1564 domain
= dev_data
->domain
;
1566 spin_lock_irqsave(&domain
->lock
, flags
);
1568 if (dev_data
->alias
!= dev
) {
1569 alias_data
= get_dev_data(dev_data
->alias
);
1570 if (atomic_dec_and_test(&alias_data
->bind
))
1571 do_detach(dev_data
->alias
);
1574 if (atomic_dec_and_test(&dev_data
->bind
))
1577 spin_unlock_irqrestore(&domain
->lock
, flags
);
1580 * If we run in passthrough mode the device must be assigned to the
1581 * passthrough domain if it is detached from any other domain.
1582 * Make sure we can deassign from the pt_domain itself.
1584 if (iommu_pass_through
&&
1585 (dev_data
->domain
== NULL
&& domain
!= pt_domain
))
1586 __attach_device(dev
, pt_domain
);
1590 * Removes a device from a protection domain (with devtable_lock held)
1592 static void detach_device(struct device
*dev
)
1594 unsigned long flags
;
1596 /* lock device table */
1597 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1598 __detach_device(dev
);
1599 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1603 * Find out the protection domain structure for a given PCI device. This
1604 * will give us the pointer to the page table root for example.
1606 static struct protection_domain
*domain_for_device(struct device
*dev
)
1608 struct protection_domain
*dom
;
1609 struct iommu_dev_data
*dev_data
, *alias_data
;
1610 unsigned long flags
;
1613 devid
= get_device_id(dev
);
1614 alias
= amd_iommu_alias_table
[devid
];
1615 dev_data
= get_dev_data(dev
);
1616 alias_data
= get_dev_data(dev_data
->alias
);
1620 read_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1621 dom
= dev_data
->domain
;
1623 alias_data
->domain
!= NULL
) {
1624 __attach_device(dev
, alias_data
->domain
);
1625 dom
= alias_data
->domain
;
1628 read_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1633 static int device_change_notifier(struct notifier_block
*nb
,
1634 unsigned long action
, void *data
)
1636 struct device
*dev
= data
;
1638 struct protection_domain
*domain
;
1639 struct dma_ops_domain
*dma_domain
;
1640 struct amd_iommu
*iommu
;
1641 unsigned long flags
;
1643 if (!check_device(dev
))
1646 devid
= get_device_id(dev
);
1647 iommu
= amd_iommu_rlookup_table
[devid
];
1650 case BUS_NOTIFY_UNBOUND_DRIVER
:
1652 domain
= domain_for_device(dev
);
1656 if (iommu_pass_through
)
1660 case BUS_NOTIFY_ADD_DEVICE
:
1662 iommu_init_device(dev
);
1664 domain
= domain_for_device(dev
);
1666 /* allocate a protection domain if a device is added */
1667 dma_domain
= find_protection_domain(devid
);
1670 dma_domain
= dma_ops_domain_alloc();
1673 dma_domain
->target_dev
= devid
;
1675 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
1676 list_add_tail(&dma_domain
->list
, &iommu_pd_list
);
1677 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
1680 case BUS_NOTIFY_DEL_DEVICE
:
1682 iommu_uninit_device(dev
);
1688 iommu_flush_device(dev
);
1689 iommu_completion_wait(iommu
);
1695 static struct notifier_block device_nb
= {
1696 .notifier_call
= device_change_notifier
,
1699 void amd_iommu_init_notifier(void)
1701 bus_register_notifier(&pci_bus_type
, &device_nb
);
1704 /*****************************************************************************
1706 * The next functions belong to the dma_ops mapping/unmapping code.
1708 *****************************************************************************/
1711 * In the dma_ops path we only have the struct device. This function
1712 * finds the corresponding IOMMU, the protection domain and the
1713 * requestor id for a given device.
1714 * If the device is not yet associated with a domain this is also done
1717 static struct protection_domain
*get_domain(struct device
*dev
)
1719 struct protection_domain
*domain
;
1720 struct dma_ops_domain
*dma_dom
;
1721 u16 devid
= get_device_id(dev
);
1723 if (!check_device(dev
))
1724 return ERR_PTR(-EINVAL
);
1726 domain
= domain_for_device(dev
);
1727 if (domain
!= NULL
&& !dma_ops_domain(domain
))
1728 return ERR_PTR(-EBUSY
);
1733 /* Device not bount yet - bind it */
1734 dma_dom
= find_protection_domain(devid
);
1736 dma_dom
= amd_iommu_rlookup_table
[devid
]->default_dom
;
1737 attach_device(dev
, &dma_dom
->domain
);
1738 DUMP_printk("Using protection domain %d for device %s\n",
1739 dma_dom
->domain
.id
, dev_name(dev
));
1741 return &dma_dom
->domain
;
1744 static void update_device_table(struct protection_domain
*domain
)
1746 struct iommu_dev_data
*dev_data
;
1748 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
1749 u16 devid
= get_device_id(dev_data
->dev
);
1750 set_dte_entry(devid
, domain
);
1754 static void update_domain(struct protection_domain
*domain
)
1756 if (!domain
->updated
)
1759 update_device_table(domain
);
1760 iommu_flush_domain_devices(domain
);
1761 iommu_flush_tlb_pde(domain
);
1763 domain
->updated
= false;
1767 * This function fetches the PTE for a given address in the aperture
1769 static u64
* dma_ops_get_pte(struct dma_ops_domain
*dom
,
1770 unsigned long address
)
1772 struct aperture_range
*aperture
;
1773 u64
*pte
, *pte_page
;
1775 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
1779 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
1781 pte
= alloc_pte(&dom
->domain
, address
, PAGE_SIZE
, &pte_page
,
1783 aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)] = pte_page
;
1785 pte
+= PM_LEVEL_INDEX(0, address
);
1787 update_domain(&dom
->domain
);
1793 * This is the generic map function. It maps one 4kb page at paddr to
1794 * the given address in the DMA address space for the domain.
1796 static dma_addr_t
dma_ops_domain_map(struct dma_ops_domain
*dom
,
1797 unsigned long address
,
1803 WARN_ON(address
> dom
->aperture_size
);
1807 pte
= dma_ops_get_pte(dom
, address
);
1809 return DMA_ERROR_CODE
;
1811 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1813 if (direction
== DMA_TO_DEVICE
)
1814 __pte
|= IOMMU_PTE_IR
;
1815 else if (direction
== DMA_FROM_DEVICE
)
1816 __pte
|= IOMMU_PTE_IW
;
1817 else if (direction
== DMA_BIDIRECTIONAL
)
1818 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
1824 return (dma_addr_t
)address
;
1828 * The generic unmapping function for on page in the DMA address space.
1830 static void dma_ops_domain_unmap(struct dma_ops_domain
*dom
,
1831 unsigned long address
)
1833 struct aperture_range
*aperture
;
1836 if (address
>= dom
->aperture_size
)
1839 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
1843 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
1847 pte
+= PM_LEVEL_INDEX(0, address
);
1855 * This function contains common code for mapping of a physically
1856 * contiguous memory region into DMA address space. It is used by all
1857 * mapping functions provided with this IOMMU driver.
1858 * Must be called with the domain lock held.
1860 static dma_addr_t
__map_single(struct device
*dev
,
1861 struct dma_ops_domain
*dma_dom
,
1868 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
1869 dma_addr_t address
, start
, ret
;
1871 unsigned long align_mask
= 0;
1874 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
1877 INC_STATS_COUNTER(total_map_requests
);
1880 INC_STATS_COUNTER(cross_page
);
1883 align_mask
= (1UL << get_order(size
)) - 1;
1886 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
, align_mask
,
1888 if (unlikely(address
== DMA_ERROR_CODE
)) {
1890 * setting next_address here will let the address
1891 * allocator only scan the new allocated range in the
1892 * first run. This is a small optimization.
1894 dma_dom
->next_address
= dma_dom
->aperture_size
;
1896 if (alloc_new_range(dma_dom
, false, GFP_ATOMIC
))
1900 * aperture was successfully enlarged by 128 MB, try
1907 for (i
= 0; i
< pages
; ++i
) {
1908 ret
= dma_ops_domain_map(dma_dom
, start
, paddr
, dir
);
1909 if (ret
== DMA_ERROR_CODE
)
1917 ADD_STATS_COUNTER(alloced_io_mem
, size
);
1919 if (unlikely(dma_dom
->need_flush
&& !amd_iommu_unmap_flush
)) {
1920 iommu_flush_tlb(&dma_dom
->domain
);
1921 dma_dom
->need_flush
= false;
1922 } else if (unlikely(amd_iommu_np_cache
))
1923 iommu_flush_pages(&dma_dom
->domain
, address
, size
);
1930 for (--i
; i
>= 0; --i
) {
1932 dma_ops_domain_unmap(dma_dom
, start
);
1935 dma_ops_free_addresses(dma_dom
, address
, pages
);
1937 return DMA_ERROR_CODE
;
1941 * Does the reverse of the __map_single function. Must be called with
1942 * the domain lock held too
1944 static void __unmap_single(struct dma_ops_domain
*dma_dom
,
1945 dma_addr_t dma_addr
,
1949 dma_addr_t i
, start
;
1952 if ((dma_addr
== DMA_ERROR_CODE
) ||
1953 (dma_addr
+ size
> dma_dom
->aperture_size
))
1956 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
1957 dma_addr
&= PAGE_MASK
;
1960 for (i
= 0; i
< pages
; ++i
) {
1961 dma_ops_domain_unmap(dma_dom
, start
);
1965 SUB_STATS_COUNTER(alloced_io_mem
, size
);
1967 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
1969 if (amd_iommu_unmap_flush
|| dma_dom
->need_flush
) {
1970 iommu_flush_pages(&dma_dom
->domain
, dma_addr
, size
);
1971 dma_dom
->need_flush
= false;
1976 * The exported map_single function for dma_ops.
1978 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
1979 unsigned long offset
, size_t size
,
1980 enum dma_data_direction dir
,
1981 struct dma_attrs
*attrs
)
1983 unsigned long flags
;
1984 struct protection_domain
*domain
;
1987 phys_addr_t paddr
= page_to_phys(page
) + offset
;
1989 INC_STATS_COUNTER(cnt_map_single
);
1991 domain
= get_domain(dev
);
1992 if (PTR_ERR(domain
) == -EINVAL
)
1993 return (dma_addr_t
)paddr
;
1994 else if (IS_ERR(domain
))
1995 return DMA_ERROR_CODE
;
1997 dma_mask
= *dev
->dma_mask
;
1999 spin_lock_irqsave(&domain
->lock
, flags
);
2001 addr
= __map_single(dev
, domain
->priv
, paddr
, size
, dir
, false,
2003 if (addr
== DMA_ERROR_CODE
)
2006 iommu_flush_complete(domain
);
2009 spin_unlock_irqrestore(&domain
->lock
, flags
);
2015 * The exported unmap_single function for dma_ops.
2017 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
2018 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
2020 unsigned long flags
;
2021 struct protection_domain
*domain
;
2023 INC_STATS_COUNTER(cnt_unmap_single
);
2025 domain
= get_domain(dev
);
2029 spin_lock_irqsave(&domain
->lock
, flags
);
2031 __unmap_single(domain
->priv
, dma_addr
, size
, dir
);
2033 iommu_flush_complete(domain
);
2035 spin_unlock_irqrestore(&domain
->lock
, flags
);
2039 * This is a special map_sg function which is used if we should map a
2040 * device which is not handled by an AMD IOMMU in the system.
2042 static int map_sg_no_iommu(struct device
*dev
, struct scatterlist
*sglist
,
2043 int nelems
, int dir
)
2045 struct scatterlist
*s
;
2048 for_each_sg(sglist
, s
, nelems
, i
) {
2049 s
->dma_address
= (dma_addr_t
)sg_phys(s
);
2050 s
->dma_length
= s
->length
;
2057 * The exported map_sg function for dma_ops (handles scatter-gather
2060 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
2061 int nelems
, enum dma_data_direction dir
,
2062 struct dma_attrs
*attrs
)
2064 unsigned long flags
;
2065 struct protection_domain
*domain
;
2067 struct scatterlist
*s
;
2069 int mapped_elems
= 0;
2072 INC_STATS_COUNTER(cnt_map_sg
);
2074 domain
= get_domain(dev
);
2075 if (PTR_ERR(domain
) == -EINVAL
)
2076 return map_sg_no_iommu(dev
, sglist
, nelems
, dir
);
2077 else if (IS_ERR(domain
))
2080 dma_mask
= *dev
->dma_mask
;
2082 spin_lock_irqsave(&domain
->lock
, flags
);
2084 for_each_sg(sglist
, s
, nelems
, i
) {
2087 s
->dma_address
= __map_single(dev
, domain
->priv
,
2088 paddr
, s
->length
, dir
, false,
2091 if (s
->dma_address
) {
2092 s
->dma_length
= s
->length
;
2098 iommu_flush_complete(domain
);
2101 spin_unlock_irqrestore(&domain
->lock
, flags
);
2103 return mapped_elems
;
2105 for_each_sg(sglist
, s
, mapped_elems
, i
) {
2107 __unmap_single(domain
->priv
, s
->dma_address
,
2108 s
->dma_length
, dir
);
2109 s
->dma_address
= s
->dma_length
= 0;
2118 * The exported map_sg function for dma_ops (handles scatter-gather
2121 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
2122 int nelems
, enum dma_data_direction dir
,
2123 struct dma_attrs
*attrs
)
2125 unsigned long flags
;
2126 struct protection_domain
*domain
;
2127 struct scatterlist
*s
;
2130 INC_STATS_COUNTER(cnt_unmap_sg
);
2132 domain
= get_domain(dev
);
2136 spin_lock_irqsave(&domain
->lock
, flags
);
2138 for_each_sg(sglist
, s
, nelems
, i
) {
2139 __unmap_single(domain
->priv
, s
->dma_address
,
2140 s
->dma_length
, dir
);
2141 s
->dma_address
= s
->dma_length
= 0;
2144 iommu_flush_complete(domain
);
2146 spin_unlock_irqrestore(&domain
->lock
, flags
);
2150 * The exported alloc_coherent function for dma_ops.
2152 static void *alloc_coherent(struct device
*dev
, size_t size
,
2153 dma_addr_t
*dma_addr
, gfp_t flag
)
2155 unsigned long flags
;
2157 struct protection_domain
*domain
;
2159 u64 dma_mask
= dev
->coherent_dma_mask
;
2161 INC_STATS_COUNTER(cnt_alloc_coherent
);
2163 domain
= get_domain(dev
);
2164 if (PTR_ERR(domain
) == -EINVAL
) {
2165 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
2166 *dma_addr
= __pa(virt_addr
);
2168 } else if (IS_ERR(domain
))
2171 dma_mask
= dev
->coherent_dma_mask
;
2172 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
2175 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
2179 paddr
= virt_to_phys(virt_addr
);
2182 dma_mask
= *dev
->dma_mask
;
2184 spin_lock_irqsave(&domain
->lock
, flags
);
2186 *dma_addr
= __map_single(dev
, domain
->priv
, paddr
,
2187 size
, DMA_BIDIRECTIONAL
, true, dma_mask
);
2189 if (*dma_addr
== DMA_ERROR_CODE
) {
2190 spin_unlock_irqrestore(&domain
->lock
, flags
);
2194 iommu_flush_complete(domain
);
2196 spin_unlock_irqrestore(&domain
->lock
, flags
);
2202 free_pages((unsigned long)virt_addr
, get_order(size
));
2208 * The exported free_coherent function for dma_ops.
2210 static void free_coherent(struct device
*dev
, size_t size
,
2211 void *virt_addr
, dma_addr_t dma_addr
)
2213 unsigned long flags
;
2214 struct protection_domain
*domain
;
2216 INC_STATS_COUNTER(cnt_free_coherent
);
2218 domain
= get_domain(dev
);
2222 spin_lock_irqsave(&domain
->lock
, flags
);
2224 __unmap_single(domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
2226 iommu_flush_complete(domain
);
2228 spin_unlock_irqrestore(&domain
->lock
, flags
);
2231 free_pages((unsigned long)virt_addr
, get_order(size
));
2235 * This function is called by the DMA layer to find out if we can handle a
2236 * particular device. It is part of the dma_ops.
2238 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
2240 return check_device(dev
);
2244 * The function for pre-allocating protection domains.
2246 * If the driver core informs the DMA layer if a driver grabs a device
2247 * we don't need to preallocate the protection domains anymore.
2248 * For now we have to.
2250 static void prealloc_protection_domains(void)
2252 struct pci_dev
*dev
= NULL
;
2253 struct dma_ops_domain
*dma_dom
;
2256 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
2258 /* Do we handle this device? */
2259 if (!check_device(&dev
->dev
))
2262 /* Is there already any domain for it? */
2263 if (domain_for_device(&dev
->dev
))
2266 devid
= get_device_id(&dev
->dev
);
2268 dma_dom
= dma_ops_domain_alloc();
2271 init_unity_mappings_for_device(dma_dom
, devid
);
2272 dma_dom
->target_dev
= devid
;
2274 attach_device(&dev
->dev
, &dma_dom
->domain
);
2276 list_add_tail(&dma_dom
->list
, &iommu_pd_list
);
2280 static struct dma_map_ops amd_iommu_dma_ops
= {
2281 .alloc_coherent
= alloc_coherent
,
2282 .free_coherent
= free_coherent
,
2283 .map_page
= map_page
,
2284 .unmap_page
= unmap_page
,
2286 .unmap_sg
= unmap_sg
,
2287 .dma_supported
= amd_iommu_dma_supported
,
2291 * The function which clues the AMD IOMMU driver into dma_ops.
2294 void __init
amd_iommu_init_api(void)
2296 register_iommu(&amd_iommu_ops
);
2299 int __init
amd_iommu_init_dma_ops(void)
2301 struct amd_iommu
*iommu
;
2305 * first allocate a default protection domain for every IOMMU we
2306 * found in the system. Devices not assigned to any other
2307 * protection domain will be assigned to the default one.
2309 for_each_iommu(iommu
) {
2310 iommu
->default_dom
= dma_ops_domain_alloc();
2311 if (iommu
->default_dom
== NULL
)
2313 iommu
->default_dom
->domain
.flags
|= PD_DEFAULT_MASK
;
2314 ret
= iommu_init_unity_mappings(iommu
);
2320 * Pre-allocate the protection domains for each device.
2322 prealloc_protection_domains();
2326 #ifdef CONFIG_GART_IOMMU
2327 gart_iommu_aperture_disabled
= 1;
2328 gart_iommu_aperture
= 0;
2331 /* Make the driver finally visible to the drivers */
2332 dma_ops
= &amd_iommu_dma_ops
;
2334 amd_iommu_stats_init();
2340 for_each_iommu(iommu
) {
2341 if (iommu
->default_dom
)
2342 dma_ops_domain_free(iommu
->default_dom
);
2348 /*****************************************************************************
2350 * The following functions belong to the exported interface of AMD IOMMU
2352 * This interface allows access to lower level functions of the IOMMU
2353 * like protection domain handling and assignement of devices to domains
2354 * which is not possible with the dma_ops interface.
2356 *****************************************************************************/
2358 static void cleanup_domain(struct protection_domain
*domain
)
2360 struct iommu_dev_data
*dev_data
, *next
;
2361 unsigned long flags
;
2363 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2365 list_for_each_entry_safe(dev_data
, next
, &domain
->dev_list
, list
) {
2366 struct device
*dev
= dev_data
->dev
;
2369 atomic_set(&dev_data
->bind
, 0);
2372 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2375 static void protection_domain_free(struct protection_domain
*domain
)
2380 del_domain_from_list(domain
);
2383 domain_id_free(domain
->id
);
2388 static struct protection_domain
*protection_domain_alloc(void)
2390 struct protection_domain
*domain
;
2392 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
2396 spin_lock_init(&domain
->lock
);
2397 domain
->id
= domain_id_alloc();
2400 INIT_LIST_HEAD(&domain
->dev_list
);
2402 add_domain_to_list(domain
);
2412 static int amd_iommu_domain_init(struct iommu_domain
*dom
)
2414 struct protection_domain
*domain
;
2416 domain
= protection_domain_alloc();
2420 domain
->mode
= PAGE_MODE_3_LEVEL
;
2421 domain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
2422 if (!domain
->pt_root
)
2430 protection_domain_free(domain
);
2435 static void amd_iommu_domain_destroy(struct iommu_domain
*dom
)
2437 struct protection_domain
*domain
= dom
->priv
;
2442 if (domain
->dev_cnt
> 0)
2443 cleanup_domain(domain
);
2445 BUG_ON(domain
->dev_cnt
!= 0);
2447 free_pagetable(domain
);
2449 domain_id_free(domain
->id
);
2456 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
2459 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
2460 struct amd_iommu
*iommu
;
2463 if (!check_device(dev
))
2466 devid
= get_device_id(dev
);
2468 if (dev_data
->domain
!= NULL
)
2471 iommu
= amd_iommu_rlookup_table
[devid
];
2475 iommu_flush_device(dev
);
2476 iommu_completion_wait(iommu
);
2479 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
2482 struct protection_domain
*domain
= dom
->priv
;
2483 struct iommu_dev_data
*dev_data
;
2484 struct amd_iommu
*iommu
;
2488 if (!check_device(dev
))
2491 dev_data
= dev
->archdata
.iommu
;
2493 devid
= get_device_id(dev
);
2495 iommu
= amd_iommu_rlookup_table
[devid
];
2499 if (dev_data
->domain
)
2502 ret
= attach_device(dev
, domain
);
2504 iommu_completion_wait(iommu
);
2509 static int amd_iommu_map(struct iommu_domain
*dom
, unsigned long iova
,
2510 phys_addr_t paddr
, int gfp_order
, int iommu_prot
)
2512 unsigned long page_size
= 0x1000UL
<< gfp_order
;
2513 struct protection_domain
*domain
= dom
->priv
;
2516 if (iommu_prot
& IOMMU_READ
)
2517 prot
|= IOMMU_PROT_IR
;
2518 if (iommu_prot
& IOMMU_WRITE
)
2519 prot
|= IOMMU_PROT_IW
;
2521 return iommu_map_page(domain
, iova
, paddr
, prot
, page_size
);
2524 static int amd_iommu_unmap(struct iommu_domain
*dom
, unsigned long iova
,
2527 struct protection_domain
*domain
= dom
->priv
;
2528 unsigned long page_size
, unmap_size
;
2530 page_size
= 0x1000UL
<< gfp_order
;
2531 unmap_size
= iommu_unmap_page(domain
, iova
, page_size
);
2533 return get_order(unmap_size
);
2536 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
2539 struct protection_domain
*domain
= dom
->priv
;
2540 unsigned long offset_mask
;
2544 pte
= fetch_pte(domain
, iova
);
2546 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
2549 if (PM_PTE_LEVEL(*pte
) == 0)
2550 offset_mask
= PAGE_SIZE
- 1;
2552 offset_mask
= PTE_PAGE_SIZE(*pte
) - 1;
2554 __pte
= *pte
& PM_ADDR_MASK
;
2555 paddr
= (__pte
& ~offset_mask
) | (iova
& offset_mask
);
2560 static int amd_iommu_domain_has_cap(struct iommu_domain
*domain
,
2566 static struct iommu_ops amd_iommu_ops
= {
2567 .domain_init
= amd_iommu_domain_init
,
2568 .domain_destroy
= amd_iommu_domain_destroy
,
2569 .attach_dev
= amd_iommu_attach_device
,
2570 .detach_dev
= amd_iommu_detach_device
,
2571 .map
= amd_iommu_map
,
2572 .unmap
= amd_iommu_unmap
,
2573 .iova_to_phys
= amd_iommu_iova_to_phys
,
2574 .domain_has_cap
= amd_iommu_domain_has_cap
,
2577 /*****************************************************************************
2579 * The next functions do a basic initialization of IOMMU for pass through
2582 * In passthrough mode the IOMMU is initialized and enabled but not used for
2583 * DMA-API translation.
2585 *****************************************************************************/
2587 int __init
amd_iommu_init_passthrough(void)
2589 struct amd_iommu
*iommu
;
2590 struct pci_dev
*dev
= NULL
;
2593 /* allocate passthrough domain */
2594 pt_domain
= protection_domain_alloc();
2598 pt_domain
->mode
|= PAGE_MODE_NONE
;
2600 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
2602 if (!check_device(&dev
->dev
))
2605 devid
= get_device_id(&dev
->dev
);
2607 iommu
= amd_iommu_rlookup_table
[devid
];
2611 attach_device(&dev
->dev
, pt_domain
);
2614 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");