2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/interrupt.h>
46 #include <linux/list.h>
47 #include <linux/dma-mapping.h>
49 #include <linux/usb/ch9.h>
50 #include <linux/usb/gadget.h>
56 static void dwc3_ep0_inspect_setup(struct dwc3
*dwc
,
57 const struct dwc3_event_depevt
*event
);
59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state
)
68 case EP0_STATUS_PHASE
:
69 return "Status Phase";
75 static int dwc3_ep0_start_trans(struct dwc3
*dwc
, u8 epnum
, dma_addr_t buf_dma
,
78 struct dwc3_gadget_ep_cmd_params params
;
79 struct dwc3_trb_hw
*trb_hw
;
85 dep
= dwc
->eps
[epnum
];
86 if (dep
->flags
& DWC3_EP_BUSY
) {
87 dev_vdbg(dwc
->dev
, "%s: still busy\n", dep
->name
);
91 trb_hw
= dwc
->ep0_trb
;
92 memset(&trb
, 0, sizeof(trb
));
103 dwc3_trb_to_hw(&trb
, trb_hw
);
105 memset(¶ms
, 0, sizeof(params
));
106 params
.param0
= upper_32_bits(dwc
->ep0_trb_addr
);
107 params
.param1
= lower_32_bits(dwc
->ep0_trb_addr
);
109 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
110 DWC3_DEPCMD_STARTTRANSFER
, ¶ms
);
112 dev_dbg(dwc
->dev
, "failed to send STARTTRANSFER command\n");
116 dep
->flags
|= DWC3_EP_BUSY
;
117 dep
->res_trans_idx
= dwc3_gadget_ep_get_transfer_index(dwc
,
120 dwc
->ep0_next_event
= DWC3_EP0_COMPLETE
;
125 static int __dwc3_gadget_ep0_queue(struct dwc3_ep
*dep
,
126 struct dwc3_request
*req
)
130 req
->request
.actual
= 0;
131 req
->request
.status
= -EINPROGRESS
;
132 req
->epnum
= dep
->number
;
134 list_add_tail(&req
->list
, &dep
->request_list
);
137 * Gadget driver might not be quick enough to queue a request
138 * before we get a Transfer Not Ready event on this endpoint.
140 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
141 * flag is set, it's telling us that as soon as Gadget queues the
142 * required request, we should kick the transfer here because the
143 * IRQ we were waiting for is long gone.
145 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
146 struct dwc3
*dwc
= dep
->dwc
;
150 direction
= !!(dep
->flags
& DWC3_EP0_DIR_IN
);
152 if (dwc
->ep0state
!= EP0_DATA_PHASE
) {
153 dev_WARN(dwc
->dev
, "Unexpected pending request\n");
157 ret
= dwc3_ep0_start_trans(dwc
, direction
,
158 req
->request
.dma
, req
->request
.length
,
159 DWC3_TRBCTL_CONTROL_DATA
);
160 dep
->flags
&= ~(DWC3_EP_PENDING_REQUEST
|
167 int dwc3_gadget_ep0_queue(struct usb_ep
*ep
, struct usb_request
*request
,
170 struct dwc3_request
*req
= to_dwc3_request(request
);
171 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
172 struct dwc3
*dwc
= dep
->dwc
;
178 spin_lock_irqsave(&dwc
->lock
, flags
);
180 dev_dbg(dwc
->dev
, "trying to queue request %p to disabled %s\n",
186 /* we share one TRB for ep0/1 */
187 if (!list_empty(&dwc
->eps
[0]->request_list
) ||
188 !list_empty(&dwc
->eps
[1]->request_list
) ||
189 dwc
->ep0_status_pending
) {
194 dev_vdbg(dwc
->dev
, "queueing request %p to %s length %d, state '%s'\n",
195 request
, dep
->name
, request
->length
,
196 dwc3_ep0_state_string(dwc
->ep0state
));
198 ret
= __dwc3_gadget_ep0_queue(dep
, req
);
201 spin_unlock_irqrestore(&dwc
->lock
, flags
);
206 static void dwc3_ep0_stall_and_restart(struct dwc3
*dwc
)
208 struct dwc3_ep
*dep
= dwc
->eps
[0];
210 /* stall is always issued on EP0 */
211 __dwc3_gadget_ep_set_halt(dwc
->eps
[0], 1);
212 dwc
->eps
[0]->flags
= DWC3_EP_ENABLED
;
214 if (!list_empty(&dep
->request_list
)) {
215 struct dwc3_request
*req
;
217 req
= next_request(&dep
->request_list
);
218 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
221 dwc
->ep0state
= EP0_SETUP_PHASE
;
222 dwc3_ep0_out_start(dwc
);
225 void dwc3_ep0_out_start(struct dwc3
*dwc
)
229 ret
= dwc3_ep0_start_trans(dwc
, 0, dwc
->ctrl_req_addr
, 8,
230 DWC3_TRBCTL_CONTROL_SETUP
);
234 static struct dwc3_ep
*dwc3_wIndex_to_dep(struct dwc3
*dwc
, __le16 wIndex_le
)
237 u32 windex
= le16_to_cpu(wIndex_le
);
240 epnum
= (windex
& USB_ENDPOINT_NUMBER_MASK
) << 1;
241 if ((windex
& USB_ENDPOINT_DIR_MASK
) == USB_DIR_IN
)
244 dep
= dwc
->eps
[epnum
];
245 if (dep
->flags
& DWC3_EP_ENABLED
)
251 static void dwc3_ep0_send_status_response(struct dwc3
*dwc
)
253 dwc3_ep0_start_trans(dwc
, 1, dwc
->setup_buf_addr
,
254 dwc
->ep0_usb_req
.length
,
255 DWC3_TRBCTL_CONTROL_DATA
);
261 static int dwc3_ep0_handle_status(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
266 __le16
*response_pkt
;
268 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
270 case USB_RECIP_DEVICE
:
272 * We are self-powered. U1/U2/LTM will be set later
273 * once we handle this states. RemoteWakeup is 0 on SS
275 usb_status
|= dwc
->is_selfpowered
<< USB_DEVICE_SELF_POWERED
;
278 case USB_RECIP_INTERFACE
:
280 * Function Remote Wake Capable D0
281 * Function Remote Wakeup D1
285 case USB_RECIP_ENDPOINT
:
286 dep
= dwc3_wIndex_to_dep(dwc
, ctrl
->wIndex
);
290 if (dep
->flags
& DWC3_EP_STALL
)
291 usb_status
= 1 << USB_ENDPOINT_HALT
;
297 response_pkt
= (__le16
*) dwc
->setup_buf
;
298 *response_pkt
= cpu_to_le16(usb_status
);
299 dwc
->ep0_usb_req
.length
= sizeof(*response_pkt
);
300 dwc
->ep0_status_pending
= 1;
305 static int dwc3_ep0_handle_feature(struct dwc3
*dwc
,
306 struct usb_ctrlrequest
*ctrl
, int set
)
316 wValue
= le16_to_cpu(ctrl
->wValue
);
317 wIndex
= le16_to_cpu(ctrl
->wIndex
);
318 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
320 case USB_RECIP_DEVICE
:
323 * 9.4.1 says only only for SS, in AddressState only for
324 * default control pipe
327 case USB_DEVICE_U1_ENABLE
:
328 case USB_DEVICE_U2_ENABLE
:
329 case USB_DEVICE_LTM_ENABLE
:
330 if (dwc
->dev_state
!= DWC3_CONFIGURED_STATE
)
332 if (dwc
->speed
!= DWC3_DSTS_SUPERSPEED
)
336 /* XXX add U[12] & LTM */
338 case USB_DEVICE_REMOTE_WAKEUP
:
340 case USB_DEVICE_U1_ENABLE
:
342 case USB_DEVICE_U2_ENABLE
:
344 case USB_DEVICE_LTM_ENABLE
:
347 case USB_DEVICE_TEST_MODE
:
348 if ((wIndex
& 0xff) != 0)
354 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
355 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
368 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
375 case USB_RECIP_INTERFACE
:
377 case USB_INTRF_FUNC_SUSPEND
:
378 if (wIndex
& USB_INTRF_FUNC_SUSPEND_LP
)
379 /* XXX enable Low power suspend */
381 if (wIndex
& USB_INTRF_FUNC_SUSPEND_RW
)
382 /* XXX enable remote wakeup */
390 case USB_RECIP_ENDPOINT
:
392 case USB_ENDPOINT_HALT
:
394 dep
= dwc3_wIndex_to_dep(dwc
, ctrl
->wIndex
);
397 ret
= __dwc3_gadget_ep_set_halt(dep
, set
);
413 static int dwc3_ep0_set_address(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
418 addr
= le16_to_cpu(ctrl
->wValue
);
422 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
423 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
424 reg
|= DWC3_DCFG_DEVADDR(addr
);
425 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
428 dwc
->dev_state
= DWC3_ADDRESS_STATE
;
430 dwc
->dev_state
= DWC3_DEFAULT_STATE
;
435 static int dwc3_ep0_delegate_req(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
439 spin_unlock(&dwc
->lock
);
440 ret
= dwc
->gadget_driver
->setup(&dwc
->gadget
, ctrl
);
441 spin_lock(&dwc
->lock
);
445 static int dwc3_ep0_set_config(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
450 dwc
->start_config_issued
= false;
451 cfg
= le16_to_cpu(ctrl
->wValue
);
453 switch (dwc
->dev_state
) {
454 case DWC3_DEFAULT_STATE
:
458 case DWC3_ADDRESS_STATE
:
459 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
460 /* if the cfg matches and the cfg is non zero */
462 dwc
->dev_state
= DWC3_CONFIGURED_STATE
;
465 case DWC3_CONFIGURED_STATE
:
466 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
468 dwc
->dev_state
= DWC3_ADDRESS_STATE
;
474 static int dwc3_ep0_std_request(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
478 switch (ctrl
->bRequest
) {
479 case USB_REQ_GET_STATUS
:
480 dev_vdbg(dwc
->dev
, "USB_REQ_GET_STATUS\n");
481 ret
= dwc3_ep0_handle_status(dwc
, ctrl
);
483 case USB_REQ_CLEAR_FEATURE
:
484 dev_vdbg(dwc
->dev
, "USB_REQ_CLEAR_FEATURE\n");
485 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 0);
487 case USB_REQ_SET_FEATURE
:
488 dev_vdbg(dwc
->dev
, "USB_REQ_SET_FEATURE\n");
489 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 1);
491 case USB_REQ_SET_ADDRESS
:
492 dev_vdbg(dwc
->dev
, "USB_REQ_SET_ADDRESS\n");
493 ret
= dwc3_ep0_set_address(dwc
, ctrl
);
495 case USB_REQ_SET_CONFIGURATION
:
496 dev_vdbg(dwc
->dev
, "USB_REQ_SET_CONFIGURATION\n");
497 ret
= dwc3_ep0_set_config(dwc
, ctrl
);
500 dev_vdbg(dwc
->dev
, "Forwarding to gadget driver\n");
501 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
508 static void dwc3_ep0_inspect_setup(struct dwc3
*dwc
,
509 const struct dwc3_event_depevt
*event
)
511 struct usb_ctrlrequest
*ctrl
= dwc
->ctrl_req
;
515 if (!dwc
->gadget_driver
)
518 len
= le16_to_cpu(ctrl
->wLength
);
520 dwc
->three_stage_setup
= false;
521 dwc
->ep0_expect_in
= false;
522 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
524 dwc
->three_stage_setup
= true;
525 dwc
->ep0_expect_in
= !!(ctrl
->bRequestType
& USB_DIR_IN
);
526 dwc
->ep0_next_event
= DWC3_EP0_NRDY_DATA
;
529 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
)
530 ret
= dwc3_ep0_std_request(dwc
, ctrl
);
532 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
538 dwc3_ep0_stall_and_restart(dwc
);
541 static void dwc3_ep0_complete_data(struct dwc3
*dwc
,
542 const struct dwc3_event_depevt
*event
)
544 struct dwc3_request
*r
= NULL
;
545 struct usb_request
*ur
;
551 epnum
= event
->endpoint_number
;
552 dep
= dwc
->eps
[epnum
];
554 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
556 if (!dwc
->ep0_status_pending
) {
557 r
= next_request(&dwc
->eps
[0]->request_list
);
560 ur
= &dwc
->ep0_usb_req
;
561 dwc
->ep0_status_pending
= 0;
564 dwc3_trb_to_nat(dwc
->ep0_trb
, &trb
);
566 if (dwc
->ep0_bounced
) {
567 struct dwc3_ep
*ep0
= dwc
->eps
[0];
569 transferred
= min_t(u32
, ur
->length
,
570 ep0
->endpoint
.maxpacket
- trb
.length
);
571 memcpy(ur
->buf
, dwc
->ep0_bounce
, transferred
);
572 dwc
->ep0_bounced
= false;
574 transferred
= ur
->length
- trb
.length
;
575 ur
->actual
+= transferred
;
578 if ((epnum
& 1) && ur
->actual
< ur
->length
) {
579 /* for some reason we did not get everything out */
581 dwc3_ep0_stall_and_restart(dwc
);
584 * handle the case where we have to send a zero packet. This
585 * seems to be case when req.length > maxpacket. Could it be?
588 dwc3_gadget_giveback(dep
, r
, 0);
592 static void dwc3_ep0_complete_req(struct dwc3
*dwc
,
593 const struct dwc3_event_depevt
*event
)
595 struct dwc3_request
*r
;
600 if (!list_empty(&dep
->request_list
)) {
601 r
= next_request(&dep
->request_list
);
603 dwc3_gadget_giveback(dep
, r
, 0);
606 dwc
->ep0state
= EP0_SETUP_PHASE
;
607 dwc3_ep0_out_start(dwc
);
610 static void dwc3_ep0_xfer_complete(struct dwc3
*dwc
,
611 const struct dwc3_event_depevt
*event
)
613 struct dwc3_ep
*dep
= dwc
->eps
[event
->endpoint_number
];
615 dep
->flags
&= ~DWC3_EP_BUSY
;
617 switch (dwc
->ep0state
) {
618 case EP0_SETUP_PHASE
:
619 dev_vdbg(dwc
->dev
, "Inspecting Setup Bytes\n");
620 dwc3_ep0_inspect_setup(dwc
, event
);
624 dev_vdbg(dwc
->dev
, "Data Phase\n");
625 dwc3_ep0_complete_data(dwc
, event
);
628 case EP0_STATUS_PHASE
:
629 dev_vdbg(dwc
->dev
, "Status Phase\n");
630 dwc3_ep0_complete_req(dwc
, event
);
633 WARN(true, "UNKNOWN ep0state %d\n", dwc
->ep0state
);
637 static void dwc3_ep0_do_control_setup(struct dwc3
*dwc
,
638 const struct dwc3_event_depevt
*event
)
640 dwc
->ep0state
= EP0_SETUP_PHASE
;
641 dwc3_ep0_out_start(dwc
);
644 static void dwc3_ep0_do_control_data(struct dwc3
*dwc
,
645 const struct dwc3_event_depevt
*event
)
648 struct dwc3_request
*req
;
652 dwc
->ep0state
= EP0_DATA_PHASE
;
654 if (dwc
->ep0_status_pending
) {
655 dwc3_ep0_send_status_response(dwc
);
659 if (list_empty(&dep
->request_list
)) {
660 dev_vdbg(dwc
->dev
, "pending request for EP0 Data phase\n");
661 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
663 if (event
->endpoint_number
)
664 dep
->flags
|= DWC3_EP0_DIR_IN
;
668 req
= next_request(&dep
->request_list
);
669 req
->direction
= !!event
->endpoint_number
;
671 dwc
->ep0state
= EP0_DATA_PHASE
;
672 if (req
->request
.length
== 0) {
673 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
674 dwc
->ctrl_req_addr
, 0,
675 DWC3_TRBCTL_CONTROL_DATA
);
676 } else if ((req
->request
.length
% dep
->endpoint
.maxpacket
)
677 && (event
->endpoint_number
== 0)) {
678 dwc3_map_buffer_to_dma(req
);
680 WARN_ON(req
->request
.length
> dep
->endpoint
.maxpacket
);
682 dwc
->ep0_bounced
= true;
685 * REVISIT in case request length is bigger than EP0
686 * wMaxPacketSize, we will need two chained TRBs to handle
689 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
690 dwc
->ep0_bounce_addr
, dep
->endpoint
.maxpacket
,
691 DWC3_TRBCTL_CONTROL_DATA
);
693 dwc3_map_buffer_to_dma(req
);
695 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
696 req
->request
.dma
, req
->request
.length
,
697 DWC3_TRBCTL_CONTROL_DATA
);
703 static void dwc3_ep0_do_control_status(struct dwc3
*dwc
,
704 const struct dwc3_event_depevt
*event
)
709 dwc
->ep0state
= EP0_STATUS_PHASE
;
711 type
= dwc
->three_stage_setup
? DWC3_TRBCTL_CONTROL_STATUS3
712 : DWC3_TRBCTL_CONTROL_STATUS2
;
714 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
715 dwc
->ctrl_req_addr
, 0, type
);
720 static void dwc3_ep0_xfernotready(struct dwc3
*dwc
,
721 const struct dwc3_event_depevt
*event
)
723 switch (event
->status
) {
724 case DEPEVT_STATUS_CONTROL_SETUP
:
725 dev_vdbg(dwc
->dev
, "Control Setup\n");
726 dwc3_ep0_do_control_setup(dwc
, event
);
729 case DEPEVT_STATUS_CONTROL_DATA
:
730 dev_vdbg(dwc
->dev
, "Control Data\n");
732 if (dwc
->ep0_next_event
!= DWC3_EP0_NRDY_DATA
) {
733 dev_vdbg(dwc
->dev
, "Expected %d got %d\n",
737 dwc3_ep0_stall_and_restart(dwc
);
742 * One of the possible error cases is when Host _does_
743 * request for Data Phase, but it does so on the wrong
746 * Here, we already know ep0_next_event is DATA (see above),
747 * so we only need to check for direction.
749 if (dwc
->ep0_expect_in
!= event
->endpoint_number
) {
750 dev_vdbg(dwc
->dev
, "Wrong direction for Data phase\n");
751 dwc3_ep0_stall_and_restart(dwc
);
755 dwc3_ep0_do_control_data(dwc
, event
);
758 case DEPEVT_STATUS_CONTROL_STATUS
:
759 dev_vdbg(dwc
->dev
, "Control Status\n");
761 if (dwc
->ep0_next_event
!= DWC3_EP0_NRDY_STATUS
) {
762 dev_vdbg(dwc
->dev
, "Expected %d got %d\n",
764 DWC3_EP0_NRDY_STATUS
);
766 dwc3_ep0_stall_and_restart(dwc
);
769 dwc3_ep0_do_control_status(dwc
, event
);
773 void dwc3_ep0_interrupt(struct dwc3
*dwc
,
774 const const struct dwc3_event_depevt
*event
)
776 u8 epnum
= event
->endpoint_number
;
778 dev_dbg(dwc
->dev
, "%s while ep%d%s in state '%s'\n",
779 dwc3_ep_event_string(event
->endpoint_event
),
780 epnum
>> 1, (epnum
& 1) ? "in" : "out",
781 dwc3_ep0_state_string(dwc
->ep0state
));
783 switch (event
->endpoint_event
) {
784 case DWC3_DEPEVT_XFERCOMPLETE
:
785 dwc3_ep0_xfer_complete(dwc
, event
);
788 case DWC3_DEPEVT_XFERNOTREADY
:
789 dwc3_ep0_xfernotready(dwc
, event
);
792 case DWC3_DEPEVT_XFERINPROGRESS
:
793 case DWC3_DEPEVT_RXTXFIFOEVT
:
794 case DWC3_DEPEVT_STREAMEVT
:
795 case DWC3_DEPEVT_EPCMDCMPLT
: