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intel-gtt: initialize our own scratch page
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / char / agp / intel-gtt.c
blobe386a44330b87c34f410d5992cbb00234a2aec66
1 /*
2 * Intel GTT (Graphics Translation Table) routines
3 *
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
10 *
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
13 * here.
14 *
15 * /fairy-tale-mode off
16 */
17
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <asm/smp.h>
25 #include "agp.h"
26 #include "intel-agp.h"
27 #include <linux/intel-gtt.h>
28 #include <drm/intel-gtt.h>
29
30 /*
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_DMAR).
34 * Only newer chipsets need to bother with this, of course.
35 */
36 #ifdef CONFIG_DMAR
37 #define USE_PCI_DMA_API 1
38 #else
39 #define USE_PCI_DMA_API 0
40 #endif
41
42 /* Max amount of stolen space, anything above will be returned to Linux */
43 int intel_max_stolen = 32 * 1024 * 1024;
44 EXPORT_SYMBOL(intel_max_stolen);
45
46 static const struct aper_size_info_fixed intel_i810_sizes[] =
47 {
48 {64, 16384, 4},
49 /* The 32M mode still requires a 64k gatt */
50 {32, 8192, 4}
51 };
52
53 #define AGP_DCACHE_MEMORY 1
54 #define AGP_PHYS_MEMORY 2
55 #define INTEL_AGP_CACHED_MEMORY 3
56
57 static struct gatt_mask intel_i810_masks[] =
58 {
59 {.mask = I810_PTE_VALID, .type = 0},
60 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
61 {.mask = I810_PTE_VALID, .type = 0},
62 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
63 .type = INTEL_AGP_CACHED_MEMORY}
64 };
65
66 #define INTEL_AGP_UNCACHED_MEMORY 0
67 #define INTEL_AGP_CACHED_MEMORY_LLC 1
68 #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
69 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3
70 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
71
72 static struct gatt_mask intel_gen6_masks[] =
73 {
74 {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED,
75 .type = INTEL_AGP_UNCACHED_MEMORY },
76 {.mask = I810_PTE_VALID | GEN6_PTE_LLC,
77 .type = INTEL_AGP_CACHED_MEMORY_LLC },
78 {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT,
79 .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT },
80 {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC,
81 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC },
82 {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT,
83 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT },
84 };
85
86 struct intel_gtt_driver {
87 unsigned int gen : 8;
88 unsigned int is_g33 : 1;
89 unsigned int is_pineview : 1;
90 unsigned int is_ironlake : 1;
91 /* Chipset specific GTT setup */
92 int (*setup)(void);
93 };
94
95 static struct _intel_private {
96 struct intel_gtt base;
97 const struct intel_gtt_driver *driver;
98 struct pci_dev *pcidev; /* device one */
99 struct pci_dev *bridge_dev;
100 u8 __iomem *registers;
101 phys_addr_t gtt_bus_addr;
102 phys_addr_t gma_bus_addr;
103 phys_addr_t pte_bus_addr;
104 u32 __iomem *gtt; /* I915G */
105 int num_dcache_entries;
106 union {
107 void __iomem *i9xx_flush_page;
108 void *i8xx_flush_page;
109 };
110 struct page *i8xx_page;
111 struct resource ifp_resource;
112 int resource_valid;
113 struct page *scratch_page;
114 dma_addr_t scratch_page_dma;
115 } intel_private;
116
117 #define INTEL_GTT_GEN intel_private.driver->gen
118 #define IS_G33 intel_private.driver->is_g33
119 #define IS_PINEVIEW intel_private.driver->is_pineview
120 #define IS_IRONLAKE intel_private.driver->is_ironlake
121
122 #if USE_PCI_DMA_API
123 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
124 {
125 *ret = pci_map_page(intel_private.pcidev, page, 0,
126 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
127 if (pci_dma_mapping_error(intel_private.pcidev, *ret))
128 return -EINVAL;
129 return 0;
130 }
131
132 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
133 {
134 pci_unmap_page(intel_private.pcidev, dma,
135 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
136 }
137
138 static void intel_agp_free_sglist(struct agp_memory *mem)
139 {
140 struct sg_table st;
141
142 st.sgl = mem->sg_list;
143 st.orig_nents = st.nents = mem->page_count;
144
145 sg_free_table(&st);
146
147 mem->sg_list = NULL;
148 mem->num_sg = 0;
149 }
150
151 static int intel_agp_map_memory(struct agp_memory *mem)
152 {
153 struct sg_table st;
154 struct scatterlist *sg;
155 int i;
156
157 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
158
159 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
160 goto err;
161
162 mem->sg_list = sg = st.sgl;
163
164 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
165 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
166
167 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
168 mem->page_count, PCI_DMA_BIDIRECTIONAL);
169 if (unlikely(!mem->num_sg))
170 goto err;
171
172 return 0;
173
174 err:
175 sg_free_table(&st);
176 return -ENOMEM;
177 }
178
179 static void intel_agp_unmap_memory(struct agp_memory *mem)
180 {
181 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
182
183 pci_unmap_sg(intel_private.pcidev, mem->sg_list,
184 mem->page_count, PCI_DMA_BIDIRECTIONAL);
185 intel_agp_free_sglist(mem);
186 }
187
188 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
189 off_t pg_start, int mask_type)
190 {
191 struct scatterlist *sg;
192 int i, j;
193
194 j = pg_start;
195
196 WARN_ON(!mem->num_sg);
197
198 if (mem->num_sg == mem->page_count) {
199 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
200 writel(agp_bridge->driver->mask_memory(agp_bridge,
201 sg_dma_address(sg), mask_type),
202 intel_private.gtt+j);
203 j++;
204 }
205 } else {
206 /* sg may merge pages, but we have to separate
207 * per-page addr for GTT */
208 unsigned int len, m;
209
210 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
211 len = sg_dma_len(sg) / PAGE_SIZE;
212 for (m = 0; m < len; m++) {
213 writel(agp_bridge->driver->mask_memory(agp_bridge,
214 sg_dma_address(sg) + m * PAGE_SIZE,
215 mask_type),
216 intel_private.gtt+j);
217 j++;
218 }
219 }
220 }
221 readl(intel_private.gtt+j-1);
222 }
223
224 #else
225
226 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
227 off_t pg_start, int mask_type)
228 {
229 int i, j;
230
231 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
232 writel(agp_bridge->driver->mask_memory(agp_bridge,
233 page_to_phys(mem->pages[i]), mask_type),
234 intel_private.gtt+j);
235 }
236
237 readl(intel_private.gtt+j-1);
238 }
239
240 #endif
241
242 static int intel_i810_fetch_size(void)
243 {
244 u32 smram_miscc;
245 struct aper_size_info_fixed *values;
246
247 pci_read_config_dword(intel_private.bridge_dev,
248 I810_SMRAM_MISCC, &smram_miscc);
249 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
250
251 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
252 dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n");
253 return 0;
254 }
255 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
256 agp_bridge->current_size = (void *) (values + 1);
257 agp_bridge->aperture_size_idx = 1;
258 return values[1].size;
259 } else {
260 agp_bridge->current_size = (void *) (values);
261 agp_bridge->aperture_size_idx = 0;
262 return values[0].size;
263 }
264
265 return 0;
266 }
267
268 static int intel_i810_configure(void)
269 {
270 struct aper_size_info_fixed *current_size;
271 u32 temp;
272 int i;
273
274 current_size = A_SIZE_FIX(agp_bridge->current_size);
275
276 if (!intel_private.registers) {
277 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
278 temp &= 0xfff80000;
279
280 intel_private.registers = ioremap(temp, 128 * 4096);
281 if (!intel_private.registers) {
282 dev_err(&intel_private.pcidev->dev,
283 "can't remap memory\n");
284 return -ENOMEM;
285 }
286 }
287
288 if ((readl(intel_private.registers+I810_DRAM_CTL)
289 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
290 /* This will need to be dynamically assigned */
291 dev_info(&intel_private.pcidev->dev,
292 "detected 4MB dedicated video ram\n");
293 intel_private.num_dcache_entries = 1024;
294 }
295 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
296 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
297 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
298 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
299
300 if (agp_bridge->driver->needs_scratch_page) {
301 for (i = 0; i < current_size->num_entries; i++) {
302 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
303 }
304 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
305 }
306 global_cache_flush();
307 return 0;
308 }
309
310 static void intel_i810_cleanup(void)
311 {
312 writel(0, intel_private.registers+I810_PGETBL_CTL);
313 readl(intel_private.registers); /* PCI Posting. */
314 iounmap(intel_private.registers);
315 }
316
317 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
318 {
319 return;
320 }
321
322 /* Exists to support ARGB cursors */
323 static struct page *i8xx_alloc_pages(void)
324 {
325 struct page *page;
326
327 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
328 if (page == NULL)
329 return NULL;
330
331 if (set_pages_uc(page, 4) < 0) {
332 set_pages_wb(page, 4);
333 __free_pages(page, 2);
334 return NULL;
335 }
336 get_page(page);
337 atomic_inc(&agp_bridge->current_memory_agp);
338 return page;
339 }
340
341 static void i8xx_destroy_pages(struct page *page)
342 {
343 if (page == NULL)
344 return;
345
346 set_pages_wb(page, 4);
347 put_page(page);
348 __free_pages(page, 2);
349 atomic_dec(&agp_bridge->current_memory_agp);
350 }
351
352 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
353 int type)
354 {
355 if (type < AGP_USER_TYPES)
356 return type;
357 else if (type == AGP_USER_CACHED_MEMORY)
358 return INTEL_AGP_CACHED_MEMORY;
359 else
360 return 0;
361 }
362
363 static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge,
364 int type)
365 {
366 unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT;
367 unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT;
368
369 if (type_mask == AGP_USER_UNCACHED_MEMORY)
370 return INTEL_AGP_UNCACHED_MEMORY;
371 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
372 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT :
373 INTEL_AGP_CACHED_MEMORY_LLC_MLC;
374 else /* set 'normal'/'cached' to LLC by default */
375 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT :
376 INTEL_AGP_CACHED_MEMORY_LLC;
377 }
378
379
380 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
381 int type)
382 {
383 int i, j, num_entries;
384 void *temp;
385 int ret = -EINVAL;
386 int mask_type;
387
388 if (mem->page_count == 0)
389 goto out;
390
391 temp = agp_bridge->current_size;
392 num_entries = A_SIZE_FIX(temp)->num_entries;
393
394 if ((pg_start + mem->page_count) > num_entries)
395 goto out_err;
396
397
398 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
399 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
400 ret = -EBUSY;
401 goto out_err;
402 }
403 }
404
405 if (type != mem->type)
406 goto out_err;
407
408 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
409
410 switch (mask_type) {
411 case AGP_DCACHE_MEMORY:
412 if (!mem->is_flushed)
413 global_cache_flush();
414 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
415 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
416 intel_private.registers+I810_PTE_BASE+(i*4));
417 }
418 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
419 break;
420 case AGP_PHYS_MEMORY:
421 case AGP_NORMAL_MEMORY:
422 if (!mem->is_flushed)
423 global_cache_flush();
424 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
425 writel(agp_bridge->driver->mask_memory(agp_bridge,
426 page_to_phys(mem->pages[i]), mask_type),
427 intel_private.registers+I810_PTE_BASE+(j*4));
428 }
429 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
430 break;
431 default:
432 goto out_err;
433 }
434
435 out:
436 ret = 0;
437 out_err:
438 mem->is_flushed = true;
439 return ret;
440 }
441
442 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
443 int type)
444 {
445 int i;
446
447 if (mem->page_count == 0)
448 return 0;
449
450 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
451 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
452 }
453 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
454
455 return 0;
456 }
457
458 /*
459 * The i810/i830 requires a physical address to program its mouse
460 * pointer into hardware.
461 * However the Xserver still writes to it through the agp aperture.
462 */
463 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
464 {
465 struct agp_memory *new;
466 struct page *page;
467
468 switch (pg_count) {
469 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
470 break;
471 case 4:
472 /* kludge to get 4 physical pages for ARGB cursor */
473 page = i8xx_alloc_pages();
474 break;
475 default:
476 return NULL;
477 }
478
479 if (page == NULL)
480 return NULL;
481
482 new = agp_create_memory(pg_count);
483 if (new == NULL)
484 return NULL;
485
486 new->pages[0] = page;
487 if (pg_count == 4) {
488 /* kludge to get 4 physical pages for ARGB cursor */
489 new->pages[1] = new->pages[0] + 1;
490 new->pages[2] = new->pages[1] + 1;
491 new->pages[3] = new->pages[2] + 1;
492 }
493 new->page_count = pg_count;
494 new->num_scratch_pages = pg_count;
495 new->type = AGP_PHYS_MEMORY;
496 new->physical = page_to_phys(new->pages[0]);
497 return new;
498 }
499
500 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
501 {
502 struct agp_memory *new;
503
504 if (type == AGP_DCACHE_MEMORY) {
505 if (pg_count != intel_private.num_dcache_entries)
506 return NULL;
507
508 new = agp_create_memory(1);
509 if (new == NULL)
510 return NULL;
511
512 new->type = AGP_DCACHE_MEMORY;
513 new->page_count = pg_count;
514 new->num_scratch_pages = 0;
515 agp_free_page_array(new);
516 return new;
517 }
518 if (type == AGP_PHYS_MEMORY)
519 return alloc_agpphysmem_i8xx(pg_count, type);
520 return NULL;
521 }
522
523 static void intel_i810_free_by_type(struct agp_memory *curr)
524 {
525 agp_free_key(curr->key);
526 if (curr->type == AGP_PHYS_MEMORY) {
527 if (curr->page_count == 4)
528 i8xx_destroy_pages(curr->pages[0]);
529 else {
530 agp_bridge->driver->agp_destroy_page(curr->pages[0],
531 AGP_PAGE_DESTROY_UNMAP);
532 agp_bridge->driver->agp_destroy_page(curr->pages[0],
533 AGP_PAGE_DESTROY_FREE);
534 }
535 agp_free_page_array(curr);
536 }
537 kfree(curr);
538 }
539
540 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
541 dma_addr_t addr, int type)
542 {
543 /* Type checking must be done elsewhere */
544 return addr | bridge->driver->masks[type].mask;
545 }
546
547 static int intel_gtt_setup_scratch_page(void)
548 {
549 struct page *page;
550 dma_addr_t dma_addr;
551
552 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
553 if (page == NULL)
554 return -ENOMEM;
555 get_page(page);
556 set_pages_uc(page, 1);
557
558 if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) {
559 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
560 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
561 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
562 return -EINVAL;
563
564 intel_private.scratch_page_dma = dma_addr;
565 } else
566 intel_private.scratch_page_dma = page_to_phys(page);
567
568 intel_private.scratch_page = page;
569
570 return 0;
571 }
572
573 static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = {
574 {128, 32768, 5},
575 /* The 64M mode still requires a 128k gatt */
576 {64, 16384, 5},
577 {256, 65536, 6},
578 {512, 131072, 7},
579 };
580
581 static unsigned int intel_gtt_stolen_entries(void)
582 {
583 u16 gmch_ctrl;
584 u8 rdct;
585 int local = 0;
586 static const int ddt[4] = { 0, 16, 32, 64 };
587 unsigned int overhead_entries, stolen_entries;
588 unsigned int stolen_size = 0;
589
590 pci_read_config_word(intel_private.bridge_dev,
591 I830_GMCH_CTRL, &gmch_ctrl);
592
593 if (INTEL_GTT_GEN > 4 || IS_PINEVIEW)
594 overhead_entries = 0;
595 else
596 overhead_entries = intel_private.base.gtt_mappable_entries
597 / 1024;
598
599 overhead_entries += 1; /* BIOS popup */
600
601 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
602 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
603 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
604 case I830_GMCH_GMS_STOLEN_512:
605 stolen_size = KB(512);
606 break;
607 case I830_GMCH_GMS_STOLEN_1024:
608 stolen_size = MB(1);
609 break;
610 case I830_GMCH_GMS_STOLEN_8192:
611 stolen_size = MB(8);
612 break;
613 case I830_GMCH_GMS_LOCAL:
614 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
615 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
616 MB(ddt[I830_RDRAM_DDT(rdct)]);
617 local = 1;
618 break;
619 default:
620 stolen_size = 0;
621 break;
622 }
623 } else if (INTEL_GTT_GEN == 6) {
624 /*
625 * SandyBridge has new memory control reg at 0x50.w
626 */
627 u16 snb_gmch_ctl;
628 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
629 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
630 case SNB_GMCH_GMS_STOLEN_32M:
631 stolen_size = MB(32);
632 break;
633 case SNB_GMCH_GMS_STOLEN_64M:
634 stolen_size = MB(64);
635 break;
636 case SNB_GMCH_GMS_STOLEN_96M:
637 stolen_size = MB(96);
638 break;
639 case SNB_GMCH_GMS_STOLEN_128M:
640 stolen_size = MB(128);
641 break;
642 case SNB_GMCH_GMS_STOLEN_160M:
643 stolen_size = MB(160);
644 break;
645 case SNB_GMCH_GMS_STOLEN_192M:
646 stolen_size = MB(192);
647 break;
648 case SNB_GMCH_GMS_STOLEN_224M:
649 stolen_size = MB(224);
650 break;
651 case SNB_GMCH_GMS_STOLEN_256M:
652 stolen_size = MB(256);
653 break;
654 case SNB_GMCH_GMS_STOLEN_288M:
655 stolen_size = MB(288);
656 break;
657 case SNB_GMCH_GMS_STOLEN_320M:
658 stolen_size = MB(320);
659 break;
660 case SNB_GMCH_GMS_STOLEN_352M:
661 stolen_size = MB(352);
662 break;
663 case SNB_GMCH_GMS_STOLEN_384M:
664 stolen_size = MB(384);
665 break;
666 case SNB_GMCH_GMS_STOLEN_416M:
667 stolen_size = MB(416);
668 break;
669 case SNB_GMCH_GMS_STOLEN_448M:
670 stolen_size = MB(448);
671 break;
672 case SNB_GMCH_GMS_STOLEN_480M:
673 stolen_size = MB(480);
674 break;
675 case SNB_GMCH_GMS_STOLEN_512M:
676 stolen_size = MB(512);
677 break;
678 }
679 } else {
680 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
681 case I855_GMCH_GMS_STOLEN_1M:
682 stolen_size = MB(1);
683 break;
684 case I855_GMCH_GMS_STOLEN_4M:
685 stolen_size = MB(4);
686 break;
687 case I855_GMCH_GMS_STOLEN_8M:
688 stolen_size = MB(8);
689 break;
690 case I855_GMCH_GMS_STOLEN_16M:
691 stolen_size = MB(16);
692 break;
693 case I855_GMCH_GMS_STOLEN_32M:
694 stolen_size = MB(32);
695 break;
696 case I915_GMCH_GMS_STOLEN_48M:
697 stolen_size = MB(48);
698 break;
699 case I915_GMCH_GMS_STOLEN_64M:
700 stolen_size = MB(64);
701 break;
702 case G33_GMCH_GMS_STOLEN_128M:
703 stolen_size = MB(128);
704 break;
705 case G33_GMCH_GMS_STOLEN_256M:
706 stolen_size = MB(256);
707 break;
708 case INTEL_GMCH_GMS_STOLEN_96M:
709 stolen_size = MB(96);
710 break;
711 case INTEL_GMCH_GMS_STOLEN_160M:
712 stolen_size = MB(160);
713 break;
714 case INTEL_GMCH_GMS_STOLEN_224M:
715 stolen_size = MB(224);
716 break;
717 case INTEL_GMCH_GMS_STOLEN_352M:
718 stolen_size = MB(352);
719 break;
720 default:
721 stolen_size = 0;
722 break;
723 }
724 }
725
726 if (!local && stolen_size > intel_max_stolen) {
727 dev_info(&intel_private.bridge_dev->dev,
728 "detected %dK stolen memory, trimming to %dK\n",
729 stolen_size / KB(1), intel_max_stolen / KB(1));
730 stolen_size = intel_max_stolen;
731 } else if (stolen_size > 0) {
732 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
733 stolen_size / KB(1), local ? "local" : "stolen");
734 } else {
735 dev_info(&intel_private.bridge_dev->dev,
736 "no pre-allocated video memory detected\n");
737 stolen_size = 0;
738 }
739
740 stolen_entries = stolen_size/KB(4) - overhead_entries;
741
742 return stolen_entries;
743 }
744
745 static unsigned int intel_gtt_total_entries(void)
746 {
747 int size;
748
749 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) {
750 u32 pgetbl_ctl;
751 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
752
753 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
754 case I965_PGETBL_SIZE_128KB:
755 size = KB(128);
756 break;
757 case I965_PGETBL_SIZE_256KB:
758 size = KB(256);
759 break;
760 case I965_PGETBL_SIZE_512KB:
761 size = KB(512);
762 break;
763 case I965_PGETBL_SIZE_1MB:
764 size = KB(1024);
765 break;
766 case I965_PGETBL_SIZE_2MB:
767 size = KB(2048);
768 break;
769 case I965_PGETBL_SIZE_1_5MB:
770 size = KB(1024 + 512);
771 break;
772 default:
773 dev_info(&intel_private.pcidev->dev,
774 "unknown page table size, assuming 512KB\n");
775 size = KB(512);
776 }
777
778 return size/4;
779 } else if (INTEL_GTT_GEN == 6) {
780 u16 snb_gmch_ctl;
781
782 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
783 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
784 default:
785 case SNB_GTT_SIZE_0M:
786 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
787 size = MB(0);
788 break;
789 case SNB_GTT_SIZE_1M:
790 size = MB(1);
791 break;
792 case SNB_GTT_SIZE_2M:
793 size = MB(2);
794 break;
795 }
796 return size/4;
797 } else {
798 /* On previous hardware, the GTT size was just what was
799 * required to map the aperture.
800 */
801 return intel_private.base.gtt_mappable_entries;
802 }
803 }
804
805 static unsigned int intel_gtt_mappable_entries(void)
806 {
807 unsigned int aperture_size;
808
809 if (INTEL_GTT_GEN == 2) {
810 u16 gmch_ctrl;
811
812 pci_read_config_word(intel_private.bridge_dev,
813 I830_GMCH_CTRL, &gmch_ctrl);
814
815 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
816 aperture_size = MB(64);
817 else
818 aperture_size = MB(128);
819 } else {
820 /* 9xx supports large sizes, just look at the length */
821 aperture_size = pci_resource_len(intel_private.pcidev, 2);
822 }
823
824 return aperture_size >> PAGE_SHIFT;
825 }
826
827 static void intel_gtt_teardown_scratch_page(void)
828 {
829 set_pages_wb(intel_private.scratch_page, 1);
830 pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
831 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
832 put_page(intel_private.scratch_page);
833 __free_page(intel_private.scratch_page);
834 }
835
836 static void intel_gtt_cleanup(void)
837 {
838 if (intel_private.i9xx_flush_page)
839 iounmap(intel_private.i9xx_flush_page);
840 if (intel_private.resource_valid)
841 release_resource(&intel_private.ifp_resource);
842 intel_private.ifp_resource.start = 0;
843 intel_private.resource_valid = 0;
844 iounmap(intel_private.gtt);
845 iounmap(intel_private.registers);
846
847 intel_gtt_teardown_scratch_page();
848 }
849
850 static int intel_gtt_init(void)
851 {
852 u32 gtt_map_size;
853 int ret;
854
855 ret = intel_private.driver->setup();
856 if (ret != 0)
857 return ret;
858
859 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
860 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
861
862 gtt_map_size = intel_private.base.gtt_total_entries * 4;
863
864 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
865 gtt_map_size);
866 if (!intel_private.gtt) {
867 iounmap(intel_private.registers);
868 return -ENOMEM;
869 }
870
871 global_cache_flush(); /* FIXME: ? */
872
873 /* we have to call this as early as possible after the MMIO base address is known */
874 intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries();
875 if (intel_private.base.gtt_stolen_entries == 0) {
876 iounmap(intel_private.registers);
877 iounmap(intel_private.gtt);
878 return -ENOMEM;
879 }
880
881 ret = intel_gtt_setup_scratch_page();
882 if (ret != 0) {
883 intel_gtt_cleanup();
884 return ret;
885 }
886
887 return 0;
888 }
889
890 static int intel_fake_agp_fetch_size(void)
891 {
892 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
893 unsigned int aper_size;
894 int i;
895
896 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
897 / MB(1);
898
899 for (i = 0; i < num_sizes; i++) {
900 if (aper_size == intel_fake_agp_sizes[i].size) {
901 agp_bridge->current_size =
902 (void *) (intel_fake_agp_sizes + i);
903 return aper_size;
904 }
905 }
906
907 return 0;
908 }
909
910 static void intel_i830_fini_flush(void)
911 {
912 kunmap(intel_private.i8xx_page);
913 intel_private.i8xx_flush_page = NULL;
914 unmap_page_from_agp(intel_private.i8xx_page);
915
916 __free_page(intel_private.i8xx_page);
917 intel_private.i8xx_page = NULL;
918 }
919
920 static void intel_i830_setup_flush(void)
921 {
922 /* return if we've already set the flush mechanism up */
923 if (intel_private.i8xx_page)
924 return;
925
926 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
927 if (!intel_private.i8xx_page)
928 return;
929
930 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
931 if (!intel_private.i8xx_flush_page)
932 intel_i830_fini_flush();
933 }
934
935 /* The chipset_flush interface needs to get data that has already been
936 * flushed out of the CPU all the way out to main memory, because the GPU
937 * doesn't snoop those buffers.
938 *
939 * The 8xx series doesn't have the same lovely interface for flushing the
940 * chipset write buffers that the later chips do. According to the 865
941 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
942 * that buffer out, we just fill 1KB and clflush it out, on the assumption
943 * that it'll push whatever was in there out. It appears to work.
944 */
945 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
946 {
947 unsigned int *pg = intel_private.i8xx_flush_page;
948
949 memset(pg, 0, 1024);
950
951 if (cpu_has_clflush)
952 clflush_cache_range(pg, 1024);
953 else if (wbinvd_on_all_cpus() != 0)
954 printk(KERN_ERR "Timed out waiting for cache flush.\n");
955 }
956
957 static void intel_enable_gtt(void)
958 {
959 u32 gma_addr;
960 u16 gmch_ctrl;
961
962 if (INTEL_GTT_GEN == 2)
963 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
964 &gma_addr);
965 else
966 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
967 &gma_addr);
968
969 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
970
971 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
972 gmch_ctrl |= I830_GMCH_ENABLED;
973 pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
974
975 writel(intel_private.pte_bus_addr|I810_PGETBL_ENABLED,
976 intel_private.registers+I810_PGETBL_CTL);
977 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
978 }
979
980 static int i830_setup(void)
981 {
982 u32 reg_addr;
983
984 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
985 reg_addr &= 0xfff80000;
986
987 intel_private.registers = ioremap(reg_addr, KB(64));
988 if (!intel_private.registers)
989 return -ENOMEM;
990
991 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
992 intel_private.pte_bus_addr =
993 readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
994
995 intel_i830_setup_flush();
996
997 return 0;
998 }
999
1000 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
1001 {
1002 agp_bridge->gatt_table_real = NULL;
1003 agp_bridge->gatt_table = NULL;
1004 agp_bridge->gatt_bus_addr = 0;
1005
1006 return 0;
1007 }
1008
1009 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
1010 {
1011 return 0;
1012 }
1013
1014 static int intel_i830_configure(void)
1015 {
1016 int i;
1017
1018 intel_enable_gtt();
1019
1020 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
1021
1022 if (agp_bridge->driver->needs_scratch_page) {
1023 for (i = intel_private.base.gtt_stolen_entries;
1024 i < intel_private.base.gtt_total_entries; i++) {
1025 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1026 }
1027 readl(intel_private.gtt+i-1); /* PCI Posting. */
1028 }
1029
1030 global_cache_flush();
1031
1032 return 0;
1033 }
1034
1035 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
1036 int type)
1037 {
1038 int i, j, num_entries;
1039 void *temp;
1040 int ret = -EINVAL;
1041 int mask_type;
1042
1043 if (mem->page_count == 0)
1044 goto out;
1045
1046 temp = agp_bridge->current_size;
1047 num_entries = A_SIZE_FIX(temp)->num_entries;
1048
1049 if (pg_start < intel_private.base.gtt_stolen_entries) {
1050 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1051 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1052 pg_start, intel_private.base.gtt_stolen_entries);
1053
1054 dev_info(&intel_private.pcidev->dev,
1055 "trying to insert into local/stolen memory\n");
1056 goto out_err;
1057 }
1058
1059 if ((pg_start + mem->page_count) > num_entries)
1060 goto out_err;
1061
1062 /* The i830 can't check the GTT for entries since its read only,
1063 * depend on the caller to make the correct offset decisions.
1064 */
1065
1066 if (type != mem->type)
1067 goto out_err;
1068
1069 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1070
1071 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1072 mask_type != INTEL_AGP_CACHED_MEMORY)
1073 goto out_err;
1074
1075 if (!mem->is_flushed)
1076 global_cache_flush();
1077
1078 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1079 writel(agp_bridge->driver->mask_memory(agp_bridge,
1080 page_to_phys(mem->pages[i]), mask_type),
1081 intel_private.gtt+j);
1082 }
1083 readl(intel_private.gtt+j-1);
1084
1085 out:
1086 ret = 0;
1087 out_err:
1088 mem->is_flushed = true;
1089 return ret;
1090 }
1091
1092 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
1093 int type)
1094 {
1095 int i;
1096
1097 if (mem->page_count == 0)
1098 return 0;
1099
1100 if (pg_start < intel_private.base.gtt_stolen_entries) {
1101 dev_info(&intel_private.pcidev->dev,
1102 "trying to disable local/stolen memory\n");
1103 return -EINVAL;
1104 }
1105
1106 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1107 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1108 }
1109 readl(intel_private.gtt+i-1);
1110
1111 return 0;
1112 }
1113
1114 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1115 int type)
1116 {
1117 if (type == AGP_PHYS_MEMORY)
1118 return alloc_agpphysmem_i8xx(pg_count, type);
1119 /* always return NULL for other allocation types for now */
1120 return NULL;
1121 }
1122
1123 static int intel_alloc_chipset_flush_resource(void)
1124 {
1125 int ret;
1126 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1127 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1128 pcibios_align_resource, intel_private.bridge_dev);
1129
1130 return ret;
1131 }
1132
1133 static void intel_i915_setup_chipset_flush(void)
1134 {
1135 int ret;
1136 u32 temp;
1137
1138 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1139 if (!(temp & 0x1)) {
1140 intel_alloc_chipset_flush_resource();
1141 intel_private.resource_valid = 1;
1142 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1143 } else {
1144 temp &= ~1;
1145
1146 intel_private.resource_valid = 1;
1147 intel_private.ifp_resource.start = temp;
1148 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1149 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1150 /* some BIOSes reserve this area in a pnp some don't */
1151 if (ret)
1152 intel_private.resource_valid = 0;
1153 }
1154 }
1155
1156 static void intel_i965_g33_setup_chipset_flush(void)
1157 {
1158 u32 temp_hi, temp_lo;
1159 int ret;
1160
1161 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1162 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1163
1164 if (!(temp_lo & 0x1)) {
1165
1166 intel_alloc_chipset_flush_resource();
1167
1168 intel_private.resource_valid = 1;
1169 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1170 upper_32_bits(intel_private.ifp_resource.start));
1171 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1172 } else {
1173 u64 l64;
1174
1175 temp_lo &= ~0x1;
1176 l64 = ((u64)temp_hi << 32) | temp_lo;
1177
1178 intel_private.resource_valid = 1;
1179 intel_private.ifp_resource.start = l64;
1180 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1181 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1182 /* some BIOSes reserve this area in a pnp some don't */
1183 if (ret)
1184 intel_private.resource_valid = 0;
1185 }
1186 }
1187
1188 static void intel_i9xx_setup_flush(void)
1189 {
1190 /* return if already configured */
1191 if (intel_private.ifp_resource.start)
1192 return;
1193
1194 if (INTEL_GTT_GEN == 6)
1195 return;
1196
1197 /* setup a resource for this object */
1198 intel_private.ifp_resource.name = "Intel Flush Page";
1199 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1200
1201 /* Setup chipset flush for 915 */
1202 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1203 intel_i965_g33_setup_chipset_flush();
1204 } else {
1205 intel_i915_setup_chipset_flush();
1206 }
1207
1208 if (intel_private.ifp_resource.start)
1209 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1210 if (!intel_private.i9xx_flush_page)
1211 dev_err(&intel_private.pcidev->dev,
1212 "can't ioremap flush page - no chipset flushing\n");
1213 }
1214
1215 static int intel_i9xx_configure(void)
1216 {
1217 int i;
1218
1219 intel_enable_gtt();
1220
1221 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
1222
1223 if (agp_bridge->driver->needs_scratch_page) {
1224 for (i = intel_private.base.gtt_stolen_entries; i <
1225 intel_private.base.gtt_total_entries; i++) {
1226 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1227 }
1228 readl(intel_private.gtt+i-1); /* PCI Posting. */
1229 }
1230
1231 global_cache_flush();
1232
1233 return 0;
1234 }
1235
1236 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1237 {
1238 if (intel_private.i9xx_flush_page)
1239 writel(1, intel_private.i9xx_flush_page);
1240 }
1241
1242 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1243 int type)
1244 {
1245 int num_entries;
1246 void *temp;
1247 int ret = -EINVAL;
1248 int mask_type;
1249
1250 if (mem->page_count == 0)
1251 goto out;
1252
1253 temp = agp_bridge->current_size;
1254 num_entries = A_SIZE_FIX(temp)->num_entries;
1255
1256 if (pg_start < intel_private.base.gtt_stolen_entries) {
1257 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1258 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1259 pg_start, intel_private.base.gtt_stolen_entries);
1260
1261 dev_info(&intel_private.pcidev->dev,
1262 "trying to insert into local/stolen memory\n");
1263 goto out_err;
1264 }
1265
1266 if ((pg_start + mem->page_count) > num_entries)
1267 goto out_err;
1268
1269 /* The i915 can't check the GTT for entries since it's read only;
1270 * depend on the caller to make the correct offset decisions.
1271 */
1272
1273 if (type != mem->type)
1274 goto out_err;
1275
1276 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1277
1278 if (INTEL_GTT_GEN != 6 && mask_type != 0 &&
1279 mask_type != AGP_PHYS_MEMORY &&
1280 mask_type != INTEL_AGP_CACHED_MEMORY)
1281 goto out_err;
1282
1283 if (!mem->is_flushed)
1284 global_cache_flush();
1285
1286 intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1287
1288 out:
1289 ret = 0;
1290 out_err:
1291 mem->is_flushed = true;
1292 return ret;
1293 }
1294
1295 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1296 int type)
1297 {
1298 int i;
1299
1300 if (mem->page_count == 0)
1301 return 0;
1302
1303 if (pg_start < intel_private.base.gtt_stolen_entries) {
1304 dev_info(&intel_private.pcidev->dev,
1305 "trying to disable local/stolen memory\n");
1306 return -EINVAL;
1307 }
1308
1309 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1310 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1311
1312 readl(intel_private.gtt+i-1);
1313
1314 return 0;
1315 }
1316
1317 static int i9xx_setup(void)
1318 {
1319 u32 reg_addr;
1320
1321 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1322
1323 reg_addr &= 0xfff80000;
1324
1325 intel_private.registers = ioremap(reg_addr, 128 * 4096);
1326 if (!intel_private.registers)
1327 return -ENOMEM;
1328
1329 if (INTEL_GTT_GEN == 3) {
1330 u32 gtt_addr;
1331
1332 pci_read_config_dword(intel_private.pcidev,
1333 I915_PTEADDR, &gtt_addr);
1334 intel_private.gtt_bus_addr = gtt_addr;
1335 } else {
1336 u32 gtt_offset;
1337
1338 switch (INTEL_GTT_GEN) {
1339 case 5:
1340 case 6:
1341 gtt_offset = MB(2);
1342 break;
1343 case 4:
1344 default:
1345 gtt_offset = KB(512);
1346 break;
1347 }
1348 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1349 }
1350
1351 intel_private.pte_bus_addr =
1352 readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1353
1354 intel_i9xx_setup_flush();
1355
1356 return 0;
1357 }
1358
1359 /*
1360 * The i965 supports 36-bit physical addresses, but to keep
1361 * the format of the GTT the same, the bits that don't fit
1362 * in a 32-bit word are shifted down to bits 4..7.
1363 *
1364 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1365 * is always zero on 32-bit architectures, so no need to make
1366 * this conditional.
1367 */
1368 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1369 dma_addr_t addr, int type)
1370 {
1371 /* Shift high bits down */
1372 addr |= (addr >> 28) & 0xf0;
1373
1374 /* Type checking must be done elsewhere */
1375 return addr | bridge->driver->masks[type].mask;
1376 }
1377
1378 static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
1379 dma_addr_t addr, int type)
1380 {
1381 /* gen6 has bit11-4 for physical addr bit39-32 */
1382 addr |= (addr >> 28) & 0xff0;
1383
1384 /* Type checking must be done elsewhere */
1385 return addr | bridge->driver->masks[type].mask;
1386 }
1387
1388 static const struct agp_bridge_driver intel_810_driver = {
1389 .owner = THIS_MODULE,
1390 .aperture_sizes = intel_i810_sizes,
1391 .size_type = FIXED_APER_SIZE,
1392 .num_aperture_sizes = 2,
1393 .needs_scratch_page = true,
1394 .configure = intel_i810_configure,
1395 .fetch_size = intel_i810_fetch_size,
1396 .cleanup = intel_i810_cleanup,
1397 .mask_memory = intel_i810_mask_memory,
1398 .masks = intel_i810_masks,
1399 .agp_enable = intel_fake_agp_enable,
1400 .cache_flush = global_cache_flush,
1401 .create_gatt_table = agp_generic_create_gatt_table,
1402 .free_gatt_table = agp_generic_free_gatt_table,
1403 .insert_memory = intel_i810_insert_entries,
1404 .remove_memory = intel_i810_remove_entries,
1405 .alloc_by_type = intel_i810_alloc_by_type,
1406 .free_by_type = intel_i810_free_by_type,
1407 .agp_alloc_page = agp_generic_alloc_page,
1408 .agp_alloc_pages = agp_generic_alloc_pages,
1409 .agp_destroy_page = agp_generic_destroy_page,
1410 .agp_destroy_pages = agp_generic_destroy_pages,
1411 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1412 };
1413
1414 static const struct agp_bridge_driver intel_830_driver = {
1415 .owner = THIS_MODULE,
1416 .size_type = FIXED_APER_SIZE,
1417 .aperture_sizes = intel_fake_agp_sizes,
1418 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1419 .needs_scratch_page = true,
1420 .configure = intel_i830_configure,
1421 .fetch_size = intel_fake_agp_fetch_size,
1422 .cleanup = intel_gtt_cleanup,
1423 .mask_memory = intel_i810_mask_memory,
1424 .masks = intel_i810_masks,
1425 .agp_enable = intel_fake_agp_enable,
1426 .cache_flush = global_cache_flush,
1427 .create_gatt_table = intel_fake_agp_create_gatt_table,
1428 .free_gatt_table = intel_fake_agp_free_gatt_table,
1429 .insert_memory = intel_i830_insert_entries,
1430 .remove_memory = intel_i830_remove_entries,
1431 .alloc_by_type = intel_fake_agp_alloc_by_type,
1432 .free_by_type = intel_i810_free_by_type,
1433 .agp_alloc_page = agp_generic_alloc_page,
1434 .agp_alloc_pages = agp_generic_alloc_pages,
1435 .agp_destroy_page = agp_generic_destroy_page,
1436 .agp_destroy_pages = agp_generic_destroy_pages,
1437 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1438 .chipset_flush = intel_i830_chipset_flush,
1439 };
1440
1441 static const struct agp_bridge_driver intel_915_driver = {
1442 .owner = THIS_MODULE,
1443 .size_type = FIXED_APER_SIZE,
1444 .aperture_sizes = intel_fake_agp_sizes,
1445 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1446 .needs_scratch_page = true,
1447 .configure = intel_i9xx_configure,
1448 .fetch_size = intel_fake_agp_fetch_size,
1449 .cleanup = intel_gtt_cleanup,
1450 .mask_memory = intel_i810_mask_memory,
1451 .masks = intel_i810_masks,
1452 .agp_enable = intel_fake_agp_enable,
1453 .cache_flush = global_cache_flush,
1454 .create_gatt_table = intel_fake_agp_create_gatt_table,
1455 .free_gatt_table = intel_fake_agp_free_gatt_table,
1456 .insert_memory = intel_i915_insert_entries,
1457 .remove_memory = intel_i915_remove_entries,
1458 .alloc_by_type = intel_fake_agp_alloc_by_type,
1459 .free_by_type = intel_i810_free_by_type,
1460 .agp_alloc_page = agp_generic_alloc_page,
1461 .agp_alloc_pages = agp_generic_alloc_pages,
1462 .agp_destroy_page = agp_generic_destroy_page,
1463 .agp_destroy_pages = agp_generic_destroy_pages,
1464 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1465 .chipset_flush = intel_i915_chipset_flush,
1466 #if USE_PCI_DMA_API
1467 .agp_map_page = intel_agp_map_page,
1468 .agp_unmap_page = intel_agp_unmap_page,
1469 .agp_map_memory = intel_agp_map_memory,
1470 .agp_unmap_memory = intel_agp_unmap_memory,
1471 #endif
1472 };
1473
1474 static const struct agp_bridge_driver intel_i965_driver = {
1475 .owner = THIS_MODULE,
1476 .size_type = FIXED_APER_SIZE,
1477 .aperture_sizes = intel_fake_agp_sizes,
1478 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1479 .needs_scratch_page = true,
1480 .configure = intel_i9xx_configure,
1481 .fetch_size = intel_fake_agp_fetch_size,
1482 .cleanup = intel_gtt_cleanup,
1483 .mask_memory = intel_i965_mask_memory,
1484 .masks = intel_i810_masks,
1485 .agp_enable = intel_fake_agp_enable,
1486 .cache_flush = global_cache_flush,
1487 .create_gatt_table = intel_fake_agp_create_gatt_table,
1488 .free_gatt_table = intel_fake_agp_free_gatt_table,
1489 .insert_memory = intel_i915_insert_entries,
1490 .remove_memory = intel_i915_remove_entries,
1491 .alloc_by_type = intel_fake_agp_alloc_by_type,
1492 .free_by_type = intel_i810_free_by_type,
1493 .agp_alloc_page = agp_generic_alloc_page,
1494 .agp_alloc_pages = agp_generic_alloc_pages,
1495 .agp_destroy_page = agp_generic_destroy_page,
1496 .agp_destroy_pages = agp_generic_destroy_pages,
1497 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1498 .chipset_flush = intel_i915_chipset_flush,
1499 #if USE_PCI_DMA_API
1500 .agp_map_page = intel_agp_map_page,
1501 .agp_unmap_page = intel_agp_unmap_page,
1502 .agp_map_memory = intel_agp_map_memory,
1503 .agp_unmap_memory = intel_agp_unmap_memory,
1504 #endif
1505 };
1506
1507 static const struct agp_bridge_driver intel_gen6_driver = {
1508 .owner = THIS_MODULE,
1509 .size_type = FIXED_APER_SIZE,
1510 .aperture_sizes = intel_fake_agp_sizes,
1511 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1512 .needs_scratch_page = true,
1513 .configure = intel_i9xx_configure,
1514 .fetch_size = intel_fake_agp_fetch_size,
1515 .cleanup = intel_gtt_cleanup,
1516 .mask_memory = intel_gen6_mask_memory,
1517 .masks = intel_gen6_masks,
1518 .agp_enable = intel_fake_agp_enable,
1519 .cache_flush = global_cache_flush,
1520 .create_gatt_table = intel_fake_agp_create_gatt_table,
1521 .free_gatt_table = intel_fake_agp_free_gatt_table,
1522 .insert_memory = intel_i915_insert_entries,
1523 .remove_memory = intel_i915_remove_entries,
1524 .alloc_by_type = intel_fake_agp_alloc_by_type,
1525 .free_by_type = intel_i810_free_by_type,
1526 .agp_alloc_page = agp_generic_alloc_page,
1527 .agp_alloc_pages = agp_generic_alloc_pages,
1528 .agp_destroy_page = agp_generic_destroy_page,
1529 .agp_destroy_pages = agp_generic_destroy_pages,
1530 .agp_type_to_mask_type = intel_gen6_type_to_mask_type,
1531 .chipset_flush = intel_i915_chipset_flush,
1532 #if USE_PCI_DMA_API
1533 .agp_map_page = intel_agp_map_page,
1534 .agp_unmap_page = intel_agp_unmap_page,
1535 .agp_map_memory = intel_agp_map_memory,
1536 .agp_unmap_memory = intel_agp_unmap_memory,
1537 #endif
1538 };
1539
1540 static const struct agp_bridge_driver intel_g33_driver = {
1541 .owner = THIS_MODULE,
1542 .size_type = FIXED_APER_SIZE,
1543 .aperture_sizes = intel_fake_agp_sizes,
1544 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1545 .needs_scratch_page = true,
1546 .configure = intel_i9xx_configure,
1547 .fetch_size = intel_fake_agp_fetch_size,
1548 .cleanup = intel_gtt_cleanup,
1549 .mask_memory = intel_i965_mask_memory,
1550 .masks = intel_i810_masks,
1551 .agp_enable = intel_fake_agp_enable,
1552 .cache_flush = global_cache_flush,
1553 .create_gatt_table = intel_fake_agp_create_gatt_table,
1554 .free_gatt_table = intel_fake_agp_free_gatt_table,
1555 .insert_memory = intel_i915_insert_entries,
1556 .remove_memory = intel_i915_remove_entries,
1557 .alloc_by_type = intel_fake_agp_alloc_by_type,
1558 .free_by_type = intel_i810_free_by_type,
1559 .agp_alloc_page = agp_generic_alloc_page,
1560 .agp_alloc_pages = agp_generic_alloc_pages,
1561 .agp_destroy_page = agp_generic_destroy_page,
1562 .agp_destroy_pages = agp_generic_destroy_pages,
1563 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1564 .chipset_flush = intel_i915_chipset_flush,
1565 #if USE_PCI_DMA_API
1566 .agp_map_page = intel_agp_map_page,
1567 .agp_unmap_page = intel_agp_unmap_page,
1568 .agp_map_memory = intel_agp_map_memory,
1569 .agp_unmap_memory = intel_agp_unmap_memory,
1570 #endif
1571 };
1572
1573 static const struct intel_gtt_driver i8xx_gtt_driver = {
1574 .gen = 2,
1575 .setup = i830_setup,
1576 };
1577 static const struct intel_gtt_driver i915_gtt_driver = {
1578 .gen = 3,
1579 .setup = i9xx_setup,
1580 };
1581 static const struct intel_gtt_driver g33_gtt_driver = {
1582 .gen = 3,
1583 .is_g33 = 1,
1584 .setup = i9xx_setup,
1585 };
1586 static const struct intel_gtt_driver pineview_gtt_driver = {
1587 .gen = 3,
1588 .is_pineview = 1, .is_g33 = 1,
1589 .setup = i9xx_setup,
1590 };
1591 static const struct intel_gtt_driver i965_gtt_driver = {
1592 .gen = 4,
1593 .setup = i9xx_setup,
1594 };
1595 static const struct intel_gtt_driver g4x_gtt_driver = {
1596 .gen = 5,
1597 .setup = i9xx_setup,
1598 };
1599 static const struct intel_gtt_driver ironlake_gtt_driver = {
1600 .gen = 5,
1601 .is_ironlake = 1,
1602 .setup = i9xx_setup,
1603 };
1604 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1605 .gen = 6,
1606 .setup = i9xx_setup,
1607 };
1608
1609 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1610 * driver and gmch_driver must be non-null, and find_gmch will determine
1611 * which one should be used if a gmch_chip_id is present.
1612 */
1613 static const struct intel_gtt_driver_description {
1614 unsigned int gmch_chip_id;
1615 char *name;
1616 const struct agp_bridge_driver *gmch_driver;
1617 const struct intel_gtt_driver *gtt_driver;
1618 } intel_gtt_chipsets[] = {
1619 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver , NULL},
1620 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver , NULL},
1621 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver , NULL},
1622 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver , NULL},
1623 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1624 &intel_830_driver , &i8xx_gtt_driver},
1625 { PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1626 &intel_830_driver , &i8xx_gtt_driver},
1627 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1628 &intel_830_driver , &i8xx_gtt_driver},
1629 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1630 &intel_830_driver , &i8xx_gtt_driver},
1631 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1632 &intel_830_driver , &i8xx_gtt_driver},
1633 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1634 &intel_915_driver , &i915_gtt_driver },
1635 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1636 &intel_915_driver , &i915_gtt_driver },
1637 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1638 &intel_915_driver , &i915_gtt_driver },
1639 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1640 &intel_915_driver , &i915_gtt_driver },
1641 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1642 &intel_915_driver , &i915_gtt_driver },
1643 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1644 &intel_915_driver , &i915_gtt_driver },
1645 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1646 &intel_i965_driver , &i965_gtt_driver },
1647 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1648 &intel_i965_driver , &i965_gtt_driver },
1649 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1650 &intel_i965_driver , &i965_gtt_driver },
1651 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1652 &intel_i965_driver , &i965_gtt_driver },
1653 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1654 &intel_i965_driver , &i965_gtt_driver },
1655 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1656 &intel_i965_driver , &i965_gtt_driver },
1657 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1658 &intel_g33_driver , &g33_gtt_driver },
1659 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1660 &intel_g33_driver , &g33_gtt_driver },
1661 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1662 &intel_g33_driver , &g33_gtt_driver },
1663 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1664 &intel_g33_driver , &pineview_gtt_driver },
1665 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1666 &intel_g33_driver , &pineview_gtt_driver },
1667 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1668 &intel_i965_driver , &g4x_gtt_driver },
1669 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1670 &intel_i965_driver , &g4x_gtt_driver },
1671 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1672 &intel_i965_driver , &g4x_gtt_driver },
1673 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1674 &intel_i965_driver , &g4x_gtt_driver },
1675 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1676 &intel_i965_driver , &g4x_gtt_driver },
1677 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1678 &intel_i965_driver , &g4x_gtt_driver },
1679 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1680 &intel_i965_driver , &g4x_gtt_driver },
1681 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1682 "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver },
1683 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1684 "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver },
1685 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1686 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1687 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1688 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1689 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1690 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1691 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1692 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1693 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1694 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1695 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1696 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1697 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1698 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1699 { 0, NULL, NULL }
1700 };
1701
1702 static int find_gmch(u16 device)
1703 {
1704 struct pci_dev *gmch_device;
1705
1706 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1707 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1708 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1709 device, gmch_device);
1710 }
1711
1712 if (!gmch_device)
1713 return 0;
1714
1715 intel_private.pcidev = gmch_device;
1716 return 1;
1717 }
1718
1719 int intel_gmch_probe(struct pci_dev *pdev,
1720 struct agp_bridge_data *bridge)
1721 {
1722 int i, mask;
1723 bridge->driver = NULL;
1724
1725 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1726 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1727 bridge->driver =
1728 intel_gtt_chipsets[i].gmch_driver;
1729 intel_private.driver =
1730 intel_gtt_chipsets[i].gtt_driver;
1731 break;
1732 }
1733 }
1734
1735 if (!bridge->driver)
1736 return 0;
1737
1738 bridge->dev_private_data = &intel_private;
1739 bridge->dev = pdev;
1740
1741 intel_private.bridge_dev = pci_dev_get(pdev);
1742
1743 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1744
1745 if (bridge->driver->mask_memory == intel_gen6_mask_memory)
1746 mask = 40;
1747 else if (bridge->driver->mask_memory == intel_i965_mask_memory)
1748 mask = 36;
1749 else
1750 mask = 32;
1751
1752 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1753 dev_err(&intel_private.pcidev->dev,
1754 "set gfx device dma mask %d-bit failed!\n", mask);
1755 else
1756 pci_set_consistent_dma_mask(intel_private.pcidev,
1757 DMA_BIT_MASK(mask));
1758
1759 if (bridge->driver == &intel_810_driver)
1760 return 1;
1761
1762 if (intel_gtt_init() != 0)
1763 return 0;
1764
1765 return 1;
1766 }
1767 EXPORT_SYMBOL(intel_gmch_probe);
1768
1769 struct intel_gtt *intel_gtt_get(void)
1770 {
1771 return &intel_private.base;
1772 }
1773 EXPORT_SYMBOL(intel_gtt_get);
1774
1775 void intel_gmch_remove(struct pci_dev *pdev)
1776 {
1777 if (intel_private.pcidev)
1778 pci_dev_put(intel_private.pcidev);
1779 if (intel_private.bridge_dev)
1780 pci_dev_put(intel_private.bridge_dev);
1781 }
1782 EXPORT_SYMBOL(intel_gmch_remove);
1783
1784 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1785 MODULE_LICENSE("GPL and additional rights");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree