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gma500: begin the config based split
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / gma500 / psb_drv.c
blob69ab61b192ca7cc6944b036289682d014966f12c
1 /**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
5 * All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 **************************************************************************/
21
22 #include <drm/drmP.h>
23 #include <drm/drm.h>
24 #include "psb_drm.h"
25 #include "psb_drv.h"
26 #include "framebuffer.h"
27 #include "psb_reg.h"
28 #include "psb_intel_reg.h"
29 #include "psb_intel_bios.h"
30 #include "mid_bios.h"
31 #include "mdfld_dsi_dbi.h"
32 #include <drm/drm_pciids.h>
33 #include "psb_powermgmt.h"
34 #include <linux/cpu.h>
35 #include <linux/notifier.h>
36 #include <linux/spinlock.h>
37 #include <linux/pm_runtime.h>
38 #include <acpi/video.h>
39
40 static int drm_psb_trap_pagefaults;
41
42 int drm_psb_no_fb;
43
44 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
45
46 MODULE_PARM_DESC(no_fb, "Disable FBdev");
47 MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
48 module_param_named(no_fb, drm_psb_no_fb, int, 0600);
49 module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
50
51
52 static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
53 { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
54 { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
55 #if defined(CONFIG_DRM_PSB_MRST)
56 { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
57 { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
58 { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
59 { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
60 { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
61 { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
62 { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
63 { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
64 #endif
65 #if defined(CONFIG_DRM_PSB_MFLD)
66 { 0x8086, 0x0130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
67 { 0x8086, 0x0131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
68 { 0x8086, 0x0132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
69 { 0x8086, 0x0133, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
70 { 0x8086, 0x0134, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
71 { 0x8086, 0x0135, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
72 { 0x8086, 0x0136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
73 { 0x8086, 0x0137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
74 #endif
75 #if defined(CONFIG_DRM_PSB_CDV)
76 { 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
77 { 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
78 { 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
79 { 0x8086, 0x0be3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
80 { 0x8086, 0x0be4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
81 { 0x8086, 0x0be5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
82 { 0x8086, 0x0be6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
83 { 0x8086, 0x0be7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
84 #endif
85 { 0, 0, 0}
86 };
87 MODULE_DEVICE_TABLE(pci, pciidlist);
88
89 /*
90 * Standard IOCTLs.
91 */
92
93 #define DRM_IOCTL_PSB_SIZES \
94 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
95 struct drm_psb_sizes_arg)
96 #define DRM_IOCTL_PSB_FUSE_REG \
97 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
98 #define DRM_IOCTL_PSB_DC_STATE \
99 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
100 struct drm_psb_dc_state_arg)
101 #define DRM_IOCTL_PSB_ADB \
102 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
103 #define DRM_IOCTL_PSB_MODE_OPERATION \
104 DRM_IOWR(DRM_PSB_MODE_OPERATION + DRM_COMMAND_BASE, \
105 struct drm_psb_mode_operation_arg)
106 #define DRM_IOCTL_PSB_STOLEN_MEMORY \
107 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
108 struct drm_psb_stolen_memory_arg)
109 #define DRM_IOCTL_PSB_REGISTER_RW \
110 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
111 struct drm_psb_register_rw_arg)
112 #define DRM_IOCTL_PSB_DPST \
113 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
114 uint32_t)
115 #define DRM_IOCTL_PSB_GAMMA \
116 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
117 struct drm_psb_dpst_lut_arg)
118 #define DRM_IOCTL_PSB_DPST_BL \
119 DRM_IOWR(DRM_PSB_DPST_BL + DRM_COMMAND_BASE, \
120 uint32_t)
121 #define DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID \
122 DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
123 struct drm_psb_get_pipe_from_crtc_id_arg)
124
125 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
126 struct drm_file *file_priv);
127 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
128 struct drm_file *file_priv);
129 static int psb_adb_ioctl(struct drm_device *dev, void *data,
130 struct drm_file *file_priv);
131 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
132 struct drm_file *file_priv);
133 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
134 struct drm_file *file_priv);
135 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
136 struct drm_file *file_priv);
137 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
138 struct drm_file *file_priv);
139 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
140 struct drm_file *file_priv);
141 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
142 struct drm_file *file_priv);
143
144 #define PSB_IOCTL_DEF(ioctl, func, flags) \
145 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
146
147 static struct drm_ioctl_desc psb_ioctls[] = {
148 PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
149 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
150 PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
151 PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
152 DRM_AUTH),
153 PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
154 DRM_AUTH),
155 PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
156 DRM_AUTH),
157 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
158 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
159 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
160 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
161 psb_intel_get_pipe_from_crtc_id, 0),
162
163 };
164
165 static void psb_lastclose(struct drm_device *dev)
166 {
167 return;
168 }
169
170 static void psb_do_takedown(struct drm_device *dev)
171 {
172 /* FIXME: do we need to clean up the gtt here ? */
173 }
174
175 static int psb_do_init(struct drm_device *dev)
176 {
177 struct drm_psb_private *dev_priv =
178 (struct drm_psb_private *) dev->dev_private;
179 struct psb_gtt *pg = dev_priv->pg;
180
181 uint32_t stolen_gtt;
182
183 int ret = -ENOMEM;
184
185 if (pg->mmu_gatt_start & 0x0FFFFFFF) {
186 dev_err(dev->dev, "Gatt must be 256M aligned. This is a bug.\n");
187 ret = -EINVAL;
188 goto out_err;
189 }
190
191
192 stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
193 stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
194 stolen_gtt =
195 (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
196
197 dev_priv->gatt_free_offset = pg->mmu_gatt_start +
198 (stolen_gtt << PAGE_SHIFT) * 1024;
199
200 if (1 || drm_debug) {
201 uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
202 uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
203 DRM_INFO("SGX core id = 0x%08x\n", core_id);
204 DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
205 (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
206 _PSB_CC_REVISION_MAJOR_SHIFT,
207 (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
208 _PSB_CC_REVISION_MINOR_SHIFT);
209 DRM_INFO
210 ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
211 (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
212 _PSB_CC_REVISION_MAINTENANCE_SHIFT,
213 (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
214 _PSB_CC_REVISION_DESIGNER_SHIFT);
215 }
216
217
218 spin_lock_init(&dev_priv->irqmask_lock);
219
220 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
221 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
222 PSB_RSGX32(PSB_CR_BIF_BANK1);
223 PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
224 PSB_CR_BIF_CTRL);
225 psb_spank(dev_priv);
226
227 /* mmu_gatt ?? */
228 PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
229 return 0;
230 out_err:
231 psb_do_takedown(dev);
232 return ret;
233 }
234
235 static int psb_driver_unload(struct drm_device *dev)
236 {
237 struct drm_psb_private *dev_priv = dev->dev_private;
238
239 /* Kill vblank etc here */
240
241 gma_backlight_exit(dev);
242
243 if (drm_psb_no_fb == 0)
244 psb_modeset_cleanup(dev);
245
246 if (dev_priv) {
247 psb_lid_timer_takedown(dev_priv);
248
249 psb_do_takedown(dev);
250
251
252 if (dev_priv->pf_pd) {
253 psb_mmu_free_pagedir(dev_priv->pf_pd);
254 dev_priv->pf_pd = NULL;
255 }
256 if (dev_priv->mmu) {
257 struct psb_gtt *pg = dev_priv->pg;
258
259 down_read(&pg->sem);
260 psb_mmu_remove_pfn_sequence(
261 psb_mmu_get_default_pd
262 (dev_priv->mmu),
263 pg->mmu_gatt_start,
264 dev_priv->vram_stolen_size >> PAGE_SHIFT);
265 up_read(&pg->sem);
266 psb_mmu_driver_takedown(dev_priv->mmu);
267 dev_priv->mmu = NULL;
268 }
269 psb_gtt_takedown(dev);
270 if (dev_priv->scratch_page) {
271 __free_page(dev_priv->scratch_page);
272 dev_priv->scratch_page = NULL;
273 }
274 if (dev_priv->vdc_reg) {
275 iounmap(dev_priv->vdc_reg);
276 dev_priv->vdc_reg = NULL;
277 }
278 if (dev_priv->sgx_reg) {
279 iounmap(dev_priv->sgx_reg);
280 dev_priv->sgx_reg = NULL;
281 }
282
283 kfree(dev_priv);
284 dev->dev_private = NULL;
285
286 /*destroy VBT data*/
287 psb_intel_destroy_bios(dev);
288 }
289
290 gma_power_uninit(dev);
291
292 return 0;
293 }
294
295
296 static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
297 {
298 struct drm_psb_private *dev_priv;
299 unsigned long resource_start;
300 struct psb_gtt *pg;
301 unsigned long irqflags;
302 int ret = -ENOMEM;
303 uint32_t tt_pages;
304 struct drm_connector *connector;
305 struct psb_intel_output *psb_intel_output;
306
307 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
308 if (dev_priv == NULL)
309 return -ENOMEM;
310
311 dev_priv->ops = (struct psb_ops *)chipset;
312 dev_priv->dev = dev;
313 dev->dev_private = (void *) dev_priv;
314
315 dev_priv->num_pipe = dev_priv->ops->pipes;
316
317 resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
318
319 dev_priv->vdc_reg =
320 ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
321 if (!dev_priv->vdc_reg)
322 goto out_err;
323
324 dev_priv->sgx_reg = ioremap(resource_start + dev_priv->ops->sgx_offset,
325 PSB_SGX_SIZE);
326 if (!dev_priv->sgx_reg)
327 goto out_err;
328
329 ret = dev_priv->ops->chip_setup(dev);
330 if (ret)
331 goto out_err;
332
333 /* Init OSPM support */
334 gma_power_init(dev);
335
336 ret = -ENOMEM;
337
338 dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
339 if (!dev_priv->scratch_page)
340 goto out_err;
341
342 set_pages_uc(dev_priv->scratch_page, 1);
343
344 ret = psb_gtt_init(dev, 0);
345 if (ret)
346 goto out_err;
347
348 dev_priv->mmu = psb_mmu_driver_init((void *)0,
349 drm_psb_trap_pagefaults, 0,
350 dev_priv);
351 if (!dev_priv->mmu)
352 goto out_err;
353
354 pg = dev_priv->pg;
355
356 tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
357 (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
358
359
360 dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
361 if (!dev_priv->pf_pd)
362 goto out_err;
363
364 psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
365 psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
366
367 ret = psb_do_init(dev);
368 if (ret)
369 return ret;
370
371 PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
372 PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
373
374 /* igd_opregion_init(&dev_priv->opregion_dev); */
375 acpi_video_register();
376 if (dev_priv->lid_state)
377 psb_lid_timer_init(dev_priv);
378
379 ret = drm_vblank_init(dev, dev_priv->num_pipe);
380 if (ret)
381 goto out_err;
382
383 /*
384 * Install interrupt handlers prior to powering off SGX or else we will
385 * crash.
386 */
387 dev_priv->vdc_irq_mask = 0;
388 dev_priv->pipestat[0] = 0;
389 dev_priv->pipestat[1] = 0;
390 dev_priv->pipestat[2] = 0;
391 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
392 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
393 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
394 PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
395 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
396 if (drm_core_check_feature(dev, DRIVER_MODESET))
397 drm_irq_install(dev);
398
399 dev->vblank_disable_allowed = 1;
400
401 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
402
403 dev->driver->get_vblank_counter = psb_get_vblank_counter;
404
405 #if defined(CONFIG_DRM_PSB_MFLD)
406 /* FIXME: this is not the right place for this stuff ! */
407 if (IS_MFLD(dev)) {
408 #ifdef CONFIG_MDFLD_DSI_DPU
409 /*init dpu info*/
410 mdfld_dbi_dpu_init(dev);
411 #else
412 mdfld_dbi_dsr_init(dev);
413 #endif /*CONFIG_MDFLD_DSI_DPU*/
414 /* INIT_WORK(&dev_priv->te_work, mdfld_te_handler_work);*/
415 }
416 #endif
417 if (drm_psb_no_fb == 0) {
418 psb_modeset_init(dev);
419 psb_fbdev_init(dev);
420 drm_kms_helper_poll_init(dev);
421 }
422
423 /* Only add backlight support if we have LVDS output */
424 list_for_each_entry(connector, &dev->mode_config.connector_list,
425 head) {
426 psb_intel_output = to_psb_intel_output(connector);
427
428 switch (psb_intel_output->type) {
429 case INTEL_OUTPUT_LVDS:
430 ret = gma_backlight_init(dev);
431 break;
432 }
433 }
434
435 if (ret)
436 return ret;
437 #if 0
438 /*enable runtime pm at last*/
439 pm_runtime_enable(&dev->pdev->dev);
440 pm_runtime_set_active(&dev->pdev->dev);
441 #endif
442 /*Intel drm driver load is done, continue doing pvr load*/
443 return 0;
444 out_err:
445 psb_driver_unload(dev);
446 return ret;
447 }
448
449 int psb_driver_device_is_agp(struct drm_device *dev)
450 {
451 return 0;
452 }
453
454
455 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
456 struct drm_file *file_priv)
457 {
458 struct drm_psb_private *dev_priv = psb_priv(dev);
459 struct drm_psb_sizes_arg *arg =
460 (struct drm_psb_sizes_arg *) data;
461
462 *arg = dev_priv->sizes;
463 return 0;
464 }
465
466 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
467 struct drm_file *file_priv)
468 {
469 uint32_t flags;
470 uint32_t obj_id;
471 struct drm_mode_object *obj;
472 struct drm_connector *connector;
473 struct drm_crtc *crtc;
474 struct drm_psb_dc_state_arg *arg =
475 (struct drm_psb_dc_state_arg *)data;
476
477
478 /* Double check MRST case */
479 if (IS_MRST(dev) || IS_MFLD(dev))
480 return -EOPNOTSUPP;
481
482 flags = arg->flags;
483 obj_id = arg->obj_id;
484
485 if (flags & PSB_DC_CRTC_MASK) {
486 obj = drm_mode_object_find(dev, obj_id,
487 DRM_MODE_OBJECT_CRTC);
488 if (!obj) {
489 dev_dbg(dev->dev, "Invalid CRTC object.\n");
490 return -EINVAL;
491 }
492
493 crtc = obj_to_crtc(obj);
494
495 mutex_lock(&dev->mode_config.mutex);
496 if (drm_helper_crtc_in_use(crtc)) {
497 if (flags & PSB_DC_CRTC_SAVE)
498 crtc->funcs->save(crtc);
499 else
500 crtc->funcs->restore(crtc);
501 }
502 mutex_unlock(&dev->mode_config.mutex);
503
504 return 0;
505 } else if (flags & PSB_DC_OUTPUT_MASK) {
506 obj = drm_mode_object_find(dev, obj_id,
507 DRM_MODE_OBJECT_CONNECTOR);
508 if (!obj) {
509 dev_dbg(dev->dev, "Invalid connector id.\n");
510 return -EINVAL;
511 }
512
513 connector = obj_to_connector(obj);
514 if (flags & PSB_DC_OUTPUT_SAVE)
515 connector->funcs->save(connector);
516 else
517 connector->funcs->restore(connector);
518
519 return 0;
520 }
521 return -EINVAL;
522 }
523
524 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
525 struct drm_file *file_priv)
526 {
527 struct drm_psb_private *dev_priv = psb_priv(dev);
528 uint32_t *arg = data;
529 struct backlight_device *bd = dev_priv->backlight_device;
530 dev_priv->blc_adj2 = *arg;
531
532 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
533 if (bd) {
534 bd->props.brightness = bd->ops->get_brightness(bd);
535 backlight_update_status(bd);
536 }
537 #endif
538 return 0;
539 }
540
541 static int psb_adb_ioctl(struct drm_device *dev, void *data,
542 struct drm_file *file_priv)
543 {
544 struct drm_psb_private *dev_priv = psb_priv(dev);
545 uint32_t *arg = data;
546 struct backlight_device *bd = dev_priv->backlight_device;
547 dev_priv->blc_adj1 = *arg;
548
549 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
550 if (bd) {
551 bd->props.brightness = bd->ops->get_brightness(bd);
552 backlight_update_status(bd);
553 }
554 #endif
555 return 0;
556 }
557
558 /* return the current mode to the dpst module */
559 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
560 struct drm_file *file_priv)
561 {
562 struct drm_psb_private *dev_priv = psb_priv(dev);
563 uint32_t *arg = data;
564 uint32_t x;
565 uint32_t y;
566 uint32_t reg;
567
568 if (!gma_power_begin(dev, 0))
569 return -EIO;
570
571 reg = PSB_RVDC32(PIPEASRC);
572
573 gma_power_end(dev);
574
575 /* horizontal is the left 16 bits */
576 x = reg >> 16;
577 /* vertical is the right 16 bits */
578 y = reg & 0x0000ffff;
579
580 /* the values are the image size minus one */
581 x++;
582 y++;
583
584 *arg = (x << 16) | y;
585
586 return 0;
587 }
588 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
589 struct drm_file *file_priv)
590 {
591 struct drm_psb_dpst_lut_arg *lut_arg = data;
592 struct drm_mode_object *obj;
593 struct drm_crtc *crtc;
594 struct drm_connector *connector;
595 struct psb_intel_crtc *psb_intel_crtc;
596 int i = 0;
597 int32_t obj_id;
598
599 obj_id = lut_arg->output_id;
600 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_CONNECTOR);
601 if (!obj) {
602 dev_dbg(dev->dev, "Invalid Connector object.\n");
603 return -EINVAL;
604 }
605
606 connector = obj_to_connector(obj);
607 crtc = connector->encoder->crtc;
608 psb_intel_crtc = to_psb_intel_crtc(crtc);
609
610 for (i = 0; i < 256; i++)
611 psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
612
613 psb_intel_crtc_load_lut(crtc);
614
615 return 0;
616 }
617
618 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
619 struct drm_file *file_priv)
620 {
621 uint32_t obj_id;
622 uint16_t op;
623 struct drm_mode_modeinfo *umode;
624 struct drm_display_mode *mode = NULL;
625 struct drm_psb_mode_operation_arg *arg;
626 struct drm_mode_object *obj;
627 struct drm_connector *connector;
628 struct drm_framebuffer *drm_fb;
629 struct psb_framebuffer *psb_fb;
630 struct drm_connector_helper_funcs *connector_funcs;
631 int ret = 0;
632 int resp = MODE_OK;
633 struct drm_psb_private *dev_priv = psb_priv(dev);
634
635 arg = (struct drm_psb_mode_operation_arg *)data;
636 obj_id = arg->obj_id;
637 op = arg->operation;
638
639 switch (op) {
640 case PSB_MODE_OPERATION_SET_DC_BASE:
641 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
642 if (!obj) {
643 dev_dbg(dev->dev, "Invalid FB id %d\n", obj_id);
644 return -EINVAL;
645 }
646
647 drm_fb = obj_to_fb(obj);
648 psb_fb = to_psb_fb(drm_fb);
649
650 if (gma_power_begin(dev, 0)) {
651 REG_WRITE(DSPASURF, psb_fb->gtt->offset);
652 REG_READ(DSPASURF);
653 gma_power_end(dev);
654 } else {
655 dev_priv->saveDSPASURF = psb_fb->gtt->offset;
656 }
657
658 return 0;
659 case PSB_MODE_OPERATION_MODE_VALID:
660 umode = &arg->mode;
661
662 mutex_lock(&dev->mode_config.mutex);
663
664 obj = drm_mode_object_find(dev, obj_id,
665 DRM_MODE_OBJECT_CONNECTOR);
666 if (!obj) {
667 ret = -EINVAL;
668 goto mode_op_out;
669 }
670
671 connector = obj_to_connector(obj);
672
673 mode = drm_mode_create(dev);
674 if (!mode) {
675 ret = -ENOMEM;
676 goto mode_op_out;
677 }
678
679 /* drm_crtc_convert_umode(mode, umode); */
680 {
681 mode->clock = umode->clock;
682 mode->hdisplay = umode->hdisplay;
683 mode->hsync_start = umode->hsync_start;
684 mode->hsync_end = umode->hsync_end;
685 mode->htotal = umode->htotal;
686 mode->hskew = umode->hskew;
687 mode->vdisplay = umode->vdisplay;
688 mode->vsync_start = umode->vsync_start;
689 mode->vsync_end = umode->vsync_end;
690 mode->vtotal = umode->vtotal;
691 mode->vscan = umode->vscan;
692 mode->vrefresh = umode->vrefresh;
693 mode->flags = umode->flags;
694 mode->type = umode->type;
695 strncpy(mode->name, umode->name, DRM_DISPLAY_MODE_LEN);
696 mode->name[DRM_DISPLAY_MODE_LEN-1] = 0;
697 }
698
699 connector_funcs = (struct drm_connector_helper_funcs *)
700 connector->helper_private;
701
702 if (connector_funcs->mode_valid) {
703 resp = connector_funcs->mode_valid(connector, mode);
704 arg->data = (void *)resp;
705 }
706
707 /*do some clean up work*/
708 if (mode)
709 drm_mode_destroy(dev, mode);
710 mode_op_out:
711 mutex_unlock(&dev->mode_config.mutex);
712 return ret;
713
714 default:
715 dev_dbg(dev->dev, "Unsupported psb mode operation\n");
716 return -EOPNOTSUPP;
717 }
718
719 return 0;
720 }
721
722 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
723 struct drm_file *file_priv)
724 {
725 struct drm_psb_private *dev_priv = psb_priv(dev);
726 struct drm_psb_stolen_memory_arg *arg = data;
727
728 arg->base = dev_priv->stolen_base;
729 arg->size = dev_priv->vram_stolen_size;
730
731 return 0;
732 }
733
734 /* FIXME: needs Medfield changes */
735 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
736 struct drm_file *file_priv)
737 {
738 struct drm_psb_private *dev_priv = psb_priv(dev);
739 struct drm_psb_register_rw_arg *arg = data;
740 bool usage = arg->b_force_hw_on ? true : false;
741
742 if (arg->display_write_mask != 0) {
743 if (gma_power_begin(dev, usage)) {
744 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
745 PSB_WVDC32(arg->display.pfit_controls,
746 PFIT_CONTROL);
747 if (arg->display_write_mask &
748 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
749 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
750 PFIT_AUTO_RATIOS);
751 if (arg->display_write_mask &
752 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
753 PSB_WVDC32(
754 arg->display.pfit_programmed_scale_ratios,
755 PFIT_PGM_RATIOS);
756 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
757 PSB_WVDC32(arg->display.pipeasrc,
758 PIPEASRC);
759 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
760 PSB_WVDC32(arg->display.pipebsrc,
761 PIPEBSRC);
762 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
763 PSB_WVDC32(arg->display.vtotal_a,
764 VTOTAL_A);
765 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
766 PSB_WVDC32(arg->display.vtotal_b,
767 VTOTAL_B);
768 gma_power_end(dev);
769 } else {
770 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
771 dev_priv->savePFIT_CONTROL =
772 arg->display.pfit_controls;
773 if (arg->display_write_mask &
774 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
775 dev_priv->savePFIT_AUTO_RATIOS =
776 arg->display.pfit_autoscale_ratios;
777 if (arg->display_write_mask &
778 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
779 dev_priv->savePFIT_PGM_RATIOS =
780 arg->display.pfit_programmed_scale_ratios;
781 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
782 dev_priv->savePIPEASRC = arg->display.pipeasrc;
783 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
784 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
785 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
786 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
787 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
788 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
789 }
790 }
791
792 if (arg->display_read_mask != 0) {
793 if (gma_power_begin(dev, usage)) {
794 if (arg->display_read_mask &
795 REGRWBITS_PFIT_CONTROLS)
796 arg->display.pfit_controls =
797 PSB_RVDC32(PFIT_CONTROL);
798 if (arg->display_read_mask &
799 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
800 arg->display.pfit_autoscale_ratios =
801 PSB_RVDC32(PFIT_AUTO_RATIOS);
802 if (arg->display_read_mask &
803 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
804 arg->display.pfit_programmed_scale_ratios =
805 PSB_RVDC32(PFIT_PGM_RATIOS);
806 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
807 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
808 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
809 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
810 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
811 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
812 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
813 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
814 gma_power_end(dev);
815 } else {
816 if (arg->display_read_mask &
817 REGRWBITS_PFIT_CONTROLS)
818 arg->display.pfit_controls =
819 dev_priv->savePFIT_CONTROL;
820 if (arg->display_read_mask &
821 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
822 arg->display.pfit_autoscale_ratios =
823 dev_priv->savePFIT_AUTO_RATIOS;
824 if (arg->display_read_mask &
825 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
826 arg->display.pfit_programmed_scale_ratios =
827 dev_priv->savePFIT_PGM_RATIOS;
828 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
829 arg->display.pipeasrc = dev_priv->savePIPEASRC;
830 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
831 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
832 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
833 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
834 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
835 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
836 }
837 }
838
839 if (arg->overlay_write_mask != 0) {
840 if (gma_power_begin(dev, usage)) {
841 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
842 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
843 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
844 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
845 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
846 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
847 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
848 }
849 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
850 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
851 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
852 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
853 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
854 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
855 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
856 }
857
858 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
859 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
860
861 if (arg->overlay.b_wait_vblank) {
862 /* Wait for 20ms.*/
863 unsigned long vblank_timeout = jiffies
864 + HZ/50;
865 uint32_t temp;
866 while (time_before_eq(jiffies,
867 vblank_timeout)) {
868 temp = PSB_RVDC32(OV_DOVASTA);
869 if ((temp & (0x1 << 31)) != 0)
870 break;
871 cpu_relax();
872 }
873 }
874 }
875 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
876 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
877 if (arg->overlay.b_wait_vblank) {
878 /* Wait for 20ms.*/
879 unsigned long vblank_timeout =
880 jiffies + HZ/50;
881 uint32_t temp;
882 while (time_before_eq(jiffies,
883 vblank_timeout)) {
884 temp = PSB_RVDC32(OVC_DOVCSTA);
885 if ((temp & (0x1 << 31)) != 0)
886 break;
887 cpu_relax();
888 }
889 }
890 }
891 gma_power_end(dev);
892 } else {
893 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
894 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
895 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
896 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
897 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
898 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
899 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
900 }
901 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
902 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
903 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
904 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
905 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
906 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
907 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
908 }
909 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
910 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
911 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
912 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
913 }
914 }
915
916 if (arg->overlay_read_mask != 0) {
917 if (gma_power_begin(dev, usage)) {
918 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
919 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
920 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
921 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
922 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
923 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
924 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
925 }
926 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
927 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
928 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
929 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
930 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
931 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
932 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
933 }
934 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
935 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
936 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
937 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
938 gma_power_end(dev);
939 } else {
940 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
941 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
942 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
943 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
944 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
945 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
946 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
947 }
948 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
949 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
950 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
951 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
952 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
953 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
954 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
955 }
956 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
957 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
958 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
959 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
960 }
961 }
962
963 if (arg->sprite_enable_mask != 0) {
964 if (gma_power_begin(dev, usage)) {
965 PSB_WVDC32(0x1F3E, DSPARB);
966 PSB_WVDC32(arg->sprite.dspa_control
967 | PSB_RVDC32(DSPACNTR), DSPACNTR);
968 PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
969 PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
970 PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
971 PSB_RVDC32(DSPASURF);
972 PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
973 PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
974 PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
975 PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
976 PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
977 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
978 PSB_RVDC32(DSPCSURF);
979 gma_power_end(dev);
980 }
981 }
982
983 if (arg->sprite_disable_mask != 0) {
984 if (gma_power_begin(dev, usage)) {
985 PSB_WVDC32(0x3F3E, DSPARB);
986 PSB_WVDC32(0x0, DSPCCNTR);
987 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
988 PSB_RVDC32(DSPCSURF);
989 gma_power_end(dev);
990 }
991 }
992
993 if (arg->subpicture_enable_mask != 0) {
994 if (gma_power_begin(dev, usage)) {
995 uint32_t temp;
996 if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
997 temp = PSB_RVDC32(DSPACNTR);
998 temp &= ~DISPPLANE_PIXFORMAT_MASK;
999 temp &= ~DISPPLANE_BOTTOM;
1000 temp |= DISPPLANE_32BPP;
1001 PSB_WVDC32(temp, DSPACNTR);
1002
1003 temp = PSB_RVDC32(DSPABASE);
1004 PSB_WVDC32(temp, DSPABASE);
1005 PSB_RVDC32(DSPABASE);
1006 temp = PSB_RVDC32(DSPASURF);
1007 PSB_WVDC32(temp, DSPASURF);
1008 PSB_RVDC32(DSPASURF);
1009 }
1010 if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
1011 temp = PSB_RVDC32(DSPBCNTR);
1012 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1013 temp &= ~DISPPLANE_BOTTOM;
1014 temp |= DISPPLANE_32BPP;
1015 PSB_WVDC32(temp, DSPBCNTR);
1016
1017 temp = PSB_RVDC32(DSPBBASE);
1018 PSB_WVDC32(temp, DSPBBASE);
1019 PSB_RVDC32(DSPBBASE);
1020 temp = PSB_RVDC32(DSPBSURF);
1021 PSB_WVDC32(temp, DSPBSURF);
1022 PSB_RVDC32(DSPBSURF);
1023 }
1024 if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1025 temp = PSB_RVDC32(DSPCCNTR);
1026 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1027 temp &= ~DISPPLANE_BOTTOM;
1028 temp |= DISPPLANE_32BPP;
1029 PSB_WVDC32(temp, DSPCCNTR);
1030
1031 temp = PSB_RVDC32(DSPCBASE);
1032 PSB_WVDC32(temp, DSPCBASE);
1033 PSB_RVDC32(DSPCBASE);
1034 temp = PSB_RVDC32(DSPCSURF);
1035 PSB_WVDC32(temp, DSPCSURF);
1036 PSB_RVDC32(DSPCSURF);
1037 }
1038 gma_power_end(dev);
1039 }
1040 }
1041
1042 if (arg->subpicture_disable_mask != 0) {
1043 if (gma_power_begin(dev, usage)) {
1044 uint32_t temp;
1045 if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1046 temp = PSB_RVDC32(DSPACNTR);
1047 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1048 temp |= DISPPLANE_32BPP_NO_ALPHA;
1049 PSB_WVDC32(temp, DSPACNTR);
1050
1051 temp = PSB_RVDC32(DSPABASE);
1052 PSB_WVDC32(temp, DSPABASE);
1053 PSB_RVDC32(DSPABASE);
1054 temp = PSB_RVDC32(DSPASURF);
1055 PSB_WVDC32(temp, DSPASURF);
1056 PSB_RVDC32(DSPASURF);
1057 }
1058 if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1059 temp = PSB_RVDC32(DSPBCNTR);
1060 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1061 temp |= DISPPLANE_32BPP_NO_ALPHA;
1062 PSB_WVDC32(temp, DSPBCNTR);
1063
1064 temp = PSB_RVDC32(DSPBBASE);
1065 PSB_WVDC32(temp, DSPBBASE);
1066 PSB_RVDC32(DSPBBASE);
1067 temp = PSB_RVDC32(DSPBSURF);
1068 PSB_WVDC32(temp, DSPBSURF);
1069 PSB_RVDC32(DSPBSURF);
1070 }
1071 if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1072 temp = PSB_RVDC32(DSPCCNTR);
1073 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1074 temp |= DISPPLANE_32BPP_NO_ALPHA;
1075 PSB_WVDC32(temp, DSPCCNTR);
1076
1077 temp = PSB_RVDC32(DSPCBASE);
1078 PSB_WVDC32(temp, DSPCBASE);
1079 PSB_RVDC32(DSPCBASE);
1080 temp = PSB_RVDC32(DSPCSURF);
1081 PSB_WVDC32(temp, DSPCSURF);
1082 PSB_RVDC32(DSPCSURF);
1083 }
1084 gma_power_end(dev);
1085 }
1086 }
1087
1088 return 0;
1089 }
1090
1091 static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1092 {
1093 return 0;
1094 }
1095
1096 static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
1097 {
1098 }
1099
1100 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
1101 unsigned long arg)
1102 {
1103 struct drm_file *file_priv = filp->private_data;
1104 struct drm_device *dev = file_priv->minor->dev;
1105 struct drm_psb_private *dev_priv = dev->dev_private;
1106 static unsigned int runtime_allowed;
1107
1108 if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
1109 runtime_allowed++;
1110 pm_runtime_allow(&dev->pdev->dev);
1111 dev_priv->rpm_enabled = 1;
1112 }
1113 return drm_ioctl(filp, cmd, arg);
1114 /* FIXME: do we need to wrap the other side of this */
1115 }
1116
1117
1118 /* When a client dies:
1119 * - Check for and clean up flipped page state
1120 */
1121 void psb_driver_preclose(struct drm_device *dev, struct drm_file *priv)
1122 {
1123 }
1124
1125 static void psb_remove(struct pci_dev *pdev)
1126 {
1127 struct drm_device *dev = pci_get_drvdata(pdev);
1128 drm_put_dev(dev);
1129 }
1130
1131 static const struct dev_pm_ops psb_pm_ops = {
1132 .runtime_suspend = psb_runtime_suspend,
1133 .runtime_resume = psb_runtime_resume,
1134 .runtime_idle = psb_runtime_idle,
1135 };
1136
1137 static struct vm_operations_struct psb_gem_vm_ops = {
1138 .fault = psb_gem_fault,
1139 .open = drm_gem_vm_open,
1140 .close = drm_gem_vm_close,
1141 };
1142
1143 static struct drm_driver driver = {
1144 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
1145 DRIVER_IRQ_VBL | DRIVER_MODESET | DRIVER_GEM ,
1146 .load = psb_driver_load,
1147 .unload = psb_driver_unload,
1148
1149 .ioctls = psb_ioctls,
1150 .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
1151 .device_is_agp = psb_driver_device_is_agp,
1152 .irq_preinstall = psb_irq_preinstall,
1153 .irq_postinstall = psb_irq_postinstall,
1154 .irq_uninstall = psb_irq_uninstall,
1155 .irq_handler = psb_irq_handler,
1156 .enable_vblank = psb_enable_vblank,
1157 .disable_vblank = psb_disable_vblank,
1158 .get_vblank_counter = psb_get_vblank_counter,
1159 .lastclose = psb_lastclose,
1160 .open = psb_driver_open,
1161 .preclose = psb_driver_preclose,
1162 .postclose = psb_driver_close,
1163 .reclaim_buffers = drm_core_reclaim_buffers,
1164
1165 .gem_init_object = psb_gem_init_object,
1166 .gem_free_object = psb_gem_free_object,
1167 .gem_vm_ops = &psb_gem_vm_ops,
1168 .dumb_create = psb_gem_dumb_create,
1169 .dumb_map_offset = psb_gem_dumb_map_gtt,
1170 .dumb_destroy = psb_gem_dumb_destroy,
1171
1172 .fops = {
1173 .owner = THIS_MODULE,
1174 .open = drm_open,
1175 .release = drm_release,
1176 .unlocked_ioctl = psb_unlocked_ioctl,
1177 .mmap = drm_gem_mmap,
1178 .poll = drm_poll,
1179 .fasync = drm_fasync,
1180 .read = drm_read,
1181 },
1182 .name = DRIVER_NAME,
1183 .desc = DRIVER_DESC,
1184 .date = PSB_DRM_DRIVER_DATE,
1185 .major = PSB_DRM_DRIVER_MAJOR,
1186 .minor = PSB_DRM_DRIVER_MINOR,
1187 .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
1188 };
1189
1190 static struct pci_driver psb_pci_driver = {
1191 .name = DRIVER_NAME,
1192 .id_table = pciidlist,
1193 .resume = gma_power_resume,
1194 .suspend = gma_power_suspend,
1195 .probe = psb_probe,
1196 .remove = psb_remove,
1197 #ifdef CONFIG_PM
1198 .driver.pm = &psb_pm_ops,
1199 #endif
1200 };
1201
1202 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1203 {
1204 /* MLD Added this from Inaky's patch */
1205 if (pci_enable_msi(pdev))
1206 dev_warn(&pdev->dev, "Enable MSI failed!\n");
1207 return drm_get_pci_dev(pdev, ent, &driver);
1208 }
1209
1210 static int __init psb_init(void)
1211 {
1212 return drm_pci_init(&driver, &psb_pci_driver);
1213 }
1214
1215 static void __exit psb_exit(void)
1216 {
1217 drm_pci_exit(&driver, &psb_pci_driver);
1218 }
1219
1220 late_initcall(psb_init);
1221 module_exit(psb_exit);
1222
1223 MODULE_AUTHOR("Alan Cox <alan@linux.intel.com> and others");
1224 MODULE_DESCRIPTION(DRIVER_DESC);
1225 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree