1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/sysdev.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/slab.h>
8 #include <linux/hpet.h>
9 #include <linux/init.h>
10 #include <linux/cpu.h>
14 #include <asm/fixmap.h>
15 #include <asm/i8253.h>
18 #define HPET_MASK CLOCKSOURCE_MASK(32)
23 #define FSEC_PER_NSEC 1000000L
25 #define HPET_DEV_USED_BIT 2
26 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
27 #define HPET_DEV_VALID 0x8
28 #define HPET_DEV_FSB_CAP 0x1000
29 #define HPET_DEV_PERI_CAP 0x2000
31 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
34 * HPET address is set in acpi/boot.c, when an ACPI entry exists
36 unsigned long hpet_address
;
37 u8 hpet_blockid
; /* OS timer block num */
41 static unsigned long hpet_num_timers
;
43 static void __iomem
*hpet_virt_address
;
46 struct clock_event_device evt
;
54 inline unsigned int hpet_readl(unsigned int a
)
56 return readl(hpet_virt_address
+ a
);
59 static inline void hpet_writel(unsigned int d
, unsigned int a
)
61 writel(d
, hpet_virt_address
+ a
);
65 #include <asm/pgtable.h>
68 static inline void hpet_set_mapping(void)
70 hpet_virt_address
= ioremap_nocache(hpet_address
, HPET_MMAP_SIZE
);
72 __set_fixmap(VSYSCALL_HPET
, hpet_address
, PAGE_KERNEL_VSYSCALL_NOCACHE
);
76 static inline void hpet_clear_mapping(void)
78 iounmap(hpet_virt_address
);
79 hpet_virt_address
= NULL
;
83 * HPET command line enable / disable
85 static int boot_hpet_disable
;
87 static int hpet_verbose
;
89 static int __init
hpet_setup(char *str
)
92 if (!strncmp("disable", str
, 7))
93 boot_hpet_disable
= 1;
94 if (!strncmp("force", str
, 5))
96 if (!strncmp("verbose", str
, 7))
101 __setup("hpet=", hpet_setup
);
103 static int __init
disable_hpet(char *str
)
105 boot_hpet_disable
= 1;
108 __setup("nohpet", disable_hpet
);
110 static inline int is_hpet_capable(void)
112 return !boot_hpet_disable
&& hpet_address
;
116 * HPET timer interrupt enable / disable
118 static int hpet_legacy_int_enabled
;
121 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
123 int is_hpet_enabled(void)
125 return is_hpet_capable() && hpet_legacy_int_enabled
;
127 EXPORT_SYMBOL_GPL(is_hpet_enabled
);
129 static void _hpet_print_config(const char *function
, int line
)
132 printk(KERN_INFO
"hpet: %s(%d):\n", function
, line
);
133 l
= hpet_readl(HPET_ID
);
134 h
= hpet_readl(HPET_PERIOD
);
135 timers
= ((l
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
) + 1;
136 printk(KERN_INFO
"hpet: ID: 0x%x, PERIOD: 0x%x\n", l
, h
);
137 l
= hpet_readl(HPET_CFG
);
138 h
= hpet_readl(HPET_STATUS
);
139 printk(KERN_INFO
"hpet: CFG: 0x%x, STATUS: 0x%x\n", l
, h
);
140 l
= hpet_readl(HPET_COUNTER
);
141 h
= hpet_readl(HPET_COUNTER
+4);
142 printk(KERN_INFO
"hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l
, h
);
144 for (i
= 0; i
< timers
; i
++) {
145 l
= hpet_readl(HPET_Tn_CFG(i
));
146 h
= hpet_readl(HPET_Tn_CFG(i
)+4);
147 printk(KERN_INFO
"hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
149 l
= hpet_readl(HPET_Tn_CMP(i
));
150 h
= hpet_readl(HPET_Tn_CMP(i
)+4);
151 printk(KERN_INFO
"hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
153 l
= hpet_readl(HPET_Tn_ROUTE(i
));
154 h
= hpet_readl(HPET_Tn_ROUTE(i
)+4);
155 printk(KERN_INFO
"hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
160 #define hpet_print_config() \
163 _hpet_print_config(__FUNCTION__, __LINE__); \
167 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
168 * timer 0 and timer 1 in case of RTC emulation.
172 static void hpet_reserve_msi_timers(struct hpet_data
*hd
);
174 static void hpet_reserve_platform_timers(unsigned int id
)
176 struct hpet __iomem
*hpet
= hpet_virt_address
;
177 struct hpet_timer __iomem
*timer
= &hpet
->hpet_timers
[2];
178 unsigned int nrtimers
, i
;
181 nrtimers
= ((id
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
) + 1;
183 memset(&hd
, 0, sizeof(hd
));
184 hd
.hd_phys_address
= hpet_address
;
185 hd
.hd_address
= hpet
;
186 hd
.hd_nirqs
= nrtimers
;
187 hpet_reserve_timer(&hd
, 0);
189 #ifdef CONFIG_HPET_EMULATE_RTC
190 hpet_reserve_timer(&hd
, 1);
194 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
195 * is wrong for i8259!) not the output IRQ. Many BIOS writers
196 * don't bother configuring *any* comparator interrupts.
198 hd
.hd_irq
[0] = HPET_LEGACY_8254
;
199 hd
.hd_irq
[1] = HPET_LEGACY_RTC
;
201 for (i
= 2; i
< nrtimers
; timer
++, i
++) {
202 hd
.hd_irq
[i
] = (readl(&timer
->hpet_config
) &
203 Tn_INT_ROUTE_CNF_MASK
) >> Tn_INT_ROUTE_CNF_SHIFT
;
206 hpet_reserve_msi_timers(&hd
);
212 static void hpet_reserve_platform_timers(unsigned int id
) { }
218 static unsigned long hpet_period
;
220 static void hpet_legacy_set_mode(enum clock_event_mode mode
,
221 struct clock_event_device
*evt
);
222 static int hpet_legacy_next_event(unsigned long delta
,
223 struct clock_event_device
*evt
);
226 * The hpet clock event device
228 static struct clock_event_device hpet_clockevent
= {
230 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
231 .set_mode
= hpet_legacy_set_mode
,
232 .set_next_event
= hpet_legacy_next_event
,
238 static void hpet_stop_counter(void)
240 unsigned long cfg
= hpet_readl(HPET_CFG
);
241 cfg
&= ~HPET_CFG_ENABLE
;
242 hpet_writel(cfg
, HPET_CFG
);
245 static void hpet_reset_counter(void)
247 hpet_writel(0, HPET_COUNTER
);
248 hpet_writel(0, HPET_COUNTER
+ 4);
251 static void hpet_start_counter(void)
253 unsigned int cfg
= hpet_readl(HPET_CFG
);
254 cfg
|= HPET_CFG_ENABLE
;
255 hpet_writel(cfg
, HPET_CFG
);
258 static void hpet_restart_counter(void)
261 hpet_reset_counter();
262 hpet_start_counter();
265 static void hpet_resume_device(void)
270 static void hpet_resume_counter(struct clocksource
*cs
)
272 hpet_resume_device();
273 hpet_restart_counter();
276 static void hpet_enable_legacy_int(void)
278 unsigned int cfg
= hpet_readl(HPET_CFG
);
280 cfg
|= HPET_CFG_LEGACY
;
281 hpet_writel(cfg
, HPET_CFG
);
282 hpet_legacy_int_enabled
= 1;
285 static void hpet_legacy_clockevent_register(void)
287 /* Start HPET legacy interrupts */
288 hpet_enable_legacy_int();
291 * The mult factor is defined as (include/linux/clockchips.h)
292 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
293 * hpet_period is in units of femtoseconds (per cycle), so
294 * mult/2^shift = cyc/ns = 10^6/hpet_period
295 * mult = (10^6 * 2^shift)/hpet_period
296 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
298 hpet_clockevent
.mult
= div_sc((unsigned long) FSEC_PER_NSEC
,
299 hpet_period
, hpet_clockevent
.shift
);
300 /* Calculate the min / max delta */
301 hpet_clockevent
.max_delta_ns
= clockevent_delta2ns(0x7FFFFFFF,
303 /* 5 usec minimum reprogramming delta. */
304 hpet_clockevent
.min_delta_ns
= 5000;
307 * Start hpet with the boot cpu mask and make it
308 * global after the IO_APIC has been initialized.
310 hpet_clockevent
.cpumask
= cpumask_of(smp_processor_id());
311 clockevents_register_device(&hpet_clockevent
);
312 global_clock_event
= &hpet_clockevent
;
313 printk(KERN_DEBUG
"hpet clockevent registered\n");
316 static int hpet_setup_msi_irq(unsigned int irq
);
318 static void hpet_set_mode(enum clock_event_mode mode
,
319 struct clock_event_device
*evt
, int timer
)
321 unsigned int cfg
, cmp
, now
;
325 case CLOCK_EVT_MODE_PERIODIC
:
327 delta
= ((uint64_t)(NSEC_PER_SEC
/HZ
)) * evt
->mult
;
328 delta
>>= evt
->shift
;
329 now
= hpet_readl(HPET_COUNTER
);
330 cmp
= now
+ (unsigned int) delta
;
331 cfg
= hpet_readl(HPET_Tn_CFG(timer
));
332 /* Make sure we use edge triggered interrupts */
333 cfg
&= ~HPET_TN_LEVEL
;
334 cfg
|= HPET_TN_ENABLE
| HPET_TN_PERIODIC
|
335 HPET_TN_SETVAL
| HPET_TN_32BIT
;
336 hpet_writel(cfg
, HPET_Tn_CFG(timer
));
337 hpet_writel(cmp
, HPET_Tn_CMP(timer
));
340 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
341 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
342 * bit is automatically cleared after the first write.
343 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
344 * Publication # 24674)
346 hpet_writel((unsigned int) delta
, HPET_Tn_CMP(timer
));
347 hpet_start_counter();
351 case CLOCK_EVT_MODE_ONESHOT
:
352 cfg
= hpet_readl(HPET_Tn_CFG(timer
));
353 cfg
&= ~HPET_TN_PERIODIC
;
354 cfg
|= HPET_TN_ENABLE
| HPET_TN_32BIT
;
355 hpet_writel(cfg
, HPET_Tn_CFG(timer
));
358 case CLOCK_EVT_MODE_UNUSED
:
359 case CLOCK_EVT_MODE_SHUTDOWN
:
360 cfg
= hpet_readl(HPET_Tn_CFG(timer
));
361 cfg
&= ~HPET_TN_ENABLE
;
362 hpet_writel(cfg
, HPET_Tn_CFG(timer
));
365 case CLOCK_EVT_MODE_RESUME
:
367 hpet_enable_legacy_int();
369 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
370 hpet_setup_msi_irq(hdev
->irq
);
371 disable_irq(hdev
->irq
);
372 irq_set_affinity(hdev
->irq
, cpumask_of(hdev
->cpu
));
373 enable_irq(hdev
->irq
);
380 static int hpet_next_event(unsigned long delta
,
381 struct clock_event_device
*evt
, int timer
)
385 cnt
= hpet_readl(HPET_COUNTER
);
387 hpet_writel(cnt
, HPET_Tn_CMP(timer
));
390 * We need to read back the CMP register on certain HPET
391 * implementations (ATI chipsets) which seem to delay the
392 * transfer of the compare register into the internal compare
393 * logic. With small deltas this might actually be too late as
394 * the counter could already be higher than the compare value
395 * at that point and we would wait for the next hpet interrupt
396 * forever. We found out that reading the CMP register back
397 * forces the transfer so we can rely on the comparison with
398 * the counter register below. If the read back from the
399 * compare register does not match the value we programmed
400 * then we might have a real hardware problem. We can not do
401 * much about it here, but at least alert the user/admin with
402 * a prominent warning.
404 * An erratum on some chipsets (ICH9,..), results in
405 * comparator read immediately following a write returning old
406 * value. Workaround for this is to read this value second
407 * time, when first read returns old value.
409 * In fact the write to the comparator register is delayed up
410 * to two HPET cycles so the workaround we tried to restrict
411 * the readback to those known to be borked ATI chipsets
412 * failed miserably. So we give up on optimizations forever
413 * and penalize all HPET incarnations unconditionally.
415 if (unlikely((u32
)hpet_readl(HPET_Tn_CMP(timer
)) != cnt
)) {
416 if (hpet_readl(HPET_Tn_CMP(timer
)) != cnt
)
417 printk_once(KERN_WARNING
418 "hpet: compare register read back failed.\n");
421 return (s32
)(hpet_readl(HPET_COUNTER
) - cnt
) >= 0 ? -ETIME
: 0;
424 static void hpet_legacy_set_mode(enum clock_event_mode mode
,
425 struct clock_event_device
*evt
)
427 hpet_set_mode(mode
, evt
, 0);
430 static int hpet_legacy_next_event(unsigned long delta
,
431 struct clock_event_device
*evt
)
433 return hpet_next_event(delta
, evt
, 0);
439 #ifdef CONFIG_PCI_MSI
441 static DEFINE_PER_CPU(struct hpet_dev
*, cpu_hpet_dev
);
442 static struct hpet_dev
*hpet_devs
;
444 void hpet_msi_unmask(unsigned int irq
)
446 struct hpet_dev
*hdev
= get_irq_data(irq
);
450 cfg
= hpet_readl(HPET_Tn_CFG(hdev
->num
));
452 hpet_writel(cfg
, HPET_Tn_CFG(hdev
->num
));
455 void hpet_msi_mask(unsigned int irq
)
458 struct hpet_dev
*hdev
= get_irq_data(irq
);
461 cfg
= hpet_readl(HPET_Tn_CFG(hdev
->num
));
463 hpet_writel(cfg
, HPET_Tn_CFG(hdev
->num
));
466 void hpet_msi_write(unsigned int irq
, struct msi_msg
*msg
)
468 struct hpet_dev
*hdev
= get_irq_data(irq
);
470 hpet_writel(msg
->data
, HPET_Tn_ROUTE(hdev
->num
));
471 hpet_writel(msg
->address_lo
, HPET_Tn_ROUTE(hdev
->num
) + 4);
474 void hpet_msi_read(unsigned int irq
, struct msi_msg
*msg
)
476 struct hpet_dev
*hdev
= get_irq_data(irq
);
478 msg
->data
= hpet_readl(HPET_Tn_ROUTE(hdev
->num
));
479 msg
->address_lo
= hpet_readl(HPET_Tn_ROUTE(hdev
->num
) + 4);
483 static void hpet_msi_set_mode(enum clock_event_mode mode
,
484 struct clock_event_device
*evt
)
486 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
487 hpet_set_mode(mode
, evt
, hdev
->num
);
490 static int hpet_msi_next_event(unsigned long delta
,
491 struct clock_event_device
*evt
)
493 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
494 return hpet_next_event(delta
, evt
, hdev
->num
);
497 static int hpet_setup_msi_irq(unsigned int irq
)
499 if (arch_setup_hpet_msi(irq
, hpet_blockid
)) {
506 static int hpet_assign_irq(struct hpet_dev
*dev
)
510 irq
= create_irq_nr(0, -1);
514 set_irq_data(irq
, dev
);
516 if (hpet_setup_msi_irq(irq
))
523 static irqreturn_t
hpet_interrupt_handler(int irq
, void *data
)
525 struct hpet_dev
*dev
= (struct hpet_dev
*)data
;
526 struct clock_event_device
*hevt
= &dev
->evt
;
528 if (!hevt
->event_handler
) {
529 printk(KERN_INFO
"Spurious HPET timer interrupt on HPET timer %d\n",
534 hevt
->event_handler(hevt
);
538 static int hpet_setup_irq(struct hpet_dev
*dev
)
541 if (request_irq(dev
->irq
, hpet_interrupt_handler
,
542 IRQF_TIMER
| IRQF_DISABLED
| IRQF_NOBALANCING
,
546 disable_irq(dev
->irq
);
547 irq_set_affinity(dev
->irq
, cpumask_of(dev
->cpu
));
548 enable_irq(dev
->irq
);
550 printk(KERN_DEBUG
"hpet: %s irq %d for MSI\n",
551 dev
->name
, dev
->irq
);
556 /* This should be called in specific @cpu */
557 static void init_one_hpet_msi_clockevent(struct hpet_dev
*hdev
, int cpu
)
559 struct clock_event_device
*evt
= &hdev
->evt
;
562 WARN_ON(cpu
!= smp_processor_id());
563 if (!(hdev
->flags
& HPET_DEV_VALID
))
566 if (hpet_setup_msi_irq(hdev
->irq
))
570 per_cpu(cpu_hpet_dev
, cpu
) = hdev
;
571 evt
->name
= hdev
->name
;
572 hpet_setup_irq(hdev
);
573 evt
->irq
= hdev
->irq
;
576 evt
->features
= CLOCK_EVT_FEAT_ONESHOT
;
577 if (hdev
->flags
& HPET_DEV_PERI_CAP
)
578 evt
->features
|= CLOCK_EVT_FEAT_PERIODIC
;
580 evt
->set_mode
= hpet_msi_set_mode
;
581 evt
->set_next_event
= hpet_msi_next_event
;
585 * The period is a femto seconds value. We need to calculate the
586 * scaled math multiplication factor for nanosecond to hpet tick
589 hpet_freq
= 1000000000000000ULL;
590 do_div(hpet_freq
, hpet_period
);
591 evt
->mult
= div_sc((unsigned long) hpet_freq
,
592 NSEC_PER_SEC
, evt
->shift
);
593 /* Calculate the max delta */
594 evt
->max_delta_ns
= clockevent_delta2ns(0x7FFFFFFF, evt
);
595 /* 5 usec minimum reprogramming delta. */
596 evt
->min_delta_ns
= 5000;
598 evt
->cpumask
= cpumask_of(hdev
->cpu
);
599 clockevents_register_device(evt
);
603 /* Reserve at least one timer for userspace (/dev/hpet) */
604 #define RESERVE_TIMERS 1
606 #define RESERVE_TIMERS 0
609 static void hpet_msi_capability_lookup(unsigned int start_timer
)
612 unsigned int num_timers
;
613 unsigned int num_timers_used
= 0;
616 if (hpet_msi_disable
)
619 if (boot_cpu_has(X86_FEATURE_ARAT
))
621 id
= hpet_readl(HPET_ID
);
623 num_timers
= ((id
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
);
624 num_timers
++; /* Value read out starts from 0 */
627 hpet_devs
= kzalloc(sizeof(struct hpet_dev
) * num_timers
, GFP_KERNEL
);
631 hpet_num_timers
= num_timers
;
633 for (i
= start_timer
; i
< num_timers
- RESERVE_TIMERS
; i
++) {
634 struct hpet_dev
*hdev
= &hpet_devs
[num_timers_used
];
635 unsigned int cfg
= hpet_readl(HPET_Tn_CFG(i
));
637 /* Only consider HPET timer with MSI support */
638 if (!(cfg
& HPET_TN_FSB_CAP
))
642 if (cfg
& HPET_TN_PERIODIC_CAP
)
643 hdev
->flags
|= HPET_DEV_PERI_CAP
;
646 sprintf(hdev
->name
, "hpet%d", i
);
647 if (hpet_assign_irq(hdev
))
650 hdev
->flags
|= HPET_DEV_FSB_CAP
;
651 hdev
->flags
|= HPET_DEV_VALID
;
653 if (num_timers_used
== num_possible_cpus())
657 printk(KERN_INFO
"HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
658 num_timers
, num_timers_used
);
662 static void hpet_reserve_msi_timers(struct hpet_data
*hd
)
669 for (i
= 0; i
< hpet_num_timers
; i
++) {
670 struct hpet_dev
*hdev
= &hpet_devs
[i
];
672 if (!(hdev
->flags
& HPET_DEV_VALID
))
675 hd
->hd_irq
[hdev
->num
] = hdev
->irq
;
676 hpet_reserve_timer(hd
, hdev
->num
);
681 static struct hpet_dev
*hpet_get_unused_timer(void)
688 for (i
= 0; i
< hpet_num_timers
; i
++) {
689 struct hpet_dev
*hdev
= &hpet_devs
[i
];
691 if (!(hdev
->flags
& HPET_DEV_VALID
))
693 if (test_and_set_bit(HPET_DEV_USED_BIT
,
694 (unsigned long *)&hdev
->flags
))
701 struct hpet_work_struct
{
702 struct delayed_work work
;
703 struct completion complete
;
706 static void hpet_work(struct work_struct
*w
)
708 struct hpet_dev
*hdev
;
709 int cpu
= smp_processor_id();
710 struct hpet_work_struct
*hpet_work
;
712 hpet_work
= container_of(w
, struct hpet_work_struct
, work
.work
);
714 hdev
= hpet_get_unused_timer();
716 init_one_hpet_msi_clockevent(hdev
, cpu
);
718 complete(&hpet_work
->complete
);
721 static int hpet_cpuhp_notify(struct notifier_block
*n
,
722 unsigned long action
, void *hcpu
)
724 unsigned long cpu
= (unsigned long)hcpu
;
725 struct hpet_work_struct work
;
726 struct hpet_dev
*hdev
= per_cpu(cpu_hpet_dev
, cpu
);
728 switch (action
& 0xf) {
730 INIT_DELAYED_WORK_ON_STACK(&work
.work
, hpet_work
);
731 init_completion(&work
.complete
);
732 /* FIXME: add schedule_work_on() */
733 schedule_delayed_work_on(cpu
, &work
.work
, 0);
734 wait_for_completion(&work
.complete
);
735 destroy_timer_on_stack(&work
.work
.timer
);
739 free_irq(hdev
->irq
, hdev
);
740 hdev
->flags
&= ~HPET_DEV_USED
;
741 per_cpu(cpu_hpet_dev
, cpu
) = NULL
;
749 static int hpet_setup_msi_irq(unsigned int irq
)
753 static void hpet_msi_capability_lookup(unsigned int start_timer
)
759 static void hpet_reserve_msi_timers(struct hpet_data
*hd
)
765 static int hpet_cpuhp_notify(struct notifier_block
*n
,
766 unsigned long action
, void *hcpu
)
774 * Clock source related code
776 static cycle_t
read_hpet(struct clocksource
*cs
)
778 return (cycle_t
)hpet_readl(HPET_COUNTER
);
782 static cycle_t __vsyscall_fn
vread_hpet(void)
784 return readl((const void __iomem
*)fix_to_virt(VSYSCALL_HPET
) + 0xf0);
788 static struct clocksource clocksource_hpet
= {
794 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
795 .resume
= hpet_resume_counter
,
801 static int hpet_clocksource_register(void)
806 /* Start the counter */
807 hpet_restart_counter();
809 /* Verify whether hpet counter works */
810 t1
= hpet_readl(HPET_COUNTER
);
814 * We don't know the TSC frequency yet, but waiting for
815 * 200000 TSC cycles is safe:
822 } while ((now
- start
) < 200000UL);
824 if (t1
== hpet_readl(HPET_COUNTER
)) {
826 "HPET counter not counting. HPET disabled\n");
831 * The definition of mult is (include/linux/clocksource.h)
832 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
833 * so we first need to convert hpet_period to ns/cyc units:
834 * mult/2^shift = ns/cyc = hpet_period/10^6
835 * mult = (hpet_period * 2^shift)/10^6
836 * mult = (hpet_period << shift)/FSEC_PER_NSEC
838 clocksource_hpet
.mult
= div_sc(hpet_period
, FSEC_PER_NSEC
, HPET_SHIFT
);
840 clocksource_register(&clocksource_hpet
);
846 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
848 int __init
hpet_enable(void)
853 if (!is_hpet_capable())
859 * Read the period and check for a sane value:
861 hpet_period
= hpet_readl(HPET_PERIOD
);
864 * AMD SB700 based systems with spread spectrum enabled use a
865 * SMM based HPET emulation to provide proper frequency
866 * setting. The SMM code is initialized with the first HPET
867 * register access and takes some time to complete. During
868 * this time the config register reads 0xffffffff. We check
869 * for max. 1000 loops whether the config register reads a non
870 * 0xffffffff value to make sure that HPET is up and running
871 * before we go further. A counting loop is safe, as the HPET
872 * access takes thousands of CPU cycles. On non SB700 based
873 * machines this check is only done once and has no side
876 for (i
= 0; hpet_readl(HPET_CFG
) == 0xFFFFFFFF; i
++) {
879 "HPET config register value = 0xFFFFFFFF. "
885 if (hpet_period
< HPET_MIN_PERIOD
|| hpet_period
> HPET_MAX_PERIOD
)
889 * Read the HPET ID register to retrieve the IRQ routing
890 * information and the number of channels
892 id
= hpet_readl(HPET_ID
);
895 #ifdef CONFIG_HPET_EMULATE_RTC
897 * The legacy routing mode needs at least two channels, tick timer
898 * and the rtc emulation channel.
900 if (!(id
& HPET_ID_NUMBER
))
904 if (hpet_clocksource_register())
907 if (id
& HPET_ID_LEGSUP
) {
908 hpet_legacy_clockevent_register();
914 hpet_clear_mapping();
920 * Needs to be late, as the reserve_timer code calls kalloc !
922 * Not a problem on i386 as hpet_enable is called from late_time_init,
923 * but on x86_64 it is necessary !
925 static __init
int hpet_late_init(void)
929 if (boot_hpet_disable
)
933 if (!force_hpet_address
)
936 hpet_address
= force_hpet_address
;
940 if (!hpet_virt_address
)
943 if (hpet_readl(HPET_ID
) & HPET_ID_LEGSUP
)
944 hpet_msi_capability_lookup(2);
946 hpet_msi_capability_lookup(0);
948 hpet_reserve_platform_timers(hpet_readl(HPET_ID
));
951 if (hpet_msi_disable
)
954 if (boot_cpu_has(X86_FEATURE_ARAT
))
957 for_each_online_cpu(cpu
) {
958 hpet_cpuhp_notify(NULL
, CPU_ONLINE
, (void *)(long)cpu
);
961 /* This notifier should be called after workqueue is ready */
962 hotcpu_notifier(hpet_cpuhp_notify
, -20);
966 fs_initcall(hpet_late_init
);
968 void hpet_disable(void)
970 if (is_hpet_capable() && hpet_virt_address
) {
971 unsigned int cfg
= hpet_readl(HPET_CFG
);
973 if (hpet_legacy_int_enabled
) {
974 cfg
&= ~HPET_CFG_LEGACY
;
975 hpet_legacy_int_enabled
= 0;
977 cfg
&= ~HPET_CFG_ENABLE
;
978 hpet_writel(cfg
, HPET_CFG
);
982 #ifdef CONFIG_HPET_EMULATE_RTC
984 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
985 * is enabled, we support RTC interrupt functionality in software.
986 * RTC has 3 kinds of interrupts:
987 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
989 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
990 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
991 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
992 * (1) and (2) above are implemented using polling at a frequency of
993 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
994 * overhead. (DEFAULT_RTC_INT_FREQ)
995 * For (3), we use interrupts at 64Hz or user specified periodic
996 * frequency, whichever is higher.
998 #include <linux/mc146818rtc.h>
999 #include <linux/rtc.h>
1000 #include <asm/rtc.h>
1002 #define DEFAULT_RTC_INT_FREQ 64
1003 #define DEFAULT_RTC_SHIFT 6
1004 #define RTC_NUM_INTS 1
1006 static unsigned long hpet_rtc_flags
;
1007 static int hpet_prev_update_sec
;
1008 static struct rtc_time hpet_alarm_time
;
1009 static unsigned long hpet_pie_count
;
1010 static u32 hpet_t1_cmp
;
1011 static u32 hpet_default_delta
;
1012 static u32 hpet_pie_delta
;
1013 static unsigned long hpet_pie_limit
;
1015 static rtc_irq_handler irq_handler
;
1018 * Check that the hpet counter c1 is ahead of the c2
1020 static inline int hpet_cnt_ahead(u32 c1
, u32 c2
)
1022 return (s32
)(c2
- c1
) < 0;
1026 * Registers a IRQ handler.
1028 int hpet_register_irq_handler(rtc_irq_handler handler
)
1030 if (!is_hpet_enabled())
1035 irq_handler
= handler
;
1039 EXPORT_SYMBOL_GPL(hpet_register_irq_handler
);
1042 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1045 void hpet_unregister_irq_handler(rtc_irq_handler handler
)
1047 if (!is_hpet_enabled())
1053 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler
);
1056 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1057 * is not supported by all HPET implementations for timer 1.
1059 * hpet_rtc_timer_init() is called when the rtc is initialized.
1061 int hpet_rtc_timer_init(void)
1063 unsigned int cfg
, cnt
, delta
;
1064 unsigned long flags
;
1066 if (!is_hpet_enabled())
1069 if (!hpet_default_delta
) {
1072 clc
= (uint64_t) hpet_clockevent
.mult
* NSEC_PER_SEC
;
1073 clc
>>= hpet_clockevent
.shift
+ DEFAULT_RTC_SHIFT
;
1074 hpet_default_delta
= clc
;
1077 if (!(hpet_rtc_flags
& RTC_PIE
) || hpet_pie_limit
)
1078 delta
= hpet_default_delta
;
1080 delta
= hpet_pie_delta
;
1082 local_irq_save(flags
);
1084 cnt
= delta
+ hpet_readl(HPET_COUNTER
);
1085 hpet_writel(cnt
, HPET_T1_CMP
);
1088 cfg
= hpet_readl(HPET_T1_CFG
);
1089 cfg
&= ~HPET_TN_PERIODIC
;
1090 cfg
|= HPET_TN_ENABLE
| HPET_TN_32BIT
;
1091 hpet_writel(cfg
, HPET_T1_CFG
);
1093 local_irq_restore(flags
);
1097 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init
);
1100 * The functions below are called from rtc driver.
1101 * Return 0 if HPET is not being used.
1102 * Otherwise do the necessary changes and return 1.
1104 int hpet_mask_rtc_irq_bit(unsigned long bit_mask
)
1106 if (!is_hpet_enabled())
1109 hpet_rtc_flags
&= ~bit_mask
;
1112 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit
);
1114 int hpet_set_rtc_irq_bit(unsigned long bit_mask
)
1116 unsigned long oldbits
= hpet_rtc_flags
;
1118 if (!is_hpet_enabled())
1121 hpet_rtc_flags
|= bit_mask
;
1123 if ((bit_mask
& RTC_UIE
) && !(oldbits
& RTC_UIE
))
1124 hpet_prev_update_sec
= -1;
1127 hpet_rtc_timer_init();
1131 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit
);
1133 int hpet_set_alarm_time(unsigned char hrs
, unsigned char min
,
1136 if (!is_hpet_enabled())
1139 hpet_alarm_time
.tm_hour
= hrs
;
1140 hpet_alarm_time
.tm_min
= min
;
1141 hpet_alarm_time
.tm_sec
= sec
;
1145 EXPORT_SYMBOL_GPL(hpet_set_alarm_time
);
1147 int hpet_set_periodic_freq(unsigned long freq
)
1151 if (!is_hpet_enabled())
1154 if (freq
<= DEFAULT_RTC_INT_FREQ
)
1155 hpet_pie_limit
= DEFAULT_RTC_INT_FREQ
/ freq
;
1157 clc
= (uint64_t) hpet_clockevent
.mult
* NSEC_PER_SEC
;
1159 clc
>>= hpet_clockevent
.shift
;
1160 hpet_pie_delta
= clc
;
1165 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq
);
1167 int hpet_rtc_dropped_irq(void)
1169 return is_hpet_enabled();
1171 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq
);
1173 static void hpet_rtc_timer_reinit(void)
1175 unsigned int cfg
, delta
;
1178 if (unlikely(!hpet_rtc_flags
)) {
1179 cfg
= hpet_readl(HPET_T1_CFG
);
1180 cfg
&= ~HPET_TN_ENABLE
;
1181 hpet_writel(cfg
, HPET_T1_CFG
);
1185 if (!(hpet_rtc_flags
& RTC_PIE
) || hpet_pie_limit
)
1186 delta
= hpet_default_delta
;
1188 delta
= hpet_pie_delta
;
1191 * Increment the comparator value until we are ahead of the
1195 hpet_t1_cmp
+= delta
;
1196 hpet_writel(hpet_t1_cmp
, HPET_T1_CMP
);
1198 } while (!hpet_cnt_ahead(hpet_t1_cmp
, hpet_readl(HPET_COUNTER
)));
1201 if (hpet_rtc_flags
& RTC_PIE
)
1202 hpet_pie_count
+= lost_ints
;
1203 if (printk_ratelimit())
1204 printk(KERN_WARNING
"hpet1: lost %d rtc interrupts\n",
1209 irqreturn_t
hpet_rtc_interrupt(int irq
, void *dev_id
)
1211 struct rtc_time curr_time
;
1212 unsigned long rtc_int_flag
= 0;
1214 hpet_rtc_timer_reinit();
1215 memset(&curr_time
, 0, sizeof(struct rtc_time
));
1217 if (hpet_rtc_flags
& (RTC_UIE
| RTC_AIE
))
1218 get_rtc_time(&curr_time
);
1220 if (hpet_rtc_flags
& RTC_UIE
&&
1221 curr_time
.tm_sec
!= hpet_prev_update_sec
) {
1222 if (hpet_prev_update_sec
>= 0)
1223 rtc_int_flag
= RTC_UF
;
1224 hpet_prev_update_sec
= curr_time
.tm_sec
;
1227 if (hpet_rtc_flags
& RTC_PIE
&&
1228 ++hpet_pie_count
>= hpet_pie_limit
) {
1229 rtc_int_flag
|= RTC_PF
;
1233 if (hpet_rtc_flags
& RTC_AIE
&&
1234 (curr_time
.tm_sec
== hpet_alarm_time
.tm_sec
) &&
1235 (curr_time
.tm_min
== hpet_alarm_time
.tm_min
) &&
1236 (curr_time
.tm_hour
== hpet_alarm_time
.tm_hour
))
1237 rtc_int_flag
|= RTC_AF
;
1240 rtc_int_flag
|= (RTC_IRQF
| (RTC_NUM_INTS
<< 8));
1242 irq_handler(rtc_int_flag
, dev_id
);
1246 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt
);