2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_proto.h>
29 #include <asm/amd_iommu_types.h>
30 #include <asm/amd_iommu.h>
31 #include <asm/iommu.h>
33 #include <asm/x86_init.h>
36 * definitions for the ACPI scanning code
38 #define IVRS_HEADER_LENGTH 48
40 #define ACPI_IVHD_TYPE 0x10
41 #define ACPI_IVMD_TYPE_ALL 0x20
42 #define ACPI_IVMD_TYPE 0x21
43 #define ACPI_IVMD_TYPE_RANGE 0x22
45 #define IVHD_DEV_ALL 0x01
46 #define IVHD_DEV_SELECT 0x02
47 #define IVHD_DEV_SELECT_RANGE_START 0x03
48 #define IVHD_DEV_RANGE_END 0x04
49 #define IVHD_DEV_ALIAS 0x42
50 #define IVHD_DEV_ALIAS_RANGE 0x43
51 #define IVHD_DEV_EXT_SELECT 0x46
52 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
54 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
55 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
56 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
57 #define IVHD_FLAG_ISOC_EN_MASK 0x08
59 #define IVMD_FLAG_EXCL_RANGE 0x08
60 #define IVMD_FLAG_UNITY_MAP 0x01
62 #define ACPI_DEVFLAG_INITPASS 0x01
63 #define ACPI_DEVFLAG_EXTINT 0x02
64 #define ACPI_DEVFLAG_NMI 0x04
65 #define ACPI_DEVFLAG_SYSMGT1 0x10
66 #define ACPI_DEVFLAG_SYSMGT2 0x20
67 #define ACPI_DEVFLAG_LINT0 0x40
68 #define ACPI_DEVFLAG_LINT1 0x80
69 #define ACPI_DEVFLAG_ATSDIS 0x10000000
72 * ACPI table definitions
74 * These data structures are laid over the table to parse the important values
79 * structure describing one IOMMU in the ACPI table. Typically followed by one
80 * or more ivhd_entrys.
92 } __attribute__((packed
));
95 * A device entry describing which devices a specific IOMMU translates and
96 * which requestor ids they use.
103 } __attribute__((packed
));
106 * An AMD IOMMU memory definition structure. It defines things like exclusion
107 * ranges for devices and regions that should be unity mapped.
118 } __attribute__((packed
));
122 static int __initdata amd_iommu_detected
;
123 static bool __initdata amd_iommu_disabled
;
125 u16 amd_iommu_last_bdf
; /* largest PCI device id we have
127 LIST_HEAD(amd_iommu_unity_map
); /* a list of required unity mappings
129 bool amd_iommu_unmap_flush
; /* if true, flush on every unmap */
131 LIST_HEAD(amd_iommu_list
); /* list of all AMD IOMMUs in the
134 /* Array to assign indices to IOMMUs*/
135 struct amd_iommu
*amd_iommus
[MAX_IOMMUS
];
136 int amd_iommus_present
;
138 /* IOMMUs have a non-present cache? */
139 bool amd_iommu_np_cache __read_mostly
;
142 * The ACPI table parsing functions set this variable on an error
144 static int __initdata amd_iommu_init_err
;
147 * List of protection domains - used during resume
149 LIST_HEAD(amd_iommu_pd_list
);
150 spinlock_t amd_iommu_pd_lock
;
153 * Pointer to the device table which is shared by all AMD IOMMUs
154 * it is indexed by the PCI device id or the HT unit id and contains
155 * information about the domain the device belongs to as well as the
156 * page table root pointer.
158 struct dev_table_entry
*amd_iommu_dev_table
;
161 * The alias table is a driver specific data structure which contains the
162 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
163 * More than one device can share the same requestor id.
165 u16
*amd_iommu_alias_table
;
168 * The rlookup table is used to find the IOMMU which is responsible
169 * for a specific device. It is also indexed by the PCI device id.
171 struct amd_iommu
**amd_iommu_rlookup_table
;
174 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
175 * to know which ones are already in use.
177 unsigned long *amd_iommu_pd_alloc_bitmap
;
179 static u32 dev_table_size
; /* size of the device table */
180 static u32 alias_table_size
; /* size of the alias table */
181 static u32 rlookup_table_size
; /* size if the rlookup table */
183 static inline void update_last_devid(u16 devid
)
185 if (devid
> amd_iommu_last_bdf
)
186 amd_iommu_last_bdf
= devid
;
189 static inline unsigned long tbl_size(int entry_size
)
191 unsigned shift
= PAGE_SHIFT
+
192 get_order(((int)amd_iommu_last_bdf
+ 1) * entry_size
);
197 /****************************************************************************
199 * AMD IOMMU MMIO register space handling functions
201 * These functions are used to program the IOMMU device registers in
202 * MMIO space required for that driver.
204 ****************************************************************************/
207 * This function set the exclusion range in the IOMMU. DMA accesses to the
208 * exclusion range are passed through untranslated
210 static void iommu_set_exclusion_range(struct amd_iommu
*iommu
)
212 u64 start
= iommu
->exclusion_start
& PAGE_MASK
;
213 u64 limit
= (start
+ iommu
->exclusion_length
) & PAGE_MASK
;
216 if (!iommu
->exclusion_start
)
219 entry
= start
| MMIO_EXCL_ENABLE_MASK
;
220 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_BASE_OFFSET
,
221 &entry
, sizeof(entry
));
224 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_LIMIT_OFFSET
,
225 &entry
, sizeof(entry
));
228 /* Programs the physical address of the device table into the IOMMU hardware */
229 static void __init
iommu_set_device_table(struct amd_iommu
*iommu
)
233 BUG_ON(iommu
->mmio_base
== NULL
);
235 entry
= virt_to_phys(amd_iommu_dev_table
);
236 entry
|= (dev_table_size
>> 12) - 1;
237 memcpy_toio(iommu
->mmio_base
+ MMIO_DEV_TABLE_OFFSET
,
238 &entry
, sizeof(entry
));
241 /* Generic functions to enable/disable certain features of the IOMMU. */
242 static void iommu_feature_enable(struct amd_iommu
*iommu
, u8 bit
)
246 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
248 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
251 static void iommu_feature_disable(struct amd_iommu
*iommu
, u8 bit
)
255 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
257 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
260 /* Function to enable the hardware */
261 static void iommu_enable(struct amd_iommu
*iommu
)
263 printk(KERN_INFO
"AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n",
264 dev_name(&iommu
->dev
->dev
), iommu
->cap_ptr
);
266 iommu_feature_enable(iommu
, CONTROL_IOMMU_EN
);
269 static void iommu_disable(struct amd_iommu
*iommu
)
271 /* Disable command buffer */
272 iommu_feature_disable(iommu
, CONTROL_CMDBUF_EN
);
274 /* Disable event logging and event interrupts */
275 iommu_feature_disable(iommu
, CONTROL_EVT_INT_EN
);
276 iommu_feature_disable(iommu
, CONTROL_EVT_LOG_EN
);
278 /* Disable IOMMU hardware itself */
279 iommu_feature_disable(iommu
, CONTROL_IOMMU_EN
);
283 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
284 * the system has one.
286 static u8
* __init
iommu_map_mmio_space(u64 address
)
290 if (!request_mem_region(address
, MMIO_REGION_LENGTH
, "amd_iommu")) {
291 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
293 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
297 ret
= ioremap_nocache(address
, MMIO_REGION_LENGTH
);
301 release_mem_region(address
, MMIO_REGION_LENGTH
);
306 static void __init
iommu_unmap_mmio_space(struct amd_iommu
*iommu
)
308 if (iommu
->mmio_base
)
309 iounmap(iommu
->mmio_base
);
310 release_mem_region(iommu
->mmio_phys
, MMIO_REGION_LENGTH
);
313 /****************************************************************************
315 * The functions below belong to the first pass of AMD IOMMU ACPI table
316 * parsing. In this pass we try to find out the highest device id this
317 * code has to handle. Upon this information the size of the shared data
318 * structures is determined later.
320 ****************************************************************************/
323 * This function calculates the length of a given IVHD entry
325 static inline int ivhd_entry_length(u8
*ivhd
)
327 return 0x04 << (*ivhd
>> 6);
331 * This function reads the last device id the IOMMU has to handle from the PCI
332 * capability header for this IOMMU
334 static int __init
find_last_devid_on_pci(int bus
, int dev
, int fn
, int cap_ptr
)
338 cap
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_RANGE_OFFSET
);
339 update_last_devid(calc_devid(MMIO_GET_BUS(cap
), MMIO_GET_LD(cap
)));
345 * After reading the highest device id from the IOMMU PCI capability header
346 * this function looks if there is a higher device id defined in the ACPI table
348 static int __init
find_last_devid_from_ivhd(struct ivhd_header
*h
)
350 u8
*p
= (void *)h
, *end
= (void *)h
;
351 struct ivhd_entry
*dev
;
356 find_last_devid_on_pci(PCI_BUS(h
->devid
),
362 dev
= (struct ivhd_entry
*)p
;
364 case IVHD_DEV_SELECT
:
365 case IVHD_DEV_RANGE_END
:
367 case IVHD_DEV_EXT_SELECT
:
368 /* all the above subfield types refer to device ids */
369 update_last_devid(dev
->devid
);
374 p
+= ivhd_entry_length(p
);
383 * Iterate over all IVHD entries in the ACPI table and find the highest device
384 * id which we need to handle. This is the first of three functions which parse
385 * the ACPI table. So we check the checksum here.
387 static int __init
find_last_devid_acpi(struct acpi_table_header
*table
)
390 u8 checksum
= 0, *p
= (u8
*)table
, *end
= (u8
*)table
;
391 struct ivhd_header
*h
;
394 * Validate checksum here so we don't need to do it when
395 * we actually parse the table
397 for (i
= 0; i
< table
->length
; ++i
)
400 /* ACPI table corrupt */
401 amd_iommu_init_err
= -ENODEV
;
405 p
+= IVRS_HEADER_LENGTH
;
407 end
+= table
->length
;
409 h
= (struct ivhd_header
*)p
;
412 find_last_devid_from_ivhd(h
);
424 /****************************************************************************
426 * The following functions belong the the code path which parses the ACPI table
427 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
428 * data structures, initialize the device/alias/rlookup table and also
429 * basically initialize the hardware.
431 ****************************************************************************/
434 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
435 * write commands to that buffer later and the IOMMU will execute them
438 static u8
* __init
alloc_command_buffer(struct amd_iommu
*iommu
)
440 u8
*cmd_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
441 get_order(CMD_BUFFER_SIZE
));
446 iommu
->cmd_buf_size
= CMD_BUFFER_SIZE
| CMD_BUFFER_UNINITIALIZED
;
452 * This function resets the command buffer if the IOMMU stopped fetching
455 void amd_iommu_reset_cmd_buffer(struct amd_iommu
*iommu
)
457 iommu_feature_disable(iommu
, CONTROL_CMDBUF_EN
);
459 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
460 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
462 iommu_feature_enable(iommu
, CONTROL_CMDBUF_EN
);
466 * This function writes the command buffer address to the hardware and
469 static void iommu_enable_command_buffer(struct amd_iommu
*iommu
)
473 BUG_ON(iommu
->cmd_buf
== NULL
);
475 entry
= (u64
)virt_to_phys(iommu
->cmd_buf
);
476 entry
|= MMIO_CMD_SIZE_512
;
478 memcpy_toio(iommu
->mmio_base
+ MMIO_CMD_BUF_OFFSET
,
479 &entry
, sizeof(entry
));
481 amd_iommu_reset_cmd_buffer(iommu
);
482 iommu
->cmd_buf_size
&= ~(CMD_BUFFER_UNINITIALIZED
);
485 static void __init
free_command_buffer(struct amd_iommu
*iommu
)
487 free_pages((unsigned long)iommu
->cmd_buf
,
488 get_order(iommu
->cmd_buf_size
& ~(CMD_BUFFER_UNINITIALIZED
)));
491 /* allocates the memory where the IOMMU will log its events to */
492 static u8
* __init
alloc_event_buffer(struct amd_iommu
*iommu
)
494 iommu
->evt_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
495 get_order(EVT_BUFFER_SIZE
));
497 if (iommu
->evt_buf
== NULL
)
500 iommu
->evt_buf_size
= EVT_BUFFER_SIZE
;
502 return iommu
->evt_buf
;
505 static void iommu_enable_event_buffer(struct amd_iommu
*iommu
)
509 BUG_ON(iommu
->evt_buf
== NULL
);
511 entry
= (u64
)virt_to_phys(iommu
->evt_buf
) | EVT_LEN_MASK
;
513 memcpy_toio(iommu
->mmio_base
+ MMIO_EVT_BUF_OFFSET
,
514 &entry
, sizeof(entry
));
516 /* set head and tail to zero manually */
517 writel(0x00, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
518 writel(0x00, iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
520 iommu_feature_enable(iommu
, CONTROL_EVT_LOG_EN
);
523 static void __init
free_event_buffer(struct amd_iommu
*iommu
)
525 free_pages((unsigned long)iommu
->evt_buf
, get_order(EVT_BUFFER_SIZE
));
528 /* sets a specific bit in the device table entry. */
529 static void set_dev_entry_bit(u16 devid
, u8 bit
)
531 int i
= (bit
>> 5) & 0x07;
532 int _bit
= bit
& 0x1f;
534 amd_iommu_dev_table
[devid
].data
[i
] |= (1 << _bit
);
537 static int get_dev_entry_bit(u16 devid
, u8 bit
)
539 int i
= (bit
>> 5) & 0x07;
540 int _bit
= bit
& 0x1f;
542 return (amd_iommu_dev_table
[devid
].data
[i
] & (1 << _bit
)) >> _bit
;
546 void amd_iommu_apply_erratum_63(u16 devid
)
550 sysmgt
= get_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
) |
551 (get_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
) << 1);
554 set_dev_entry_bit(devid
, DEV_ENTRY_IW
);
557 /* Writes the specific IOMMU for a device into the rlookup table */
558 static void __init
set_iommu_for_device(struct amd_iommu
*iommu
, u16 devid
)
560 amd_iommu_rlookup_table
[devid
] = iommu
;
564 * This function takes the device specific flags read from the ACPI
565 * table and sets up the device table entry with that information
567 static void __init
set_dev_entry_from_acpi(struct amd_iommu
*iommu
,
568 u16 devid
, u32 flags
, u32 ext_flags
)
570 if (flags
& ACPI_DEVFLAG_INITPASS
)
571 set_dev_entry_bit(devid
, DEV_ENTRY_INIT_PASS
);
572 if (flags
& ACPI_DEVFLAG_EXTINT
)
573 set_dev_entry_bit(devid
, DEV_ENTRY_EINT_PASS
);
574 if (flags
& ACPI_DEVFLAG_NMI
)
575 set_dev_entry_bit(devid
, DEV_ENTRY_NMI_PASS
);
576 if (flags
& ACPI_DEVFLAG_SYSMGT1
)
577 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
);
578 if (flags
& ACPI_DEVFLAG_SYSMGT2
)
579 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
);
580 if (flags
& ACPI_DEVFLAG_LINT0
)
581 set_dev_entry_bit(devid
, DEV_ENTRY_LINT0_PASS
);
582 if (flags
& ACPI_DEVFLAG_LINT1
)
583 set_dev_entry_bit(devid
, DEV_ENTRY_LINT1_PASS
);
585 amd_iommu_apply_erratum_63(devid
);
587 set_iommu_for_device(iommu
, devid
);
591 * Reads the device exclusion range from ACPI and initialize IOMMU with
594 static void __init
set_device_exclusion_range(u16 devid
, struct ivmd_header
*m
)
596 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
598 if (!(m
->flags
& IVMD_FLAG_EXCL_RANGE
))
603 * We only can configure exclusion ranges per IOMMU, not
604 * per device. But we can enable the exclusion range per
605 * device. This is done here
607 set_dev_entry_bit(m
->devid
, DEV_ENTRY_EX
);
608 iommu
->exclusion_start
= m
->range_start
;
609 iommu
->exclusion_length
= m
->range_length
;
614 * This function reads some important data from the IOMMU PCI space and
615 * initializes the driver data structure with it. It reads the hardware
616 * capabilities and the first/last device entries
618 static void __init
init_iommu_from_pci(struct amd_iommu
*iommu
)
620 int cap_ptr
= iommu
->cap_ptr
;
623 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_CAP_HDR_OFFSET
,
625 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_RANGE_OFFSET
,
627 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_MISC_OFFSET
,
630 iommu
->first_device
= calc_devid(MMIO_GET_BUS(range
),
632 iommu
->last_device
= calc_devid(MMIO_GET_BUS(range
),
634 iommu
->evt_msi_num
= MMIO_MSI_NUM(misc
);
636 if (is_rd890_iommu(iommu
->dev
)) {
637 pci_read_config_dword(iommu
->dev
, 0xf0, &iommu
->cache_cfg
[0]);
638 pci_read_config_dword(iommu
->dev
, 0xf4, &iommu
->cache_cfg
[1]);
639 pci_read_config_dword(iommu
->dev
, 0xf8, &iommu
->cache_cfg
[2]);
640 pci_read_config_dword(iommu
->dev
, 0xfc, &iommu
->cache_cfg
[3]);
645 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
646 * initializes the hardware and our data structures with it.
648 static void __init
init_iommu_from_acpi(struct amd_iommu
*iommu
,
649 struct ivhd_header
*h
)
652 u8
*end
= p
, flags
= 0;
653 u16 devid
= 0, devid_start
= 0, devid_to
= 0;
654 u32 dev_i
, ext_flags
= 0;
656 struct ivhd_entry
*e
;
659 * First save the recommended feature enable bits from ACPI
661 iommu
->acpi_flags
= h
->flags
;
664 * Done. Now parse the device entries
666 p
+= sizeof(struct ivhd_header
);
671 e
= (struct ivhd_entry
*)p
;
675 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
676 " last device %02x:%02x.%x flags: %02x\n",
677 PCI_BUS(iommu
->first_device
),
678 PCI_SLOT(iommu
->first_device
),
679 PCI_FUNC(iommu
->first_device
),
680 PCI_BUS(iommu
->last_device
),
681 PCI_SLOT(iommu
->last_device
),
682 PCI_FUNC(iommu
->last_device
),
685 for (dev_i
= iommu
->first_device
;
686 dev_i
<= iommu
->last_device
; ++dev_i
)
687 set_dev_entry_from_acpi(iommu
, dev_i
,
690 case IVHD_DEV_SELECT
:
692 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
700 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
702 case IVHD_DEV_SELECT_RANGE_START
:
704 DUMP_printk(" DEV_SELECT_RANGE_START\t "
705 "devid: %02x:%02x.%x flags: %02x\n",
711 devid_start
= e
->devid
;
718 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
719 "flags: %02x devid_to: %02x:%02x.%x\n",
724 PCI_BUS(e
->ext
>> 8),
725 PCI_SLOT(e
->ext
>> 8),
726 PCI_FUNC(e
->ext
>> 8));
729 devid_to
= e
->ext
>> 8;
730 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
731 set_dev_entry_from_acpi(iommu
, devid_to
, e
->flags
, 0);
732 amd_iommu_alias_table
[devid
] = devid_to
;
734 case IVHD_DEV_ALIAS_RANGE
:
736 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
737 "devid: %02x:%02x.%x flags: %02x "
738 "devid_to: %02x:%02x.%x\n",
743 PCI_BUS(e
->ext
>> 8),
744 PCI_SLOT(e
->ext
>> 8),
745 PCI_FUNC(e
->ext
>> 8));
747 devid_start
= e
->devid
;
749 devid_to
= e
->ext
>> 8;
753 case IVHD_DEV_EXT_SELECT
:
755 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
756 "flags: %02x ext: %08x\n",
763 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
,
766 case IVHD_DEV_EXT_SELECT_RANGE
:
768 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
769 "%02x:%02x.%x flags: %02x ext: %08x\n",
775 devid_start
= e
->devid
;
780 case IVHD_DEV_RANGE_END
:
782 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
788 for (dev_i
= devid_start
; dev_i
<= devid
; ++dev_i
) {
790 amd_iommu_alias_table
[dev_i
] = devid_to
;
791 set_dev_entry_from_acpi(iommu
,
792 devid_to
, flags
, ext_flags
);
794 set_dev_entry_from_acpi(iommu
, dev_i
,
802 p
+= ivhd_entry_length(p
);
806 /* Initializes the device->iommu mapping for the driver */
807 static int __init
init_iommu_devices(struct amd_iommu
*iommu
)
811 for (i
= iommu
->first_device
; i
<= iommu
->last_device
; ++i
)
812 set_iommu_for_device(iommu
, i
);
817 static void __init
free_iommu_one(struct amd_iommu
*iommu
)
819 free_command_buffer(iommu
);
820 free_event_buffer(iommu
);
821 iommu_unmap_mmio_space(iommu
);
824 static void __init
free_iommu_all(void)
826 struct amd_iommu
*iommu
, *next
;
828 for_each_iommu_safe(iommu
, next
) {
829 list_del(&iommu
->list
);
830 free_iommu_one(iommu
);
836 * This function clues the initialization function for one IOMMU
837 * together and also allocates the command buffer and programs the
838 * hardware. It does NOT enable the IOMMU. This is done afterwards.
840 static int __init
init_iommu_one(struct amd_iommu
*iommu
, struct ivhd_header
*h
)
842 spin_lock_init(&iommu
->lock
);
844 /* Add IOMMU to internal data structures */
845 list_add_tail(&iommu
->list
, &amd_iommu_list
);
846 iommu
->index
= amd_iommus_present
++;
848 if (unlikely(iommu
->index
>= MAX_IOMMUS
)) {
849 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
853 /* Index is fine - add IOMMU to the array */
854 amd_iommus
[iommu
->index
] = iommu
;
857 * Copy data from ACPI table entry to the iommu struct
859 iommu
->dev
= pci_get_bus_and_slot(PCI_BUS(h
->devid
), h
->devid
& 0xff);
863 iommu
->cap_ptr
= h
->cap_ptr
;
864 iommu
->pci_seg
= h
->pci_seg
;
865 iommu
->mmio_phys
= h
->mmio_phys
;
866 iommu
->mmio_base
= iommu_map_mmio_space(h
->mmio_phys
);
867 if (!iommu
->mmio_base
)
870 iommu
->cmd_buf
= alloc_command_buffer(iommu
);
874 iommu
->evt_buf
= alloc_event_buffer(iommu
);
878 iommu
->int_enabled
= false;
880 init_iommu_from_pci(iommu
);
881 init_iommu_from_acpi(iommu
, h
);
882 init_iommu_devices(iommu
);
884 if (iommu
->cap
& (1UL << IOMMU_CAP_NPCACHE
))
885 amd_iommu_np_cache
= true;
887 return pci_enable_device(iommu
->dev
);
891 * Iterates over all IOMMU entries in the ACPI table, allocates the
892 * IOMMU structure and initializes it with init_iommu_one()
894 static int __init
init_iommu_all(struct acpi_table_header
*table
)
896 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
897 struct ivhd_header
*h
;
898 struct amd_iommu
*iommu
;
901 end
+= table
->length
;
902 p
+= IVRS_HEADER_LENGTH
;
905 h
= (struct ivhd_header
*)p
;
909 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
910 "seg: %d flags: %01x info %04x\n",
911 PCI_BUS(h
->devid
), PCI_SLOT(h
->devid
),
912 PCI_FUNC(h
->devid
), h
->cap_ptr
,
913 h
->pci_seg
, h
->flags
, h
->info
);
914 DUMP_printk(" mmio-addr: %016llx\n",
917 iommu
= kzalloc(sizeof(struct amd_iommu
), GFP_KERNEL
);
919 amd_iommu_init_err
= -ENOMEM
;
923 ret
= init_iommu_one(iommu
, h
);
925 amd_iommu_init_err
= ret
;
940 /****************************************************************************
942 * The following functions initialize the MSI interrupts for all IOMMUs
943 * in the system. Its a bit challenging because there could be multiple
944 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
947 ****************************************************************************/
949 static int iommu_setup_msi(struct amd_iommu
*iommu
)
953 if (pci_enable_msi(iommu
->dev
))
956 r
= request_irq(iommu
->dev
->irq
, amd_iommu_int_handler
,
962 pci_disable_msi(iommu
->dev
);
966 iommu
->int_enabled
= true;
967 iommu_feature_enable(iommu
, CONTROL_EVT_INT_EN
);
972 static int iommu_init_msi(struct amd_iommu
*iommu
)
974 if (iommu
->int_enabled
)
977 if (pci_find_capability(iommu
->dev
, PCI_CAP_ID_MSI
))
978 return iommu_setup_msi(iommu
);
983 /****************************************************************************
985 * The next functions belong to the third pass of parsing the ACPI
986 * table. In this last pass the memory mapping requirements are
987 * gathered (like exclusion and unity mapping reanges).
989 ****************************************************************************/
991 static void __init
free_unity_maps(void)
993 struct unity_map_entry
*entry
, *next
;
995 list_for_each_entry_safe(entry
, next
, &amd_iommu_unity_map
, list
) {
996 list_del(&entry
->list
);
1001 /* called when we find an exclusion range definition in ACPI */
1002 static int __init
init_exclusion_range(struct ivmd_header
*m
)
1007 case ACPI_IVMD_TYPE
:
1008 set_device_exclusion_range(m
->devid
, m
);
1010 case ACPI_IVMD_TYPE_ALL
:
1011 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
1012 set_device_exclusion_range(i
, m
);
1014 case ACPI_IVMD_TYPE_RANGE
:
1015 for (i
= m
->devid
; i
<= m
->aux
; ++i
)
1016 set_device_exclusion_range(i
, m
);
1025 /* called for unity map ACPI definition */
1026 static int __init
init_unity_map_range(struct ivmd_header
*m
)
1028 struct unity_map_entry
*e
= 0;
1031 e
= kzalloc(sizeof(*e
), GFP_KERNEL
);
1039 case ACPI_IVMD_TYPE
:
1040 s
= "IVMD_TYPEi\t\t\t";
1041 e
->devid_start
= e
->devid_end
= m
->devid
;
1043 case ACPI_IVMD_TYPE_ALL
:
1044 s
= "IVMD_TYPE_ALL\t\t";
1046 e
->devid_end
= amd_iommu_last_bdf
;
1048 case ACPI_IVMD_TYPE_RANGE
:
1049 s
= "IVMD_TYPE_RANGE\t\t";
1050 e
->devid_start
= m
->devid
;
1051 e
->devid_end
= m
->aux
;
1054 e
->address_start
= PAGE_ALIGN(m
->range_start
);
1055 e
->address_end
= e
->address_start
+ PAGE_ALIGN(m
->range_length
);
1056 e
->prot
= m
->flags
>> 1;
1058 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1059 " range_start: %016llx range_end: %016llx flags: %x\n", s
,
1060 PCI_BUS(e
->devid_start
), PCI_SLOT(e
->devid_start
),
1061 PCI_FUNC(e
->devid_start
), PCI_BUS(e
->devid_end
),
1062 PCI_SLOT(e
->devid_end
), PCI_FUNC(e
->devid_end
),
1063 e
->address_start
, e
->address_end
, m
->flags
);
1065 list_add_tail(&e
->list
, &amd_iommu_unity_map
);
1070 /* iterates over all memory definitions we find in the ACPI table */
1071 static int __init
init_memory_definitions(struct acpi_table_header
*table
)
1073 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
1074 struct ivmd_header
*m
;
1076 end
+= table
->length
;
1077 p
+= IVRS_HEADER_LENGTH
;
1080 m
= (struct ivmd_header
*)p
;
1081 if (m
->flags
& IVMD_FLAG_EXCL_RANGE
)
1082 init_exclusion_range(m
);
1083 else if (m
->flags
& IVMD_FLAG_UNITY_MAP
)
1084 init_unity_map_range(m
);
1093 * Init the device table to not allow DMA access for devices and
1094 * suppress all page faults
1096 static void init_device_table(void)
1100 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
) {
1101 set_dev_entry_bit(devid
, DEV_ENTRY_VALID
);
1102 set_dev_entry_bit(devid
, DEV_ENTRY_TRANSLATION
);
1106 static void iommu_init_flags(struct amd_iommu
*iommu
)
1108 iommu
->acpi_flags
& IVHD_FLAG_HT_TUN_EN_MASK
?
1109 iommu_feature_enable(iommu
, CONTROL_HT_TUN_EN
) :
1110 iommu_feature_disable(iommu
, CONTROL_HT_TUN_EN
);
1112 iommu
->acpi_flags
& IVHD_FLAG_PASSPW_EN_MASK
?
1113 iommu_feature_enable(iommu
, CONTROL_PASSPW_EN
) :
1114 iommu_feature_disable(iommu
, CONTROL_PASSPW_EN
);
1116 iommu
->acpi_flags
& IVHD_FLAG_RESPASSPW_EN_MASK
?
1117 iommu_feature_enable(iommu
, CONTROL_RESPASSPW_EN
) :
1118 iommu_feature_disable(iommu
, CONTROL_RESPASSPW_EN
);
1120 iommu
->acpi_flags
& IVHD_FLAG_ISOC_EN_MASK
?
1121 iommu_feature_enable(iommu
, CONTROL_ISOC_EN
) :
1122 iommu_feature_disable(iommu
, CONTROL_ISOC_EN
);
1125 * make IOMMU memory accesses cache coherent
1127 iommu_feature_enable(iommu
, CONTROL_COHERENT_EN
);
1130 static void iommu_apply_quirks(struct amd_iommu
*iommu
)
1132 if (is_rd890_iommu(iommu
->dev
)) {
1133 pci_write_config_dword(iommu
->dev
, 0xf0, iommu
->cache_cfg
[0]);
1134 pci_write_config_dword(iommu
->dev
, 0xf4, iommu
->cache_cfg
[1]);
1135 pci_write_config_dword(iommu
->dev
, 0xf8, iommu
->cache_cfg
[2]);
1136 pci_write_config_dword(iommu
->dev
, 0xfc, iommu
->cache_cfg
[3]);
1141 * This function finally enables all IOMMUs found in the system after
1142 * they have been initialized
1144 static void enable_iommus(void)
1146 struct amd_iommu
*iommu
;
1148 for_each_iommu(iommu
) {
1149 iommu_disable(iommu
);
1150 iommu_apply_quirks(iommu
);
1151 iommu_init_flags(iommu
);
1152 iommu_set_device_table(iommu
);
1153 iommu_enable_command_buffer(iommu
);
1154 iommu_enable_event_buffer(iommu
);
1155 iommu_set_exclusion_range(iommu
);
1156 iommu_init_msi(iommu
);
1157 iommu_enable(iommu
);
1161 static void disable_iommus(void)
1163 struct amd_iommu
*iommu
;
1165 for_each_iommu(iommu
)
1166 iommu_disable(iommu
);
1170 * Suspend/Resume support
1171 * disable suspend until real resume implemented
1174 static int amd_iommu_resume(struct sys_device
*dev
)
1176 /* re-load the hardware */
1180 * we have to flush after the IOMMUs are enabled because a
1181 * disabled IOMMU will never execute the commands we send
1183 amd_iommu_flush_all_devices();
1184 amd_iommu_flush_all_domains();
1189 static int amd_iommu_suspend(struct sys_device
*dev
, pm_message_t state
)
1191 /* disable IOMMUs to go out of the way for BIOS */
1197 static struct sysdev_class amd_iommu_sysdev_class
= {
1198 .name
= "amd_iommu",
1199 .suspend
= amd_iommu_suspend
,
1200 .resume
= amd_iommu_resume
,
1203 static struct sys_device device_amd_iommu
= {
1205 .cls
= &amd_iommu_sysdev_class
,
1209 * This is the core init function for AMD IOMMU hardware in the system.
1210 * This function is called from the generic x86 DMA layer initialization
1213 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1216 * 1 pass) Find the highest PCI device id the driver has to handle.
1217 * Upon this information the size of the data structures is
1218 * determined that needs to be allocated.
1220 * 2 pass) Initialize the data structures just allocated with the
1221 * information in the ACPI table about available AMD IOMMUs
1222 * in the system. It also maps the PCI devices in the
1223 * system to specific IOMMUs
1225 * 3 pass) After the basic data structures are allocated and
1226 * initialized we update them with information about memory
1227 * remapping requirements parsed out of the ACPI table in
1230 * After that the hardware is initialized and ready to go. In the last
1231 * step we do some Linux specific things like registering the driver in
1232 * the dma_ops interface and initializing the suspend/resume support
1233 * functions. Finally it prints some information about AMD IOMMUs and
1234 * the driver state and enables the hardware.
1236 static int __init
amd_iommu_init(void)
1241 * First parse ACPI tables to find the largest Bus/Dev/Func
1242 * we need to handle. Upon this information the shared data
1243 * structures for the IOMMUs in the system will be allocated
1245 if (acpi_table_parse("IVRS", find_last_devid_acpi
) != 0)
1248 ret
= amd_iommu_init_err
;
1252 dev_table_size
= tbl_size(DEV_TABLE_ENTRY_SIZE
);
1253 alias_table_size
= tbl_size(ALIAS_TABLE_ENTRY_SIZE
);
1254 rlookup_table_size
= tbl_size(RLOOKUP_TABLE_ENTRY_SIZE
);
1258 /* Device table - directly used by all IOMMUs */
1259 amd_iommu_dev_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
1260 get_order(dev_table_size
));
1261 if (amd_iommu_dev_table
== NULL
)
1265 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1266 * IOMMU see for that device
1268 amd_iommu_alias_table
= (void *)__get_free_pages(GFP_KERNEL
,
1269 get_order(alias_table_size
));
1270 if (amd_iommu_alias_table
== NULL
)
1273 /* IOMMU rlookup table - find the IOMMU for a specific device */
1274 amd_iommu_rlookup_table
= (void *)__get_free_pages(
1275 GFP_KERNEL
| __GFP_ZERO
,
1276 get_order(rlookup_table_size
));
1277 if (amd_iommu_rlookup_table
== NULL
)
1280 amd_iommu_pd_alloc_bitmap
= (void *)__get_free_pages(
1281 GFP_KERNEL
| __GFP_ZERO
,
1282 get_order(MAX_DOMAIN_ID
/8));
1283 if (amd_iommu_pd_alloc_bitmap
== NULL
)
1286 /* init the device table */
1287 init_device_table();
1290 * let all alias entries point to itself
1292 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
1293 amd_iommu_alias_table
[i
] = i
;
1296 * never allocate domain 0 because its used as the non-allocated and
1297 * error value placeholder
1299 amd_iommu_pd_alloc_bitmap
[0] = 1;
1301 spin_lock_init(&amd_iommu_pd_lock
);
1304 * now the data structures are allocated and basically initialized
1305 * start the real acpi table scan
1308 if (acpi_table_parse("IVRS", init_iommu_all
) != 0)
1311 if (amd_iommu_init_err
) {
1312 ret
= amd_iommu_init_err
;
1316 if (acpi_table_parse("IVRS", init_memory_definitions
) != 0)
1319 if (amd_iommu_init_err
) {
1320 ret
= amd_iommu_init_err
;
1324 ret
= sysdev_class_register(&amd_iommu_sysdev_class
);
1328 ret
= sysdev_register(&device_amd_iommu
);
1332 ret
= amd_iommu_init_devices();
1338 if (iommu_pass_through
)
1339 ret
= amd_iommu_init_passthrough();
1341 ret
= amd_iommu_init_dma_ops();
1346 amd_iommu_init_api();
1348 amd_iommu_init_notifier();
1350 if (iommu_pass_through
)
1353 if (amd_iommu_unmap_flush
)
1354 printk(KERN_INFO
"AMD-Vi: IO/TLB flush on unmap enabled\n");
1356 printk(KERN_INFO
"AMD-Vi: Lazy IO/TLB flushing enabled\n");
1358 x86_platform
.iommu_shutdown
= disable_iommus
;
1366 amd_iommu_uninit_devices();
1368 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap
,
1369 get_order(MAX_DOMAIN_ID
/8));
1371 free_pages((unsigned long)amd_iommu_rlookup_table
,
1372 get_order(rlookup_table_size
));
1374 free_pages((unsigned long)amd_iommu_alias_table
,
1375 get_order(alias_table_size
));
1377 free_pages((unsigned long)amd_iommu_dev_table
,
1378 get_order(dev_table_size
));
1384 #ifdef CONFIG_GART_IOMMU
1386 * We failed to initialize the AMD IOMMU - try fallback to GART
1396 /****************************************************************************
1398 * Early detect code. This code runs at IOMMU detection time in the DMA
1399 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1402 ****************************************************************************/
1403 static int __init
early_amd_iommu_detect(struct acpi_table_header
*table
)
1408 void __init
amd_iommu_detect(void)
1410 if (no_iommu
|| (iommu_detected
&& !gart_iommu_aperture
))
1413 if (amd_iommu_disabled
)
1416 if (acpi_table_parse("IVRS", early_amd_iommu_detect
) == 0) {
1418 amd_iommu_detected
= 1;
1419 x86_init
.iommu
.iommu_init
= amd_iommu_init
;
1421 /* Make sure ACS will be enabled */
1426 /****************************************************************************
1428 * Parsing functions for the AMD IOMMU specific kernel command line
1431 ****************************************************************************/
1433 static int __init
parse_amd_iommu_dump(char *str
)
1435 amd_iommu_dump
= true;
1440 static int __init
parse_amd_iommu_options(char *str
)
1442 for (; *str
; ++str
) {
1443 if (strncmp(str
, "fullflush", 9) == 0)
1444 amd_iommu_unmap_flush
= true;
1445 if (strncmp(str
, "off", 3) == 0)
1446 amd_iommu_disabled
= true;
1452 __setup("amd_iommu_dump", parse_amd_iommu_dump
);
1453 __setup("amd_iommu=", parse_amd_iommu_options
);