drivers/usb/host/pci-quirks.c

   1 /*
   2  * This file contains code to reset and initialize USB host controllers.
   3  * Some of it includes work-arounds for PCI hardware and BIOS quirks.
   4  * It may need to run early during booting -- before USB would normally
   5  * initialize -- to ensure that Linux doesn't use any legacy modes.
   6  *
   7  *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
   8  *  (and others)
   9  */
  10
  11 #include <linux/types.h>
  12 #include <linux/kernel.h>
  13 #include <linux/pci.h>
  14 #include <linux/init.h>
  15 #include <linux/delay.h>
  16 #include <linux/acpi.h>
  17 #include <linux/dmi.h>
  18 #include "pci-quirks.h"
  19 #include "xhci-ext-caps.h"
  20
  21
  22 #define UHCI_USBLEGSUP          0xc0            /* legacy support */
  23 #define UHCI_USBCMD             0               /* command register */
  24 #define UHCI_USBINTR            4               /* interrupt register */
  25 #define UHCI_USBLEGSUP_RWC      0x8f00          /* the R/WC bits */
  26 #define UHCI_USBLEGSUP_RO       0x5040          /* R/O and reserved bits */
  27 #define UHCI_USBCMD_RUN         0x0001          /* RUN/STOP bit */
  28 #define UHCI_USBCMD_HCRESET     0x0002          /* Host Controller reset */
  29 #define UHCI_USBCMD_EGSM        0x0008          /* Global Suspend Mode */
  30 #define UHCI_USBCMD_CONFIGURE   0x0040          /* Config Flag */
  31 #define UHCI_USBINTR_RESUME     0x0002          /* Resume interrupt enable */
  32
  33 #define OHCI_CONTROL            0x04
  34 #define OHCI_CMDSTATUS          0x08
  35 #define OHCI_INTRSTATUS         0x0c
  36 #define OHCI_INTRENABLE         0x10
  37 #define OHCI_INTRDISABLE        0x14
  38 #define OHCI_FMINTERVAL         0x34
  39 #define OHCI_HCFS               (3 << 6)        /* hc functional state */
  40 #define OHCI_HCR                (1 << 0)        /* host controller reset */
  41 #define OHCI_OCR                (1 << 3)        /* ownership change request */
  42 #define OHCI_CTRL_RWC           (1 << 9)        /* remote wakeup connected */
  43 #define OHCI_CTRL_IR            (1 << 8)        /* interrupt routing */
  44 #define OHCI_INTR_OC            (1 << 30)       /* ownership change */
  45
  46 #define EHCI_HCC_PARAMS         0x08            /* extended capabilities */
  47 #define EHCI_USBCMD             0               /* command register */
  48 #define EHCI_USBCMD_RUN         (1 << 0)        /* RUN/STOP bit */
  49 #define EHCI_USBSTS             4               /* status register */
  50 #define EHCI_USBSTS_HALTED      (1 << 12)       /* HCHalted bit */
  51 #define EHCI_USBINTR            8               /* interrupt register */
  52 #define EHCI_CONFIGFLAG         0x40            /* configured flag register */
  53 #define EHCI_USBLEGSUP          0               /* legacy support register */
  54 #define EHCI_USBLEGSUP_BIOS     (1 << 16)       /* BIOS semaphore */
  55 #define EHCI_USBLEGSUP_OS       (1 << 24)       /* OS semaphore */
  56 #define EHCI_USBLEGCTLSTS       4               /* legacy control/status */
  57 #define EHCI_USBLEGCTLSTS_SOOE  (1 << 13)       /* SMI on ownership change */
  58
  59 /* AMD quirk use */
  60 #define AB_REG_BAR_LOW          0xe0
  61 #define AB_REG_BAR_HIGH         0xe1
  62 #define AB_REG_BAR_SB700        0xf0
  63 #define AB_INDX(addr)           ((addr) + 0x00)
  64 #define AB_DATA(addr)           ((addr) + 0x04)
  65 #define AX_INDXC                0x30
  66 #define AX_DATAC                0x34
  67
  68 #define NB_PCIE_INDX_ADDR       0xe0
  69 #define NB_PCIE_INDX_DATA       0xe4
  70 #define PCIE_P_CNTL             0x10040
  71 #define BIF_NB                  0x10002
  72 #define NB_PIF0_PWRDOWN_0       0x01100012
  73 #define NB_PIF0_PWRDOWN_1       0x01100013
  74
  75 #define USB_INTEL_XUSB2PR      0xD0
  76 #define USB_INTEL_USB3_PSSEN   0xD8
  77
  78 static struct amd_chipset_info {
  79         struct pci_dev  *nb_dev;
  80         struct pci_dev  *smbus_dev;
  81         int nb_type;
  82         int sb_type;
  83         int isoc_reqs;
  84         int probe_count;
  85         int probe_result;
  86 } amd_chipset;
  87
  88 static DEFINE_SPINLOCK(amd_lock);
  89
  90 int usb_amd_find_chipset_info(void)
  91 {
  92         u8 rev = 0;
  93         unsigned long flags;
  94         struct amd_chipset_info info;
  95         int ret;
  96
  97         spin_lock_irqsave(&amd_lock, flags);
  98
  99         /* probe only once */
 100         if (amd_chipset.probe_count > 0) {
 101                 amd_chipset.probe_count++;
 102                 spin_unlock_irqrestore(&amd_lock, flags);
 103                 return amd_chipset.probe_result;
 104         }
 105         memset(&info, 0, sizeof(info));
 106         spin_unlock_irqrestore(&amd_lock, flags);
 107
 108         info.smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
 109         if (info.smbus_dev) {
 110                 rev = info.smbus_dev->revision;
 111                 if (rev >= 0x40)
 112                         info.sb_type = 1;
 113                 else if (rev >= 0x30 && rev <= 0x3b)
 114                         info.sb_type = 3;
 115         } else {
 116                 info.smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
 117                                                 0x780b, NULL);
 118                 if (!info.smbus_dev) {
 119                         ret = 0;
 120                         goto commit;
 121                 }
 122
 123                 rev = info.smbus_dev->revision;
 124                 if (rev >= 0x11 && rev <= 0x18)
 125                         info.sb_type = 2;
 126         }
 127
 128         if (info.sb_type == 0) {
 129                 if (info.smbus_dev) {
 130                         pci_dev_put(info.smbus_dev);
 131                         info.smbus_dev = NULL;
 132                 }
 133                 ret = 0;
 134                 goto commit;
 135         }
 136
 137         info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
 138         if (info.nb_dev) {
 139                 info.nb_type = 1;
 140         } else {
 141                 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
 142                 if (info.nb_dev) {
 143                         info.nb_type = 2;
 144                 } else {
 145                         info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
 146                                                      0x9600, NULL);
 147                         if (info.nb_dev)
 148                                 info.nb_type = 3;
 149                 }
 150         }
 151
 152         ret = info.probe_result = 1;
 153         printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
 154
 155 commit:
 156
 157         spin_lock_irqsave(&amd_lock, flags);
 158         if (amd_chipset.probe_count > 0) {
 159                 /* race - someone else was faster - drop devices */
 160
 161                 /* Mark that we where here */
 162                 amd_chipset.probe_count++;
 163                 ret = amd_chipset.probe_result;
 164
 165                 spin_unlock_irqrestore(&amd_lock, flags);
 166
 167                 if (info.nb_dev)
 168                         pci_dev_put(info.nb_dev);
 169                 if (info.smbus_dev)
 170                         pci_dev_put(info.smbus_dev);
 171
 172         } else {
 173                 /* no race - commit the result */
 174                 info.probe_count++;
 175                 amd_chipset = info;
 176                 spin_unlock_irqrestore(&amd_lock, flags);
 177         }
 178
 179         return ret;
 180 }
 181 EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
 182
 183 /*
 184  * The hardware normally enables the A-link power management feature, which
 185  * lets the system lower the power consumption in idle states.
 186  *
 187  * This USB quirk prevents the link going into that lower power state
 188  * during isochronous transfers.
 189  *
 190  * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
 191  * some AMD platforms may stutter or have breaks occasionally.
 192  */
 193 static void usb_amd_quirk_pll(int disable)
 194 {
 195         u32 addr, addr_low, addr_high, val;
 196         u32 bit = disable ? 0 : 1;
 197         unsigned long flags;
 198
 199         spin_lock_irqsave(&amd_lock, flags);
 200
 201         if (disable) {
 202                 amd_chipset.isoc_reqs++;
 203                 if (amd_chipset.isoc_reqs > 1) {
 204                         spin_unlock_irqrestore(&amd_lock, flags);
 205                         return;
 206                 }
 207         } else {
 208                 amd_chipset.isoc_reqs--;
 209                 if (amd_chipset.isoc_reqs > 0) {
 210                         spin_unlock_irqrestore(&amd_lock, flags);
 211                         return;
 212                 }
 213         }
 214
 215         if (amd_chipset.sb_type == 1 || amd_chipset.sb_type == 2) {
 216                 outb_p(AB_REG_BAR_LOW, 0xcd6);
 217                 addr_low = inb_p(0xcd7);
 218                 outb_p(AB_REG_BAR_HIGH, 0xcd6);
 219                 addr_high = inb_p(0xcd7);
 220                 addr = addr_high << 8 | addr_low;
 221
 222                 outl_p(0x30, AB_INDX(addr));
 223                 outl_p(0x40, AB_DATA(addr));
 224                 outl_p(0x34, AB_INDX(addr));
 225                 val = inl_p(AB_DATA(addr));
 226         } else if (amd_chipset.sb_type == 3) {
 227                 pci_read_config_dword(amd_chipset.smbus_dev,
 228                                         AB_REG_BAR_SB700, &addr);
 229                 outl(AX_INDXC, AB_INDX(addr));
 230                 outl(0x40, AB_DATA(addr));
 231                 outl(AX_DATAC, AB_INDX(addr));
 232                 val = inl(AB_DATA(addr));
 233         } else {
 234                 spin_unlock_irqrestore(&amd_lock, flags);
 235                 return;
 236         }
 237
 238         if (disable) {
 239                 val &= ~0x08;
 240                 val |= (1 << 4) | (1 << 9);
 241         } else {
 242                 val |= 0x08;
 243                 val &= ~((1 << 4) | (1 << 9));
 244         }
 245         outl_p(val, AB_DATA(addr));
 246
 247         if (!amd_chipset.nb_dev) {
 248                 spin_unlock_irqrestore(&amd_lock, flags);
 249                 return;
 250         }
 251
 252         if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
 253                 addr = PCIE_P_CNTL;
 254                 pci_write_config_dword(amd_chipset.nb_dev,
 255                                         NB_PCIE_INDX_ADDR, addr);
 256                 pci_read_config_dword(amd_chipset.nb_dev,
 257                                         NB_PCIE_INDX_DATA, &val);
 258
 259                 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
 260                 val |= bit | (bit << 3) | (bit << 12);
 261                 val |= ((!bit) << 4) | ((!bit) << 9);
 262                 pci_write_config_dword(amd_chipset.nb_dev,
 263                                         NB_PCIE_INDX_DATA, val);
 264
 265                 addr = BIF_NB;
 266                 pci_write_config_dword(amd_chipset.nb_dev,
 267                                         NB_PCIE_INDX_ADDR, addr);
 268                 pci_read_config_dword(amd_chipset.nb_dev,
 269                                         NB_PCIE_INDX_DATA, &val);
 270                 val &= ~(1 << 8);
 271                 val |= bit << 8;
 272
 273                 pci_write_config_dword(amd_chipset.nb_dev,
 274                                         NB_PCIE_INDX_DATA, val);
 275         } else if (amd_chipset.nb_type == 2) {
 276                 addr = NB_PIF0_PWRDOWN_0;
 277                 pci_write_config_dword(amd_chipset.nb_dev,
 278                                         NB_PCIE_INDX_ADDR, addr);
 279                 pci_read_config_dword(amd_chipset.nb_dev,
 280                                         NB_PCIE_INDX_DATA, &val);
 281                 if (disable)
 282                         val &= ~(0x3f << 7);
 283                 else
 284                         val |= 0x3f << 7;
 285
 286                 pci_write_config_dword(amd_chipset.nb_dev,
 287                                         NB_PCIE_INDX_DATA, val);
 288
 289                 addr = NB_PIF0_PWRDOWN_1;
 290                 pci_write_config_dword(amd_chipset.nb_dev,
 291                                         NB_PCIE_INDX_ADDR, addr);
 292                 pci_read_config_dword(amd_chipset.nb_dev,
 293                                         NB_PCIE_INDX_DATA, &val);
 294                 if (disable)
 295                         val &= ~(0x3f << 7);
 296                 else
 297                         val |= 0x3f << 7;
 298
 299                 pci_write_config_dword(amd_chipset.nb_dev,
 300                                         NB_PCIE_INDX_DATA, val);
 301         }
 302
 303         spin_unlock_irqrestore(&amd_lock, flags);
 304         return;
 305 }
 306
 307 void usb_amd_quirk_pll_disable(void)
 308 {
 309         usb_amd_quirk_pll(1);
 310 }
 311 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
 312
 313 void usb_amd_quirk_pll_enable(void)
 314 {
 315         usb_amd_quirk_pll(0);
 316 }
 317 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
 318
 319 void usb_amd_dev_put(void)
 320 {
 321         struct pci_dev *nb, *smbus;
 322         unsigned long flags;
 323
 324         spin_lock_irqsave(&amd_lock, flags);
 325
 326         amd_chipset.probe_count--;
 327         if (amd_chipset.probe_count > 0) {
 328                 spin_unlock_irqrestore(&amd_lock, flags);
 329                 return;
 330         }
 331
 332         /* save them to pci_dev_put outside of spinlock */
 333         nb    = amd_chipset.nb_dev;
 334         smbus = amd_chipset.smbus_dev;
 335
 336         amd_chipset.nb_dev = NULL;
 337         amd_chipset.smbus_dev = NULL;
 338         amd_chipset.nb_type = 0;
 339         amd_chipset.sb_type = 0;
 340         amd_chipset.isoc_reqs = 0;
 341         amd_chipset.probe_result = 0;
 342
 343         spin_unlock_irqrestore(&amd_lock, flags);
 344
 345         if (nb)
 346                 pci_dev_put(nb);
 347         if (smbus)
 348                 pci_dev_put(smbus);
 349 }
 350 EXPORT_SYMBOL_GPL(usb_amd_dev_put);
 351
 352 /*
 353  * Make sure the controller is completely inactive, unable to
 354  * generate interrupts or do DMA.
 355  */
 356 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
 357 {
 358         /* Turn off PIRQ enable and SMI enable.  (This also turns off the
 359          * BIOS's USB Legacy Support.)  Turn off all the R/WC bits too.
 360          */
 361         pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
 362
 363         /* Reset the HC - this will force us to get a
 364          * new notification of any already connected
 365          * ports due to the virtual disconnect that it
 366          * implies.
 367          */
 368         outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
 369         mb();
 370         udelay(5);
 371         if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
 372                 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
 373
 374         /* Just to be safe, disable interrupt requests and
 375          * make sure the controller is stopped.
 376          */
 377         outw(0, base + UHCI_USBINTR);
 378         outw(0, base + UHCI_USBCMD);
 379 }
 380 EXPORT_SYMBOL_GPL(uhci_reset_hc);
 381
 382 /*
 383  * Initialize a controller that was newly discovered or has just been
 384  * resumed.  In either case we can't be sure of its previous state.
 385  *
 386  * Returns: 1 if the controller was reset, 0 otherwise.
 387  */
 388 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
 389 {
 390         u16 legsup;
 391         unsigned int cmd, intr;
 392
 393         /*
 394          * When restarting a suspended controller, we expect all the
 395          * settings to be the same as we left them:
 396          *
 397          *      PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
 398          *      Controller is stopped and configured with EGSM set;
 399          *      No interrupts enabled except possibly Resume Detect.
 400          *
 401          * If any of these conditions are violated we do a complete reset.
 402          */
 403         pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
 404         if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
 405                 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
 406                                 __func__, legsup);
 407                 goto reset_needed;
 408         }
 409
 410         cmd = inw(base + UHCI_USBCMD);
 411         if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
 412                         !(cmd & UHCI_USBCMD_EGSM)) {
 413                 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
 414                                 __func__, cmd);
 415                 goto reset_needed;
 416         }
 417
 418         intr = inw(base + UHCI_USBINTR);
 419         if (intr & (~UHCI_USBINTR_RESUME)) {
 420                 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
 421                                 __func__, intr);
 422                 goto reset_needed;
 423         }
 424         return 0;
 425
 426 reset_needed:
 427         dev_dbg(&pdev->dev, "Performing full reset\n");
 428         uhci_reset_hc(pdev, base);
 429         return 1;
 430 }
 431 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
 432
 433 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
 434 {
 435         u16 cmd;
 436         return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
 437 }
 438
 439 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
 440 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
 441
 442 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
 443 {
 444         unsigned long base = 0;
 445         int i;
 446
 447         if (!pio_enabled(pdev))
 448                 return;
 449
 450         for (i = 0; i < PCI_ROM_RESOURCE; i++)
 451                 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
 452                         base = pci_resource_start(pdev, i);
 453                         break;
 454                 }
 455
 456         if (base)
 457                 uhci_check_and_reset_hc(pdev, base);
 458 }
 459
 460 static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)
 461 {
 462         return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
 463 }
 464
 465 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
 466 {
 467         void __iomem *base;
 468         u32 control;
 469         u32 fminterval;
 470         int cnt;
 471
 472         if (!mmio_resource_enabled(pdev, 0))
 473                 return;
 474
 475         base = pci_ioremap_bar(pdev, 0);
 476         if (base == NULL)
 477                 return;
 478
 479         control = readl(base + OHCI_CONTROL);
 480
 481 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
 482 #ifdef __hppa__
 483 #define OHCI_CTRL_MASK          (OHCI_CTRL_RWC | OHCI_CTRL_IR)
 484 #else
 485 #define OHCI_CTRL_MASK          OHCI_CTRL_RWC
 486
 487         if (control & OHCI_CTRL_IR) {
 488                 int wait_time = 500; /* arbitrary; 5 seconds */
 489                 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
 490                 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
 491                 while (wait_time > 0 &&
 492                                 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
 493                         wait_time -= 10;
 494                         msleep(10);
 495                 }
 496                 if (wait_time <= 0)
 497                         dev_warn(&pdev->dev, "OHCI: BIOS handoff failed"
 498                                         " (BIOS bug?) %08x\n",
 499                                         readl(base + OHCI_CONTROL));
 500         }
 501 #endif
 502
 503         /* disable interrupts */
 504         writel((u32) ~0, base + OHCI_INTRDISABLE);
 505
 506         /* Reset the USB bus, if the controller isn't already in RESET */
 507         if (control & OHCI_HCFS) {
 508                 /* Go into RESET, preserving RWC (and possibly IR) */
 509                 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
 510                 readl(base + OHCI_CONTROL);
 511
 512                 /* drive bus reset for at least 50 ms (7.1.7.5) */
 513                 msleep(50);
 514         }
 515
 516         /* software reset of the controller, preserving HcFmInterval */
 517         fminterval = readl(base + OHCI_FMINTERVAL);
 518         writel(OHCI_HCR, base + OHCI_CMDSTATUS);
 519
 520         /* reset requires max 10 us delay */
 521         for (cnt = 30; cnt > 0; --cnt) {        /* ... allow extra time */
 522                 if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
 523                         break;
 524                 udelay(1);
 525         }
 526         writel(fminterval, base + OHCI_FMINTERVAL);
 527
 528         /* Now the controller is safely in SUSPEND and nothing can wake it up */
 529         iounmap(base);
 530 }
 531
 532 static const struct dmi_system_id __devinitconst ehci_dmi_nohandoff_table[] = {
 533         {
 534                 /*  Pegatron Lucid (ExoPC) */
 535                 .matches = {
 536                         DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"),
 537                         DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"),
 538                 },
 539         },
 540         {
 541                 /*  Pegatron Lucid (Ordissimo AIRIS) */
 542                 .matches = {
 543                         DMI_MATCH(DMI_BOARD_NAME, "M11JB"),
 544                         DMI_MATCH(DMI_BIOS_VERSION, "Lucid-GE-133"),
 545                 },
 546         },
 547         { }
 548 };
 549
 550 static void __devinit ehci_bios_handoff(struct pci_dev *pdev,
 551                                         void __iomem *op_reg_base,
 552                                         u32 cap, u8 offset)
 553 {
 554         int try_handoff = 1, tried_handoff = 0;
 555
 556         /* The Pegatron Lucid tablet sporadically waits for 98 seconds trying
 557          * the handoff on its unused controller.  Skip it. */
 558         if (pdev->vendor == 0x8086 && pdev->device == 0x283a) {
 559                 if (dmi_check_system(ehci_dmi_nohandoff_table))
 560                         try_handoff = 0;
 561         }
 562
 563         if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
 564                 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
 565
 566 #if 0
 567 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
 568  * but that seems dubious in general (the BIOS left it off intentionally)
 569  * and is known to prevent some systems from booting.  so we won't do this
 570  * unless maybe we can determine when we're on a system that needs SMI forced.
 571  */
 572                 /* BIOS workaround (?): be sure the pre-Linux code
 573                  * receives the SMI
 574                  */
 575                 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
 576                 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
 577                                        val | EHCI_USBLEGCTLSTS_SOOE);
 578 #endif
 579
 580                 /* some systems get upset if this semaphore is
 581                  * set for any other reason than forcing a BIOS
 582                  * handoff..
 583                  */
 584                 pci_write_config_byte(pdev, offset + 3, 1);
 585         }
 586
 587         /* if boot firmware now owns EHCI, spin till it hands it over. */
 588         if (try_handoff) {
 589                 int msec = 1000;
 590                 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
 591                         tried_handoff = 1;
 592                         msleep(10);
 593                         msec -= 10;
 594                         pci_read_config_dword(pdev, offset, &cap);
 595                 }
 596         }
 597
 598         if (cap & EHCI_USBLEGSUP_BIOS) {
 599                 /* well, possibly buggy BIOS... try to shut it down,
 600                  * and hope nothing goes too wrong
 601                  */
 602                 if (try_handoff)
 603                         dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
 604                                  " (BIOS bug?) %08x\n", cap);
 605                 pci_write_config_byte(pdev, offset + 2, 0);
 606         }
 607
 608         /* just in case, always disable EHCI SMIs */
 609         pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
 610
 611         /* If the BIOS ever owned the controller then we can't expect
 612          * any power sessions to remain intact.
 613          */
 614         if (tried_handoff)
 615                 writel(0, op_reg_base + EHCI_CONFIGFLAG);
 616 }
 617
 618 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
 619 {
 620         void __iomem *base, *op_reg_base;
 621         u32     hcc_params, cap, val;
 622         u8      offset, cap_length;
 623         int     wait_time, count = 256/4;
 624
 625         if (!mmio_resource_enabled(pdev, 0))
 626                 return;
 627
 628         base = pci_ioremap_bar(pdev, 0);
 629         if (base == NULL)
 630                 return;
 631
 632         cap_length = readb(base);
 633         op_reg_base = base + cap_length;
 634
 635         /* EHCI 0.96 and later may have "extended capabilities"
 636          * spec section 5.1 explains the bios handoff, e.g. for
 637          * booting from USB disk or using a usb keyboard
 638          */
 639         hcc_params = readl(base + EHCI_HCC_PARAMS);
 640         offset = (hcc_params >> 8) & 0xff;
 641         while (offset && --count) {
 642                 pci_read_config_dword(pdev, offset, &cap);
 643
 644                 switch (cap & 0xff) {
 645                 case 1:
 646                         ehci_bios_handoff(pdev, op_reg_base, cap, offset);
 647                         break;
 648                 case 0: /* Illegal reserved cap, set cap=0 so we exit */
 649                         cap = 0; /* then fallthrough... */
 650                 default:
 651                         dev_warn(&pdev->dev, "EHCI: unrecognized capability "
 652                                  "%02x\n", cap & 0xff);
 653                 }
 654                 offset = (cap >> 8) & 0xff;
 655         }
 656         if (!count)
 657                 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
 658
 659         /*
 660          * halt EHCI & disable its interrupts in any case
 661          */
 662         val = readl(op_reg_base + EHCI_USBSTS);
 663         if ((val & EHCI_USBSTS_HALTED) == 0) {
 664                 val = readl(op_reg_base + EHCI_USBCMD);
 665                 val &= ~EHCI_USBCMD_RUN;
 666                 writel(val, op_reg_base + EHCI_USBCMD);
 667
 668                 wait_time = 2000;
 669                 do {
 670                         writel(0x3f, op_reg_base + EHCI_USBSTS);
 671                         udelay(100);
 672                         wait_time -= 100;
 673                         val = readl(op_reg_base + EHCI_USBSTS);
 674                         if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
 675                                 break;
 676                         }
 677                 } while (wait_time > 0);
 678         }
 679         writel(0, op_reg_base + EHCI_USBINTR);
 680         writel(0x3f, op_reg_base + EHCI_USBSTS);
 681
 682         iounmap(base);
 683 }
 684
 685 /*
 686  * handshake - spin reading a register until handshake completes
 687  * @ptr: address of hc register to be read
 688  * @mask: bits to look at in result of read
 689  * @done: value of those bits when handshake succeeds
 690  * @wait_usec: timeout in microseconds
 691  * @delay_usec: delay in microseconds to wait between polling
 692  *
 693  * Polls a register every delay_usec microseconds.
 694  * Returns 0 when the mask bits have the value done.
 695  * Returns -ETIMEDOUT if this condition is not true after
 696  * wait_usec microseconds have passed.
 697  */
 698 static int handshake(void __iomem *ptr, u32 mask, u32 done,
 699                 int wait_usec, int delay_usec)
 700 {
 701         u32     result;
 702
 703         do {
 704                 result = readl(ptr);
 705                 result &= mask;
 706                 if (result == done)
 707                         return 0;
 708                 udelay(delay_usec);
 709                 wait_usec -= delay_usec;
 710         } while (wait_usec > 0);
 711         return -ETIMEDOUT;
 712 }
 713
 714 bool usb_is_intel_switchable_xhci(struct pci_dev *pdev)
 715 {
 716         return pdev->class == PCI_CLASS_SERIAL_USB_XHCI &&
 717                 pdev->vendor == PCI_VENDOR_ID_INTEL &&
 718                 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI;
 719 }
 720 EXPORT_SYMBOL_GPL(usb_is_intel_switchable_xhci);
 721
 722 /*
 723  * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
 724  * share some number of ports.  These ports can be switched between either
 725  * controller.  Not all of the ports under the EHCI host controller may be
 726  * switchable.
 727  *
 728  * The ports should be switched over to xHCI before PCI probes for any device
 729  * start.  This avoids active devices under EHCI being disconnected during the
 730  * port switchover, which could cause loss of data on USB storage devices, or
 731  * failed boot when the root file system is on a USB mass storage device and is
 732  * enumerated under EHCI first.
 733  *
 734  * We write into the xHC's PCI configuration space in some Intel-specific
 735  * registers to switch the ports over.  The USB 3.0 terminations and the USB
 736  * 2.0 data wires are switched separately.  We want to enable the SuperSpeed
 737  * terminations before switching the USB 2.0 wires over, so that USB 3.0
 738  * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
 739  */
 740 void usb_enable_xhci_ports(struct pci_dev *xhci_pdev)
 741 {
 742         u32             ports_available;
 743
 744         ports_available = 0xffffffff;
 745         /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
 746          * Register, to turn on SuperSpeed terminations for all
 747          * available ports.
 748          */
 749         pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
 750                         cpu_to_le32(ports_available));
 751
 752         pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
 753                         &ports_available);
 754         dev_dbg(&xhci_pdev->dev, "USB 3.0 ports that are now enabled "
 755                         "under xHCI: 0x%x\n", ports_available);
 756
 757         ports_available = 0xffffffff;
 758         /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
 759          * switch the USB 2.0 power and data lines over to the xHCI
 760          * host.
 761          */
 762         pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
 763                         cpu_to_le32(ports_available));
 764
 765         pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
 766                         &ports_available);
 767         dev_dbg(&xhci_pdev->dev, "USB 2.0 ports that are now switched over "
 768                         "to xHCI: 0x%x\n", ports_available);
 769 }
 770 EXPORT_SYMBOL_GPL(usb_enable_xhci_ports);
 771
 772 /**
 773  * PCI Quirks for xHCI.
 774  *
 775  * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
 776  * It signals to the BIOS that the OS wants control of the host controller,
 777  * and then waits 5 seconds for the BIOS to hand over control.
 778  * If we timeout, assume the BIOS is broken and take control anyway.
 779  */
 780 static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev)
 781 {
 782         void __iomem *base;
 783         int ext_cap_offset;
 784         void __iomem *op_reg_base;
 785         u32 val;
 786         int timeout;
 787
 788         if (!mmio_resource_enabled(pdev, 0))
 789                 return;
 790
 791         base = ioremap_nocache(pci_resource_start(pdev, 0),
 792                                 pci_resource_len(pdev, 0));
 793         if (base == NULL)
 794                 return;
 795
 796         /*
 797          * Find the Legacy Support Capability register -
 798          * this is optional for xHCI host controllers.
 799          */
 800         ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET);
 801         do {
 802                 if (!ext_cap_offset)
 803                         /* We've reached the end of the extended capabilities */
 804                         goto hc_init;
 805                 val = readl(base + ext_cap_offset);
 806                 if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY)
 807                         break;
 808                 ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset);
 809         } while (1);
 810
 811         /* If the BIOS owns the HC, signal that the OS wants it, and wait */
 812         if (val & XHCI_HC_BIOS_OWNED) {
 813                 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
 814
 815                 /* Wait for 5 seconds with 10 microsecond polling interval */
 816                 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
 817                                 0, 5000, 10);
 818
 819                 /* Assume a buggy BIOS and take HC ownership anyway */
 820                 if (timeout) {
 821                         dev_warn(&pdev->dev, "xHCI BIOS handoff failed"
 822                                         " (BIOS bug ?) %08x\n", val);
 823                         writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
 824                 }
 825         }
 826
 827         /* Disable any BIOS SMIs */
 828         writel(XHCI_LEGACY_DISABLE_SMI,
 829                         base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
 830
 831         if (usb_is_intel_switchable_xhci(pdev))
 832                 usb_enable_xhci_ports(pdev);
 833 hc_init:
 834         op_reg_base = base + XHCI_HC_LENGTH(readl(base));
 835
 836         /* Wait for the host controller to be ready before writing any
 837          * operational or runtime registers.  Wait 5 seconds and no more.
 838          */
 839         timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
 840                         5000, 10);
 841         /* Assume a buggy HC and start HC initialization anyway */
 842         if (timeout) {
 843                 val = readl(op_reg_base + XHCI_STS_OFFSET);
 844                 dev_warn(&pdev->dev,
 845                                 "xHCI HW not ready after 5 sec (HC bug?) "
 846                                 "status = 0x%x\n", val);
 847         }
 848
 849         /* Send the halt and disable interrupts command */
 850         val = readl(op_reg_base + XHCI_CMD_OFFSET);
 851         val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
 852         writel(val, op_reg_base + XHCI_CMD_OFFSET);
 853
 854         /* Wait for the HC to halt - poll every 125 usec (one microframe). */
 855         timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
 856                         XHCI_MAX_HALT_USEC, 125);
 857         if (timeout) {
 858                 val = readl(op_reg_base + XHCI_STS_OFFSET);
 859                 dev_warn(&pdev->dev,
 860                                 "xHCI HW did not halt within %d usec "
 861                                 "status = 0x%x\n", XHCI_MAX_HALT_USEC, val);
 862         }
 863
 864         iounmap(base);
 865 }
 866
 867 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
 868 {
 869         if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
 870                 quirk_usb_handoff_uhci(pdev);
 871         else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
 872                 quirk_usb_handoff_ohci(pdev);
 873         else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
 874                 quirk_usb_disable_ehci(pdev);
 875         else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
 876                 quirk_usb_handoff_xhci(pdev);
 877 }
 878 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);