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KVM: VMX: Check cpl before emulating debug register access
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / vmx.c
bloba179ffdb0ce65282fe1ef7623bc7e94a25e68433
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
29 #include "x86.h"
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33 #include <asm/vmx.h>
34 #include <asm/virtext.h>
35 #include <asm/mce.h>
36
37 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38
39 MODULE_AUTHOR("Qumranet");
40 MODULE_LICENSE("GPL");
41
42 static int bypass_guest_pf = 1;
43 module_param(bypass_guest_pf, bool, 0);
44
45 static int enable_vpid = 1;
46 module_param(enable_vpid, bool, 0);
47
48 static int flexpriority_enabled = 1;
49 module_param(flexpriority_enabled, bool, 0);
50
51 static int enable_ept = 1;
52 module_param(enable_ept, bool, 0);
53
54 static int emulate_invalid_guest_state = 0;
55 module_param(emulate_invalid_guest_state, bool, 0);
56
57 struct vmcs {
58 u32 revision_id;
59 u32 abort;
60 char data[0];
61 };
62
63 struct vcpu_vmx {
64 struct kvm_vcpu vcpu;
65 struct list_head local_vcpus_link;
66 unsigned long host_rsp;
67 int launched;
68 u8 fail;
69 u32 idt_vectoring_info;
70 struct kvm_msr_entry *guest_msrs;
71 struct kvm_msr_entry *host_msrs;
72 int nmsrs;
73 int save_nmsrs;
74 int msr_offset_efer;
75 #ifdef CONFIG_X86_64
76 int msr_offset_kernel_gs_base;
77 #endif
78 struct vmcs *vmcs;
79 struct {
80 int loaded;
81 u16 fs_sel, gs_sel, ldt_sel;
82 int gs_ldt_reload_needed;
83 int fs_reload_needed;
84 int guest_efer_loaded;
85 } host_state;
86 struct {
87 struct {
88 bool pending;
89 u8 vector;
90 unsigned rip;
91 } irq;
92 } rmode;
93 int vpid;
94 bool emulation_required;
95 enum emulation_result invalid_state_emulation_result;
96
97 /* Support for vnmi-less CPUs */
98 int soft_vnmi_blocked;
99 ktime_t entry_time;
100 s64 vnmi_blocked_time;
101
102 u32 exit_reason;
103 };
104
105 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
106 {
107 return container_of(vcpu, struct vcpu_vmx, vcpu);
108 }
109
110 static int init_rmode(struct kvm *kvm);
111 static u64 construct_eptp(unsigned long root_hpa);
112
113 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
114 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
115 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
116
117 static struct page *vmx_io_bitmap_a;
118 static struct page *vmx_io_bitmap_b;
119 static struct page *vmx_msr_bitmap;
120
121 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
122 static DEFINE_SPINLOCK(vmx_vpid_lock);
123
124 static struct vmcs_config {
125 int size;
126 int order;
127 u32 revision_id;
128 u32 pin_based_exec_ctrl;
129 u32 cpu_based_exec_ctrl;
130 u32 cpu_based_2nd_exec_ctrl;
131 u32 vmexit_ctrl;
132 u32 vmentry_ctrl;
133 } vmcs_config;
134
135 static struct vmx_capability {
136 u32 ept;
137 u32 vpid;
138 } vmx_capability;
139
140 #define VMX_SEGMENT_FIELD(seg) \
141 [VCPU_SREG_##seg] = { \
142 .selector = GUEST_##seg##_SELECTOR, \
143 .base = GUEST_##seg##_BASE, \
144 .limit = GUEST_##seg##_LIMIT, \
145 .ar_bytes = GUEST_##seg##_AR_BYTES, \
146 }
147
148 static struct kvm_vmx_segment_field {
149 unsigned selector;
150 unsigned base;
151 unsigned limit;
152 unsigned ar_bytes;
153 } kvm_vmx_segment_fields[] = {
154 VMX_SEGMENT_FIELD(CS),
155 VMX_SEGMENT_FIELD(DS),
156 VMX_SEGMENT_FIELD(ES),
157 VMX_SEGMENT_FIELD(FS),
158 VMX_SEGMENT_FIELD(GS),
159 VMX_SEGMENT_FIELD(SS),
160 VMX_SEGMENT_FIELD(TR),
161 VMX_SEGMENT_FIELD(LDTR),
162 };
163
164 /*
165 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
166 * away by decrementing the array size.
167 */
168 static const u32 vmx_msr_index[] = {
169 #ifdef CONFIG_X86_64
170 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
171 #endif
172 MSR_EFER, MSR_K6_STAR,
173 };
174 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
175
176 static void load_msrs(struct kvm_msr_entry *e, int n)
177 {
178 int i;
179
180 for (i = 0; i < n; ++i)
181 wrmsrl(e[i].index, e[i].data);
182 }
183
184 static void save_msrs(struct kvm_msr_entry *e, int n)
185 {
186 int i;
187
188 for (i = 0; i < n; ++i)
189 rdmsrl(e[i].index, e[i].data);
190 }
191
192 static inline int is_page_fault(u32 intr_info)
193 {
194 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
195 INTR_INFO_VALID_MASK)) ==
196 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
197 }
198
199 static inline int is_no_device(u32 intr_info)
200 {
201 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
202 INTR_INFO_VALID_MASK)) ==
203 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
204 }
205
206 static inline int is_invalid_opcode(u32 intr_info)
207 {
208 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
209 INTR_INFO_VALID_MASK)) ==
210 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
211 }
212
213 static inline int is_external_interrupt(u32 intr_info)
214 {
215 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
216 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
217 }
218
219 static inline int cpu_has_vmx_msr_bitmap(void)
220 {
221 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
222 }
223
224 static inline int cpu_has_vmx_tpr_shadow(void)
225 {
226 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
227 }
228
229 static inline int vm_need_tpr_shadow(struct kvm *kvm)
230 {
231 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
232 }
233
234 static inline int cpu_has_secondary_exec_ctrls(void)
235 {
236 return (vmcs_config.cpu_based_exec_ctrl &
237 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
238 }
239
240 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
241 {
242 return flexpriority_enabled
243 && (vmcs_config.cpu_based_2nd_exec_ctrl &
244 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
245 }
246
247 static inline int cpu_has_vmx_invept_individual_addr(void)
248 {
249 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
250 }
251
252 static inline int cpu_has_vmx_invept_context(void)
253 {
254 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
255 }
256
257 static inline int cpu_has_vmx_invept_global(void)
258 {
259 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
260 }
261
262 static inline int cpu_has_vmx_ept(void)
263 {
264 return (vmcs_config.cpu_based_2nd_exec_ctrl &
265 SECONDARY_EXEC_ENABLE_EPT);
266 }
267
268 static inline int vm_need_ept(void)
269 {
270 return (cpu_has_vmx_ept() && enable_ept);
271 }
272
273 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
274 {
275 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
276 (irqchip_in_kernel(kvm)));
277 }
278
279 static inline int cpu_has_vmx_vpid(void)
280 {
281 return (vmcs_config.cpu_based_2nd_exec_ctrl &
282 SECONDARY_EXEC_ENABLE_VPID);
283 }
284
285 static inline int cpu_has_virtual_nmis(void)
286 {
287 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
288 }
289
290 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
291 {
292 int i;
293
294 for (i = 0; i < vmx->nmsrs; ++i)
295 if (vmx->guest_msrs[i].index == msr)
296 return i;
297 return -1;
298 }
299
300 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
301 {
302 struct {
303 u64 vpid : 16;
304 u64 rsvd : 48;
305 u64 gva;
306 } operand = { vpid, 0, gva };
307
308 asm volatile (__ex(ASM_VMX_INVVPID)
309 /* CF==1 or ZF==1 --> rc = -1 */
310 "; ja 1f ; ud2 ; 1:"
311 : : "a"(&operand), "c"(ext) : "cc", "memory");
312 }
313
314 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
315 {
316 struct {
317 u64 eptp, gpa;
318 } operand = {eptp, gpa};
319
320 asm volatile (__ex(ASM_VMX_INVEPT)
321 /* CF==1 or ZF==1 --> rc = -1 */
322 "; ja 1f ; ud2 ; 1:\n"
323 : : "a" (&operand), "c" (ext) : "cc", "memory");
324 }
325
326 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
327 {
328 int i;
329
330 i = __find_msr_index(vmx, msr);
331 if (i >= 0)
332 return &vmx->guest_msrs[i];
333 return NULL;
334 }
335
336 static void vmcs_clear(struct vmcs *vmcs)
337 {
338 u64 phys_addr = __pa(vmcs);
339 u8 error;
340
341 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
342 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
343 : "cc", "memory");
344 if (error)
345 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
346 vmcs, phys_addr);
347 }
348
349 static void __vcpu_clear(void *arg)
350 {
351 struct vcpu_vmx *vmx = arg;
352 int cpu = raw_smp_processor_id();
353
354 if (vmx->vcpu.cpu == cpu)
355 vmcs_clear(vmx->vmcs);
356 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
357 per_cpu(current_vmcs, cpu) = NULL;
358 rdtscll(vmx->vcpu.arch.host_tsc);
359 list_del(&vmx->local_vcpus_link);
360 vmx->vcpu.cpu = -1;
361 vmx->launched = 0;
362 }
363
364 static void vcpu_clear(struct vcpu_vmx *vmx)
365 {
366 if (vmx->vcpu.cpu == -1)
367 return;
368 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
369 }
370
371 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
372 {
373 if (vmx->vpid == 0)
374 return;
375
376 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
377 }
378
379 static inline void ept_sync_global(void)
380 {
381 if (cpu_has_vmx_invept_global())
382 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
383 }
384
385 static inline void ept_sync_context(u64 eptp)
386 {
387 if (vm_need_ept()) {
388 if (cpu_has_vmx_invept_context())
389 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
390 else
391 ept_sync_global();
392 }
393 }
394
395 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
396 {
397 if (vm_need_ept()) {
398 if (cpu_has_vmx_invept_individual_addr())
399 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
400 eptp, gpa);
401 else
402 ept_sync_context(eptp);
403 }
404 }
405
406 static unsigned long vmcs_readl(unsigned long field)
407 {
408 unsigned long value;
409
410 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
411 : "=a"(value) : "d"(field) : "cc");
412 return value;
413 }
414
415 static u16 vmcs_read16(unsigned long field)
416 {
417 return vmcs_readl(field);
418 }
419
420 static u32 vmcs_read32(unsigned long field)
421 {
422 return vmcs_readl(field);
423 }
424
425 static u64 vmcs_read64(unsigned long field)
426 {
427 #ifdef CONFIG_X86_64
428 return vmcs_readl(field);
429 #else
430 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
431 #endif
432 }
433
434 static noinline void vmwrite_error(unsigned long field, unsigned long value)
435 {
436 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
437 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
438 dump_stack();
439 }
440
441 static void vmcs_writel(unsigned long field, unsigned long value)
442 {
443 u8 error;
444
445 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
446 : "=q"(error) : "a"(value), "d"(field) : "cc");
447 if (unlikely(error))
448 vmwrite_error(field, value);
449 }
450
451 static void vmcs_write16(unsigned long field, u16 value)
452 {
453 vmcs_writel(field, value);
454 }
455
456 static void vmcs_write32(unsigned long field, u32 value)
457 {
458 vmcs_writel(field, value);
459 }
460
461 static void vmcs_write64(unsigned long field, u64 value)
462 {
463 vmcs_writel(field, value);
464 #ifndef CONFIG_X86_64
465 asm volatile ("");
466 vmcs_writel(field+1, value >> 32);
467 #endif
468 }
469
470 static void vmcs_clear_bits(unsigned long field, u32 mask)
471 {
472 vmcs_writel(field, vmcs_readl(field) & ~mask);
473 }
474
475 static void vmcs_set_bits(unsigned long field, u32 mask)
476 {
477 vmcs_writel(field, vmcs_readl(field) | mask);
478 }
479
480 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
481 {
482 u32 eb;
483
484 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
485 if (!vcpu->fpu_active)
486 eb |= 1u << NM_VECTOR;
487 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
488 if (vcpu->guest_debug &
489 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
490 eb |= 1u << DB_VECTOR;
491 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
492 eb |= 1u << BP_VECTOR;
493 }
494 if (vcpu->arch.rmode.active)
495 eb = ~0;
496 if (vm_need_ept())
497 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
498 vmcs_write32(EXCEPTION_BITMAP, eb);
499 }
500
501 static void reload_tss(void)
502 {
503 /*
504 * VT restores TR but not its size. Useless.
505 */
506 struct descriptor_table gdt;
507 struct desc_struct *descs;
508
509 kvm_get_gdt(&gdt);
510 descs = (void *)gdt.base;
511 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
512 load_TR_desc();
513 }
514
515 static void load_transition_efer(struct vcpu_vmx *vmx)
516 {
517 int efer_offset = vmx->msr_offset_efer;
518 u64 host_efer = vmx->host_msrs[efer_offset].data;
519 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
520 u64 ignore_bits;
521
522 if (efer_offset < 0)
523 return;
524 /*
525 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
526 * outside long mode
527 */
528 ignore_bits = EFER_NX | EFER_SCE;
529 #ifdef CONFIG_X86_64
530 ignore_bits |= EFER_LMA | EFER_LME;
531 /* SCE is meaningful only in long mode on Intel */
532 if (guest_efer & EFER_LMA)
533 ignore_bits &= ~(u64)EFER_SCE;
534 #endif
535 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
536 return;
537
538 vmx->host_state.guest_efer_loaded = 1;
539 guest_efer &= ~ignore_bits;
540 guest_efer |= host_efer & ignore_bits;
541 wrmsrl(MSR_EFER, guest_efer);
542 vmx->vcpu.stat.efer_reload++;
543 }
544
545 static void reload_host_efer(struct vcpu_vmx *vmx)
546 {
547 if (vmx->host_state.guest_efer_loaded) {
548 vmx->host_state.guest_efer_loaded = 0;
549 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
550 }
551 }
552
553 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
554 {
555 struct vcpu_vmx *vmx = to_vmx(vcpu);
556
557 if (vmx->host_state.loaded)
558 return;
559
560 vmx->host_state.loaded = 1;
561 /*
562 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
563 * allow segment selectors with cpl > 0 or ti == 1.
564 */
565 vmx->host_state.ldt_sel = kvm_read_ldt();
566 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
567 vmx->host_state.fs_sel = kvm_read_fs();
568 if (!(vmx->host_state.fs_sel & 7)) {
569 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
570 vmx->host_state.fs_reload_needed = 0;
571 } else {
572 vmcs_write16(HOST_FS_SELECTOR, 0);
573 vmx->host_state.fs_reload_needed = 1;
574 }
575 vmx->host_state.gs_sel = kvm_read_gs();
576 if (!(vmx->host_state.gs_sel & 7))
577 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
578 else {
579 vmcs_write16(HOST_GS_SELECTOR, 0);
580 vmx->host_state.gs_ldt_reload_needed = 1;
581 }
582
583 #ifdef CONFIG_X86_64
584 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
585 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
586 #else
587 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
588 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
589 #endif
590
591 #ifdef CONFIG_X86_64
592 if (is_long_mode(&vmx->vcpu))
593 save_msrs(vmx->host_msrs +
594 vmx->msr_offset_kernel_gs_base, 1);
595
596 #endif
597 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
598 load_transition_efer(vmx);
599 }
600
601 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
602 {
603 unsigned long flags;
604
605 if (!vmx->host_state.loaded)
606 return;
607
608 ++vmx->vcpu.stat.host_state_reload;
609 vmx->host_state.loaded = 0;
610 if (vmx->host_state.fs_reload_needed)
611 kvm_load_fs(vmx->host_state.fs_sel);
612 if (vmx->host_state.gs_ldt_reload_needed) {
613 kvm_load_ldt(vmx->host_state.ldt_sel);
614 /*
615 * If we have to reload gs, we must take care to
616 * preserve our gs base.
617 */
618 local_irq_save(flags);
619 kvm_load_gs(vmx->host_state.gs_sel);
620 #ifdef CONFIG_X86_64
621 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
622 #endif
623 local_irq_restore(flags);
624 }
625 reload_tss();
626 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
627 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
628 reload_host_efer(vmx);
629 }
630
631 static void vmx_load_host_state(struct vcpu_vmx *vmx)
632 {
633 preempt_disable();
634 __vmx_load_host_state(vmx);
635 preempt_enable();
636 }
637
638 /*
639 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
640 * vcpu mutex is already taken.
641 */
642 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
643 {
644 struct vcpu_vmx *vmx = to_vmx(vcpu);
645 u64 phys_addr = __pa(vmx->vmcs);
646 u64 tsc_this, delta, new_offset;
647
648 if (vcpu->cpu != cpu) {
649 vcpu_clear(vmx);
650 kvm_migrate_timers(vcpu);
651 vpid_sync_vcpu_all(vmx);
652 local_irq_disable();
653 list_add(&vmx->local_vcpus_link,
654 &per_cpu(vcpus_on_cpu, cpu));
655 local_irq_enable();
656 }
657
658 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
659 u8 error;
660
661 per_cpu(current_vmcs, cpu) = vmx->vmcs;
662 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
663 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
664 : "cc");
665 if (error)
666 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
667 vmx->vmcs, phys_addr);
668 }
669
670 if (vcpu->cpu != cpu) {
671 struct descriptor_table dt;
672 unsigned long sysenter_esp;
673
674 vcpu->cpu = cpu;
675 /*
676 * Linux uses per-cpu TSS and GDT, so set these when switching
677 * processors.
678 */
679 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
680 kvm_get_gdt(&dt);
681 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
682
683 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
684 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
685
686 /*
687 * Make sure the time stamp counter is monotonous.
688 */
689 rdtscll(tsc_this);
690 if (tsc_this < vcpu->arch.host_tsc) {
691 delta = vcpu->arch.host_tsc - tsc_this;
692 new_offset = vmcs_read64(TSC_OFFSET) + delta;
693 vmcs_write64(TSC_OFFSET, new_offset);
694 }
695 }
696 }
697
698 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
699 {
700 __vmx_load_host_state(to_vmx(vcpu));
701 }
702
703 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
704 {
705 if (vcpu->fpu_active)
706 return;
707 vcpu->fpu_active = 1;
708 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
709 if (vcpu->arch.cr0 & X86_CR0_TS)
710 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
711 update_exception_bitmap(vcpu);
712 }
713
714 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
715 {
716 if (!vcpu->fpu_active)
717 return;
718 vcpu->fpu_active = 0;
719 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
720 update_exception_bitmap(vcpu);
721 }
722
723 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
724 {
725 return vmcs_readl(GUEST_RFLAGS);
726 }
727
728 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
729 {
730 if (vcpu->arch.rmode.active)
731 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
732 vmcs_writel(GUEST_RFLAGS, rflags);
733 }
734
735 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
736 {
737 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
738 int ret = 0;
739
740 if (interruptibility & GUEST_INTR_STATE_STI)
741 ret |= X86_SHADOW_INT_STI;
742 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
743 ret |= X86_SHADOW_INT_MOV_SS;
744
745 return ret & mask;
746 }
747
748 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
749 {
750 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
751 u32 interruptibility = interruptibility_old;
752
753 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
754
755 if (mask & X86_SHADOW_INT_MOV_SS)
756 interruptibility |= GUEST_INTR_STATE_MOV_SS;
757 if (mask & X86_SHADOW_INT_STI)
758 interruptibility |= GUEST_INTR_STATE_STI;
759
760 if ((interruptibility != interruptibility_old))
761 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
762 }
763
764 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
765 {
766 unsigned long rip;
767
768 rip = kvm_rip_read(vcpu);
769 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
770 kvm_rip_write(vcpu, rip);
771
772 /* skipping an emulated instruction also counts */
773 vmx_set_interrupt_shadow(vcpu, 0);
774 vcpu->arch.interrupt_window_open = 1;
775 }
776
777 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
778 bool has_error_code, u32 error_code)
779 {
780 struct vcpu_vmx *vmx = to_vmx(vcpu);
781 u32 intr_info = nr | INTR_INFO_VALID_MASK;
782
783 if (has_error_code) {
784 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
785 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
786 }
787
788 if (vcpu->arch.rmode.active) {
789 vmx->rmode.irq.pending = true;
790 vmx->rmode.irq.vector = nr;
791 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
792 if (nr == BP_VECTOR || nr == OF_VECTOR)
793 vmx->rmode.irq.rip++;
794 intr_info |= INTR_TYPE_SOFT_INTR;
795 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
796 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
797 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
798 return;
799 }
800
801 if (nr == BP_VECTOR || nr == OF_VECTOR) {
802 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
803 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
804 } else
805 intr_info |= INTR_TYPE_HARD_EXCEPTION;
806
807 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
808 }
809
810 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
811 {
812 return false;
813 }
814
815 /*
816 * Swap MSR entry in host/guest MSR entry array.
817 */
818 #ifdef CONFIG_X86_64
819 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
820 {
821 struct kvm_msr_entry tmp;
822
823 tmp = vmx->guest_msrs[to];
824 vmx->guest_msrs[to] = vmx->guest_msrs[from];
825 vmx->guest_msrs[from] = tmp;
826 tmp = vmx->host_msrs[to];
827 vmx->host_msrs[to] = vmx->host_msrs[from];
828 vmx->host_msrs[from] = tmp;
829 }
830 #endif
831
832 /*
833 * Set up the vmcs to automatically save and restore system
834 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
835 * mode, as fiddling with msrs is very expensive.
836 */
837 static void setup_msrs(struct vcpu_vmx *vmx)
838 {
839 int save_nmsrs;
840
841 vmx_load_host_state(vmx);
842 save_nmsrs = 0;
843 #ifdef CONFIG_X86_64
844 if (is_long_mode(&vmx->vcpu)) {
845 int index;
846
847 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
848 if (index >= 0)
849 move_msr_up(vmx, index, save_nmsrs++);
850 index = __find_msr_index(vmx, MSR_LSTAR);
851 if (index >= 0)
852 move_msr_up(vmx, index, save_nmsrs++);
853 index = __find_msr_index(vmx, MSR_CSTAR);
854 if (index >= 0)
855 move_msr_up(vmx, index, save_nmsrs++);
856 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
857 if (index >= 0)
858 move_msr_up(vmx, index, save_nmsrs++);
859 /*
860 * MSR_K6_STAR is only needed on long mode guests, and only
861 * if efer.sce is enabled.
862 */
863 index = __find_msr_index(vmx, MSR_K6_STAR);
864 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
865 move_msr_up(vmx, index, save_nmsrs++);
866 }
867 #endif
868 vmx->save_nmsrs = save_nmsrs;
869
870 #ifdef CONFIG_X86_64
871 vmx->msr_offset_kernel_gs_base =
872 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
873 #endif
874 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
875 }
876
877 /*
878 * reads and returns guest's timestamp counter "register"
879 * guest_tsc = host_tsc + tsc_offset -- 21.3
880 */
881 static u64 guest_read_tsc(void)
882 {
883 u64 host_tsc, tsc_offset;
884
885 rdtscll(host_tsc);
886 tsc_offset = vmcs_read64(TSC_OFFSET);
887 return host_tsc + tsc_offset;
888 }
889
890 /*
891 * writes 'guest_tsc' into guest's timestamp counter "register"
892 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
893 */
894 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
895 {
896 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
897 }
898
899 /*
900 * Reads an msr value (of 'msr_index') into 'pdata'.
901 * Returns 0 on success, non-0 otherwise.
902 * Assumes vcpu_load() was already called.
903 */
904 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
905 {
906 u64 data;
907 struct kvm_msr_entry *msr;
908
909 if (!pdata) {
910 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
911 return -EINVAL;
912 }
913
914 switch (msr_index) {
915 #ifdef CONFIG_X86_64
916 case MSR_FS_BASE:
917 data = vmcs_readl(GUEST_FS_BASE);
918 break;
919 case MSR_GS_BASE:
920 data = vmcs_readl(GUEST_GS_BASE);
921 break;
922 case MSR_EFER:
923 return kvm_get_msr_common(vcpu, msr_index, pdata);
924 #endif
925 case MSR_IA32_TIME_STAMP_COUNTER:
926 data = guest_read_tsc();
927 break;
928 case MSR_IA32_SYSENTER_CS:
929 data = vmcs_read32(GUEST_SYSENTER_CS);
930 break;
931 case MSR_IA32_SYSENTER_EIP:
932 data = vmcs_readl(GUEST_SYSENTER_EIP);
933 break;
934 case MSR_IA32_SYSENTER_ESP:
935 data = vmcs_readl(GUEST_SYSENTER_ESP);
936 break;
937 default:
938 vmx_load_host_state(to_vmx(vcpu));
939 msr = find_msr_entry(to_vmx(vcpu), msr_index);
940 if (msr) {
941 data = msr->data;
942 break;
943 }
944 return kvm_get_msr_common(vcpu, msr_index, pdata);
945 }
946
947 *pdata = data;
948 return 0;
949 }
950
951 /*
952 * Writes msr value into into the appropriate "register".
953 * Returns 0 on success, non-0 otherwise.
954 * Assumes vcpu_load() was already called.
955 */
956 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
957 {
958 struct vcpu_vmx *vmx = to_vmx(vcpu);
959 struct kvm_msr_entry *msr;
960 u64 host_tsc;
961 int ret = 0;
962
963 switch (msr_index) {
964 case MSR_EFER:
965 vmx_load_host_state(vmx);
966 ret = kvm_set_msr_common(vcpu, msr_index, data);
967 break;
968 #ifdef CONFIG_X86_64
969 case MSR_FS_BASE:
970 vmcs_writel(GUEST_FS_BASE, data);
971 break;
972 case MSR_GS_BASE:
973 vmcs_writel(GUEST_GS_BASE, data);
974 break;
975 #endif
976 case MSR_IA32_SYSENTER_CS:
977 vmcs_write32(GUEST_SYSENTER_CS, data);
978 break;
979 case MSR_IA32_SYSENTER_EIP:
980 vmcs_writel(GUEST_SYSENTER_EIP, data);
981 break;
982 case MSR_IA32_SYSENTER_ESP:
983 vmcs_writel(GUEST_SYSENTER_ESP, data);
984 break;
985 case MSR_IA32_TIME_STAMP_COUNTER:
986 rdtscll(host_tsc);
987 guest_write_tsc(data, host_tsc);
988 break;
989 case MSR_P6_PERFCTR0:
990 case MSR_P6_PERFCTR1:
991 case MSR_P6_EVNTSEL0:
992 case MSR_P6_EVNTSEL1:
993 /*
994 * Just discard all writes to the performance counters; this
995 * should keep both older linux and windows 64-bit guests
996 * happy
997 */
998 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
999
1000 break;
1001 case MSR_IA32_CR_PAT:
1002 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1003 vmcs_write64(GUEST_IA32_PAT, data);
1004 vcpu->arch.pat = data;
1005 break;
1006 }
1007 /* Otherwise falls through to kvm_set_msr_common */
1008 default:
1009 vmx_load_host_state(vmx);
1010 msr = find_msr_entry(vmx, msr_index);
1011 if (msr) {
1012 msr->data = data;
1013 break;
1014 }
1015 ret = kvm_set_msr_common(vcpu, msr_index, data);
1016 }
1017
1018 return ret;
1019 }
1020
1021 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1022 {
1023 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1024 switch (reg) {
1025 case VCPU_REGS_RSP:
1026 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1027 break;
1028 case VCPU_REGS_RIP:
1029 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1030 break;
1031 default:
1032 break;
1033 }
1034 }
1035
1036 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1037 {
1038 int old_debug = vcpu->guest_debug;
1039 unsigned long flags;
1040
1041 vcpu->guest_debug = dbg->control;
1042 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1043 vcpu->guest_debug = 0;
1044
1045 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1046 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1047 else
1048 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1049
1050 flags = vmcs_readl(GUEST_RFLAGS);
1051 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1052 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1053 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1054 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1055 vmcs_writel(GUEST_RFLAGS, flags);
1056
1057 update_exception_bitmap(vcpu);
1058
1059 return 0;
1060 }
1061
1062 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1063 {
1064 if (!vcpu->arch.interrupt.pending)
1065 return -1;
1066 return vcpu->arch.interrupt.nr;
1067 }
1068
1069 static __init int cpu_has_kvm_support(void)
1070 {
1071 return cpu_has_vmx();
1072 }
1073
1074 static __init int vmx_disabled_by_bios(void)
1075 {
1076 u64 msr;
1077
1078 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1079 return (msr & (FEATURE_CONTROL_LOCKED |
1080 FEATURE_CONTROL_VMXON_ENABLED))
1081 == FEATURE_CONTROL_LOCKED;
1082 /* locked but not enabled */
1083 }
1084
1085 static void hardware_enable(void *garbage)
1086 {
1087 int cpu = raw_smp_processor_id();
1088 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1089 u64 old;
1090
1091 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1092 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1093 if ((old & (FEATURE_CONTROL_LOCKED |
1094 FEATURE_CONTROL_VMXON_ENABLED))
1095 != (FEATURE_CONTROL_LOCKED |
1096 FEATURE_CONTROL_VMXON_ENABLED))
1097 /* enable and lock */
1098 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1099 FEATURE_CONTROL_LOCKED |
1100 FEATURE_CONTROL_VMXON_ENABLED);
1101 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1102 asm volatile (ASM_VMX_VMXON_RAX
1103 : : "a"(&phys_addr), "m"(phys_addr)
1104 : "memory", "cc");
1105 }
1106
1107 static void vmclear_local_vcpus(void)
1108 {
1109 int cpu = raw_smp_processor_id();
1110 struct vcpu_vmx *vmx, *n;
1111
1112 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1113 local_vcpus_link)
1114 __vcpu_clear(vmx);
1115 }
1116
1117
1118 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1119 * tricks.
1120 */
1121 static void kvm_cpu_vmxoff(void)
1122 {
1123 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1124 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1125 }
1126
1127 static void hardware_disable(void *garbage)
1128 {
1129 vmclear_local_vcpus();
1130 kvm_cpu_vmxoff();
1131 }
1132
1133 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1134 u32 msr, u32 *result)
1135 {
1136 u32 vmx_msr_low, vmx_msr_high;
1137 u32 ctl = ctl_min | ctl_opt;
1138
1139 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1140
1141 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1142 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1143
1144 /* Ensure minimum (required) set of control bits are supported. */
1145 if (ctl_min & ~ctl)
1146 return -EIO;
1147
1148 *result = ctl;
1149 return 0;
1150 }
1151
1152 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1153 {
1154 u32 vmx_msr_low, vmx_msr_high;
1155 u32 min, opt, min2, opt2;
1156 u32 _pin_based_exec_control = 0;
1157 u32 _cpu_based_exec_control = 0;
1158 u32 _cpu_based_2nd_exec_control = 0;
1159 u32 _vmexit_control = 0;
1160 u32 _vmentry_control = 0;
1161
1162 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1163 opt = PIN_BASED_VIRTUAL_NMIS;
1164 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1165 &_pin_based_exec_control) < 0)
1166 return -EIO;
1167
1168 min = CPU_BASED_HLT_EXITING |
1169 #ifdef CONFIG_X86_64
1170 CPU_BASED_CR8_LOAD_EXITING |
1171 CPU_BASED_CR8_STORE_EXITING |
1172 #endif
1173 CPU_BASED_CR3_LOAD_EXITING |
1174 CPU_BASED_CR3_STORE_EXITING |
1175 CPU_BASED_USE_IO_BITMAPS |
1176 CPU_BASED_MOV_DR_EXITING |
1177 CPU_BASED_USE_TSC_OFFSETING |
1178 CPU_BASED_INVLPG_EXITING;
1179 opt = CPU_BASED_TPR_SHADOW |
1180 CPU_BASED_USE_MSR_BITMAPS |
1181 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1182 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1183 &_cpu_based_exec_control) < 0)
1184 return -EIO;
1185 #ifdef CONFIG_X86_64
1186 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1187 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1188 ~CPU_BASED_CR8_STORE_EXITING;
1189 #endif
1190 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1191 min2 = 0;
1192 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1193 SECONDARY_EXEC_WBINVD_EXITING |
1194 SECONDARY_EXEC_ENABLE_VPID |
1195 SECONDARY_EXEC_ENABLE_EPT;
1196 if (adjust_vmx_controls(min2, opt2,
1197 MSR_IA32_VMX_PROCBASED_CTLS2,
1198 &_cpu_based_2nd_exec_control) < 0)
1199 return -EIO;
1200 }
1201 #ifndef CONFIG_X86_64
1202 if (!(_cpu_based_2nd_exec_control &
1203 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1204 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1205 #endif
1206 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1207 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1208 enabled */
1209 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1210 CPU_BASED_CR3_STORE_EXITING |
1211 CPU_BASED_INVLPG_EXITING);
1212 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1213 &_cpu_based_exec_control) < 0)
1214 return -EIO;
1215 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1216 vmx_capability.ept, vmx_capability.vpid);
1217 }
1218
1219 min = 0;
1220 #ifdef CONFIG_X86_64
1221 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1222 #endif
1223 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1224 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1225 &_vmexit_control) < 0)
1226 return -EIO;
1227
1228 min = 0;
1229 opt = VM_ENTRY_LOAD_IA32_PAT;
1230 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1231 &_vmentry_control) < 0)
1232 return -EIO;
1233
1234 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1235
1236 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1237 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1238 return -EIO;
1239
1240 #ifdef CONFIG_X86_64
1241 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1242 if (vmx_msr_high & (1u<<16))
1243 return -EIO;
1244 #endif
1245
1246 /* Require Write-Back (WB) memory type for VMCS accesses. */
1247 if (((vmx_msr_high >> 18) & 15) != 6)
1248 return -EIO;
1249
1250 vmcs_conf->size = vmx_msr_high & 0x1fff;
1251 vmcs_conf->order = get_order(vmcs_config.size);
1252 vmcs_conf->revision_id = vmx_msr_low;
1253
1254 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1255 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1256 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1257 vmcs_conf->vmexit_ctrl = _vmexit_control;
1258 vmcs_conf->vmentry_ctrl = _vmentry_control;
1259
1260 return 0;
1261 }
1262
1263 static struct vmcs *alloc_vmcs_cpu(int cpu)
1264 {
1265 int node = cpu_to_node(cpu);
1266 struct page *pages;
1267 struct vmcs *vmcs;
1268
1269 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1270 if (!pages)
1271 return NULL;
1272 vmcs = page_address(pages);
1273 memset(vmcs, 0, vmcs_config.size);
1274 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1275 return vmcs;
1276 }
1277
1278 static struct vmcs *alloc_vmcs(void)
1279 {
1280 return alloc_vmcs_cpu(raw_smp_processor_id());
1281 }
1282
1283 static void free_vmcs(struct vmcs *vmcs)
1284 {
1285 free_pages((unsigned long)vmcs, vmcs_config.order);
1286 }
1287
1288 static void free_kvm_area(void)
1289 {
1290 int cpu;
1291
1292 for_each_online_cpu(cpu)
1293 free_vmcs(per_cpu(vmxarea, cpu));
1294 }
1295
1296 static __init int alloc_kvm_area(void)
1297 {
1298 int cpu;
1299
1300 for_each_online_cpu(cpu) {
1301 struct vmcs *vmcs;
1302
1303 vmcs = alloc_vmcs_cpu(cpu);
1304 if (!vmcs) {
1305 free_kvm_area();
1306 return -ENOMEM;
1307 }
1308
1309 per_cpu(vmxarea, cpu) = vmcs;
1310 }
1311 return 0;
1312 }
1313
1314 static __init int hardware_setup(void)
1315 {
1316 if (setup_vmcs_config(&vmcs_config) < 0)
1317 return -EIO;
1318
1319 if (boot_cpu_has(X86_FEATURE_NX))
1320 kvm_enable_efer_bits(EFER_NX);
1321
1322 return alloc_kvm_area();
1323 }
1324
1325 static __exit void hardware_unsetup(void)
1326 {
1327 free_kvm_area();
1328 }
1329
1330 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1331 {
1332 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1333
1334 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1335 vmcs_write16(sf->selector, save->selector);
1336 vmcs_writel(sf->base, save->base);
1337 vmcs_write32(sf->limit, save->limit);
1338 vmcs_write32(sf->ar_bytes, save->ar);
1339 } else {
1340 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1341 << AR_DPL_SHIFT;
1342 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1343 }
1344 }
1345
1346 static void enter_pmode(struct kvm_vcpu *vcpu)
1347 {
1348 unsigned long flags;
1349 struct vcpu_vmx *vmx = to_vmx(vcpu);
1350
1351 vmx->emulation_required = 1;
1352 vcpu->arch.rmode.active = 0;
1353
1354 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1355 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1356 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1357
1358 flags = vmcs_readl(GUEST_RFLAGS);
1359 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1360 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1361 vmcs_writel(GUEST_RFLAGS, flags);
1362
1363 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1364 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1365
1366 update_exception_bitmap(vcpu);
1367
1368 if (emulate_invalid_guest_state)
1369 return;
1370
1371 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1372 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1373 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1374 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1375
1376 vmcs_write16(GUEST_SS_SELECTOR, 0);
1377 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1378
1379 vmcs_write16(GUEST_CS_SELECTOR,
1380 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1381 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1382 }
1383
1384 static gva_t rmode_tss_base(struct kvm *kvm)
1385 {
1386 if (!kvm->arch.tss_addr) {
1387 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1388 kvm->memslots[0].npages - 3;
1389 return base_gfn << PAGE_SHIFT;
1390 }
1391 return kvm->arch.tss_addr;
1392 }
1393
1394 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1395 {
1396 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1397
1398 save->selector = vmcs_read16(sf->selector);
1399 save->base = vmcs_readl(sf->base);
1400 save->limit = vmcs_read32(sf->limit);
1401 save->ar = vmcs_read32(sf->ar_bytes);
1402 vmcs_write16(sf->selector, save->base >> 4);
1403 vmcs_write32(sf->base, save->base & 0xfffff);
1404 vmcs_write32(sf->limit, 0xffff);
1405 vmcs_write32(sf->ar_bytes, 0xf3);
1406 }
1407
1408 static void enter_rmode(struct kvm_vcpu *vcpu)
1409 {
1410 unsigned long flags;
1411 struct vcpu_vmx *vmx = to_vmx(vcpu);
1412
1413 vmx->emulation_required = 1;
1414 vcpu->arch.rmode.active = 1;
1415
1416 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1417 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1418
1419 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1420 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1421
1422 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1423 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1424
1425 flags = vmcs_readl(GUEST_RFLAGS);
1426 vcpu->arch.rmode.save_iopl
1427 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1428
1429 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1430
1431 vmcs_writel(GUEST_RFLAGS, flags);
1432 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1433 update_exception_bitmap(vcpu);
1434
1435 if (emulate_invalid_guest_state)
1436 goto continue_rmode;
1437
1438 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1439 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1440 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1441
1442 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1443 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1444 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1445 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1446 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1447
1448 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1449 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1450 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1451 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1452
1453 continue_rmode:
1454 kvm_mmu_reset_context(vcpu);
1455 init_rmode(vcpu->kvm);
1456 }
1457
1458 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1459 {
1460 struct vcpu_vmx *vmx = to_vmx(vcpu);
1461 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1462
1463 vcpu->arch.shadow_efer = efer;
1464 if (!msr)
1465 return;
1466 if (efer & EFER_LMA) {
1467 vmcs_write32(VM_ENTRY_CONTROLS,
1468 vmcs_read32(VM_ENTRY_CONTROLS) |
1469 VM_ENTRY_IA32E_MODE);
1470 msr->data = efer;
1471 } else {
1472 vmcs_write32(VM_ENTRY_CONTROLS,
1473 vmcs_read32(VM_ENTRY_CONTROLS) &
1474 ~VM_ENTRY_IA32E_MODE);
1475
1476 msr->data = efer & ~EFER_LME;
1477 }
1478 setup_msrs(vmx);
1479 }
1480
1481 #ifdef CONFIG_X86_64
1482
1483 static void enter_lmode(struct kvm_vcpu *vcpu)
1484 {
1485 u32 guest_tr_ar;
1486
1487 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1488 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1489 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1490 __func__);
1491 vmcs_write32(GUEST_TR_AR_BYTES,
1492 (guest_tr_ar & ~AR_TYPE_MASK)
1493 | AR_TYPE_BUSY_64_TSS);
1494 }
1495 vcpu->arch.shadow_efer |= EFER_LMA;
1496 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1497 }
1498
1499 static void exit_lmode(struct kvm_vcpu *vcpu)
1500 {
1501 vcpu->arch.shadow_efer &= ~EFER_LMA;
1502
1503 vmcs_write32(VM_ENTRY_CONTROLS,
1504 vmcs_read32(VM_ENTRY_CONTROLS)
1505 & ~VM_ENTRY_IA32E_MODE);
1506 }
1507
1508 #endif
1509
1510 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1511 {
1512 vpid_sync_vcpu_all(to_vmx(vcpu));
1513 if (vm_need_ept())
1514 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1515 }
1516
1517 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1518 {
1519 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1520 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1521 }
1522
1523 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1524 {
1525 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1526 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1527 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1528 return;
1529 }
1530 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1531 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1532 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1533 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1534 }
1535 }
1536
1537 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1538
1539 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1540 unsigned long cr0,
1541 struct kvm_vcpu *vcpu)
1542 {
1543 if (!(cr0 & X86_CR0_PG)) {
1544 /* From paging/starting to nonpaging */
1545 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1546 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1547 (CPU_BASED_CR3_LOAD_EXITING |
1548 CPU_BASED_CR3_STORE_EXITING));
1549 vcpu->arch.cr0 = cr0;
1550 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1551 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1552 *hw_cr0 &= ~X86_CR0_WP;
1553 } else if (!is_paging(vcpu)) {
1554 /* From nonpaging to paging */
1555 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1556 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1557 ~(CPU_BASED_CR3_LOAD_EXITING |
1558 CPU_BASED_CR3_STORE_EXITING));
1559 vcpu->arch.cr0 = cr0;
1560 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1561 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1562 *hw_cr0 &= ~X86_CR0_WP;
1563 }
1564 }
1565
1566 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1567 struct kvm_vcpu *vcpu)
1568 {
1569 if (!is_paging(vcpu)) {
1570 *hw_cr4 &= ~X86_CR4_PAE;
1571 *hw_cr4 |= X86_CR4_PSE;
1572 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1573 *hw_cr4 &= ~X86_CR4_PAE;
1574 }
1575
1576 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1577 {
1578 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1579 KVM_VM_CR0_ALWAYS_ON;
1580
1581 vmx_fpu_deactivate(vcpu);
1582
1583 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1584 enter_pmode(vcpu);
1585
1586 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1587 enter_rmode(vcpu);
1588
1589 #ifdef CONFIG_X86_64
1590 if (vcpu->arch.shadow_efer & EFER_LME) {
1591 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1592 enter_lmode(vcpu);
1593 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1594 exit_lmode(vcpu);
1595 }
1596 #endif
1597
1598 if (vm_need_ept())
1599 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1600
1601 vmcs_writel(CR0_READ_SHADOW, cr0);
1602 vmcs_writel(GUEST_CR0, hw_cr0);
1603 vcpu->arch.cr0 = cr0;
1604
1605 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1606 vmx_fpu_activate(vcpu);
1607 }
1608
1609 static u64 construct_eptp(unsigned long root_hpa)
1610 {
1611 u64 eptp;
1612
1613 /* TODO write the value reading from MSR */
1614 eptp = VMX_EPT_DEFAULT_MT |
1615 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1616 eptp |= (root_hpa & PAGE_MASK);
1617
1618 return eptp;
1619 }
1620
1621 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1622 {
1623 unsigned long guest_cr3;
1624 u64 eptp;
1625
1626 guest_cr3 = cr3;
1627 if (vm_need_ept()) {
1628 eptp = construct_eptp(cr3);
1629 vmcs_write64(EPT_POINTER, eptp);
1630 ept_sync_context(eptp);
1631 ept_load_pdptrs(vcpu);
1632 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1633 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1634 }
1635
1636 vmx_flush_tlb(vcpu);
1637 vmcs_writel(GUEST_CR3, guest_cr3);
1638 if (vcpu->arch.cr0 & X86_CR0_PE)
1639 vmx_fpu_deactivate(vcpu);
1640 }
1641
1642 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1643 {
1644 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1645 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1646
1647 vcpu->arch.cr4 = cr4;
1648 if (vm_need_ept())
1649 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1650
1651 vmcs_writel(CR4_READ_SHADOW, cr4);
1652 vmcs_writel(GUEST_CR4, hw_cr4);
1653 }
1654
1655 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1656 {
1657 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1658
1659 return vmcs_readl(sf->base);
1660 }
1661
1662 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1663 struct kvm_segment *var, int seg)
1664 {
1665 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1666 u32 ar;
1667
1668 var->base = vmcs_readl(sf->base);
1669 var->limit = vmcs_read32(sf->limit);
1670 var->selector = vmcs_read16(sf->selector);
1671 ar = vmcs_read32(sf->ar_bytes);
1672 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1673 ar = 0;
1674 var->type = ar & 15;
1675 var->s = (ar >> 4) & 1;
1676 var->dpl = (ar >> 5) & 3;
1677 var->present = (ar >> 7) & 1;
1678 var->avl = (ar >> 12) & 1;
1679 var->l = (ar >> 13) & 1;
1680 var->db = (ar >> 14) & 1;
1681 var->g = (ar >> 15) & 1;
1682 var->unusable = (ar >> 16) & 1;
1683 }
1684
1685 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1686 {
1687 struct kvm_segment kvm_seg;
1688
1689 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1690 return 0;
1691
1692 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1693 return 3;
1694
1695 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1696 return kvm_seg.selector & 3;
1697 }
1698
1699 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1700 {
1701 u32 ar;
1702
1703 if (var->unusable)
1704 ar = 1 << 16;
1705 else {
1706 ar = var->type & 15;
1707 ar |= (var->s & 1) << 4;
1708 ar |= (var->dpl & 3) << 5;
1709 ar |= (var->present & 1) << 7;
1710 ar |= (var->avl & 1) << 12;
1711 ar |= (var->l & 1) << 13;
1712 ar |= (var->db & 1) << 14;
1713 ar |= (var->g & 1) << 15;
1714 }
1715 if (ar == 0) /* a 0 value means unusable */
1716 ar = AR_UNUSABLE_MASK;
1717
1718 return ar;
1719 }
1720
1721 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1722 struct kvm_segment *var, int seg)
1723 {
1724 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1725 u32 ar;
1726
1727 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1728 vcpu->arch.rmode.tr.selector = var->selector;
1729 vcpu->arch.rmode.tr.base = var->base;
1730 vcpu->arch.rmode.tr.limit = var->limit;
1731 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1732 return;
1733 }
1734 vmcs_writel(sf->base, var->base);
1735 vmcs_write32(sf->limit, var->limit);
1736 vmcs_write16(sf->selector, var->selector);
1737 if (vcpu->arch.rmode.active && var->s) {
1738 /*
1739 * Hack real-mode segments into vm86 compatibility.
1740 */
1741 if (var->base == 0xffff0000 && var->selector == 0xf000)
1742 vmcs_writel(sf->base, 0xf0000);
1743 ar = 0xf3;
1744 } else
1745 ar = vmx_segment_access_rights(var);
1746 vmcs_write32(sf->ar_bytes, ar);
1747 }
1748
1749 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1750 {
1751 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1752
1753 *db = (ar >> 14) & 1;
1754 *l = (ar >> 13) & 1;
1755 }
1756
1757 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1758 {
1759 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1760 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1761 }
1762
1763 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1764 {
1765 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1766 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1767 }
1768
1769 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1770 {
1771 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1772 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1773 }
1774
1775 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1776 {
1777 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1778 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1779 }
1780
1781 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1782 {
1783 struct kvm_segment var;
1784 u32 ar;
1785
1786 vmx_get_segment(vcpu, &var, seg);
1787 ar = vmx_segment_access_rights(&var);
1788
1789 if (var.base != (var.selector << 4))
1790 return false;
1791 if (var.limit != 0xffff)
1792 return false;
1793 if (ar != 0xf3)
1794 return false;
1795
1796 return true;
1797 }
1798
1799 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1800 {
1801 struct kvm_segment cs;
1802 unsigned int cs_rpl;
1803
1804 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1805 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1806
1807 if (cs.unusable)
1808 return false;
1809 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1810 return false;
1811 if (!cs.s)
1812 return false;
1813 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1814 if (cs.dpl > cs_rpl)
1815 return false;
1816 } else {
1817 if (cs.dpl != cs_rpl)
1818 return false;
1819 }
1820 if (!cs.present)
1821 return false;
1822
1823 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1824 return true;
1825 }
1826
1827 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1828 {
1829 struct kvm_segment ss;
1830 unsigned int ss_rpl;
1831
1832 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1833 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1834
1835 if (ss.unusable)
1836 return true;
1837 if (ss.type != 3 && ss.type != 7)
1838 return false;
1839 if (!ss.s)
1840 return false;
1841 if (ss.dpl != ss_rpl) /* DPL != RPL */
1842 return false;
1843 if (!ss.present)
1844 return false;
1845
1846 return true;
1847 }
1848
1849 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1850 {
1851 struct kvm_segment var;
1852 unsigned int rpl;
1853
1854 vmx_get_segment(vcpu, &var, seg);
1855 rpl = var.selector & SELECTOR_RPL_MASK;
1856
1857 if (var.unusable)
1858 return true;
1859 if (!var.s)
1860 return false;
1861 if (!var.present)
1862 return false;
1863 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1864 if (var.dpl < rpl) /* DPL < RPL */
1865 return false;
1866 }
1867
1868 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1869 * rights flags
1870 */
1871 return true;
1872 }
1873
1874 static bool tr_valid(struct kvm_vcpu *vcpu)
1875 {
1876 struct kvm_segment tr;
1877
1878 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1879
1880 if (tr.unusable)
1881 return false;
1882 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1883 return false;
1884 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1885 return false;
1886 if (!tr.present)
1887 return false;
1888
1889 return true;
1890 }
1891
1892 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1893 {
1894 struct kvm_segment ldtr;
1895
1896 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1897
1898 if (ldtr.unusable)
1899 return true;
1900 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1901 return false;
1902 if (ldtr.type != 2)
1903 return false;
1904 if (!ldtr.present)
1905 return false;
1906
1907 return true;
1908 }
1909
1910 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1911 {
1912 struct kvm_segment cs, ss;
1913
1914 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1915 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1916
1917 return ((cs.selector & SELECTOR_RPL_MASK) ==
1918 (ss.selector & SELECTOR_RPL_MASK));
1919 }
1920
1921 /*
1922 * Check if guest state is valid. Returns true if valid, false if
1923 * not.
1924 * We assume that registers are always usable
1925 */
1926 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1927 {
1928 /* real mode guest state checks */
1929 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1930 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1931 return false;
1932 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1933 return false;
1934 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1935 return false;
1936 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1937 return false;
1938 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1939 return false;
1940 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1941 return false;
1942 } else {
1943 /* protected mode guest state checks */
1944 if (!cs_ss_rpl_check(vcpu))
1945 return false;
1946 if (!code_segment_valid(vcpu))
1947 return false;
1948 if (!stack_segment_valid(vcpu))
1949 return false;
1950 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1951 return false;
1952 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1953 return false;
1954 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1955 return false;
1956 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1957 return false;
1958 if (!tr_valid(vcpu))
1959 return false;
1960 if (!ldtr_valid(vcpu))
1961 return false;
1962 }
1963 /* TODO:
1964 * - Add checks on RIP
1965 * - Add checks on RFLAGS
1966 */
1967
1968 return true;
1969 }
1970
1971 static int init_rmode_tss(struct kvm *kvm)
1972 {
1973 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1974 u16 data = 0;
1975 int ret = 0;
1976 int r;
1977
1978 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1979 if (r < 0)
1980 goto out;
1981 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1982 r = kvm_write_guest_page(kvm, fn++, &data,
1983 TSS_IOPB_BASE_OFFSET, sizeof(u16));
1984 if (r < 0)
1985 goto out;
1986 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1987 if (r < 0)
1988 goto out;
1989 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1990 if (r < 0)
1991 goto out;
1992 data = ~0;
1993 r = kvm_write_guest_page(kvm, fn, &data,
1994 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1995 sizeof(u8));
1996 if (r < 0)
1997 goto out;
1998
1999 ret = 1;
2000 out:
2001 return ret;
2002 }
2003
2004 static int init_rmode_identity_map(struct kvm *kvm)
2005 {
2006 int i, r, ret;
2007 pfn_t identity_map_pfn;
2008 u32 tmp;
2009
2010 if (!vm_need_ept())
2011 return 1;
2012 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2013 printk(KERN_ERR "EPT: identity-mapping pagetable "
2014 "haven't been allocated!\n");
2015 return 0;
2016 }
2017 if (likely(kvm->arch.ept_identity_pagetable_done))
2018 return 1;
2019 ret = 0;
2020 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2021 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2022 if (r < 0)
2023 goto out;
2024 /* Set up identity-mapping pagetable for EPT in real mode */
2025 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2026 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2027 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2028 r = kvm_write_guest_page(kvm, identity_map_pfn,
2029 &tmp, i * sizeof(tmp), sizeof(tmp));
2030 if (r < 0)
2031 goto out;
2032 }
2033 kvm->arch.ept_identity_pagetable_done = true;
2034 ret = 1;
2035 out:
2036 return ret;
2037 }
2038
2039 static void seg_setup(int seg)
2040 {
2041 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2042
2043 vmcs_write16(sf->selector, 0);
2044 vmcs_writel(sf->base, 0);
2045 vmcs_write32(sf->limit, 0xffff);
2046 vmcs_write32(sf->ar_bytes, 0xf3);
2047 }
2048
2049 static int alloc_apic_access_page(struct kvm *kvm)
2050 {
2051 struct kvm_userspace_memory_region kvm_userspace_mem;
2052 int r = 0;
2053
2054 down_write(&kvm->slots_lock);
2055 if (kvm->arch.apic_access_page)
2056 goto out;
2057 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2058 kvm_userspace_mem.flags = 0;
2059 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2060 kvm_userspace_mem.memory_size = PAGE_SIZE;
2061 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2062 if (r)
2063 goto out;
2064
2065 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2066 out:
2067 up_write(&kvm->slots_lock);
2068 return r;
2069 }
2070
2071 static int alloc_identity_pagetable(struct kvm *kvm)
2072 {
2073 struct kvm_userspace_memory_region kvm_userspace_mem;
2074 int r = 0;
2075
2076 down_write(&kvm->slots_lock);
2077 if (kvm->arch.ept_identity_pagetable)
2078 goto out;
2079 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2080 kvm_userspace_mem.flags = 0;
2081 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2082 kvm_userspace_mem.memory_size = PAGE_SIZE;
2083 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2084 if (r)
2085 goto out;
2086
2087 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2088 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2089 out:
2090 up_write(&kvm->slots_lock);
2091 return r;
2092 }
2093
2094 static void allocate_vpid(struct vcpu_vmx *vmx)
2095 {
2096 int vpid;
2097
2098 vmx->vpid = 0;
2099 if (!enable_vpid || !cpu_has_vmx_vpid())
2100 return;
2101 spin_lock(&vmx_vpid_lock);
2102 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2103 if (vpid < VMX_NR_VPIDS) {
2104 vmx->vpid = vpid;
2105 __set_bit(vpid, vmx_vpid_bitmap);
2106 }
2107 spin_unlock(&vmx_vpid_lock);
2108 }
2109
2110 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
2111 {
2112 void *va;
2113
2114 if (!cpu_has_vmx_msr_bitmap())
2115 return;
2116
2117 /*
2118 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2119 * have the write-low and read-high bitmap offsets the wrong way round.
2120 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2121 */
2122 va = kmap(msr_bitmap);
2123 if (msr <= 0x1fff) {
2124 __clear_bit(msr, va + 0x000); /* read-low */
2125 __clear_bit(msr, va + 0x800); /* write-low */
2126 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2127 msr &= 0x1fff;
2128 __clear_bit(msr, va + 0x400); /* read-high */
2129 __clear_bit(msr, va + 0xc00); /* write-high */
2130 }
2131 kunmap(msr_bitmap);
2132 }
2133
2134 /*
2135 * Sets up the vmcs for emulated real mode.
2136 */
2137 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2138 {
2139 u32 host_sysenter_cs, msr_low, msr_high;
2140 u32 junk;
2141 u64 host_pat, tsc_this, tsc_base;
2142 unsigned long a;
2143 struct descriptor_table dt;
2144 int i;
2145 unsigned long kvm_vmx_return;
2146 u32 exec_control;
2147
2148 /* I/O */
2149 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2150 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
2151
2152 if (cpu_has_vmx_msr_bitmap())
2153 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2154
2155 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2156
2157 /* Control */
2158 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2159 vmcs_config.pin_based_exec_ctrl);
2160
2161 exec_control = vmcs_config.cpu_based_exec_ctrl;
2162 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2163 exec_control &= ~CPU_BASED_TPR_SHADOW;
2164 #ifdef CONFIG_X86_64
2165 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2166 CPU_BASED_CR8_LOAD_EXITING;
2167 #endif
2168 }
2169 if (!vm_need_ept())
2170 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2171 CPU_BASED_CR3_LOAD_EXITING |
2172 CPU_BASED_INVLPG_EXITING;
2173 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2174
2175 if (cpu_has_secondary_exec_ctrls()) {
2176 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2177 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2178 exec_control &=
2179 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2180 if (vmx->vpid == 0)
2181 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2182 if (!vm_need_ept())
2183 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2184 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2185 }
2186
2187 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2188 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2189 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2190
2191 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2192 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2193 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2194
2195 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2196 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2197 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2198 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2199 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2200 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2201 #ifdef CONFIG_X86_64
2202 rdmsrl(MSR_FS_BASE, a);
2203 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2204 rdmsrl(MSR_GS_BASE, a);
2205 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2206 #else
2207 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2208 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2209 #endif
2210
2211 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2212
2213 kvm_get_idt(&dt);
2214 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2215
2216 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2217 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2218 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2219 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2220 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2221
2222 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2223 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2224 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2225 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2226 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2227 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2228
2229 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2230 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2231 host_pat = msr_low | ((u64) msr_high << 32);
2232 vmcs_write64(HOST_IA32_PAT, host_pat);
2233 }
2234 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2235 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2236 host_pat = msr_low | ((u64) msr_high << 32);
2237 /* Write the default value follow host pat */
2238 vmcs_write64(GUEST_IA32_PAT, host_pat);
2239 /* Keep arch.pat sync with GUEST_IA32_PAT */
2240 vmx->vcpu.arch.pat = host_pat;
2241 }
2242
2243 for (i = 0; i < NR_VMX_MSR; ++i) {
2244 u32 index = vmx_msr_index[i];
2245 u32 data_low, data_high;
2246 u64 data;
2247 int j = vmx->nmsrs;
2248
2249 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2250 continue;
2251 if (wrmsr_safe(index, data_low, data_high) < 0)
2252 continue;
2253 data = data_low | ((u64)data_high << 32);
2254 vmx->host_msrs[j].index = index;
2255 vmx->host_msrs[j].reserved = 0;
2256 vmx->host_msrs[j].data = data;
2257 vmx->guest_msrs[j] = vmx->host_msrs[j];
2258 ++vmx->nmsrs;
2259 }
2260
2261 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2262
2263 /* 22.2.1, 20.8.1 */
2264 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2265
2266 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2267 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2268
2269 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2270 rdtscll(tsc_this);
2271 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2272 tsc_base = tsc_this;
2273
2274 guest_write_tsc(0, tsc_base);
2275
2276 return 0;
2277 }
2278
2279 static int init_rmode(struct kvm *kvm)
2280 {
2281 if (!init_rmode_tss(kvm))
2282 return 0;
2283 if (!init_rmode_identity_map(kvm))
2284 return 0;
2285 return 1;
2286 }
2287
2288 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2289 {
2290 struct vcpu_vmx *vmx = to_vmx(vcpu);
2291 u64 msr;
2292 int ret;
2293
2294 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2295 down_read(&vcpu->kvm->slots_lock);
2296 if (!init_rmode(vmx->vcpu.kvm)) {
2297 ret = -ENOMEM;
2298 goto out;
2299 }
2300
2301 vmx->vcpu.arch.rmode.active = 0;
2302
2303 vmx->soft_vnmi_blocked = 0;
2304
2305 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2306 kvm_set_cr8(&vmx->vcpu, 0);
2307 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2308 if (vmx->vcpu.vcpu_id == 0)
2309 msr |= MSR_IA32_APICBASE_BSP;
2310 kvm_set_apic_base(&vmx->vcpu, msr);
2311
2312 fx_init(&vmx->vcpu);
2313
2314 seg_setup(VCPU_SREG_CS);
2315 /*
2316 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2317 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2318 */
2319 if (vmx->vcpu.vcpu_id == 0) {
2320 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2321 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2322 } else {
2323 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2324 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2325 }
2326
2327 seg_setup(VCPU_SREG_DS);
2328 seg_setup(VCPU_SREG_ES);
2329 seg_setup(VCPU_SREG_FS);
2330 seg_setup(VCPU_SREG_GS);
2331 seg_setup(VCPU_SREG_SS);
2332
2333 vmcs_write16(GUEST_TR_SELECTOR, 0);
2334 vmcs_writel(GUEST_TR_BASE, 0);
2335 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2336 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2337
2338 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2339 vmcs_writel(GUEST_LDTR_BASE, 0);
2340 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2341 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2342
2343 vmcs_write32(GUEST_SYSENTER_CS, 0);
2344 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2345 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2346
2347 vmcs_writel(GUEST_RFLAGS, 0x02);
2348 if (vmx->vcpu.vcpu_id == 0)
2349 kvm_rip_write(vcpu, 0xfff0);
2350 else
2351 kvm_rip_write(vcpu, 0);
2352 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2353
2354 vmcs_writel(GUEST_DR7, 0x400);
2355
2356 vmcs_writel(GUEST_GDTR_BASE, 0);
2357 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2358
2359 vmcs_writel(GUEST_IDTR_BASE, 0);
2360 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2361
2362 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2363 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2364 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2365
2366 /* Special registers */
2367 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2368
2369 setup_msrs(vmx);
2370
2371 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2372
2373 if (cpu_has_vmx_tpr_shadow()) {
2374 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2375 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2376 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2377 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2378 vmcs_write32(TPR_THRESHOLD, 0);
2379 }
2380
2381 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2382 vmcs_write64(APIC_ACCESS_ADDR,
2383 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2384
2385 if (vmx->vpid != 0)
2386 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2387
2388 vmx->vcpu.arch.cr0 = 0x60000010;
2389 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2390 vmx_set_cr4(&vmx->vcpu, 0);
2391 vmx_set_efer(&vmx->vcpu, 0);
2392 vmx_fpu_activate(&vmx->vcpu);
2393 update_exception_bitmap(&vmx->vcpu);
2394
2395 vpid_sync_vcpu_all(vmx);
2396
2397 ret = 0;
2398
2399 /* HACK: Don't enable emulation on guest boot/reset */
2400 vmx->emulation_required = 0;
2401
2402 out:
2403 up_read(&vcpu->kvm->slots_lock);
2404 return ret;
2405 }
2406
2407 static void enable_irq_window(struct kvm_vcpu *vcpu)
2408 {
2409 u32 cpu_based_vm_exec_control;
2410
2411 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2412 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2413 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2414 }
2415
2416 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2417 {
2418 u32 cpu_based_vm_exec_control;
2419
2420 if (!cpu_has_virtual_nmis()) {
2421 enable_irq_window(vcpu);
2422 return;
2423 }
2424
2425 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2426 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2427 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2428 }
2429
2430 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2431 {
2432 struct vcpu_vmx *vmx = to_vmx(vcpu);
2433
2434 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2435
2436 ++vcpu->stat.irq_injections;
2437 if (vcpu->arch.rmode.active) {
2438 vmx->rmode.irq.pending = true;
2439 vmx->rmode.irq.vector = irq;
2440 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2441 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2442 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2443 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2444 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2445 return;
2446 }
2447 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2448 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2449 }
2450
2451 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2452 {
2453 struct vcpu_vmx *vmx = to_vmx(vcpu);
2454
2455 if (!cpu_has_virtual_nmis()) {
2456 /*
2457 * Tracking the NMI-blocked state in software is built upon
2458 * finding the next open IRQ window. This, in turn, depends on
2459 * well-behaving guests: They have to keep IRQs disabled at
2460 * least as long as the NMI handler runs. Otherwise we may
2461 * cause NMI nesting, maybe breaking the guest. But as this is
2462 * highly unlikely, we can live with the residual risk.
2463 */
2464 vmx->soft_vnmi_blocked = 1;
2465 vmx->vnmi_blocked_time = 0;
2466 }
2467
2468 ++vcpu->stat.nmi_injections;
2469 if (vcpu->arch.rmode.active) {
2470 vmx->rmode.irq.pending = true;
2471 vmx->rmode.irq.vector = NMI_VECTOR;
2472 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2473 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2474 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2475 INTR_INFO_VALID_MASK);
2476 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2477 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2478 return;
2479 }
2480 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2481 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2482 }
2483
2484 static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2485 {
2486 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2487
2488 vcpu->arch.nmi_window_open =
2489 !(guest_intr & (GUEST_INTR_STATE_STI |
2490 GUEST_INTR_STATE_MOV_SS |
2491 GUEST_INTR_STATE_NMI));
2492 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2493 vcpu->arch.nmi_window_open = 0;
2494
2495 vcpu->arch.interrupt_window_open =
2496 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2497 !(guest_intr & (GUEST_INTR_STATE_STI |
2498 GUEST_INTR_STATE_MOV_SS)));
2499 }
2500
2501 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2502 {
2503 int word_index = __ffs(vcpu->arch.irq_summary);
2504 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2505 int irq = word_index * BITS_PER_LONG + bit_index;
2506
2507 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2508 if (!vcpu->arch.irq_pending[word_index])
2509 clear_bit(word_index, &vcpu->arch.irq_summary);
2510 kvm_queue_interrupt(vcpu, irq);
2511 }
2512
2513 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2514 struct kvm_run *kvm_run)
2515 {
2516 vmx_update_window_states(vcpu);
2517
2518 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2519 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2520 GUEST_INTR_STATE_STI |
2521 GUEST_INTR_STATE_MOV_SS);
2522
2523 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2524 if (vcpu->arch.interrupt.pending) {
2525 enable_nmi_window(vcpu);
2526 } else if (vcpu->arch.nmi_window_open) {
2527 vcpu->arch.nmi_pending = false;
2528 vcpu->arch.nmi_injected = true;
2529 } else {
2530 enable_nmi_window(vcpu);
2531 return;
2532 }
2533 }
2534 if (vcpu->arch.nmi_injected) {
2535 vmx_inject_nmi(vcpu);
2536 if (vcpu->arch.nmi_pending)
2537 enable_nmi_window(vcpu);
2538 else if (vcpu->arch.irq_summary
2539 || kvm_run->request_interrupt_window)
2540 enable_irq_window(vcpu);
2541 return;
2542 }
2543
2544 if (vcpu->arch.interrupt_window_open) {
2545 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2546 kvm_do_inject_irq(vcpu);
2547
2548 if (vcpu->arch.interrupt.pending)
2549 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2550 }
2551 if (!vcpu->arch.interrupt_window_open &&
2552 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2553 enable_irq_window(vcpu);
2554 }
2555
2556 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2557 {
2558 int ret;
2559 struct kvm_userspace_memory_region tss_mem = {
2560 .slot = TSS_PRIVATE_MEMSLOT,
2561 .guest_phys_addr = addr,
2562 .memory_size = PAGE_SIZE * 3,
2563 .flags = 0,
2564 };
2565
2566 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2567 if (ret)
2568 return ret;
2569 kvm->arch.tss_addr = addr;
2570 return 0;
2571 }
2572
2573 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2574 int vec, u32 err_code)
2575 {
2576 /*
2577 * Instruction with address size override prefix opcode 0x67
2578 * Cause the #SS fault with 0 error code in VM86 mode.
2579 */
2580 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2581 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2582 return 1;
2583 /*
2584 * Forward all other exceptions that are valid in real mode.
2585 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2586 * the required debugging infrastructure rework.
2587 */
2588 switch (vec) {
2589 case DB_VECTOR:
2590 if (vcpu->guest_debug &
2591 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2592 return 0;
2593 kvm_queue_exception(vcpu, vec);
2594 return 1;
2595 case BP_VECTOR:
2596 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2597 return 0;
2598 /* fall through */
2599 case DE_VECTOR:
2600 case OF_VECTOR:
2601 case BR_VECTOR:
2602 case UD_VECTOR:
2603 case DF_VECTOR:
2604 case SS_VECTOR:
2605 case GP_VECTOR:
2606 case MF_VECTOR:
2607 kvm_queue_exception(vcpu, vec);
2608 return 1;
2609 }
2610 return 0;
2611 }
2612
2613 /*
2614 * Trigger machine check on the host. We assume all the MSRs are already set up
2615 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2616 * We pass a fake environment to the machine check handler because we want
2617 * the guest to be always treated like user space, no matter what context
2618 * it used internally.
2619 */
2620 static void kvm_machine_check(void)
2621 {
2622 #ifdef CONFIG_X86_MCE
2623 struct pt_regs regs = {
2624 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2625 .flags = X86_EFLAGS_IF,
2626 };
2627
2628 #ifdef CONFIG_X86_64
2629 do_machine_check(&regs, 0);
2630 #else
2631 machine_check_vector(&regs, 0);
2632 #endif
2633 #endif
2634 }
2635
2636 static int handle_machine_check(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2637 {
2638 /* already handled by vcpu_run */
2639 return 1;
2640 }
2641
2642 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2643 {
2644 struct vcpu_vmx *vmx = to_vmx(vcpu);
2645 u32 intr_info, ex_no, error_code;
2646 unsigned long cr2, rip, dr6;
2647 u32 vect_info;
2648 enum emulation_result er;
2649
2650 vect_info = vmx->idt_vectoring_info;
2651 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2652
2653 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2654 if (ex_no == MC_VECTOR)
2655 return handle_machine_check(vcpu, kvm_run);
2656
2657 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2658 !is_page_fault(intr_info))
2659 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2660 "intr info 0x%x\n", __func__, vect_info, intr_info);
2661
2662 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2663 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2664 set_bit(irq, vcpu->arch.irq_pending);
2665 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2666 }
2667
2668 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2669 return 1; /* already handled by vmx_vcpu_run() */
2670
2671 if (is_no_device(intr_info)) {
2672 vmx_fpu_activate(vcpu);
2673 return 1;
2674 }
2675
2676 if (is_invalid_opcode(intr_info)) {
2677 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2678 if (er != EMULATE_DONE)
2679 kvm_queue_exception(vcpu, UD_VECTOR);
2680 return 1;
2681 }
2682
2683 error_code = 0;
2684 rip = kvm_rip_read(vcpu);
2685 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2686 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2687 if (is_page_fault(intr_info)) {
2688 /* EPT won't cause page fault directly */
2689 if (vm_need_ept())
2690 BUG();
2691 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2692 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2693 (u32)((u64)cr2 >> 32), handler);
2694 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2695 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2696 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2697 }
2698
2699 if (vcpu->arch.rmode.active &&
2700 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2701 error_code)) {
2702 if (vcpu->arch.halt_request) {
2703 vcpu->arch.halt_request = 0;
2704 return kvm_emulate_halt(vcpu);
2705 }
2706 return 1;
2707 }
2708
2709 switch (ex_no) {
2710 case DB_VECTOR:
2711 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2712 if (!(vcpu->guest_debug &
2713 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2714 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2715 kvm_queue_exception(vcpu, DB_VECTOR);
2716 return 1;
2717 }
2718 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2719 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2720 /* fall through */
2721 case BP_VECTOR:
2722 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2723 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2724 kvm_run->debug.arch.exception = ex_no;
2725 break;
2726 default:
2727 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2728 kvm_run->ex.exception = ex_no;
2729 kvm_run->ex.error_code = error_code;
2730 break;
2731 }
2732 return 0;
2733 }
2734
2735 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2736 struct kvm_run *kvm_run)
2737 {
2738 ++vcpu->stat.irq_exits;
2739 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2740 return 1;
2741 }
2742
2743 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2744 {
2745 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2746 return 0;
2747 }
2748
2749 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2750 {
2751 unsigned long exit_qualification;
2752 int size, in, string;
2753 unsigned port;
2754
2755 ++vcpu->stat.io_exits;
2756 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2757 string = (exit_qualification & 16) != 0;
2758
2759 if (string) {
2760 if (emulate_instruction(vcpu,
2761 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2762 return 0;
2763 return 1;
2764 }
2765
2766 size = (exit_qualification & 7) + 1;
2767 in = (exit_qualification & 8) != 0;
2768 port = exit_qualification >> 16;
2769
2770 skip_emulated_instruction(vcpu);
2771 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2772 }
2773
2774 static void
2775 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2776 {
2777 /*
2778 * Patch in the VMCALL instruction:
2779 */
2780 hypercall[0] = 0x0f;
2781 hypercall[1] = 0x01;
2782 hypercall[2] = 0xc1;
2783 }
2784
2785 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2786 {
2787 unsigned long exit_qualification;
2788 int cr;
2789 int reg;
2790
2791 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2792 cr = exit_qualification & 15;
2793 reg = (exit_qualification >> 8) & 15;
2794 switch ((exit_qualification >> 4) & 3) {
2795 case 0: /* mov to cr */
2796 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2797 (u32)kvm_register_read(vcpu, reg),
2798 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2799 handler);
2800 switch (cr) {
2801 case 0:
2802 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2803 skip_emulated_instruction(vcpu);
2804 return 1;
2805 case 3:
2806 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2807 skip_emulated_instruction(vcpu);
2808 return 1;
2809 case 4:
2810 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2811 skip_emulated_instruction(vcpu);
2812 return 1;
2813 case 8:
2814 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2815 skip_emulated_instruction(vcpu);
2816 if (irqchip_in_kernel(vcpu->kvm))
2817 return 1;
2818 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2819 return 0;
2820 };
2821 break;
2822 case 2: /* clts */
2823 vmx_fpu_deactivate(vcpu);
2824 vcpu->arch.cr0 &= ~X86_CR0_TS;
2825 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2826 vmx_fpu_activate(vcpu);
2827 KVMTRACE_0D(CLTS, vcpu, handler);
2828 skip_emulated_instruction(vcpu);
2829 return 1;
2830 case 1: /*mov from cr*/
2831 switch (cr) {
2832 case 3:
2833 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2834 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2835 (u32)kvm_register_read(vcpu, reg),
2836 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2837 handler);
2838 skip_emulated_instruction(vcpu);
2839 return 1;
2840 case 8:
2841 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2842 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2843 (u32)kvm_register_read(vcpu, reg), handler);
2844 skip_emulated_instruction(vcpu);
2845 return 1;
2846 }
2847 break;
2848 case 3: /* lmsw */
2849 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2850
2851 skip_emulated_instruction(vcpu);
2852 return 1;
2853 default:
2854 break;
2855 }
2856 kvm_run->exit_reason = 0;
2857 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2858 (int)(exit_qualification >> 4) & 3, cr);
2859 return 0;
2860 }
2861
2862 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2863 {
2864 unsigned long exit_qualification;
2865 unsigned long val;
2866 int dr, reg;
2867
2868 if (!kvm_require_cpl(vcpu, 0))
2869 return 1;
2870 dr = vmcs_readl(GUEST_DR7);
2871 if (dr & DR7_GD) {
2872 /*
2873 * As the vm-exit takes precedence over the debug trap, we
2874 * need to emulate the latter, either for the host or the
2875 * guest debugging itself.
2876 */
2877 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2878 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2879 kvm_run->debug.arch.dr7 = dr;
2880 kvm_run->debug.arch.pc =
2881 vmcs_readl(GUEST_CS_BASE) +
2882 vmcs_readl(GUEST_RIP);
2883 kvm_run->debug.arch.exception = DB_VECTOR;
2884 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2885 return 0;
2886 } else {
2887 vcpu->arch.dr7 &= ~DR7_GD;
2888 vcpu->arch.dr6 |= DR6_BD;
2889 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2890 kvm_queue_exception(vcpu, DB_VECTOR);
2891 return 1;
2892 }
2893 }
2894
2895 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2896 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2897 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2898 if (exit_qualification & TYPE_MOV_FROM_DR) {
2899 switch (dr) {
2900 case 0 ... 3:
2901 val = vcpu->arch.db[dr];
2902 break;
2903 case 6:
2904 val = vcpu->arch.dr6;
2905 break;
2906 case 7:
2907 val = vcpu->arch.dr7;
2908 break;
2909 default:
2910 val = 0;
2911 }
2912 kvm_register_write(vcpu, reg, val);
2913 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2914 } else {
2915 val = vcpu->arch.regs[reg];
2916 switch (dr) {
2917 case 0 ... 3:
2918 vcpu->arch.db[dr] = val;
2919 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2920 vcpu->arch.eff_db[dr] = val;
2921 break;
2922 case 4 ... 5:
2923 if (vcpu->arch.cr4 & X86_CR4_DE)
2924 kvm_queue_exception(vcpu, UD_VECTOR);
2925 break;
2926 case 6:
2927 if (val & 0xffffffff00000000ULL) {
2928 kvm_queue_exception(vcpu, GP_VECTOR);
2929 break;
2930 }
2931 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2932 break;
2933 case 7:
2934 if (val & 0xffffffff00000000ULL) {
2935 kvm_queue_exception(vcpu, GP_VECTOR);
2936 break;
2937 }
2938 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2939 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2940 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2941 vcpu->arch.switch_db_regs =
2942 (val & DR7_BP_EN_MASK);
2943 }
2944 break;
2945 }
2946 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
2947 }
2948 skip_emulated_instruction(vcpu);
2949 return 1;
2950 }
2951
2952 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2953 {
2954 kvm_emulate_cpuid(vcpu);
2955 return 1;
2956 }
2957
2958 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2959 {
2960 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2961 u64 data;
2962
2963 if (vmx_get_msr(vcpu, ecx, &data)) {
2964 kvm_inject_gp(vcpu, 0);
2965 return 1;
2966 }
2967
2968 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2969 handler);
2970
2971 /* FIXME: handling of bits 32:63 of rax, rdx */
2972 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2973 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2974 skip_emulated_instruction(vcpu);
2975 return 1;
2976 }
2977
2978 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2979 {
2980 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2981 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2982 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2983
2984 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2985 handler);
2986
2987 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2988 kvm_inject_gp(vcpu, 0);
2989 return 1;
2990 }
2991
2992 skip_emulated_instruction(vcpu);
2993 return 1;
2994 }
2995
2996 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2997 struct kvm_run *kvm_run)
2998 {
2999 return 1;
3000 }
3001
3002 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
3003 struct kvm_run *kvm_run)
3004 {
3005 u32 cpu_based_vm_exec_control;
3006
3007 /* clear pending irq */
3008 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3009 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3010 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3011
3012 KVMTRACE_0D(PEND_INTR, vcpu, handler);
3013 ++vcpu->stat.irq_window_exits;
3014
3015 /*
3016 * If the user space waits to inject interrupts, exit as soon as
3017 * possible
3018 */
3019 if (kvm_run->request_interrupt_window &&
3020 !vcpu->arch.irq_summary) {
3021 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3022 return 0;
3023 }
3024 return 1;
3025 }
3026
3027 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3028 {
3029 skip_emulated_instruction(vcpu);
3030 return kvm_emulate_halt(vcpu);
3031 }
3032
3033 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3034 {
3035 skip_emulated_instruction(vcpu);
3036 kvm_emulate_hypercall(vcpu);
3037 return 1;
3038 }
3039
3040 static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3041 {
3042 kvm_queue_exception(vcpu, UD_VECTOR);
3043 return 1;
3044 }
3045
3046 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3047 {
3048 u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3049
3050 kvm_mmu_invlpg(vcpu, exit_qualification);
3051 skip_emulated_instruction(vcpu);
3052 return 1;
3053 }
3054
3055 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3056 {
3057 skip_emulated_instruction(vcpu);
3058 /* TODO: Add support for VT-d/pass-through device */
3059 return 1;
3060 }
3061
3062 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3063 {
3064 u64 exit_qualification;
3065 enum emulation_result er;
3066 unsigned long offset;
3067
3068 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3069 offset = exit_qualification & 0xffful;
3070
3071 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3072
3073 if (er != EMULATE_DONE) {
3074 printk(KERN_ERR
3075 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3076 offset);
3077 return -ENOTSUPP;
3078 }
3079 return 1;
3080 }
3081
3082 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3083 {
3084 struct vcpu_vmx *vmx = to_vmx(vcpu);
3085 unsigned long exit_qualification;
3086 u16 tss_selector;
3087 int reason;
3088
3089 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3090
3091 reason = (u32)exit_qualification >> 30;
3092 if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
3093 (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
3094 (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
3095 == INTR_TYPE_NMI_INTR) {
3096 vcpu->arch.nmi_injected = false;
3097 if (cpu_has_virtual_nmis())
3098 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3099 GUEST_INTR_STATE_NMI);
3100 }
3101 tss_selector = exit_qualification;
3102
3103 if (!kvm_task_switch(vcpu, tss_selector, reason))
3104 return 0;
3105
3106 /* clear all local breakpoint enable flags */
3107 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3108
3109 /*
3110 * TODO: What about debug traps on tss switch?
3111 * Are we supposed to inject them and update dr6?
3112 */
3113
3114 return 1;
3115 }
3116
3117 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3118 {
3119 u64 exit_qualification;
3120 gpa_t gpa;
3121 int gla_validity;
3122
3123 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3124
3125 if (exit_qualification & (1 << 6)) {
3126 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3127 return -ENOTSUPP;
3128 }
3129
3130 gla_validity = (exit_qualification >> 7) & 0x3;
3131 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3132 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3133 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3134 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3135 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3136 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3137 (long unsigned int)exit_qualification);
3138 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3139 kvm_run->hw.hardware_exit_reason = 0;
3140 return -ENOTSUPP;
3141 }
3142
3143 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3144 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3145 }
3146
3147 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3148 {
3149 u32 cpu_based_vm_exec_control;
3150
3151 /* clear pending NMI */
3152 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3153 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3154 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3155 ++vcpu->stat.nmi_window_exits;
3156
3157 return 1;
3158 }
3159
3160 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3161 struct kvm_run *kvm_run)
3162 {
3163 struct vcpu_vmx *vmx = to_vmx(vcpu);
3164 enum emulation_result err = EMULATE_DONE;
3165
3166 preempt_enable();
3167 local_irq_enable();
3168
3169 while (!guest_state_valid(vcpu)) {
3170 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3171
3172 if (err == EMULATE_DO_MMIO)
3173 break;
3174
3175 if (err != EMULATE_DONE) {
3176 kvm_report_emulation_failure(vcpu, "emulation failure");
3177 return;
3178 }
3179
3180 if (signal_pending(current))
3181 break;
3182 if (need_resched())
3183 schedule();
3184 }
3185
3186 local_irq_disable();
3187 preempt_disable();
3188
3189 vmx->invalid_state_emulation_result = err;
3190 }
3191
3192 /*
3193 * The exit handlers return 1 if the exit was handled fully and guest execution
3194 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3195 * to be done to userspace and return 0.
3196 */
3197 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3198 struct kvm_run *kvm_run) = {
3199 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3200 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3201 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3202 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3203 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3204 [EXIT_REASON_CR_ACCESS] = handle_cr,
3205 [EXIT_REASON_DR_ACCESS] = handle_dr,
3206 [EXIT_REASON_CPUID] = handle_cpuid,
3207 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3208 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3209 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3210 [EXIT_REASON_HLT] = handle_halt,
3211 [EXIT_REASON_INVLPG] = handle_invlpg,
3212 [EXIT_REASON_VMCALL] = handle_vmcall,
3213 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3214 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3215 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3216 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3217 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3218 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3219 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3220 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3221 [EXIT_REASON_VMON] = handle_vmx_insn,
3222 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3223 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3224 [EXIT_REASON_WBINVD] = handle_wbinvd,
3225 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3226 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3227 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3228 };
3229
3230 static const int kvm_vmx_max_exit_handlers =
3231 ARRAY_SIZE(kvm_vmx_exit_handlers);
3232
3233 /*
3234 * The guest has exited. See if we can fix it or if we need userspace
3235 * assistance.
3236 */
3237 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3238 {
3239 struct vcpu_vmx *vmx = to_vmx(vcpu);
3240 u32 exit_reason = vmx->exit_reason;
3241 u32 vectoring_info = vmx->idt_vectoring_info;
3242
3243 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3244 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3245
3246 /* If we need to emulate an MMIO from handle_invalid_guest_state
3247 * we just return 0 */
3248 if (vmx->emulation_required && emulate_invalid_guest_state) {
3249 if (guest_state_valid(vcpu))
3250 vmx->emulation_required = 0;
3251 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3252 }
3253
3254 /* Access CR3 don't cause VMExit in paging mode, so we need
3255 * to sync with guest real CR3. */
3256 if (vm_need_ept() && is_paging(vcpu)) {
3257 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3258 ept_load_pdptrs(vcpu);
3259 }
3260
3261 if (unlikely(vmx->fail)) {
3262 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3263 kvm_run->fail_entry.hardware_entry_failure_reason
3264 = vmcs_read32(VM_INSTRUCTION_ERROR);
3265 return 0;
3266 }
3267
3268 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3269 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3270 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3271 exit_reason != EXIT_REASON_TASK_SWITCH))
3272 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3273 "(0x%x) and exit reason is 0x%x\n",
3274 __func__, vectoring_info, exit_reason);
3275
3276 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3277 if (vcpu->arch.interrupt_window_open) {
3278 vmx->soft_vnmi_blocked = 0;
3279 vcpu->arch.nmi_window_open = 1;
3280 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3281 vcpu->arch.nmi_pending) {
3282 /*
3283 * This CPU don't support us in finding the end of an
3284 * NMI-blocked window if the guest runs with IRQs
3285 * disabled. So we pull the trigger after 1 s of
3286 * futile waiting, but inform the user about this.
3287 */
3288 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3289 "state on VCPU %d after 1 s timeout\n",
3290 __func__, vcpu->vcpu_id);
3291 vmx->soft_vnmi_blocked = 0;
3292 vmx->vcpu.arch.nmi_window_open = 1;
3293 }
3294 }
3295
3296 if (exit_reason < kvm_vmx_max_exit_handlers
3297 && kvm_vmx_exit_handlers[exit_reason])
3298 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3299 else {
3300 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3301 kvm_run->hw.hardware_exit_reason = exit_reason;
3302 }
3303 return 0;
3304 }
3305
3306 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3307 {
3308 int max_irr, tpr;
3309
3310 if (!vm_need_tpr_shadow(vcpu->kvm))
3311 return;
3312
3313 if (!kvm_lapic_enabled(vcpu) ||
3314 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3315 vmcs_write32(TPR_THRESHOLD, 0);
3316 return;
3317 }
3318
3319 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3320 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3321 }
3322
3323 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3324 {
3325 u32 exit_intr_info;
3326 u32 idt_vectoring_info;
3327 bool unblock_nmi;
3328 u8 vector;
3329 int type;
3330 bool idtv_info_valid;
3331 u32 error;
3332
3333 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3334 if (cpu_has_virtual_nmis()) {
3335 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3336 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3337 /*
3338 * SDM 3: 25.7.1.2
3339 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3340 * a guest IRET fault.
3341 */
3342 if (unblock_nmi && vector != DF_VECTOR)
3343 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3344 GUEST_INTR_STATE_NMI);
3345 } else if (unlikely(vmx->soft_vnmi_blocked))
3346 vmx->vnmi_blocked_time +=
3347 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3348
3349 idt_vectoring_info = vmx->idt_vectoring_info;
3350 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3351 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3352 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3353 if (vmx->vcpu.arch.nmi_injected) {
3354 /*
3355 * SDM 3: 25.7.1.2
3356 * Clear bit "block by NMI" before VM entry if a NMI delivery
3357 * faulted.
3358 */
3359 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3360 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3361 GUEST_INTR_STATE_NMI);
3362 else
3363 vmx->vcpu.arch.nmi_injected = false;
3364 }
3365 kvm_clear_exception_queue(&vmx->vcpu);
3366 if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION ||
3367 type == INTR_TYPE_SOFT_EXCEPTION)) {
3368 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3369 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3370 kvm_queue_exception_e(&vmx->vcpu, vector, error);
3371 } else
3372 kvm_queue_exception(&vmx->vcpu, vector);
3373 vmx->idt_vectoring_info = 0;
3374 }
3375 kvm_clear_interrupt_queue(&vmx->vcpu);
3376 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3377 kvm_queue_interrupt(&vmx->vcpu, vector);
3378 vmx->idt_vectoring_info = 0;
3379 }
3380 }
3381
3382 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3383 {
3384 update_tpr_threshold(vcpu);
3385
3386 vmx_update_window_states(vcpu);
3387
3388 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3389 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3390 GUEST_INTR_STATE_STI |
3391 GUEST_INTR_STATE_MOV_SS);
3392
3393 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3394 if (vcpu->arch.interrupt.pending) {
3395 enable_nmi_window(vcpu);
3396 } else if (vcpu->arch.nmi_window_open) {
3397 vcpu->arch.nmi_pending = false;
3398 vcpu->arch.nmi_injected = true;
3399 } else {
3400 enable_nmi_window(vcpu);
3401 return;
3402 }
3403 }
3404 if (vcpu->arch.nmi_injected) {
3405 vmx_inject_nmi(vcpu);
3406 if (vcpu->arch.nmi_pending)
3407 enable_nmi_window(vcpu);
3408 else if (kvm_cpu_has_interrupt(vcpu))
3409 enable_irq_window(vcpu);
3410 return;
3411 }
3412 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3413 if (vcpu->arch.interrupt_window_open)
3414 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3415 else
3416 enable_irq_window(vcpu);
3417 }
3418 if (vcpu->arch.interrupt.pending) {
3419 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3420 if (kvm_cpu_has_interrupt(vcpu))
3421 enable_irq_window(vcpu);
3422 }
3423 }
3424
3425 /*
3426 * Failure to inject an interrupt should give us the information
3427 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3428 * when fetching the interrupt redirection bitmap in the real-mode
3429 * tss, this doesn't happen. So we do it ourselves.
3430 */
3431 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3432 {
3433 vmx->rmode.irq.pending = 0;
3434 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3435 return;
3436 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3437 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3438 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3439 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3440 return;
3441 }
3442 vmx->idt_vectoring_info =
3443 VECTORING_INFO_VALID_MASK
3444 | INTR_TYPE_EXT_INTR
3445 | vmx->rmode.irq.vector;
3446 }
3447
3448 #ifdef CONFIG_X86_64
3449 #define R "r"
3450 #define Q "q"
3451 #else
3452 #define R "e"
3453 #define Q "l"
3454 #endif
3455
3456 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3457 {
3458 struct vcpu_vmx *vmx = to_vmx(vcpu);
3459 u32 intr_info;
3460
3461 /* Record the guest's net vcpu time for enforced NMI injections. */
3462 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3463 vmx->entry_time = ktime_get();
3464
3465 /* Handle invalid guest state instead of entering VMX */
3466 if (vmx->emulation_required && emulate_invalid_guest_state) {
3467 handle_invalid_guest_state(vcpu, kvm_run);
3468 return;
3469 }
3470
3471 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3472 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3473 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3474 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3475
3476 /*
3477 * Loading guest fpu may have cleared host cr0.ts
3478 */
3479 vmcs_writel(HOST_CR0, read_cr0());
3480
3481 set_debugreg(vcpu->arch.dr6, 6);
3482
3483 asm(
3484 /* Store host registers */
3485 "push %%"R"dx; push %%"R"bp;"
3486 "push %%"R"cx \n\t"
3487 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3488 "je 1f \n\t"
3489 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3490 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3491 "1: \n\t"
3492 /* Check if vmlaunch of vmresume is needed */
3493 "cmpl $0, %c[launched](%0) \n\t"
3494 /* Load guest registers. Don't clobber flags. */
3495 "mov %c[cr2](%0), %%"R"ax \n\t"
3496 "mov %%"R"ax, %%cr2 \n\t"
3497 "mov %c[rax](%0), %%"R"ax \n\t"
3498 "mov %c[rbx](%0), %%"R"bx \n\t"
3499 "mov %c[rdx](%0), %%"R"dx \n\t"
3500 "mov %c[rsi](%0), %%"R"si \n\t"
3501 "mov %c[rdi](%0), %%"R"di \n\t"
3502 "mov %c[rbp](%0), %%"R"bp \n\t"
3503 #ifdef CONFIG_X86_64
3504 "mov %c[r8](%0), %%r8 \n\t"
3505 "mov %c[r9](%0), %%r9 \n\t"
3506 "mov %c[r10](%0), %%r10 \n\t"
3507 "mov %c[r11](%0), %%r11 \n\t"
3508 "mov %c[r12](%0), %%r12 \n\t"
3509 "mov %c[r13](%0), %%r13 \n\t"
3510 "mov %c[r14](%0), %%r14 \n\t"
3511 "mov %c[r15](%0), %%r15 \n\t"
3512 #endif
3513 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3514
3515 /* Enter guest mode */
3516 "jne .Llaunched \n\t"
3517 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3518 "jmp .Lkvm_vmx_return \n\t"
3519 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3520 ".Lkvm_vmx_return: "
3521 /* Save guest registers, load host registers, keep flags */
3522 "xchg %0, (%%"R"sp) \n\t"
3523 "mov %%"R"ax, %c[rax](%0) \n\t"
3524 "mov %%"R"bx, %c[rbx](%0) \n\t"
3525 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3526 "mov %%"R"dx, %c[rdx](%0) \n\t"
3527 "mov %%"R"si, %c[rsi](%0) \n\t"
3528 "mov %%"R"di, %c[rdi](%0) \n\t"
3529 "mov %%"R"bp, %c[rbp](%0) \n\t"
3530 #ifdef CONFIG_X86_64
3531 "mov %%r8, %c[r8](%0) \n\t"
3532 "mov %%r9, %c[r9](%0) \n\t"
3533 "mov %%r10, %c[r10](%0) \n\t"
3534 "mov %%r11, %c[r11](%0) \n\t"
3535 "mov %%r12, %c[r12](%0) \n\t"
3536 "mov %%r13, %c[r13](%0) \n\t"
3537 "mov %%r14, %c[r14](%0) \n\t"
3538 "mov %%r15, %c[r15](%0) \n\t"
3539 #endif
3540 "mov %%cr2, %%"R"ax \n\t"
3541 "mov %%"R"ax, %c[cr2](%0) \n\t"
3542
3543 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3544 "setbe %c[fail](%0) \n\t"
3545 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3546 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3547 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3548 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3549 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3550 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3551 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3552 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3553 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3554 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3555 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3556 #ifdef CONFIG_X86_64
3557 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3558 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3559 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3560 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3561 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3562 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3563 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3564 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3565 #endif
3566 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3567 : "cc", "memory"
3568 , R"bx", R"di", R"si"
3569 #ifdef CONFIG_X86_64
3570 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3571 #endif
3572 );
3573
3574 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3575 vcpu->arch.regs_dirty = 0;
3576
3577 get_debugreg(vcpu->arch.dr6, 6);
3578
3579 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3580 if (vmx->rmode.irq.pending)
3581 fixup_rmode_irq(vmx);
3582
3583 vmx_update_window_states(vcpu);
3584
3585 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3586 vmx->launched = 1;
3587
3588 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3589
3590 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3591
3592 /* Handle machine checks before interrupts are enabled */
3593 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) ||
3594 (intr_info & INTR_INFO_VECTOR_MASK) == MC_VECTOR)
3595 kvm_machine_check();
3596
3597 /* We need to handle NMIs before interrupts are enabled */
3598 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3599 (intr_info & INTR_INFO_VALID_MASK)) {
3600 KVMTRACE_0D(NMI, vcpu, handler);
3601 asm("int $2");
3602 }
3603
3604 vmx_complete_interrupts(vmx);
3605 }
3606
3607 #undef R
3608 #undef Q
3609
3610 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3611 {
3612 struct vcpu_vmx *vmx = to_vmx(vcpu);
3613
3614 if (vmx->vmcs) {
3615 vcpu_clear(vmx);
3616 free_vmcs(vmx->vmcs);
3617 vmx->vmcs = NULL;
3618 }
3619 }
3620
3621 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3622 {
3623 struct vcpu_vmx *vmx = to_vmx(vcpu);
3624
3625 spin_lock(&vmx_vpid_lock);
3626 if (vmx->vpid != 0)
3627 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3628 spin_unlock(&vmx_vpid_lock);
3629 vmx_free_vmcs(vcpu);
3630 kfree(vmx->host_msrs);
3631 kfree(vmx->guest_msrs);
3632 kvm_vcpu_uninit(vcpu);
3633 kmem_cache_free(kvm_vcpu_cache, vmx);
3634 }
3635
3636 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3637 {
3638 int err;
3639 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3640 int cpu;
3641
3642 if (!vmx)
3643 return ERR_PTR(-ENOMEM);
3644
3645 allocate_vpid(vmx);
3646
3647 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3648 if (err)
3649 goto free_vcpu;
3650
3651 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3652 if (!vmx->guest_msrs) {
3653 err = -ENOMEM;
3654 goto uninit_vcpu;
3655 }
3656
3657 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3658 if (!vmx->host_msrs)
3659 goto free_guest_msrs;
3660
3661 vmx->vmcs = alloc_vmcs();
3662 if (!vmx->vmcs)
3663 goto free_msrs;
3664
3665 vmcs_clear(vmx->vmcs);
3666
3667 cpu = get_cpu();
3668 vmx_vcpu_load(&vmx->vcpu, cpu);
3669 err = vmx_vcpu_setup(vmx);
3670 vmx_vcpu_put(&vmx->vcpu);
3671 put_cpu();
3672 if (err)
3673 goto free_vmcs;
3674 if (vm_need_virtualize_apic_accesses(kvm))
3675 if (alloc_apic_access_page(kvm) != 0)
3676 goto free_vmcs;
3677
3678 if (vm_need_ept())
3679 if (alloc_identity_pagetable(kvm) != 0)
3680 goto free_vmcs;
3681
3682 return &vmx->vcpu;
3683
3684 free_vmcs:
3685 free_vmcs(vmx->vmcs);
3686 free_msrs:
3687 kfree(vmx->host_msrs);
3688 free_guest_msrs:
3689 kfree(vmx->guest_msrs);
3690 uninit_vcpu:
3691 kvm_vcpu_uninit(&vmx->vcpu);
3692 free_vcpu:
3693 kmem_cache_free(kvm_vcpu_cache, vmx);
3694 return ERR_PTR(err);
3695 }
3696
3697 static void __init vmx_check_processor_compat(void *rtn)
3698 {
3699 struct vmcs_config vmcs_conf;
3700
3701 *(int *)rtn = 0;
3702 if (setup_vmcs_config(&vmcs_conf) < 0)
3703 *(int *)rtn = -EIO;
3704 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3705 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3706 smp_processor_id());
3707 *(int *)rtn = -EIO;
3708 }
3709 }
3710
3711 static int get_ept_level(void)
3712 {
3713 return VMX_EPT_DEFAULT_GAW + 1;
3714 }
3715
3716 static int vmx_get_mt_mask_shift(void)
3717 {
3718 return VMX_EPT_MT_EPTE_SHIFT;
3719 }
3720
3721 static struct kvm_x86_ops vmx_x86_ops = {
3722 .cpu_has_kvm_support = cpu_has_kvm_support,
3723 .disabled_by_bios = vmx_disabled_by_bios,
3724 .hardware_setup = hardware_setup,
3725 .hardware_unsetup = hardware_unsetup,
3726 .check_processor_compatibility = vmx_check_processor_compat,
3727 .hardware_enable = hardware_enable,
3728 .hardware_disable = hardware_disable,
3729 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3730
3731 .vcpu_create = vmx_create_vcpu,
3732 .vcpu_free = vmx_free_vcpu,
3733 .vcpu_reset = vmx_vcpu_reset,
3734
3735 .prepare_guest_switch = vmx_save_host_state,
3736 .vcpu_load = vmx_vcpu_load,
3737 .vcpu_put = vmx_vcpu_put,
3738
3739 .set_guest_debug = set_guest_debug,
3740 .get_msr = vmx_get_msr,
3741 .set_msr = vmx_set_msr,
3742 .get_segment_base = vmx_get_segment_base,
3743 .get_segment = vmx_get_segment,
3744 .set_segment = vmx_set_segment,
3745 .get_cpl = vmx_get_cpl,
3746 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3747 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3748 .set_cr0 = vmx_set_cr0,
3749 .set_cr3 = vmx_set_cr3,
3750 .set_cr4 = vmx_set_cr4,
3751 .set_efer = vmx_set_efer,
3752 .get_idt = vmx_get_idt,
3753 .set_idt = vmx_set_idt,
3754 .get_gdt = vmx_get_gdt,
3755 .set_gdt = vmx_set_gdt,
3756 .cache_reg = vmx_cache_reg,
3757 .get_rflags = vmx_get_rflags,
3758 .set_rflags = vmx_set_rflags,
3759
3760 .tlb_flush = vmx_flush_tlb,
3761
3762 .run = vmx_vcpu_run,
3763 .handle_exit = kvm_handle_exit,
3764 .skip_emulated_instruction = skip_emulated_instruction,
3765 .set_interrupt_shadow = vmx_set_interrupt_shadow,
3766 .get_interrupt_shadow = vmx_get_interrupt_shadow,
3767 .patch_hypercall = vmx_patch_hypercall,
3768 .get_irq = vmx_get_irq,
3769 .set_irq = vmx_inject_irq,
3770 .queue_exception = vmx_queue_exception,
3771 .exception_injected = vmx_exception_injected,
3772 .inject_pending_irq = vmx_intr_assist,
3773 .inject_pending_vectors = do_interrupt_requests,
3774
3775 .set_tss_addr = vmx_set_tss_addr,
3776 .get_tdp_level = get_ept_level,
3777 .get_mt_mask_shift = vmx_get_mt_mask_shift,
3778 };
3779
3780 static int __init vmx_init(void)
3781 {
3782 void *va;
3783 int r;
3784
3785 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3786 if (!vmx_io_bitmap_a)
3787 return -ENOMEM;
3788
3789 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3790 if (!vmx_io_bitmap_b) {
3791 r = -ENOMEM;
3792 goto out;
3793 }
3794
3795 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3796 if (!vmx_msr_bitmap) {
3797 r = -ENOMEM;
3798 goto out1;
3799 }
3800
3801 /*
3802 * Allow direct access to the PC debug port (it is often used for I/O
3803 * delays, but the vmexits simply slow things down).
3804 */
3805 va = kmap(vmx_io_bitmap_a);
3806 memset(va, 0xff, PAGE_SIZE);
3807 clear_bit(0x80, va);
3808 kunmap(vmx_io_bitmap_a);
3809
3810 va = kmap(vmx_io_bitmap_b);
3811 memset(va, 0xff, PAGE_SIZE);
3812 kunmap(vmx_io_bitmap_b);
3813
3814 va = kmap(vmx_msr_bitmap);
3815 memset(va, 0xff, PAGE_SIZE);
3816 kunmap(vmx_msr_bitmap);
3817
3818 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3819
3820 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3821 if (r)
3822 goto out2;
3823
3824 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3825 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3826 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3827 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3828 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3829
3830 if (vm_need_ept()) {
3831 bypass_guest_pf = 0;
3832 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3833 VMX_EPT_WRITABLE_MASK);
3834 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3835 VMX_EPT_EXECUTABLE_MASK,
3836 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3837 kvm_enable_tdp();
3838 } else
3839 kvm_disable_tdp();
3840
3841 if (bypass_guest_pf)
3842 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3843
3844 ept_sync_global();
3845
3846 return 0;
3847
3848 out2:
3849 __free_page(vmx_msr_bitmap);
3850 out1:
3851 __free_page(vmx_io_bitmap_b);
3852 out:
3853 __free_page(vmx_io_bitmap_a);
3854 return r;
3855 }
3856
3857 static void __exit vmx_exit(void)
3858 {
3859 __free_page(vmx_msr_bitmap);
3860 __free_page(vmx_io_bitmap_b);
3861 __free_page(vmx_io_bitmap_a);
3862
3863 kvm_exit();
3864 }
3865
3866 module_init(vmx_init)
3867 module_exit(vmx_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree