| blob | cabd8f556a1f71a2f87eddf166cadd5c02035b80 |
1 config ARM
2 bool
3 default y
4 select HAVE_AOUT
5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
7 select HAVE_MEMBLOCK
8 select RTC_LIB
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_ARCH_KGDB
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
20 select HAVE_GENERIC_DMA_COHERENT
21 select HAVE_KERNEL_GZIP
22 select HAVE_KERNEL_LZO
23 select HAVE_KERNEL_LZMA
24 select HAVE_IRQ_WORK
25 select HAVE_PERF_EVENTS
26 select PERF_USE_VMALLOC
27 select HAVE_REGS_AND_STACK_ACCESS_API
28 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
29 select HAVE_C_RECORDMCOUNT
30 select HAVE_GENERIC_HARDIRQS
31 select HAVE_SPARSE_IRQ
32 select GENERIC_IRQ_SHOW
33 select CPU_PM if (SUSPEND || CPU_IDLE)
34 select GENERIC_PCI_IOMAP
35 help
36 The ARM series is a line of low-power-consumption RISC chip designs
37 licensed by ARM Ltd and targeted at embedded applications and
38 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
39 manufactured, but legacy ARM-based PC hardware remains popular in
40 Europe. There is an ARM Linux project with a web page at
41 <http://www.arm.linux.org.uk/>.
43 config ARM_HAS_SG_CHAIN
44 bool
46 config HAVE_PWM
47 bool
49 config MIGHT_HAVE_PCI
50 bool
52 config SYS_SUPPORTS_APM_EMULATION
53 bool
55 config HAVE_SCHED_CLOCK
56 bool
58 config GENERIC_GPIO
59 bool
61 config ARCH_USES_GETTIMEOFFSET
62 bool
63 default n
65 config GENERIC_CLOCKEVENTS
66 bool
68 config GENERIC_CLOCKEVENTS_BROADCAST
69 bool
70 depends on GENERIC_CLOCKEVENTS
71 default y if SMP
73 config KTIME_SCALAR
74 bool
75 default y
77 config HAVE_TCM
78 bool
79 select GENERIC_ALLOCATOR
81 config HAVE_PROC_CPU
82 bool
84 config NO_IOPORT
85 bool
87 config EISA
88 bool
89 ---help---
90 The Extended Industry Standard Architecture (EISA) bus was
91 developed as an open alternative to the IBM MicroChannel bus.
93 The EISA bus provided some of the features of the IBM MicroChannel
94 bus while maintaining backward compatibility with cards made for
95 the older ISA bus. The EISA bus saw limited use between 1988 and
96 1995 when it was made obsolete by the PCI bus.
98 Say Y here if you are building a kernel for an EISA-based machine.
100 Otherwise, say N.
102 config SBUS
103 bool
105 config MCA
106 bool
107 help
108 MicroChannel Architecture is found in some IBM PS/2 machines and
109 laptops. It is a bus system similar to PCI or ISA. See
110 <file:Documentation/mca.txt> (and especially the web page given
111 there) before attempting to build an MCA bus kernel.
113 config STACKTRACE_SUPPORT
114 bool
115 default y
117 config HAVE_LATENCYTOP_SUPPORT
118 bool
119 depends on !SMP
120 default y
122 config LOCKDEP_SUPPORT
123 bool
124 default y
126 config TRACE_IRQFLAGS_SUPPORT
127 bool
128 default y
130 config HARDIRQS_SW_RESEND
131 bool
132 default y
134 config GENERIC_IRQ_PROBE
135 bool
136 default y
138 config GENERIC_LOCKBREAK
139 bool
140 default y
141 depends on SMP && PREEMPT
143 config RWSEM_GENERIC_SPINLOCK
144 bool
145 default y
147 config RWSEM_XCHGADD_ALGORITHM
148 bool
150 config ARCH_HAS_ILOG2_U32
151 bool
153 config ARCH_HAS_ILOG2_U64
154 bool
156 config ARCH_HAS_CPUFREQ
157 bool
158 help
159 Internal node to signify that the ARCH has CPUFREQ support
160 and that the relevant menu configurations are displayed for
161 it.
163 config ARCH_HAS_CPU_IDLE_WAIT
164 def_bool y
166 config GENERIC_HWEIGHT
167 bool
168 default y
170 config GENERIC_CALIBRATE_DELAY
171 bool
172 default y
174 config ARCH_MAY_HAVE_PC_FDC
175 bool
177 config ZONE_DMA
178 bool
180 config NEED_DMA_MAP_STATE
181 def_bool y
183 config GENERIC_ISA_DMA
184 bool
186 config FIQ
187 bool
189 config ARCH_MTD_XIP
190 bool
192 config VECTORS_BASE
193 hex
194 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
195 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 default 0x00000000
197 help
198 The base address of exception vectors.
200 config ARM_PATCH_PHYS_VIRT
201 bool "Patch physical to virtual translations at runtime" if EMBEDDED
202 default y
203 depends on !XIP_KERNEL && MMU
204 depends on !ARCH_REALVIEW || !SPARSEMEM
205 help
206 Patch phys-to-virt and virt-to-phys translation functions at
207 boot and module load time according to the position of the
208 kernel in system memory.
210 This can only be used with non-XIP MMU kernels where the base
211 of physical memory is at a 16MB boundary.
213 Only disable this option if you know that you do not require
214 this feature (eg, building a kernel for a single machine) and
215 you need to shrink the kernel to the minimal size.
217 config NEED_MACH_MEMORY_H
218 bool
219 help
220 Select this when mach/memory.h is required to provide special
221 definitions for this platform. The need for mach/memory.h should
222 be avoided when possible.
224 config PHYS_OFFSET
225 hex "Physical address of main memory" if MMU
226 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
227 default DRAM_BASE if !MMU
228 help
229 Please provide the physical address corresponding to the
230 location of main memory in your system.
232 config GENERIC_BUG
233 def_bool y
234 depends on BUG
236 source "init/Kconfig"
238 source "kernel/Kconfig.freezer"
240 menu "System Type"
242 config MMU
243 bool "MMU-based Paged Memory Management Support"
244 default y
245 help
246 Select if you want MMU-based virtualised addressing space
247 support by paged memory management. If unsure, say 'Y'.
249 #
250 # The "ARM system type" choice list is ordered alphabetically by option
251 # text. Please add new entries in the option alphabetic order.
252 #
253 choice
254 prompt "ARM system type"
255 default ARCH_VERSATILE
257 config ARCH_INTEGRATOR
258 bool "ARM Ltd. Integrator family"
259 select ARM_AMBA
260 select ARCH_HAS_CPUFREQ
261 select CLKDEV_LOOKUP
262 select HAVE_MACH_CLKDEV
263 select HAVE_TCM
264 select ICST
265 select GENERIC_CLOCKEVENTS
266 select PLAT_VERSATILE
267 select PLAT_VERSATILE_FPGA_IRQ
268 select NEED_MACH_MEMORY_H
269 help
270 Support for ARM's Integrator platform.
272 config ARCH_REALVIEW
273 bool "ARM Ltd. RealView family"
274 select ARM_AMBA
275 select CLKDEV_LOOKUP
276 select HAVE_MACH_CLKDEV
277 select ICST
278 select GENERIC_CLOCKEVENTS
279 select ARCH_WANT_OPTIONAL_GPIOLIB
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_CLCD
282 select ARM_TIMER_SP804
283 select GPIO_PL061 if GPIOLIB
284 select NEED_MACH_MEMORY_H
285 help
286 This enables support for ARM Ltd RealView boards.
288 config ARCH_VERSATILE
289 bool "ARM Ltd. Versatile family"
290 select ARM_AMBA
291 select ARM_VIC
292 select CLKDEV_LOOKUP
293 select HAVE_MACH_CLKDEV
294 select ICST
295 select GENERIC_CLOCKEVENTS
296 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select PLAT_VERSATILE
298 select PLAT_VERSATILE_CLCD
299 select PLAT_VERSATILE_FPGA_IRQ
300 select ARM_TIMER_SP804
301 help
302 This enables support for ARM Ltd Versatile board.
304 config ARCH_VEXPRESS
305 bool "ARM Ltd. Versatile Express family"
306 select ARCH_WANT_OPTIONAL_GPIOLIB
307 select ARM_AMBA
308 select ARM_TIMER_SP804
309 select CLKDEV_LOOKUP
310 select HAVE_MACH_CLKDEV
311 select GENERIC_CLOCKEVENTS
312 select HAVE_CLK
313 select HAVE_PATA_PLATFORM
314 select ICST
315 select PLAT_VERSATILE
316 select PLAT_VERSATILE_CLCD
317 help
318 This enables support for the ARM Ltd Versatile Express boards.
320 config ARCH_AT91
321 bool "Atmel AT91"
322 select ARCH_REQUIRE_GPIOLIB
323 select HAVE_CLK
324 select CLKDEV_LOOKUP
325 select IRQ_DOMAIN
326 help
327 This enables support for systems based on the Atmel AT91RM9200,
328 AT91SAM9 processors.
330 config ARCH_BCMRING
331 bool "Broadcom BCMRING"
332 depends on MMU
333 select CPU_V6
334 select ARM_AMBA
335 select ARM_TIMER_SP804
336 select CLKDEV_LOOKUP
337 select GENERIC_CLOCKEVENTS
338 select ARCH_WANT_OPTIONAL_GPIOLIB
339 help
340 Support for Broadcom's BCMRing platform.
342 config ARCH_HIGHBANK
343 bool "Calxeda Highbank-based"
344 select ARCH_WANT_OPTIONAL_GPIOLIB
345 select ARM_AMBA
346 select ARM_GIC
347 select ARM_TIMER_SP804
348 select CACHE_L2X0
349 select CLKDEV_LOOKUP
350 select CPU_V7
351 select GENERIC_CLOCKEVENTS
352 select HAVE_ARM_SCU
353 select HAVE_SMP
354 select USE_OF
355 help
356 Support for the Calxeda Highbank SoC based boards.
358 config ARCH_CLPS711X
359 bool "Cirrus Logic CLPS711x/EP721x-based"
360 select CPU_ARM720T
361 select ARCH_USES_GETTIMEOFFSET
362 select NEED_MACH_MEMORY_H
363 help
364 Support for Cirrus Logic 711x/721x based boards.
366 config ARCH_CNS3XXX
367 bool "Cavium Networks CNS3XXX family"
368 select CPU_V6K
369 select GENERIC_CLOCKEVENTS
370 select ARM_GIC
371 select MIGHT_HAVE_CACHE_L2X0
372 select MIGHT_HAVE_PCI
373 select PCI_DOMAINS if PCI
374 help
375 Support for Cavium Networks CNS3XXX platform.
377 config ARCH_GEMINI
378 bool "Cortina Systems Gemini"
379 select CPU_FA526
380 select ARCH_REQUIRE_GPIOLIB
381 select ARCH_USES_GETTIMEOFFSET
382 help
383 Support for the Cortina Systems Gemini family SoCs
385 config ARCH_PRIMA2
386 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
387 select CPU_V7
388 select NO_IOPORT
389 select GENERIC_CLOCKEVENTS
390 select CLKDEV_LOOKUP
391 select GENERIC_IRQ_CHIP
392 select MIGHT_HAVE_CACHE_L2X0
393 select USE_OF
394 select ZONE_DMA
395 help
396 Support for CSR SiRFSoC ARM Cortex A9 Platform
398 config ARCH_EBSA110
399 bool "EBSA-110"
400 select CPU_SA110
401 select ISA
402 select NO_IOPORT
403 select ARCH_USES_GETTIMEOFFSET
404 select NEED_MACH_MEMORY_H
405 help
406 This is an evaluation board for the StrongARM processor available
407 from Digital. It has limited hardware on-board, including an
408 Ethernet interface, two PCMCIA sockets, two serial ports and a
409 parallel port.
411 config ARCH_EP93XX
412 bool "EP93xx-based"
413 select CPU_ARM920T
414 select ARM_AMBA
415 select ARM_VIC
416 select CLKDEV_LOOKUP
417 select ARCH_REQUIRE_GPIOLIB
418 select ARCH_HAS_HOLES_MEMORYMODEL
419 select ARCH_USES_GETTIMEOFFSET
420 select NEED_MACH_MEMORY_H
421 help
422 This enables support for the Cirrus EP93xx series of CPUs.
424 config ARCH_FOOTBRIDGE
425 bool "FootBridge"
426 select CPU_SA110
427 select FOOTBRIDGE
428 select GENERIC_CLOCKEVENTS
429 select HAVE_IDE
430 select NEED_MACH_MEMORY_H
431 help
432 Support for systems based on the DC21285 companion chip
433 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
435 config ARCH_MXC
436 bool "Freescale MXC/iMX-based"
437 select GENERIC_CLOCKEVENTS
438 select ARCH_REQUIRE_GPIOLIB
439 select CLKDEV_LOOKUP
440 select CLKSRC_MMIO
441 select GENERIC_IRQ_CHIP
442 select HAVE_SCHED_CLOCK
443 select MULTI_IRQ_HANDLER
444 help
445 Support for Freescale MXC/iMX-based family of processors
447 config ARCH_MXS
448 bool "Freescale MXS-based"
449 select GENERIC_CLOCKEVENTS
450 select ARCH_REQUIRE_GPIOLIB
451 select CLKDEV_LOOKUP
452 select CLKSRC_MMIO
453 select HAVE_CLK_PREPARE
454 help
455 Support for Freescale MXS-based family of processors
457 config ARCH_NETX
458 bool "Hilscher NetX based"
459 select CLKSRC_MMIO
460 select CPU_ARM926T
461 select ARM_VIC
462 select GENERIC_CLOCKEVENTS
463 help
464 This enables support for systems based on the Hilscher NetX Soc
466 config ARCH_H720X
467 bool "Hynix HMS720x-based"
468 select CPU_ARM720T
469 select ISA_DMA_API
470 select ARCH_USES_GETTIMEOFFSET
471 help
472 This enables support for systems based on the Hynix HMS720x
474 config ARCH_IOP13XX
475 bool "IOP13xx-based"
476 depends on MMU
477 select CPU_XSC3
478 select PLAT_IOP
479 select PCI
480 select ARCH_SUPPORTS_MSI
481 select VMSPLIT_1G
482 select NEED_MACH_MEMORY_H
483 help
484 Support for Intel's IOP13XX (XScale) family of processors.
486 config ARCH_IOP32X
487 bool "IOP32x-based"
488 depends on MMU
489 select CPU_XSCALE
490 select PLAT_IOP
491 select PCI
492 select ARCH_REQUIRE_GPIOLIB
493 help
494 Support for Intel's 80219 and IOP32X (XScale) family of
495 processors.
497 config ARCH_IOP33X
498 bool "IOP33x-based"
499 depends on MMU
500 select CPU_XSCALE
501 select PLAT_IOP
502 select PCI
503 select ARCH_REQUIRE_GPIOLIB
504 help
505 Support for Intel's IOP33X (XScale) family of processors.
507 config ARCH_IXP23XX
508 bool "IXP23XX-based"
509 depends on MMU
510 select CPU_XSC3
511 select PCI
512 select ARCH_USES_GETTIMEOFFSET
513 select NEED_MACH_MEMORY_H
514 help
515 Support for Intel's IXP23xx (XScale) family of processors.
517 config ARCH_IXP2000
518 bool "IXP2400/2800-based"
519 depends on MMU
520 select CPU_XSCALE
521 select PCI
522 select ARCH_USES_GETTIMEOFFSET
523 select NEED_MACH_MEMORY_H
524 help
525 Support for Intel's IXP2400/2800 (XScale) family of processors.
527 config ARCH_IXP4XX
528 bool "IXP4xx-based"
529 depends on MMU
530 select CLKSRC_MMIO
531 select CPU_XSCALE
532 select GENERIC_GPIO
533 select GENERIC_CLOCKEVENTS
534 select HAVE_SCHED_CLOCK
535 select MIGHT_HAVE_PCI
536 select DMABOUNCE if PCI
537 help
538 Support for Intel's IXP4XX (XScale) family of processors.
540 config ARCH_DOVE
541 bool "Marvell Dove"
542 select CPU_V7
543 select PCI
544 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
546 select PLAT_ORION
547 help
548 Support for the Marvell Dove SoC 88AP510
550 config ARCH_KIRKWOOD
551 bool "Marvell Kirkwood"
552 select CPU_FEROCEON
553 select PCI
554 select ARCH_REQUIRE_GPIOLIB
555 select GENERIC_CLOCKEVENTS
556 select PLAT_ORION
557 help
558 Support for the following Marvell Kirkwood series SoCs:
559 88F6180, 88F6192 and 88F6281.
561 config ARCH_LPC32XX
562 bool "NXP LPC32XX"
563 select CLKSRC_MMIO
564 select CPU_ARM926T
565 select ARCH_REQUIRE_GPIOLIB
566 select HAVE_IDE
567 select ARM_AMBA
568 select USB_ARCH_HAS_OHCI
569 select CLKDEV_LOOKUP
570 select GENERIC_CLOCKEVENTS
571 help
572 Support for the NXP LPC32XX family of processors
574 config ARCH_MV78XX0
575 bool "Marvell MV78xx0"
576 select CPU_FEROCEON
577 select PCI
578 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
580 select PLAT_ORION
581 help
582 Support for the following Marvell MV78xx0 series SoCs:
583 MV781x0, MV782x0.
585 config ARCH_ORION5X
586 bool "Marvell Orion"
587 depends on MMU
588 select CPU_FEROCEON
589 select PCI
590 select ARCH_REQUIRE_GPIOLIB
591 select GENERIC_CLOCKEVENTS
592 select PLAT_ORION
593 help
594 Support for the following Marvell Orion 5x series SoCs:
595 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
596 Orion-2 (5281), Orion-1-90 (6183).
598 config ARCH_MMP
599 bool "Marvell PXA168/910/MMP2"
600 depends on MMU
601 select ARCH_REQUIRE_GPIOLIB
602 select CLKDEV_LOOKUP
603 select GENERIC_CLOCKEVENTS
604 select GPIO_PXA
605 select HAVE_SCHED_CLOCK
606 select TICK_ONESHOT
607 select PLAT_PXA
608 select SPARSE_IRQ
609 select GENERIC_ALLOCATOR
610 help
611 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
613 config ARCH_KS8695
614 bool "Micrel/Kendin KS8695"
615 select CPU_ARM922T
616 select ARCH_REQUIRE_GPIOLIB
617 select ARCH_USES_GETTIMEOFFSET
618 select NEED_MACH_MEMORY_H
619 help
620 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
621 System-on-Chip devices.
623 config ARCH_W90X900
624 bool "Nuvoton W90X900 CPU"
625 select CPU_ARM926T
626 select ARCH_REQUIRE_GPIOLIB
627 select CLKDEV_LOOKUP
628 select CLKSRC_MMIO
629 select GENERIC_CLOCKEVENTS
630 help
631 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
632 At present, the w90x900 has been renamed nuc900, regarding
633 the ARM series product line, you can login the following
634 link address to know more.
636 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
637 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
639 config ARCH_TEGRA
640 bool "NVIDIA Tegra"
641 select CLKDEV_LOOKUP
642 select CLKSRC_MMIO
643 select GENERIC_CLOCKEVENTS
644 select GENERIC_GPIO
645 select HAVE_CLK
646 select HAVE_SCHED_CLOCK
647 select HAVE_SMP
648 select MIGHT_HAVE_CACHE_L2X0
649 select ARCH_HAS_CPUFREQ
650 help
651 This enables support for NVIDIA Tegra based systems (Tegra APX,
652 Tegra 6xx and Tegra 2 series).
654 config ARCH_PICOXCELL
655 bool "Picochip picoXcell"
656 select ARCH_REQUIRE_GPIOLIB
657 select ARM_PATCH_PHYS_VIRT
658 select ARM_VIC
659 select CPU_V6K
660 select DW_APB_TIMER
661 select GENERIC_CLOCKEVENTS
662 select GENERIC_GPIO
663 select HAVE_SCHED_CLOCK
664 select HAVE_TCM
665 select NO_IOPORT
666 select SPARSE_IRQ
667 select USE_OF
668 help
669 This enables support for systems based on the Picochip picoXcell
670 family of Femtocell devices. The picoxcell support requires device tree
671 for all boards.
673 config ARCH_PNX4008
674 bool "Philips Nexperia PNX4008 Mobile"
675 select CPU_ARM926T
676 select CLKDEV_LOOKUP
677 select ARCH_USES_GETTIMEOFFSET
678 help
679 This enables support for Philips PNX4008 mobile platform.
681 config ARCH_PXA
682 bool "PXA2xx/PXA3xx-based"
683 depends on MMU
684 select ARCH_MTD_XIP
685 select ARCH_HAS_CPUFREQ
686 select CLKDEV_LOOKUP
687 select CLKSRC_MMIO
688 select ARCH_REQUIRE_GPIOLIB
689 select GENERIC_CLOCKEVENTS
690 select GPIO_PXA
691 select HAVE_SCHED_CLOCK
692 select TICK_ONESHOT
693 select PLAT_PXA
694 select SPARSE_IRQ
695 select AUTO_ZRELADDR
696 select MULTI_IRQ_HANDLER
697 select ARM_CPU_SUSPEND if PM
698 select HAVE_IDE
699 help
700 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
702 config ARCH_MSM
703 bool "Qualcomm MSM"
704 select HAVE_CLK
705 select GENERIC_CLOCKEVENTS
706 select ARCH_REQUIRE_GPIOLIB
707 select CLKDEV_LOOKUP
708 help
709 Support for Qualcomm MSM/QSD based systems. This runs on the
710 apps processor of the MSM/QSD and depends on a shared memory
711 interface to the modem processor which runs the baseband
712 stack and controls some vital subsystems
713 (clock and power control, etc).
715 config ARCH_SHMOBILE
716 bool "Renesas SH-Mobile / R-Mobile"
717 select HAVE_CLK
718 select CLKDEV_LOOKUP
719 select HAVE_MACH_CLKDEV
720 select HAVE_SMP
721 select GENERIC_CLOCKEVENTS
722 select MIGHT_HAVE_CACHE_L2X0
723 select NO_IOPORT
724 select SPARSE_IRQ
725 select MULTI_IRQ_HANDLER
726 select PM_GENERIC_DOMAINS if PM
727 select NEED_MACH_MEMORY_H
728 help
729 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
731 config ARCH_RPC
732 bool "RiscPC"
733 select ARCH_ACORN
734 select FIQ
735 select TIMER_ACORN
736 select ARCH_MAY_HAVE_PC_FDC
737 select HAVE_PATA_PLATFORM
738 select ISA_DMA_API
739 select NO_IOPORT
740 select ARCH_SPARSEMEM_ENABLE
741 select ARCH_USES_GETTIMEOFFSET
742 select HAVE_IDE
743 select NEED_MACH_MEMORY_H
744 help
745 On the Acorn Risc-PC, Linux can support the internal IDE disk and
746 CD-ROM interface, serial and parallel port, and the floppy drive.
748 config ARCH_SA1100
749 bool "SA1100-based"
750 select CLKSRC_MMIO
751 select CPU_SA1100
752 select ISA
753 select ARCH_SPARSEMEM_ENABLE
754 select ARCH_MTD_XIP
755 select ARCH_HAS_CPUFREQ
756 select CPU_FREQ
757 select GENERIC_CLOCKEVENTS
758 select HAVE_CLK
759 select HAVE_SCHED_CLOCK
760 select TICK_ONESHOT
761 select ARCH_REQUIRE_GPIOLIB
762 select HAVE_IDE
763 select NEED_MACH_MEMORY_H
764 help
765 Support for StrongARM 11x0 based boards.
767 config ARCH_S3C2410
768 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
769 select GENERIC_GPIO
770 select ARCH_HAS_CPUFREQ
771 select HAVE_CLK
772 select CLKDEV_LOOKUP
773 select ARCH_USES_GETTIMEOFFSET
774 select HAVE_S3C2410_I2C if I2C
775 help
776 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
777 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
778 the Samsung SMDK2410 development board (and derivatives).
780 Note, the S3C2416 and the S3C2450 are so close that they even share
781 the same SoC ID code. This means that there is no separate machine
782 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
784 config ARCH_S3C64XX
785 bool "Samsung S3C64XX"
786 select PLAT_SAMSUNG
787 select CPU_V6
788 select ARM_VIC
789 select HAVE_CLK
790 select HAVE_TCM
791 select CLKDEV_LOOKUP
792 select NO_IOPORT
793 select ARCH_USES_GETTIMEOFFSET
794 select ARCH_HAS_CPUFREQ
795 select ARCH_REQUIRE_GPIOLIB
796 select SAMSUNG_CLKSRC
797 select SAMSUNG_IRQ_VIC_TIMER
798 select S3C_GPIO_TRACK
799 select S3C_DEV_NAND
800 select USB_ARCH_HAS_OHCI
801 select SAMSUNG_GPIOLIB_4BIT
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C2410_WATCHDOG if WATCHDOG
804 help
805 Samsung S3C64XX series based systems
807 config ARCH_S5P64X0
808 bool "Samsung S5P6440 S5P6450"
809 select CPU_V6
810 select GENERIC_GPIO
811 select HAVE_CLK
812 select CLKDEV_LOOKUP
813 select CLKSRC_MMIO
814 select HAVE_S3C2410_WATCHDOG if WATCHDOG
815 select GENERIC_CLOCKEVENTS
816 select HAVE_SCHED_CLOCK
817 select HAVE_S3C2410_I2C if I2C
818 select HAVE_S3C_RTC if RTC_CLASS
819 help
820 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
821 SMDK6450.
823 config ARCH_S5PC100
824 bool "Samsung S5PC100"
825 select GENERIC_GPIO
826 select HAVE_CLK
827 select CLKDEV_LOOKUP
828 select CPU_V7
829 select ARCH_USES_GETTIMEOFFSET
830 select HAVE_S3C2410_I2C if I2C
831 select HAVE_S3C_RTC if RTC_CLASS
832 select HAVE_S3C2410_WATCHDOG if WATCHDOG
833 help
834 Samsung S5PC100 series based systems
836 config ARCH_S5PV210
837 bool "Samsung S5PV210/S5PC110"
838 select CPU_V7
839 select ARCH_SPARSEMEM_ENABLE
840 select ARCH_HAS_HOLES_MEMORYMODEL
841 select GENERIC_GPIO
842 select HAVE_CLK
843 select CLKDEV_LOOKUP
844 select CLKSRC_MMIO
845 select ARCH_HAS_CPUFREQ
846 select GENERIC_CLOCKEVENTS
847 select HAVE_SCHED_CLOCK
848 select HAVE_S3C2410_I2C if I2C
849 select HAVE_S3C_RTC if RTC_CLASS
850 select HAVE_S3C2410_WATCHDOG if WATCHDOG
851 select NEED_MACH_MEMORY_H
852 help
853 Samsung S5PV210/S5PC110 series based systems
855 config ARCH_EXYNOS
856 bool "SAMSUNG EXYNOS"
857 select CPU_V7
858 select ARCH_SPARSEMEM_ENABLE
859 select ARCH_HAS_HOLES_MEMORYMODEL
860 select GENERIC_GPIO
861 select HAVE_CLK
862 select CLKDEV_LOOKUP
863 select ARCH_HAS_CPUFREQ
864 select GENERIC_CLOCKEVENTS
865 select HAVE_S3C_RTC if RTC_CLASS
866 select HAVE_S3C2410_I2C if I2C
867 select HAVE_S3C2410_WATCHDOG if WATCHDOG
868 select NEED_MACH_MEMORY_H
869 help
870 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
872 config ARCH_SHARK
873 bool "Shark"
874 select CPU_SA110
875 select ISA
876 select ISA_DMA
877 select ZONE_DMA
878 select PCI
879 select ARCH_USES_GETTIMEOFFSET
880 select NEED_MACH_MEMORY_H
881 help
882 Support for the StrongARM based Digital DNARD machine, also known
883 as "Shark" (<http://www.shark-linux.de/shark.html>).
885 config ARCH_U300
886 bool "ST-Ericsson U300 Series"
887 depends on MMU
888 select CLKSRC_MMIO
889 select CPU_ARM926T
890 select HAVE_SCHED_CLOCK
891 select HAVE_TCM
892 select ARM_AMBA
893 select ARM_PATCH_PHYS_VIRT
894 select ARM_VIC
895 select GENERIC_CLOCKEVENTS
896 select CLKDEV_LOOKUP
897 select HAVE_MACH_CLKDEV
898 select GENERIC_GPIO
899 select ARCH_REQUIRE_GPIOLIB
900 help
901 Support for ST-Ericsson U300 series mobile platforms.
903 config ARCH_U8500
904 bool "ST-Ericsson U8500 Series"
905 select CPU_V7
906 select ARM_AMBA
907 select GENERIC_CLOCKEVENTS
908 select CLKDEV_LOOKUP
909 select ARCH_REQUIRE_GPIOLIB
910 select ARCH_HAS_CPUFREQ
911 select HAVE_SMP
912 select MIGHT_HAVE_CACHE_L2X0
913 help
914 Support for ST-Ericsson's Ux500 architecture
916 config ARCH_NOMADIK
917 bool "STMicroelectronics Nomadik"
918 select ARM_AMBA
919 select ARM_VIC
920 select CPU_ARM926T
921 select CLKDEV_LOOKUP
922 select GENERIC_CLOCKEVENTS
923 select MIGHT_HAVE_CACHE_L2X0
924 select ARCH_REQUIRE_GPIOLIB
925 help
926 Support for the Nomadik platform by ST-Ericsson
928 config ARCH_DAVINCI
929 bool "TI DaVinci"
930 select GENERIC_CLOCKEVENTS
931 select ARCH_REQUIRE_GPIOLIB
932 select ZONE_DMA
933 select HAVE_IDE
934 select CLKDEV_LOOKUP
935 select GENERIC_ALLOCATOR
936 select GENERIC_IRQ_CHIP
937 select ARCH_HAS_HOLES_MEMORYMODEL
938 help
939 Support for TI's DaVinci platform.
941 config ARCH_OMAP
942 bool "TI OMAP"
943 select HAVE_CLK
944 select ARCH_REQUIRE_GPIOLIB
945 select ARCH_HAS_CPUFREQ
946 select CLKSRC_MMIO
947 select GENERIC_CLOCKEVENTS
948 select HAVE_SCHED_CLOCK
949 select ARCH_HAS_HOLES_MEMORYMODEL
950 help
951 Support for TI's OMAP platform (OMAP1/2/3/4).
953 config PLAT_SPEAR
954 bool "ST SPEAr"
955 select ARM_AMBA
956 select ARCH_REQUIRE_GPIOLIB
957 select CLKDEV_LOOKUP
958 select CLKSRC_MMIO
959 select GENERIC_CLOCKEVENTS
960 select HAVE_CLK
961 help
962 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
964 config ARCH_VT8500
965 bool "VIA/WonderMedia 85xx"
966 select CPU_ARM926T
967 select GENERIC_GPIO
968 select ARCH_HAS_CPUFREQ
969 select GENERIC_CLOCKEVENTS
970 select ARCH_REQUIRE_GPIOLIB
971 select HAVE_PWM
972 help
973 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
975 config ARCH_ZYNQ
976 bool "Xilinx Zynq ARM Cortex A9 Platform"
977 select CPU_V7
978 select GENERIC_CLOCKEVENTS
979 select CLKDEV_LOOKUP
980 select ARM_GIC
981 select ARM_AMBA
982 select ICST
983 select MIGHT_HAVE_CACHE_L2X0
984 select USE_OF
985 help
986 Support for Xilinx Zynq ARM Cortex A9 Platform
987 endchoice
989 #
990 # This is sorted alphabetically by mach-* pathname. However, plat-*
991 # Kconfigs may be included either alphabetically (according to the
992 # plat- suffix) or along side the corresponding mach-* source.
993 #
994 source "arch/arm/mach-at91/Kconfig"
996 source "arch/arm/mach-bcmring/Kconfig"
998 source "arch/arm/mach-clps711x/Kconfig"
1000 source "arch/arm/mach-cns3xxx/Kconfig"
1002 source "arch/arm/mach-davinci/Kconfig"
1004 source "arch/arm/mach-dove/Kconfig"
1006 source "arch/arm/mach-ep93xx/Kconfig"
1008 source "arch/arm/mach-footbridge/Kconfig"
1010 source "arch/arm/mach-gemini/Kconfig"
1012 source "arch/arm/mach-h720x/Kconfig"
1014 source "arch/arm/mach-integrator/Kconfig"
1016 source "arch/arm/mach-iop32x/Kconfig"
1018 source "arch/arm/mach-iop33x/Kconfig"
1020 source "arch/arm/mach-iop13xx/Kconfig"
1022 source "arch/arm/mach-ixp4xx/Kconfig"
1024 source "arch/arm/mach-ixp2000/Kconfig"
1026 source "arch/arm/mach-ixp23xx/Kconfig"
1028 source "arch/arm/mach-kirkwood/Kconfig"
1030 source "arch/arm/mach-ks8695/Kconfig"
1032 source "arch/arm/mach-lpc32xx/Kconfig"
1034 source "arch/arm/mach-msm/Kconfig"
1036 source "arch/arm/mach-mv78xx0/Kconfig"
1038 source "arch/arm/plat-mxc/Kconfig"
1040 source "arch/arm/mach-mxs/Kconfig"
1042 source "arch/arm/mach-netx/Kconfig"
1044 source "arch/arm/mach-nomadik/Kconfig"
1045 source "arch/arm/plat-nomadik/Kconfig"
1047 source "arch/arm/plat-omap/Kconfig"
1049 source "arch/arm/mach-omap1/Kconfig"
1051 source "arch/arm/mach-omap2/Kconfig"
1053 source "arch/arm/mach-orion5x/Kconfig"
1055 source "arch/arm/mach-pxa/Kconfig"
1056 source "arch/arm/plat-pxa/Kconfig"
1058 source "arch/arm/mach-mmp/Kconfig"
1060 source "arch/arm/mach-realview/Kconfig"
1062 source "arch/arm/mach-sa1100/Kconfig"
1064 source "arch/arm/plat-samsung/Kconfig"
1065 source "arch/arm/plat-s3c24xx/Kconfig"
1066 source "arch/arm/plat-s5p/Kconfig"
1068 source "arch/arm/plat-spear/Kconfig"
1070 if ARCH_S3C2410
1071 source "arch/arm/mach-s3c2410/Kconfig"
1072 source "arch/arm/mach-s3c2412/Kconfig"
1073 source "arch/arm/mach-s3c2416/Kconfig"
1074 source "arch/arm/mach-s3c2440/Kconfig"
1075 source "arch/arm/mach-s3c2443/Kconfig"
1076 endif
1078 if ARCH_S3C64XX
1079 source "arch/arm/mach-s3c64xx/Kconfig"
1080 endif
1082 source "arch/arm/mach-s5p64x0/Kconfig"
1084 source "arch/arm/mach-s5pc100/Kconfig"
1086 source "arch/arm/mach-s5pv210/Kconfig"
1088 source "arch/arm/mach-exynos/Kconfig"
1090 source "arch/arm/mach-shmobile/Kconfig"
1092 source "arch/arm/mach-tegra/Kconfig"
1094 source "arch/arm/mach-u300/Kconfig"
1096 source "arch/arm/mach-ux500/Kconfig"
1098 source "arch/arm/mach-versatile/Kconfig"
1100 source "arch/arm/mach-vexpress/Kconfig"
1101 source "arch/arm/plat-versatile/Kconfig"
1103 source "arch/arm/mach-vt8500/Kconfig"
1105 source "arch/arm/mach-w90x900/Kconfig"
1107 # Definitions to make life easier
1108 config ARCH_ACORN
1109 bool
1111 config PLAT_IOP
1112 bool
1113 select GENERIC_CLOCKEVENTS
1114 select HAVE_SCHED_CLOCK
1116 config PLAT_ORION
1117 bool
1118 select CLKSRC_MMIO
1119 select GENERIC_IRQ_CHIP
1120 select HAVE_SCHED_CLOCK
1122 config PLAT_PXA
1123 bool
1125 config PLAT_VERSATILE
1126 bool
1128 config ARM_TIMER_SP804
1129 bool
1130 select CLKSRC_MMIO
1132 source arch/arm/mm/Kconfig
1134 config ARM_NR_BANKS
1135 int
1136 default 16 if ARCH_EP93XX
1137 default 8
1139 config IWMMXT
1140 bool "Enable iWMMXt support"
1141 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1142 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1143 help
1144 Enable support for iWMMXt context switching at run time if
1145 running on a CPU that supports it.
1147 config XSCALE_PMU
1148 bool
1149 depends on CPU_XSCALE
1150 default y
1152 config CPU_HAS_PMU
1153 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1154 (!ARCH_OMAP3 || OMAP3_EMU)
1155 default y
1156 bool
1158 config MULTI_IRQ_HANDLER
1159 bool
1160 help
1161 Allow each machine to specify it's own IRQ handler at run time.
1163 if !MMU
1164 source "arch/arm/Kconfig-nommu"
1165 endif
1167 config ARM_ERRATA_411920
1168 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1169 depends on CPU_V6 || CPU_V6K
1170 help
1171 Invalidation of the Instruction Cache operation can
1172 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1173 It does not affect the MPCore. This option enables the ARM Ltd.
1174 recommended workaround.
1176 config ARM_ERRATA_430973
1177 bool "ARM errata: Stale prediction on replaced interworking branch"
1178 depends on CPU_V7
1179 help
1180 This option enables the workaround for the 430973 Cortex-A8
1181 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1182 interworking branch is replaced with another code sequence at the
1183 same virtual address, whether due to self-modifying code or virtual
1184 to physical address re-mapping, Cortex-A8 does not recover from the
1185 stale interworking branch prediction. This results in Cortex-A8
1186 executing the new code sequence in the incorrect ARM or Thumb state.
1187 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1188 and also flushes the branch target cache at every context switch.
1189 Note that setting specific bits in the ACTLR register may not be
1190 available in non-secure mode.
1192 config ARM_ERRATA_458693
1193 bool "ARM errata: Processor deadlock when a false hazard is created"
1194 depends on CPU_V7
1195 help
1196 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1197 erratum. For very specific sequences of memory operations, it is
1198 possible for a hazard condition intended for a cache line to instead
1199 be incorrectly associated with a different cache line. This false
1200 hazard might then cause a processor deadlock. The workaround enables
1201 the L1 caching of the NEON accesses and disables the PLD instruction
1202 in the ACTLR register. Note that setting specific bits in the ACTLR
1203 register may not be available in non-secure mode.
1205 config ARM_ERRATA_460075
1206 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1207 depends on CPU_V7
1208 help
1209 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1210 erratum. Any asynchronous access to the L2 cache may encounter a
1211 situation in which recent store transactions to the L2 cache are lost
1212 and overwritten with stale memory contents from external memory. The
1213 workaround disables the write-allocate mode for the L2 cache via the
1214 ACTLR register. Note that setting specific bits in the ACTLR register
1215 may not be available in non-secure mode.
1217 config ARM_ERRATA_742230
1218 bool "ARM errata: DMB operation may be faulty"
1219 depends on CPU_V7 && SMP
1220 help
1221 This option enables the workaround for the 742230 Cortex-A9
1222 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1223 between two write operations may not ensure the correct visibility
1224 ordering of the two writes. This workaround sets a specific bit in
1225 the diagnostic register of the Cortex-A9 which causes the DMB
1226 instruction to behave as a DSB, ensuring the correct behaviour of
1227 the two writes.
1229 config ARM_ERRATA_742231
1230 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1231 depends on CPU_V7 && SMP
1232 help
1233 This option enables the workaround for the 742231 Cortex-A9
1234 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1235 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1236 accessing some data located in the same cache line, may get corrupted
1237 data due to bad handling of the address hazard when the line gets
1238 replaced from one of the CPUs at the same time as another CPU is
1239 accessing it. This workaround sets specific bits in the diagnostic
1240 register of the Cortex-A9 which reduces the linefill issuing
1241 capabilities of the processor.
1243 config PL310_ERRATA_588369
1244 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1245 depends on CACHE_L2X0
1246 help
1247 The PL310 L2 cache controller implements three types of Clean &
1248 Invalidate maintenance operations: by Physical Address
1249 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1250 They are architecturally defined to behave as the execution of a
1251 clean operation followed immediately by an invalidate operation,
1252 both performing to the same memory location. This functionality
1253 is not correctly implemented in PL310 as clean lines are not
1254 invalidated as a result of these operations.
1256 config ARM_ERRATA_720789
1257 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1258 depends on CPU_V7
1259 help
1260 This option enables the workaround for the 720789 Cortex-A9 (prior to
1261 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1262 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1263 As a consequence of this erratum, some TLB entries which should be
1264 invalidated are not, resulting in an incoherency in the system page
1265 tables. The workaround changes the TLB flushing routines to invalidate
1266 entries regardless of the ASID.
1268 config PL310_ERRATA_727915
1269 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1270 depends on CACHE_L2X0
1271 help
1272 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1273 operation (offset 0x7FC). This operation runs in background so that
1274 PL310 can handle normal accesses while it is in progress. Under very
1275 rare circumstances, due to this erratum, write data can be lost when
1276 PL310 treats a cacheable write transaction during a Clean &
1277 Invalidate by Way operation.
1279 config ARM_ERRATA_743622
1280 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1281 depends on CPU_V7
1282 help
1283 This option enables the workaround for the 743622 Cortex-A9
1284 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1285 optimisation in the Cortex-A9 Store Buffer may lead to data
1286 corruption. This workaround sets a specific bit in the diagnostic
1287 register of the Cortex-A9 which disables the Store Buffer
1288 optimisation, preventing the defect from occurring. This has no
1289 visible impact on the overall performance or power consumption of the
1290 processor.
1292 config ARM_ERRATA_751472
1293 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1294 depends on CPU_V7
1295 help
1296 This option enables the workaround for the 751472 Cortex-A9 (prior
1297 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1298 completion of a following broadcasted operation if the second
1299 operation is received by a CPU before the ICIALLUIS has completed,
1300 potentially leading to corrupted entries in the cache or TLB.
1302 config PL310_ERRATA_753970
1303 bool "PL310 errata: cache sync operation may be faulty"
1304 depends on CACHE_PL310
1305 help
1306 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1308 Under some condition the effect of cache sync operation on
1309 the store buffer still remains when the operation completes.
1310 This means that the store buffer is always asked to drain and
1311 this prevents it from merging any further writes. The workaround
1312 is to replace the normal offset of cache sync operation (0x730)
1313 by another offset targeting an unmapped PL310 register 0x740.
1314 This has the same effect as the cache sync operation: store buffer
1315 drain and waiting for all buffers empty.
1317 config ARM_ERRATA_754322
1318 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1319 depends on CPU_V7
1320 help
1321 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1322 r3p*) erratum. A speculative memory access may cause a page table walk
1323 which starts prior to an ASID switch but completes afterwards. This
1324 can populate the micro-TLB with a stale entry which may be hit with
1325 the new ASID. This workaround places two dsb instructions in the mm
1326 switching code so that no page table walks can cross the ASID switch.
1328 config ARM_ERRATA_754327
1329 bool "ARM errata: no automatic Store Buffer drain"
1330 depends on CPU_V7 && SMP
1331 help
1332 This option enables the workaround for the 754327 Cortex-A9 (prior to
1333 r2p0) erratum. The Store Buffer does not have any automatic draining
1334 mechanism and therefore a livelock may occur if an external agent
1335 continuously polls a memory location waiting to observe an update.
1336 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1337 written polling loops from denying visibility of updates to memory.
1339 config ARM_ERRATA_364296
1340 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1341 depends on CPU_V6 && !SMP
1342 help
1343 This options enables the workaround for the 364296 ARM1136
1344 r0p2 erratum (possible cache data corruption with
1345 hit-under-miss enabled). It sets the undocumented bit 31 in
1346 the auxiliary control register and the FI bit in the control
1347 register, thus disabling hit-under-miss without putting the
1348 processor into full low interrupt latency mode. ARM11MPCore
1349 is not affected.
1351 config ARM_ERRATA_764369
1352 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1353 depends on CPU_V7 && SMP
1354 help
1355 This option enables the workaround for erratum 764369
1356 affecting Cortex-A9 MPCore with two or more processors (all
1357 current revisions). Under certain timing circumstances, a data
1358 cache line maintenance operation by MVA targeting an Inner
1359 Shareable memory region may fail to proceed up to either the
1360 Point of Coherency or to the Point of Unification of the
1361 system. This workaround adds a DSB instruction before the
1362 relevant cache maintenance functions and sets a specific bit
1363 in the diagnostic control register of the SCU.
1365 config PL310_ERRATA_769419
1366 bool "PL310 errata: no automatic Store Buffer drain"
1367 depends on CACHE_L2X0
1368 help
1369 On revisions of the PL310 prior to r3p2, the Store Buffer does
1370 not automatically drain. This can cause normal, non-cacheable
1371 writes to be retained when the memory system is idle, leading
1372 to suboptimal I/O performance for drivers using coherent DMA.
1373 This option adds a write barrier to the cpu_idle loop so that,
1374 on systems with an outer cache, the store buffer is drained
1375 explicitly.
1377 endmenu
1379 source "arch/arm/common/Kconfig"
1381 menu "Bus support"
1383 config ARM_AMBA
1384 bool
1386 config ISA
1387 bool
1388 help
1389 Find out whether you have ISA slots on your motherboard. ISA is the
1390 name of a bus system, i.e. the way the CPU talks to the other stuff
1391 inside your box. Other bus systems are PCI, EISA, MicroChannel
1392 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1393 newer boards don't support it. If you have ISA, say Y, otherwise N.
1395 # Select ISA DMA controller support
1396 config ISA_DMA
1397 bool
1398 select ISA_DMA_API
1400 # Select ISA DMA interface
1401 config ISA_DMA_API
1402 bool
1404 config PCI
1405 bool "PCI support" if MIGHT_HAVE_PCI
1406 help
1407 Find out whether you have a PCI motherboard. PCI is the name of a
1408 bus system, i.e. the way the CPU talks to the other stuff inside
1409 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1410 VESA. If you have PCI, say Y, otherwise N.
1412 config PCI_DOMAINS
1413 bool
1414 depends on PCI
1416 config PCI_NANOENGINE
1417 bool "BSE nanoEngine PCI support"
1418 depends on SA1100_NANOENGINE
1419 help
1420 Enable PCI on the BSE nanoEngine board.
1422 config PCI_SYSCALL
1423 def_bool PCI
1425 # Select the host bridge type
1426 config PCI_HOST_VIA82C505
1427 bool
1428 depends on PCI && ARCH_SHARK
1429 default y
1431 config PCI_HOST_ITE8152
1432 bool
1433 depends on PCI && MACH_ARMCORE
1434 default y
1435 select DMABOUNCE
1437 source "drivers/pci/Kconfig"
1439 source "drivers/pcmcia/Kconfig"
1441 endmenu
1443 menu "Kernel Features"
1445 source "kernel/time/Kconfig"
1447 config HAVE_SMP
1448 bool
1449 help
1450 This option should be selected by machines which have an SMP-
1451 capable CPU.
1453 The only effect of this option is to make the SMP-related
1454 options available to the user for configuration.
1456 config SMP
1457 bool "Symmetric Multi-Processing"
1458 depends on CPU_V6K || CPU_V7
1459 depends on GENERIC_CLOCKEVENTS
1460 depends on HAVE_SMP
1461 depends on MMU
1462 select USE_GENERIC_SMP_HELPERS
1463 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1464 help
1465 This enables support for systems with more than one CPU. If you have
1466 a system with only one CPU, like most personal computers, say N. If
1467 you have a system with more than one CPU, say Y.
1469 If you say N here, the kernel will run on single and multiprocessor
1470 machines, but will use only one CPU of a multiprocessor machine. If
1471 you say Y here, the kernel will run on many, but not all, single
1472 processor machines. On a single processor machine, the kernel will
1473 run faster if you say N here.
1475 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1476 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1477 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1479 If you don't know what to do here, say N.
1481 config SMP_ON_UP
1482 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1483 depends on EXPERIMENTAL
1484 depends on SMP && !XIP_KERNEL
1485 default y
1486 help
1487 SMP kernels contain instructions which fail on non-SMP processors.
1488 Enabling this option allows the kernel to modify itself to make
1489 these instructions safe. Disabling it allows about 1K of space
1490 savings.
1492 If you don't know what to do here, say Y.
1494 config ARM_CPU_TOPOLOGY
1495 bool "Support cpu topology definition"
1496 depends on SMP && CPU_V7
1497 default y
1498 help
1499 Support ARM cpu topology definition. The MPIDR register defines
1500 affinity between processors which is then used to describe the cpu
1501 topology of an ARM System.
1503 config SCHED_MC
1504 bool "Multi-core scheduler support"
1505 depends on ARM_CPU_TOPOLOGY
1506 help
1507 Multi-core scheduler support improves the CPU scheduler's decision
1508 making when dealing with multi-core CPU chips at a cost of slightly
1509 increased overhead in some places. If unsure say N here.
1511 config SCHED_SMT
1512 bool "SMT scheduler support"
1513 depends on ARM_CPU_TOPOLOGY
1514 help
1515 Improves the CPU scheduler's decision making when dealing with
1516 MultiThreading at a cost of slightly increased overhead in some
1517 places. If unsure say N here.
1519 config HAVE_ARM_SCU
1520 bool
1521 help
1522 This option enables support for the ARM system coherency unit
1524 config HAVE_ARM_TWD
1525 bool
1526 depends on SMP
1527 select TICK_ONESHOT
1528 help
1529 This options enables support for the ARM timer and watchdog unit
1531 choice
1532 prompt "Memory split"
1533 default VMSPLIT_3G
1534 help
1535 Select the desired split between kernel and user memory.
1537 If you are not absolutely sure what you are doing, leave this
1538 option alone!
1540 config VMSPLIT_3G
1541 bool "3G/1G user/kernel split"
1542 config VMSPLIT_2G
1543 bool "2G/2G user/kernel split"
1544 config VMSPLIT_1G
1545 bool "1G/3G user/kernel split"
1546 endchoice
1548 config PAGE_OFFSET
1549 hex
1550 default 0x40000000 if VMSPLIT_1G
1551 default 0x80000000 if VMSPLIT_2G
1552 default 0xC0000000
1554 config NR_CPUS
1555 int "Maximum number of CPUs (2-32)"
1556 range 2 32
1557 depends on SMP
1558 default "4"
1560 config HOTPLUG_CPU
1561 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1562 depends on SMP && HOTPLUG && EXPERIMENTAL
1563 help
1564 Say Y here to experiment with turning CPUs off and on. CPUs
1565 can be controlled through /sys/devices/system/cpu.
1567 config LOCAL_TIMERS
1568 bool "Use local timer interrupts"
1569 depends on SMP
1570 default y
1571 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1572 help
1573 Enable support for local timers on SMP platforms, rather then the
1574 legacy IPI broadcast method. Local timers allows the system
1575 accounting to be spread across the timer interval, preventing a
1576 "thundering herd" at every timer tick.
1578 config ARCH_NR_GPIO
1579 int
1580 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1581 default 350 if ARCH_U8500
1582 default 0
1583 help
1584 Maximum number of GPIOs in the system.
1586 If unsure, leave the default value.
1588 source kernel/Kconfig.preempt
1590 config HZ
1591 int
1592 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1593 ARCH_S5PV210 || ARCH_EXYNOS4
1594 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1595 default AT91_TIMER_HZ if ARCH_AT91
1596 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1597 default 100
1599 config THUMB2_KERNEL
1600 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1601 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1602 select AEABI
1603 select ARM_ASM_UNIFIED
1604 select ARM_UNWIND
1605 help
1606 By enabling this option, the kernel will be compiled in
1607 Thumb-2 mode. A compiler/assembler that understand the unified
1608 ARM-Thumb syntax is needed.
1610 If unsure, say N.
1612 config THUMB2_AVOID_R_ARM_THM_JUMP11
1613 bool "Work around buggy Thumb-2 short branch relocations in gas"
1614 depends on THUMB2_KERNEL && MODULES
1615 default y
1616 help
1617 Various binutils versions can resolve Thumb-2 branches to
1618 locally-defined, preemptible global symbols as short-range "b.n"
1619 branch instructions.
1621 This is a problem, because there's no guarantee the final
1622 destination of the symbol, or any candidate locations for a
1623 trampoline, are within range of the branch. For this reason, the
1624 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1625 relocation in modules at all, and it makes little sense to add
1626 support.
1628 The symptom is that the kernel fails with an "unsupported
1629 relocation" error when loading some modules.
1631 Until fixed tools are available, passing
1632 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1633 code which hits this problem, at the cost of a bit of extra runtime
1634 stack usage in some cases.
1636 The problem is described in more detail at:
1637 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1639 Only Thumb-2 kernels are affected.
1641 Unless you are sure your tools don't have this problem, say Y.
1643 config ARM_ASM_UNIFIED
1644 bool
1646 config AEABI
1647 bool "Use the ARM EABI to compile the kernel"
1648 help
1649 This option allows for the kernel to be compiled using the latest
1650 ARM ABI (aka EABI). This is only useful if you are using a user
1651 space environment that is also compiled with EABI.
1653 Since there are major incompatibilities between the legacy ABI and
1654 EABI, especially with regard to structure member alignment, this
1655 option also changes the kernel syscall calling convention to
1656 disambiguate both ABIs and allow for backward compatibility support
1657 (selected with CONFIG_OABI_COMPAT).
1659 To use this you need GCC version 4.0.0 or later.
1661 config OABI_COMPAT
1662 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1663 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1664 default y
1665 help
1666 This option preserves the old syscall interface along with the
1667 new (ARM EABI) one. It also provides a compatibility layer to
1668 intercept syscalls that have structure arguments which layout
1669 in memory differs between the legacy ABI and the new ARM EABI
1670 (only for non "thumb" binaries). This option adds a tiny
1671 overhead to all syscalls and produces a slightly larger kernel.
1672 If you know you'll be using only pure EABI user space then you
1673 can say N here. If this option is not selected and you attempt
1674 to execute a legacy ABI binary then the result will be
1675 UNPREDICTABLE (in fact it can be predicted that it won't work
1676 at all). If in doubt say Y.
1678 config ARCH_HAS_HOLES_MEMORYMODEL
1679 bool
1681 config ARCH_SPARSEMEM_ENABLE
1682 bool
1684 config ARCH_SPARSEMEM_DEFAULT
1685 def_bool ARCH_SPARSEMEM_ENABLE
1687 config ARCH_SELECT_MEMORY_MODEL
1688 def_bool ARCH_SPARSEMEM_ENABLE
1690 config HAVE_ARCH_PFN_VALID
1691 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1693 config HIGHMEM
1694 bool "High Memory Support"
1695 depends on MMU
1696 help
1697 The address space of ARM processors is only 4 Gigabytes large
1698 and it has to accommodate user address space, kernel address
1699 space as well as some memory mapped IO. That means that, if you
1700 have a large amount of physical memory and/or IO, not all of the
1701 memory can be "permanently mapped" by the kernel. The physical
1702 memory that is not permanently mapped is called "high memory".
1704 Depending on the selected kernel/user memory split, minimum
1705 vmalloc space and actual amount of RAM, you may not need this
1706 option which should result in a slightly faster kernel.
1708 If unsure, say n.
1710 config HIGHPTE
1711 bool "Allocate 2nd-level pagetables from highmem"
1712 depends on HIGHMEM
1714 config HW_PERF_EVENTS
1715 bool "Enable hardware performance counter support for perf events"
1716 depends on PERF_EVENTS && CPU_HAS_PMU
1717 default y
1718 help
1719 Enable hardware performance counter support for perf events. If
1720 disabled, perf events will use software events only.
1722 source "mm/Kconfig"
1724 config FORCE_MAX_ZONEORDER
1725 int "Maximum zone order" if ARCH_SHMOBILE
1726 range 11 64 if ARCH_SHMOBILE
1727 default "9" if SA1111
1728 default "11"
1729 help
1730 The kernel memory allocator divides physically contiguous memory
1731 blocks into "zones", where each zone is a power of two number of
1732 pages. This option selects the largest power of two that the kernel
1733 keeps in the memory allocator. If you need to allocate very large
1734 blocks of physically contiguous memory, then you may need to
1735 increase this value.
1737 This config option is actually maximum order plus one. For example,
1738 a value of 11 means that the largest free memory block is 2^10 pages.
1740 config LEDS
1741 bool "Timer and CPU usage LEDs"
1742 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1743 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1744 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1745 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1746 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1747 ARCH_AT91 || ARCH_DAVINCI || \
1748 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1749 help
1750 If you say Y here, the LEDs on your machine will be used
1751 to provide useful information about your current system status.
1753 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1754 be able to select which LEDs are active using the options below. If
1755 you are compiling a kernel for the EBSA-110 or the LART however, the
1756 red LED will simply flash regularly to indicate that the system is
1757 still functional. It is safe to say Y here if you have a CATS
1758 system, but the driver will do nothing.
1760 config LEDS_TIMER
1761 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1762 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1763 || MACH_OMAP_PERSEUS2
1764 depends on LEDS
1765 depends on !GENERIC_CLOCKEVENTS
1766 default y if ARCH_EBSA110
1767 help
1768 If you say Y here, one of the system LEDs (the green one on the
1769 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1770 will flash regularly to indicate that the system is still
1771 operational. This is mainly useful to kernel hackers who are
1772 debugging unstable kernels.
1774 The LART uses the same LED for both Timer LED and CPU usage LED
1775 functions. You may choose to use both, but the Timer LED function
1776 will overrule the CPU usage LED.
1778 config LEDS_CPU
1779 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1780 !ARCH_OMAP) \
1781 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1782 || MACH_OMAP_PERSEUS2
1783 depends on LEDS
1784 help
1785 If you say Y here, the red LED will be used to give a good real
1786 time indication of CPU usage, by lighting whenever the idle task
1787 is not currently executing.
1789 The LART uses the same LED for both Timer LED and CPU usage LED
1790 functions. You may choose to use both, but the Timer LED function
1791 will overrule the CPU usage LED.
1793 config ALIGNMENT_TRAP
1794 bool
1795 depends on CPU_CP15_MMU
1796 default y if !ARCH_EBSA110
1797 select HAVE_PROC_CPU if PROC_FS
1798 help
1799 ARM processors cannot fetch/store information which is not
1800 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1801 address divisible by 4. On 32-bit ARM processors, these non-aligned
1802 fetch/store instructions will be emulated in software if you say
1803 here, which has a severe performance impact. This is necessary for
1804 correct operation of some network protocols. With an IP-only
1805 configuration it is safe to say N, otherwise say Y.
1807 config UACCESS_WITH_MEMCPY
1808 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1809 depends on MMU && EXPERIMENTAL
1810 default y if CPU_FEROCEON
1811 help
1812 Implement faster copy_to_user and clear_user methods for CPU
1813 cores where a 8-word STM instruction give significantly higher
1814 memory write throughput than a sequence of individual 32bit stores.
1816 A possible side effect is a slight increase in scheduling latency
1817 between threads sharing the same address space if they invoke
1818 such copy operations with large buffers.
1820 However, if the CPU data cache is using a write-allocate mode,
1821 this option is unlikely to provide any performance gain.
1823 config SECCOMP
1824 bool
1825 prompt "Enable seccomp to safely compute untrusted bytecode"
1826 ---help---
1827 This kernel feature is useful for number crunching applications
1828 that may need to compute untrusted bytecode during their
1829 execution. By using pipes or other transports made available to
1830 the process as file descriptors supporting the read/write
1831 syscalls, it's possible to isolate those applications in
1832 their own address space using seccomp. Once seccomp is
1833 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1834 and the task is only allowed to execute a few safe syscalls
1835 defined by each seccomp mode.
1837 config CC_STACKPROTECTOR
1838 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1839 depends on EXPERIMENTAL
1840 help
1841 This option turns on the -fstack-protector GCC feature. This
1842 feature puts, at the beginning of functions, a canary value on
1843 the stack just before the return address, and validates
1844 the value just before actually returning. Stack based buffer
1845 overflows (that need to overwrite this return address) now also
1846 overwrite the canary, which gets detected and the attack is then
1847 neutralized via a kernel panic.
1848 This feature requires gcc version 4.2 or above.
1850 config DEPRECATED_PARAM_STRUCT
1851 bool "Provide old way to pass kernel parameters"
1852 help
1853 This was deprecated in 2001 and announced to live on for 5 years.
1854 Some old boot loaders still use this way.
1856 endmenu
1858 menu "Boot options"
1860 config USE_OF
1861 bool "Flattened Device Tree support"
1862 select OF
1863 select OF_EARLY_FLATTREE
1864 select IRQ_DOMAIN
1865 help
1866 Include support for flattened device tree machine descriptions.
1868 # Compressed boot loader in ROM. Yes, we really want to ask about
1869 # TEXT and BSS so we preserve their values in the config files.
1870 config ZBOOT_ROM_TEXT
1871 hex "Compressed ROM boot loader base address"
1872 default "0"
1873 help
1874 The physical address at which the ROM-able zImage is to be
1875 placed in the target. Platforms which normally make use of
1876 ROM-able zImage formats normally set this to a suitable
1877 value in their defconfig file.
1879 If ZBOOT_ROM is not enabled, this has no effect.
1881 config ZBOOT_ROM_BSS
1882 hex "Compressed ROM boot loader BSS address"
1883 default "0"
1884 help
1885 The base address of an area of read/write memory in the target
1886 for the ROM-able zImage which must be available while the
1887 decompressor is running. It must be large enough to hold the
1888 entire decompressed kernel plus an additional 128 KiB.
1889 Platforms which normally make use of ROM-able zImage formats
1890 normally set this to a suitable value in their defconfig file.
1892 If ZBOOT_ROM is not enabled, this has no effect.
1894 config ZBOOT_ROM
1895 bool "Compressed boot loader in ROM/flash"
1896 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1897 help
1898 Say Y here if you intend to execute your compressed kernel image
1899 (zImage) directly from ROM or flash. If unsure, say N.
1901 choice
1902 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1903 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1904 default ZBOOT_ROM_NONE
1905 help
1906 Include experimental SD/MMC loading code in the ROM-able zImage.
1907 With this enabled it is possible to write the the ROM-able zImage
1908 kernel image to an MMC or SD card and boot the kernel straight
1909 from the reset vector. At reset the processor Mask ROM will load
1910 the first part of the the ROM-able zImage which in turn loads the
1911 rest the kernel image to RAM.
1913 config ZBOOT_ROM_NONE
1914 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1915 help
1916 Do not load image from SD or MMC
1918 config ZBOOT_ROM_MMCIF
1919 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1920 help
1921 Load image from MMCIF hardware block.
1923 config ZBOOT_ROM_SH_MOBILE_SDHI
1924 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1925 help
1926 Load image from SDHI hardware block
1928 endchoice
1930 config ARM_APPENDED_DTB
1931 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1932 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1933 help
1934 With this option, the boot code will look for a device tree binary
1935 (DTB) appended to zImage
1936 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1938 This is meant as a backward compatibility convenience for those
1939 systems with a bootloader that can't be upgraded to accommodate
1940 the documented boot protocol using a device tree.
1942 Beware that there is very little in terms of protection against
1943 this option being confused by leftover garbage in memory that might
1944 look like a DTB header after a reboot if no actual DTB is appended
1945 to zImage. Do not leave this option active in a production kernel
1946 if you don't intend to always append a DTB. Proper passing of the
1947 location into r2 of a bootloader provided DTB is always preferable
1948 to this option.
1950 config ARM_ATAG_DTB_COMPAT
1951 bool "Supplement the appended DTB with traditional ATAG information"
1952 depends on ARM_APPENDED_DTB
1953 help
1954 Some old bootloaders can't be updated to a DTB capable one, yet
1955 they provide ATAGs with memory configuration, the ramdisk address,
1956 the kernel cmdline string, etc. Such information is dynamically
1957 provided by the bootloader and can't always be stored in a static
1958 DTB. To allow a device tree enabled kernel to be used with such
1959 bootloaders, this option allows zImage to extract the information
1960 from the ATAG list and store it at run time into the appended DTB.
1962 config CMDLINE
1963 string "Default kernel command string"
1964 default ""
1965 help
1966 On some architectures (EBSA110 and CATS), there is currently no way
1967 for the boot loader to pass arguments to the kernel. For these
1968 architectures, you should supply some command-line options at build
1969 time by entering them here. As a minimum, you should specify the
1970 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1972 choice
1973 prompt "Kernel command line type" if CMDLINE != ""
1974 default CMDLINE_FROM_BOOTLOADER
1976 config CMDLINE_FROM_BOOTLOADER
1977 bool "Use bootloader kernel arguments if available"
1978 help
1979 Uses the command-line options passed by the boot loader. If
1980 the boot loader doesn't provide any, the default kernel command
1981 string provided in CMDLINE will be used.
1983 config CMDLINE_EXTEND
1984 bool "Extend bootloader kernel arguments"
1985 help
1986 The command-line arguments provided by the boot loader will be
1987 appended to the default kernel command string.
1989 config CMDLINE_FORCE
1990 bool "Always use the default kernel command string"
1991 help
1992 Always use the default kernel command string, even if the boot
1993 loader passes other arguments to the kernel.
1994 This is useful if you cannot or don't want to change the
1995 command-line options your boot loader passes to the kernel.
1996 endchoice
1998 config XIP_KERNEL
1999 bool "Kernel Execute-In-Place from ROM"
2000 depends on !ZBOOT_ROM && !ARM_LPAE
2001 help
2002 Execute-In-Place allows the kernel to run from non-volatile storage
2003 directly addressable by the CPU, such as NOR flash. This saves RAM
2004 space since the text section of the kernel is not loaded from flash
2005 to RAM. Read-write sections, such as the data section and stack,
2006 are still copied to RAM. The XIP kernel is not compressed since
2007 it has to run directly from flash, so it will take more space to
2008 store it. The flash address used to link the kernel object files,
2009 and for storing it, is configuration dependent. Therefore, if you
2010 say Y here, you must know the proper physical address where to
2011 store the kernel image depending on your own flash memory usage.
2013 Also note that the make target becomes "make xipImage" rather than
2014 "make zImage" or "make Image". The final kernel binary to put in
2015 ROM memory will be arch/arm/boot/xipImage.
2017 If unsure, say N.
2019 config XIP_PHYS_ADDR
2020 hex "XIP Kernel Physical Location"
2021 depends on XIP_KERNEL
2022 default "0x00080000"
2023 help
2024 This is the physical address in your flash memory the kernel will
2025 be linked for and stored to. This address is dependent on your
2026 own flash usage.
2028 config KEXEC
2029 bool "Kexec system call (EXPERIMENTAL)"
2030 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2031 help
2032 kexec is a system call that implements the ability to shutdown your
2033 current kernel, and to start another kernel. It is like a reboot
2034 but it is independent of the system firmware. And like a reboot
2035 you can start any kernel with it, not just Linux.
2037 It is an ongoing process to be certain the hardware in a machine
2038 is properly shutdown, so do not be surprised if this code does not
2039 initially work for you. It may help to enable device hotplugging
2040 support.
2042 config ATAGS_PROC
2043 bool "Export atags in procfs"
2044 depends on KEXEC
2045 default y
2046 help
2047 Should the atags used to boot the kernel be exported in an "atags"
2048 file in procfs. Useful with kexec.
2050 config CRASH_DUMP
2051 bool "Build kdump crash kernel (EXPERIMENTAL)"
2052 depends on EXPERIMENTAL
2053 help
2054 Generate crash dump after being started by kexec. This should
2055 be normally only set in special crash dump kernels which are
2056 loaded in the main kernel with kexec-tools into a specially
2057 reserved region and then later executed after a crash by
2058 kdump/kexec. The crash dump kernel must be compiled to a
2059 memory address not used by the main kernel
2061 For more details see Documentation/kdump/kdump.txt
2063 config AUTO_ZRELADDR
2064 bool "Auto calculation of the decompressed kernel image address"
2065 depends on !ZBOOT_ROM && !ARCH_U300
2066 help
2067 ZRELADDR is the physical address where the decompressed kernel
2068 image will be placed. If AUTO_ZRELADDR is selected, the address
2069 will be determined at run-time by masking the current IP with
2070 0xf8000000. This assumes the zImage being placed in the first 128MB
2071 from start of memory.
2073 endmenu
2075 menu "CPU Power Management"
2077 if ARCH_HAS_CPUFREQ
2079 source "drivers/cpufreq/Kconfig"
2081 config CPU_FREQ_IMX
2082 tristate "CPUfreq driver for i.MX CPUs"
2083 depends on ARCH_MXC && CPU_FREQ
2084 help
2085 This enables the CPUfreq driver for i.MX CPUs.
2087 config CPU_FREQ_SA1100
2088 bool
2090 config CPU_FREQ_SA1110
2091 bool
2093 config CPU_FREQ_INTEGRATOR
2094 tristate "CPUfreq driver for ARM Integrator CPUs"
2095 depends on ARCH_INTEGRATOR && CPU_FREQ
2096 default y
2097 help
2098 This enables the CPUfreq driver for ARM Integrator CPUs.
2100 For details, take a look at <file:Documentation/cpu-freq>.
2102 If in doubt, say Y.
2104 config CPU_FREQ_PXA
2105 bool
2106 depends on CPU_FREQ && ARCH_PXA && PXA25x
2107 default y
2108 select CPU_FREQ_TABLE
2109 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2111 config CPU_FREQ_S3C
2112 bool
2113 help
2114 Internal configuration node for common cpufreq on Samsung SoC
2116 config CPU_FREQ_S3C24XX
2117 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2118 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2119 select CPU_FREQ_S3C
2120 help
2121 This enables the CPUfreq driver for the Samsung S3C24XX family
2122 of CPUs.
2124 For details, take a look at <file:Documentation/cpu-freq>.
2126 If in doubt, say N.
2128 config CPU_FREQ_S3C24XX_PLL
2129 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2130 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2131 help
2132 Compile in support for changing the PLL frequency from the
2133 S3C24XX series CPUfreq driver. The PLL takes time to settle
2134 after a frequency change, so by default it is not enabled.
2136 This also means that the PLL tables for the selected CPU(s) will
2137 be built which may increase the size of the kernel image.
2139 config CPU_FREQ_S3C24XX_DEBUG
2140 bool "Debug CPUfreq Samsung driver core"
2141 depends on CPU_FREQ_S3C24XX
2142 help
2143 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2145 config CPU_FREQ_S3C24XX_IODEBUG
2146 bool "Debug CPUfreq Samsung driver IO timing"
2147 depends on CPU_FREQ_S3C24XX
2148 help
2149 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2151 config CPU_FREQ_S3C24XX_DEBUGFS
2152 bool "Export debugfs for CPUFreq"
2153 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2154 help
2155 Export status information via debugfs.
2157 endif
2159 source "drivers/cpuidle/Kconfig"
2161 endmenu
2163 menu "Floating point emulation"
2165 comment "At least one emulation must be selected"
2167 config FPE_NWFPE
2168 bool "NWFPE math emulation"
2169 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2170 ---help---
2171 Say Y to include the NWFPE floating point emulator in the kernel.
2172 This is necessary to run most binaries. Linux does not currently
2173 support floating point hardware so you need to say Y here even if
2174 your machine has an FPA or floating point co-processor podule.
2176 You may say N here if you are going to load the Acorn FPEmulator
2177 early in the bootup.
2179 config FPE_NWFPE_XP
2180 bool "Support extended precision"
2181 depends on FPE_NWFPE
2182 help
2183 Say Y to include 80-bit support in the kernel floating-point
2184 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2185 Note that gcc does not generate 80-bit operations by default,
2186 so in most cases this option only enlarges the size of the
2187 floating point emulator without any good reason.
2189 You almost surely want to say N here.
2191 config FPE_FASTFPE
2192 bool "FastFPE math emulation (EXPERIMENTAL)"
2193 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2194 ---help---
2195 Say Y here to include the FAST floating point emulator in the kernel.
2196 This is an experimental much faster emulator which now also has full
2197 precision for the mantissa. It does not support any exceptions.
2198 It is very simple, and approximately 3-6 times faster than NWFPE.
2200 It should be sufficient for most programs. It may be not suitable
2201 for scientific calculations, but you have to check this for yourself.
2202 If you do not feel you need a faster FP emulation you should better
2203 choose NWFPE.
2205 config VFP
2206 bool "VFP-format floating point maths"
2207 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2208 help
2209 Say Y to include VFP support code in the kernel. This is needed
2210 if your hardware includes a VFP unit.
2212 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2213 release notes and additional status information.
2215 Say N if your target does not have VFP hardware.
2217 config VFPv3
2218 bool
2219 depends on VFP
2220 default y if CPU_V7
2222 config NEON
2223 bool "Advanced SIMD (NEON) Extension support"
2224 depends on VFPv3 && CPU_V7
2225 help
2226 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2227 Extension.
2229 endmenu
2231 menu "Userspace binary formats"
2233 source "fs/Kconfig.binfmt"
2235 config ARTHUR
2236 tristate "RISC OS personality"
2237 depends on !AEABI
2238 help
2239 Say Y here to include the kernel code necessary if you want to run
2240 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2241 experimental; if this sounds frightening, say N and sleep in peace.
2242 You can also say M here to compile this support as a module (which
2243 will be called arthur).
2245 endmenu
2247 menu "Power management options"
2249 source "kernel/power/Kconfig"
2251 config ARCH_SUSPEND_POSSIBLE
2252 depends on !ARCH_S5PC100
2253 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2254 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2255 def_bool y
2257 config ARM_CPU_SUSPEND
2258 def_bool PM_SLEEP
2260 endmenu
2262 source "net/Kconfig"
2264 source "drivers/Kconfig"
2266 source "fs/Kconfig"
2268 source "arch/arm/Kconfig.debug"
2270 source "security/Kconfig"
2272 source "crypto/Kconfig"
2274 source "lib/Kconfig"