include/video/omapdss.h

   1 /*
   2  * Copyright (C) 2008 Nokia Corporation
   3  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __OMAP_OMAPDSS_H
  19 #define __OMAP_OMAPDSS_H
  20
  21 #include <linux/list.h>
  22 #include <linux/kobject.h>
  23 #include <linux/device.h>
  24 #include <linux/interrupt.h>
  25
  26 #define DISPC_IRQ_FRAMEDONE             (1 << 0)
  27 #define DISPC_IRQ_VSYNC                 (1 << 1)
  28 #define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
  29 #define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
  30 #define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
  31 #define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
  32 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
  33 #define DISPC_IRQ_GFX_END_WIN           (1 << 7)
  34 #define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
  35 #define DISPC_IRQ_OCP_ERR               (1 << 9)
  36 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
  37 #define DISPC_IRQ_VID1_END_WIN          (1 << 11)
  38 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
  39 #define DISPC_IRQ_VID2_END_WIN          (1 << 13)
  40 #define DISPC_IRQ_SYNC_LOST             (1 << 14)
  41 #define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
  42 #define DISPC_IRQ_WAKEUP                (1 << 16)
  43 #define DISPC_IRQ_SYNC_LOST2            (1 << 17)
  44 #define DISPC_IRQ_VSYNC2                (1 << 18)
  45 #define DISPC_IRQ_VID3_END_WIN          (1 << 19)
  46 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW   (1 << 20)
  47 #define DISPC_IRQ_ACBIAS_COUNT_STAT2    (1 << 21)
  48 #define DISPC_IRQ_FRAMEDONE2            (1 << 22)
  49 #define DISPC_IRQ_FRAMEDONEWB           (1 << 23)
  50 #define DISPC_IRQ_FRAMEDONETV           (1 << 24)
  51 #define DISPC_IRQ_WBBUFFEROVERFLOW      (1 << 25)
  52 #define DISPC_IRQ_SYNC_LOST3            (1 << 27)
  53 #define DISPC_IRQ_VSYNC3                (1 << 28)
  54 #define DISPC_IRQ_ACBIAS_COUNT_STAT3    (1 << 29)
  55 #define DISPC_IRQ_FRAMEDONE3            (1 << 30)
  56
  57 struct omap_dss_device;
  58 struct omap_overlay_manager;
  59 struct dss_lcd_mgr_config;
  60 struct snd_aes_iec958;
  61 struct snd_cea_861_aud_if;
  62
  63 enum omap_display_type {
  64         OMAP_DISPLAY_TYPE_NONE          = 0,
  65         OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
  66         OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
  67         OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
  68         OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
  69         OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
  70         OMAP_DISPLAY_TYPE_HDMI          = 1 << 5,
  71 };
  72
  73 enum omap_plane {
  74         OMAP_DSS_GFX    = 0,
  75         OMAP_DSS_VIDEO1 = 1,
  76         OMAP_DSS_VIDEO2 = 2,
  77         OMAP_DSS_VIDEO3 = 3,
  78         OMAP_DSS_WB     = 4,
  79 };
  80
  81 enum omap_channel {
  82         OMAP_DSS_CHANNEL_LCD    = 0,
  83         OMAP_DSS_CHANNEL_DIGIT  = 1,
  84         OMAP_DSS_CHANNEL_LCD2   = 2,
  85         OMAP_DSS_CHANNEL_LCD3   = 3,
  86 };
  87
  88 enum omap_color_mode {
  89         OMAP_DSS_COLOR_CLUT1    = 1 << 0,  /* BITMAP 1 */
  90         OMAP_DSS_COLOR_CLUT2    = 1 << 1,  /* BITMAP 2 */
  91         OMAP_DSS_COLOR_CLUT4    = 1 << 2,  /* BITMAP 4 */
  92         OMAP_DSS_COLOR_CLUT8    = 1 << 3,  /* BITMAP 8 */
  93         OMAP_DSS_COLOR_RGB12U   = 1 << 4,  /* RGB12, 16-bit container */
  94         OMAP_DSS_COLOR_ARGB16   = 1 << 5,  /* ARGB16 */
  95         OMAP_DSS_COLOR_RGB16    = 1 << 6,  /* RGB16 */
  96         OMAP_DSS_COLOR_RGB24U   = 1 << 7,  /* RGB24, 32-bit container */
  97         OMAP_DSS_COLOR_RGB24P   = 1 << 8,  /* RGB24, 24-bit container */
  98         OMAP_DSS_COLOR_YUV2     = 1 << 9,  /* YUV2 4:2:2 co-sited */
  99         OMAP_DSS_COLOR_UYVY     = 1 << 10, /* UYVY 4:2:2 co-sited */
 100         OMAP_DSS_COLOR_ARGB32   = 1 << 11, /* ARGB32 */
 101         OMAP_DSS_COLOR_RGBA32   = 1 << 12, /* RGBA32 */
 102         OMAP_DSS_COLOR_RGBX32   = 1 << 13, /* RGBx32 */
 103         OMAP_DSS_COLOR_NV12             = 1 << 14, /* NV12 format: YUV 4:2:0 */
 104         OMAP_DSS_COLOR_RGBA16           = 1 << 15, /* RGBA16 - 4444 */
 105         OMAP_DSS_COLOR_RGBX16           = 1 << 16, /* RGBx16 - 4444 */
 106         OMAP_DSS_COLOR_ARGB16_1555      = 1 << 17, /* ARGB16 - 1555 */
 107         OMAP_DSS_COLOR_XRGB16_1555      = 1 << 18, /* xRGB16 - 1555 */
 108 };
 109
 110 enum omap_dss_load_mode {
 111         OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
 112         OMAP_DSS_LOAD_CLUT_ONLY         = 1,
 113         OMAP_DSS_LOAD_FRAME_ONLY        = 2,
 114         OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
 115 };
 116
 117 enum omap_dss_trans_key_type {
 118         OMAP_DSS_COLOR_KEY_GFX_DST = 0,
 119         OMAP_DSS_COLOR_KEY_VID_SRC = 1,
 120 };
 121
 122 enum omap_rfbi_te_mode {
 123         OMAP_DSS_RFBI_TE_MODE_1 = 1,
 124         OMAP_DSS_RFBI_TE_MODE_2 = 2,
 125 };
 126
 127 enum omap_dss_signal_level {
 128         OMAPDSS_SIG_ACTIVE_HIGH = 0,
 129         OMAPDSS_SIG_ACTIVE_LOW  = 1,
 130 };
 131
 132 enum omap_dss_signal_edge {
 133         OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
 134         OMAPDSS_DRIVE_SIG_RISING_EDGE,
 135         OMAPDSS_DRIVE_SIG_FALLING_EDGE,
 136 };
 137
 138 enum omap_dss_venc_type {
 139         OMAP_DSS_VENC_TYPE_COMPOSITE,
 140         OMAP_DSS_VENC_TYPE_SVIDEO,
 141 };
 142
 143 enum omap_dss_dsi_pixel_format {
 144         OMAP_DSS_DSI_FMT_RGB888,
 145         OMAP_DSS_DSI_FMT_RGB666,
 146         OMAP_DSS_DSI_FMT_RGB666_PACKED,
 147         OMAP_DSS_DSI_FMT_RGB565,
 148 };
 149
 150 enum omap_dss_dsi_mode {
 151         OMAP_DSS_DSI_CMD_MODE = 0,
 152         OMAP_DSS_DSI_VIDEO_MODE,
 153 };
 154
 155 enum omap_display_caps {
 156         OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE      = 1 << 0,
 157         OMAP_DSS_DISPLAY_CAP_TEAR_ELIM          = 1 << 1,
 158 };
 159
 160 enum omap_dss_display_state {
 161         OMAP_DSS_DISPLAY_DISABLED = 0,
 162         OMAP_DSS_DISPLAY_ACTIVE,
 163 };
 164
 165 enum omap_dss_audio_state {
 166         OMAP_DSS_AUDIO_DISABLED = 0,
 167         OMAP_DSS_AUDIO_ENABLED,
 168         OMAP_DSS_AUDIO_CONFIGURED,
 169         OMAP_DSS_AUDIO_PLAYING,
 170 };
 171
 172 enum omap_dss_rotation_type {
 173         OMAP_DSS_ROT_DMA        = 1 << 0,
 174         OMAP_DSS_ROT_VRFB       = 1 << 1,
 175         OMAP_DSS_ROT_TILER      = 1 << 2,
 176 };
 177
 178 /* clockwise rotation angle */
 179 enum omap_dss_rotation_angle {
 180         OMAP_DSS_ROT_0   = 0,
 181         OMAP_DSS_ROT_90  = 1,
 182         OMAP_DSS_ROT_180 = 2,
 183         OMAP_DSS_ROT_270 = 3,
 184 };
 185
 186 enum omap_overlay_caps {
 187         OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
 188         OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
 189         OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
 190         OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
 191         OMAP_DSS_OVL_CAP_POS = 1 << 4,
 192         OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
 193 };
 194
 195 enum omap_overlay_manager_caps {
 196         OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
 197 };
 198
 199 enum omap_dss_clk_source {
 200         OMAP_DSS_CLK_SRC_FCK = 0,               /* OMAP2/3: DSS1_ALWON_FCLK
 201                                                  * OMAP4: DSS_FCLK */
 202         OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,   /* OMAP3: DSI1_PLL_FCLK
 203                                                  * OMAP4: PLL1_CLK1 */
 204         OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,     /* OMAP3: DSI2_PLL_FCLK
 205                                                  * OMAP4: PLL1_CLK2 */
 206         OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC,  /* OMAP4: PLL2_CLK1 */
 207         OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI,    /* OMAP4: PLL2_CLK2 */
 208 };
 209
 210 enum omap_hdmi_flags {
 211         OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
 212 };
 213
 214 enum omap_dss_output_id {
 215         OMAP_DSS_OUTPUT_DPI     = 1 << 0,
 216         OMAP_DSS_OUTPUT_DBI     = 1 << 1,
 217         OMAP_DSS_OUTPUT_SDI     = 1 << 2,
 218         OMAP_DSS_OUTPUT_DSI1    = 1 << 3,
 219         OMAP_DSS_OUTPUT_DSI2    = 1 << 4,
 220         OMAP_DSS_OUTPUT_VENC    = 1 << 5,
 221         OMAP_DSS_OUTPUT_HDMI    = 1 << 6,
 222 };
 223
 224 /* RFBI */
 225
 226 struct rfbi_timings {
 227         int cs_on_time;
 228         int cs_off_time;
 229         int we_on_time;
 230         int we_off_time;
 231         int re_on_time;
 232         int re_off_time;
 233         int we_cycle_time;
 234         int re_cycle_time;
 235         int cs_pulse_width;
 236         int access_time;
 237
 238         int clk_div;
 239
 240         u32 tim[5];             /* set by rfbi_convert_timings() */
 241
 242         int converted;
 243 };
 244
 245 void omap_rfbi_write_command(const void *buf, u32 len);
 246 void omap_rfbi_read_data(void *buf, u32 len);
 247 void omap_rfbi_write_data(const void *buf, u32 len);
 248 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
 249                 u16 x, u16 y,
 250                 u16 w, u16 h);
 251 int omap_rfbi_enable_te(bool enable, unsigned line);
 252 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
 253                              unsigned hs_pulse_time, unsigned vs_pulse_time,
 254                              int hs_pol_inv, int vs_pol_inv, int extif_div);
 255 void rfbi_bus_lock(void);
 256 void rfbi_bus_unlock(void);
 257
 258 /* DSI */
 259
 260 struct omap_dss_dsi_videomode_timings {
 261         /* DSI video mode blanking data */
 262         /* Unit: byte clock cycles */
 263         u16 hsa;
 264         u16 hfp;
 265         u16 hbp;
 266         /* Unit: line clocks */
 267         u16 vsa;
 268         u16 vfp;
 269         u16 vbp;
 270
 271         /* DSI blanking modes */
 272         int blanking_mode;
 273         int hsa_blanking_mode;
 274         int hbp_blanking_mode;
 275         int hfp_blanking_mode;
 276
 277         /* Video port sync events */
 278         bool vp_vsync_end;
 279         bool vp_hsync_end;
 280
 281         bool ddr_clk_always_on;
 282         int window_sync;
 283 };
 284
 285 void dsi_bus_lock(struct omap_dss_device *dssdev);
 286 void dsi_bus_unlock(struct omap_dss_device *dssdev);
 287 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
 288                 int len);
 289 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
 290                 int len);
 291 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
 292 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
 293 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 294                 u8 param);
 295 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
 296                 u8 param);
 297 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
 298                 u8 param1, u8 param2);
 299 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
 300                 u8 *data, int len);
 301 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
 302                 u8 *data, int len);
 303 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 304                 u8 *buf, int buflen);
 305 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
 306                 int buflen);
 307 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
 308                 u8 *buf, int buflen);
 309 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
 310                 u8 param1, u8 param2, u8 *buf, int buflen);
 311 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
 312                 u16 len);
 313 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
 314 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
 315 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
 316 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
 317
 318 enum omapdss_version {
 319         OMAPDSS_VER_UNKNOWN = 0,
 320         OMAPDSS_VER_OMAP24xx,
 321         OMAPDSS_VER_OMAP34xx_ES1,       /* OMAP3430 ES1.0, 2.0 */
 322         OMAPDSS_VER_OMAP34xx_ES3,       /* OMAP3430 ES3.0+ */
 323         OMAPDSS_VER_OMAP3630,
 324         OMAPDSS_VER_AM35xx,
 325         OMAPDSS_VER_OMAP4430_ES1,       /* OMAP4430 ES1.0 */
 326         OMAPDSS_VER_OMAP4430_ES2,       /* OMAP4430 ES2.0, 2.1, 2.2 */
 327         OMAPDSS_VER_OMAP4,              /* All other OMAP4s */
 328         OMAPDSS_VER_OMAP5,
 329 };
 330
 331 /* Board specific data */
 332 struct omap_dss_board_info {
 333         int (*get_context_loss_count)(struct device *dev);
 334         int num_devices;
 335         struct omap_dss_device **devices;
 336         struct omap_dss_device *default_device;
 337         int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
 338         void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
 339         int (*set_min_bus_tput)(struct device *dev, unsigned long r);
 340         enum omapdss_version version;
 341 };
 342
 343 /* Init with the board info */
 344 extern int omap_display_init(struct omap_dss_board_info *board_data);
 345 /* HDMI mux init*/
 346 extern int omap_hdmi_init(enum omap_hdmi_flags flags);
 347
 348 struct omap_video_timings {
 349         /* Unit: pixels */
 350         u16 x_res;
 351         /* Unit: pixels */
 352         u16 y_res;
 353         /* Unit: KHz */
 354         u32 pixel_clock;
 355         /* Unit: pixel clocks */
 356         u16 hsw;        /* Horizontal synchronization pulse width */
 357         /* Unit: pixel clocks */
 358         u16 hfp;        /* Horizontal front porch */
 359         /* Unit: pixel clocks */
 360         u16 hbp;        /* Horizontal back porch */
 361         /* Unit: line clocks */
 362         u16 vsw;        /* Vertical synchronization pulse width */
 363         /* Unit: line clocks */
 364         u16 vfp;        /* Vertical front porch */
 365         /* Unit: line clocks */
 366         u16 vbp;        /* Vertical back porch */
 367
 368         /* Vsync logic level */
 369         enum omap_dss_signal_level vsync_level;
 370         /* Hsync logic level */
 371         enum omap_dss_signal_level hsync_level;
 372         /* Interlaced or Progressive timings */
 373         bool interlace;
 374         /* Pixel clock edge to drive LCD data */
 375         enum omap_dss_signal_edge data_pclk_edge;
 376         /* Data enable logic level */
 377         enum omap_dss_signal_level de_level;
 378         /* Pixel clock edges to drive HSYNC and VSYNC signals */
 379         enum omap_dss_signal_edge sync_pclk_edge;
 380 };
 381
 382 #ifdef CONFIG_OMAP2_DSS_VENC
 383 /* Hardcoded timings for tv modes. Venc only uses these to
 384  * identify the mode, and does not actually use the configs
 385  * itself. However, the configs should be something that
 386  * a normal monitor can also show */
 387 extern const struct omap_video_timings omap_dss_pal_timings;
 388 extern const struct omap_video_timings omap_dss_ntsc_timings;
 389 #endif
 390
 391 struct omap_dss_cpr_coefs {
 392         s16 rr, rg, rb;
 393         s16 gr, gg, gb;
 394         s16 br, bg, bb;
 395 };
 396
 397 struct omap_overlay_info {
 398         u32 paddr;
 399         u32 p_uv_addr;  /* for NV12 format */
 400         u16 screen_width;
 401         u16 width;
 402         u16 height;
 403         enum omap_color_mode color_mode;
 404         u8 rotation;
 405         enum omap_dss_rotation_type rotation_type;
 406         bool mirror;
 407
 408         u16 pos_x;
 409         u16 pos_y;
 410         u16 out_width;  /* if 0, out_width == width */
 411         u16 out_height; /* if 0, out_height == height */
 412         u8 global_alpha;
 413         u8 pre_mult_alpha;
 414         u8 zorder;
 415 };
 416
 417 struct omap_overlay {
 418         struct kobject kobj;
 419         struct list_head list;
 420
 421         /* static fields */
 422         const char *name;
 423         enum omap_plane id;
 424         enum omap_color_mode supported_modes;
 425         enum omap_overlay_caps caps;
 426
 427         /* dynamic fields */
 428         struct omap_overlay_manager *manager;
 429
 430         /*
 431          * The following functions do not block:
 432          *
 433          * is_enabled
 434          * set_overlay_info
 435          * get_overlay_info
 436          *
 437          * The rest of the functions may block and cannot be called from
 438          * interrupt context
 439          */
 440
 441         int (*enable)(struct omap_overlay *ovl);
 442         int (*disable)(struct omap_overlay *ovl);
 443         bool (*is_enabled)(struct omap_overlay *ovl);
 444
 445         int (*set_manager)(struct omap_overlay *ovl,
 446                 struct omap_overlay_manager *mgr);
 447         int (*unset_manager)(struct omap_overlay *ovl);
 448
 449         int (*set_overlay_info)(struct omap_overlay *ovl,
 450                         struct omap_overlay_info *info);
 451         void (*get_overlay_info)(struct omap_overlay *ovl,
 452                         struct omap_overlay_info *info);
 453
 454         int (*wait_for_go)(struct omap_overlay *ovl);
 455
 456         struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
 457 };
 458
 459 struct omap_overlay_manager_info {
 460         u32 default_color;
 461
 462         enum omap_dss_trans_key_type trans_key_type;
 463         u32 trans_key;
 464         bool trans_enabled;
 465
 466         bool partial_alpha_enabled;
 467
 468         bool cpr_enable;
 469         struct omap_dss_cpr_coefs cpr_coefs;
 470 };
 471
 472 struct omap_overlay_manager {
 473         struct kobject kobj;
 474
 475         /* static fields */
 476         const char *name;
 477         enum omap_channel id;
 478         enum omap_overlay_manager_caps caps;
 479         struct list_head overlays;
 480         enum omap_display_type supported_displays;
 481         enum omap_dss_output_id supported_outputs;
 482
 483         /* dynamic fields */
 484         struct omap_dss_output *output;
 485
 486         /*
 487          * The following functions do not block:
 488          *
 489          * set_manager_info
 490          * get_manager_info
 491          * apply
 492          *
 493          * The rest of the functions may block and cannot be called from
 494          * interrupt context
 495          */
 496
 497         int (*set_output)(struct omap_overlay_manager *mgr,
 498                 struct omap_dss_output *output);
 499         int (*unset_output)(struct omap_overlay_manager *mgr);
 500
 501         int (*set_manager_info)(struct omap_overlay_manager *mgr,
 502                         struct omap_overlay_manager_info *info);
 503         void (*get_manager_info)(struct omap_overlay_manager *mgr,
 504                         struct omap_overlay_manager_info *info);
 505
 506         int (*apply)(struct omap_overlay_manager *mgr);
 507         int (*wait_for_go)(struct omap_overlay_manager *mgr);
 508         int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
 509
 510         struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
 511 };
 512
 513 /* 22 pins means 1 clk lane and 10 data lanes */
 514 #define OMAP_DSS_MAX_DSI_PINS 22
 515
 516 struct omap_dsi_pin_config {
 517         int num_pins;
 518         /*
 519          * pin numbers in the following order:
 520          * clk+, clk-
 521          * data1+, data1-
 522          * data2+, data2-
 523          * ...
 524          */
 525         int pins[OMAP_DSS_MAX_DSI_PINS];
 526 };
 527
 528 struct omap_dss_writeback_info {
 529         u32 paddr;
 530         u32 p_uv_addr;
 531         u16 buf_width;
 532         u16 width;
 533         u16 height;
 534         enum omap_color_mode color_mode;
 535         u8 rotation;
 536         enum omap_dss_rotation_type rotation_type;
 537         bool mirror;
 538         u8 pre_mult_alpha;
 539 };
 540
 541 struct omap_dss_output {
 542         struct list_head list;
 543
 544         /* display type supported by the output */
 545         enum omap_display_type type;
 546
 547         /* output instance */
 548         enum omap_dss_output_id id;
 549
 550         /* output's platform device pointer */
 551         struct platform_device *pdev;
 552
 553         /* dynamic fields */
 554         struct omap_overlay_manager *manager;
 555
 556         struct omap_dss_device *device;
 557 };
 558
 559 struct omap_dss_device {
 560         struct device dev;
 561
 562         enum omap_display_type type;
 563
 564         enum omap_channel channel;
 565
 566         union {
 567                 struct {
 568                         u8 data_lines;
 569                 } dpi;
 570
 571                 struct {
 572                         u8 channel;
 573                         u8 data_lines;
 574                 } rfbi;
 575
 576                 struct {
 577                         u8 datapairs;
 578                 } sdi;
 579
 580                 struct {
 581                         int module;
 582
 583                         bool ext_te;
 584                         u8 ext_te_gpio;
 585                 } dsi;
 586
 587                 struct {
 588                         enum omap_dss_venc_type type;
 589                         bool invert_polarity;
 590                 } venc;
 591         } phy;
 592
 593         struct {
 594                 struct {
 595                         struct {
 596                                 u16 lck_div;
 597                                 u16 pck_div;
 598                                 enum omap_dss_clk_source lcd_clk_src;
 599                         } channel;
 600
 601                         enum omap_dss_clk_source dispc_fclk_src;
 602                 } dispc;
 603
 604                 struct {
 605                         /* regn is one greater than TRM's REGN value */
 606                         u16 regn;
 607                         u16 regm;
 608                         u16 regm_dispc;
 609                         u16 regm_dsi;
 610
 611                         u16 lp_clk_div;
 612                         enum omap_dss_clk_source dsi_fclk_src;
 613                 } dsi;
 614
 615                 struct {
 616                         /* regn is one greater than TRM's REGN value */
 617                         u16 regn;
 618                         u16 regm2;
 619                 } hdmi;
 620         } clocks;
 621
 622         struct {
 623                 struct omap_video_timings timings;
 624
 625                 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
 626                 enum omap_dss_dsi_mode dsi_mode;
 627                 struct omap_dss_dsi_videomode_timings dsi_vm_timings;
 628         } panel;
 629
 630         struct {
 631                 u8 pixel_size;
 632                 struct rfbi_timings rfbi_timings;
 633         } ctrl;
 634
 635         int reset_gpio;
 636
 637         int max_backlight_level;
 638
 639         const char *name;
 640
 641         /* used to match device to driver */
 642         const char *driver_name;
 643
 644         void *data;
 645
 646         struct omap_dss_driver *driver;
 647
 648         /* helper variable for driver suspend/resume */
 649         bool activate_after_resume;
 650
 651         enum omap_display_caps caps;
 652
 653         struct omap_dss_output *output;
 654
 655         enum omap_dss_display_state state;
 656
 657         enum omap_dss_audio_state audio_state;
 658
 659         /* platform specific  */
 660         int (*platform_enable)(struct omap_dss_device *dssdev);
 661         void (*platform_disable)(struct omap_dss_device *dssdev);
 662         int (*set_backlight)(struct omap_dss_device *dssdev, int level);
 663         int (*get_backlight)(struct omap_dss_device *dssdev);
 664 };
 665
 666 struct omap_dss_hdmi_data
 667 {
 668         int ct_cp_hpd_gpio;
 669         int ls_oe_gpio;
 670         int hpd_gpio;
 671 };
 672
 673 struct omap_dss_audio {
 674         struct snd_aes_iec958 *iec;
 675         struct snd_cea_861_aud_if *cea;
 676 };
 677
 678 struct omap_dss_driver {
 679         struct device_driver driver;
 680
 681         int (*probe)(struct omap_dss_device *);
 682         void (*remove)(struct omap_dss_device *);
 683
 684         int (*enable)(struct omap_dss_device *display);
 685         void (*disable)(struct omap_dss_device *display);
 686         int (*run_test)(struct omap_dss_device *display, int test);
 687
 688         int (*update)(struct omap_dss_device *dssdev,
 689                                u16 x, u16 y, u16 w, u16 h);
 690         int (*sync)(struct omap_dss_device *dssdev);
 691
 692         int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
 693         int (*get_te)(struct omap_dss_device *dssdev);
 694
 695         u8 (*get_rotate)(struct omap_dss_device *dssdev);
 696         int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
 697
 698         bool (*get_mirror)(struct omap_dss_device *dssdev);
 699         int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
 700
 701         int (*memory_read)(struct omap_dss_device *dssdev,
 702                         void *buf, size_t size,
 703                         u16 x, u16 y, u16 w, u16 h);
 704
 705         void (*get_resolution)(struct omap_dss_device *dssdev,
 706                         u16 *xres, u16 *yres);
 707         void (*get_dimensions)(struct omap_dss_device *dssdev,
 708                         u32 *width, u32 *height);
 709         int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
 710
 711         int (*check_timings)(struct omap_dss_device *dssdev,
 712                         struct omap_video_timings *timings);
 713         void (*set_timings)(struct omap_dss_device *dssdev,
 714                         struct omap_video_timings *timings);
 715         void (*get_timings)(struct omap_dss_device *dssdev,
 716                         struct omap_video_timings *timings);
 717
 718         int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
 719         u32 (*get_wss)(struct omap_dss_device *dssdev);
 720
 721         int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
 722         bool (*detect)(struct omap_dss_device *dssdev);
 723
 724         /*
 725          * For display drivers that support audio. This encompasses
 726          * HDMI and DisplayPort at the moment.
 727          */
 728         /*
 729          * Note: These functions might sleep. Do not call while
 730          * holding a spinlock/readlock.
 731          */
 732         int (*audio_enable)(struct omap_dss_device *dssdev);
 733         void (*audio_disable)(struct omap_dss_device *dssdev);
 734         bool (*audio_supported)(struct omap_dss_device *dssdev);
 735         int (*audio_config)(struct omap_dss_device *dssdev,
 736                 struct omap_dss_audio *audio);
 737         /* Note: These functions may not sleep */
 738         int (*audio_start)(struct omap_dss_device *dssdev);
 739         void (*audio_stop)(struct omap_dss_device *dssdev);
 740
 741 };
 742
 743 enum omapdss_version omapdss_get_version(void);
 744
 745 int omap_dss_register_driver(struct omap_dss_driver *);
 746 void omap_dss_unregister_driver(struct omap_dss_driver *);
 747
 748 void omap_dss_get_device(struct omap_dss_device *dssdev);
 749 void omap_dss_put_device(struct omap_dss_device *dssdev);
 750 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
 751 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
 752 struct omap_dss_device *omap_dss_find_device(void *data,
 753                 int (*match)(struct omap_dss_device *dssdev, void *data));
 754 const char *omapdss_get_default_display_name(void);
 755
 756 int omap_dss_start_device(struct omap_dss_device *dssdev);
 757 void omap_dss_stop_device(struct omap_dss_device *dssdev);
 758
 759 int dss_feat_get_num_mgrs(void);
 760 int dss_feat_get_num_ovls(void);
 761 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
 762 enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
 763 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
 764
 765
 766
 767 int omap_dss_get_num_overlay_managers(void);
 768 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
 769
 770 int omap_dss_get_num_overlays(void);
 771 struct omap_overlay *omap_dss_get_overlay(int num);
 772
 773 struct omap_dss_output *omap_dss_get_output(enum omap_dss_output_id id);
 774 int omapdss_output_set_device(struct omap_dss_output *out,
 775                 struct omap_dss_device *dssdev);
 776 int omapdss_output_unset_device(struct omap_dss_output *out);
 777
 778 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
 779                 u16 *xres, u16 *yres);
 780 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
 781 void omapdss_default_get_timings(struct omap_dss_device *dssdev,
 782                 struct omap_video_timings *timings);
 783
 784 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
 785 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 786 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 787
 788 u32 dispc_read_irqstatus(void);
 789 void dispc_clear_irqstatus(u32 mask);
 790 u32 dispc_read_irqenable(void);
 791 void dispc_write_irqenable(u32 mask);
 792
 793 int dispc_request_irq(irq_handler_t handler, void *dev_id);
 794 void dispc_free_irq(void *dev_id);
 795
 796 int dispc_runtime_get(void);
 797 void dispc_runtime_put(void);
 798
 799 void dispc_mgr_enable(enum omap_channel channel, bool enable);
 800 bool dispc_mgr_is_enabled(enum omap_channel channel);
 801 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
 802 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
 803 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
 804 bool dispc_mgr_go_busy(enum omap_channel channel);
 805 void dispc_mgr_go(enum omap_channel channel);
 806 void dispc_mgr_set_lcd_config(enum omap_channel channel,
 807                 const struct dss_lcd_mgr_config *config);
 808 void dispc_mgr_set_timings(enum omap_channel channel,
 809                 const struct omap_video_timings *timings);
 810 void dispc_mgr_setup(enum omap_channel channel,
 811                 const struct omap_overlay_manager_info *info);
 812
 813 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
 814                 const struct omap_overlay_info *oi,
 815                 const struct omap_video_timings *timings,
 816                 int *x_predecim, int *y_predecim);
 817
 818 int dispc_ovl_enable(enum omap_plane plane, bool enable);
 819 bool dispc_ovl_enabled(enum omap_plane plane);
 820 void dispc_ovl_set_channel_out(enum omap_plane plane,
 821                 enum omap_channel channel);
 822 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
 823                 bool replication, const struct omap_video_timings *mgr_timings,
 824                 bool mem_to_mem);
 825
 826 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
 827 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
 828
 829 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
 830                 bool enable);
 831 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
 832 void omapdss_dsi_set_timings(struct omap_dss_device *dssdev,
 833                 struct omap_video_timings *timings);
 834 void omapdss_dsi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
 835 void omapdss_dsi_set_pixel_format(struct omap_dss_device *dssdev,
 836                 enum omap_dss_dsi_pixel_format fmt);
 837 void omapdss_dsi_set_operation_mode(struct omap_dss_device *dssdev,
 838                 enum omap_dss_dsi_mode mode);
 839 void omapdss_dsi_set_videomode_timings(struct omap_dss_device *dssdev,
 840                 struct omap_dss_dsi_videomode_timings *timings);
 841
 842 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
 843                 void (*callback)(int, void *), void *data);
 844 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
 845 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
 846 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
 847 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
 848                 const struct omap_dsi_pin_config *pin_cfg);
 849 int omapdss_dsi_set_clocks(struct omap_dss_device *dssdev,
 850                 unsigned long ddr_clk, unsigned long lp_clk);
 851
 852 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
 853 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
 854                 bool disconnect_lanes, bool enter_ulps);
 855
 856 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
 857 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
 858 void omapdss_dpi_set_timings(struct omap_dss_device *dssdev,
 859                 struct omap_video_timings *timings);
 860 int dpi_check_timings(struct omap_dss_device *dssdev,
 861                         struct omap_video_timings *timings);
 862 void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines);
 863
 864 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
 865 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
 866 void omapdss_sdi_set_timings(struct omap_dss_device *dssdev,
 867                 struct omap_video_timings *timings);
 868 void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs);
 869
 870 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
 871 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
 872 int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *),
 873                 void *data);
 874 int omap_rfbi_configure(struct omap_dss_device *dssdev);
 875 void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
 876 void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev,
 877                 int pixel_size);
 878 void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev,
 879                 int data_lines);
 880 void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev,
 881                 struct rfbi_timings *timings);
 882
 883 int omapdss_compat_init(void);
 884 void omapdss_compat_uninit(void);
 885
 886 struct dss_mgr_ops {
 887         void (*start_update)(struct omap_overlay_manager *mgr);
 888         int (*enable)(struct omap_overlay_manager *mgr);
 889         void (*disable)(struct omap_overlay_manager *mgr);
 890         void (*set_timings)(struct omap_overlay_manager *mgr,
 891                         const struct omap_video_timings *timings);
 892         void (*set_lcd_config)(struct omap_overlay_manager *mgr,
 893                         const struct dss_lcd_mgr_config *config);
 894         int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
 895                         void (*handler)(void *), void *data);
 896         void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
 897                         void (*handler)(void *), void *data);
 898 };
 899
 900 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
 901 void dss_uninstall_mgr_ops(void);
 902
 903 void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
 904                 const struct omap_video_timings *timings);
 905 void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
 906                 const struct dss_lcd_mgr_config *config);
 907 int dss_mgr_enable(struct omap_overlay_manager *mgr);
 908 void dss_mgr_disable(struct omap_overlay_manager *mgr);
 909 void dss_mgr_start_update(struct omap_overlay_manager *mgr);
 910 int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
 911                 void (*handler)(void *), void *data);
 912 void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
 913                 void (*handler)(void *), void *data);
 914 #endif