2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
37 #include "drm_dp_helper.h"
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43 #define DP_LINK_CONFIGURATION_SIZE 9
46 struct intel_encoder base
;
49 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
57 struct i2c_adapter adapter
;
58 struct i2c_algo_dp_aux_data algo
;
61 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
65 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
66 * @intel_dp: DP struct
68 * If a CPU or PCH DP output is attached to an eDP panel, this function
69 * will return true, and false otherwise.
71 static bool is_edp(struct intel_dp
*intel_dp
)
73 return intel_dp
->base
.type
== INTEL_OUTPUT_EDP
;
77 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
78 * @intel_dp: DP struct
80 * Returns true if the given DP struct corresponds to a PCH DP port attached
81 * to an eDP panel, false otherwise. Helpful for determining whether we
82 * may need FDI resources for a given DP output or not.
84 static bool is_pch_edp(struct intel_dp
*intel_dp
)
86 return intel_dp
->is_pch_edp
;
89 static struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
91 return container_of(encoder
, struct intel_dp
, base
.base
);
94 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
96 return container_of(intel_attached_encoder(connector
),
97 struct intel_dp
, base
);
101 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
102 * @encoder: DRM encoder
104 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
105 * by intel_display.c.
107 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
109 struct intel_dp
*intel_dp
;
114 intel_dp
= enc_to_intel_dp(encoder
);
116 return is_pch_edp(intel_dp
);
119 static void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
120 static void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
121 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
124 intel_edp_link_config(struct intel_encoder
*intel_encoder
,
125 int *lane_num
, int *link_bw
)
127 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
129 *lane_num
= intel_dp
->lane_count
;
130 if (intel_dp
->link_bw
== DP_LINK_BW_1_62
)
132 else if (intel_dp
->link_bw
== DP_LINK_BW_2_7
)
137 intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
139 int max_lane_count
= 4;
141 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
142 max_lane_count
= intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & 0x1f;
143 switch (max_lane_count
) {
144 case 1: case 2: case 4:
150 return max_lane_count
;
154 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
156 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
158 switch (max_link_bw
) {
159 case DP_LINK_BW_1_62
:
163 max_link_bw
= DP_LINK_BW_1_62
;
170 intel_dp_link_clock(uint8_t link_bw
)
172 if (link_bw
== DP_LINK_BW_2_7
)
178 /* I think this is a fiction */
180 intel_dp_link_required(struct drm_device
*dev
, struct intel_dp
*intel_dp
, int pixel_clock
)
182 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
183 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
187 bpp
= intel_crtc
->bpp
;
189 return (pixel_clock
* bpp
+ 7) / 8;
193 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
195 return (max_link_clock
* max_lanes
* 8) / 10;
199 intel_dp_mode_valid(struct drm_connector
*connector
,
200 struct drm_display_mode
*mode
)
202 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
203 struct drm_device
*dev
= connector
->dev
;
204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
205 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
206 int max_lanes
= intel_dp_max_lane_count(intel_dp
);
208 if (is_edp(intel_dp
) && dev_priv
->panel_fixed_mode
) {
209 if (mode
->hdisplay
> dev_priv
->panel_fixed_mode
->hdisplay
)
212 if (mode
->vdisplay
> dev_priv
->panel_fixed_mode
->vdisplay
)
216 /* only refuse the mode on non eDP since we have seen some weird eDP panels
217 which are outside spec tolerances but somehow work by magic */
218 if (!is_edp(intel_dp
) &&
219 (intel_dp_link_required(connector
->dev
, intel_dp
, mode
->clock
)
220 > intel_dp_max_data_rate(max_link_clock
, max_lanes
)))
221 return MODE_CLOCK_HIGH
;
223 if (mode
->clock
< 10000)
224 return MODE_CLOCK_LOW
;
230 pack_aux(uint8_t *src
, int src_bytes
)
237 for (i
= 0; i
< src_bytes
; i
++)
238 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
243 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
248 for (i
= 0; i
< dst_bytes
; i
++)
249 dst
[i
] = src
>> ((3-i
) * 8);
252 /* hrawclock is 1/4 the FSB frequency */
254 intel_hrawclk(struct drm_device
*dev
)
256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
259 clkcfg
= I915_READ(CLKCFG
);
260 switch (clkcfg
& CLKCFG_FSB_MASK
) {
269 case CLKCFG_FSB_1067
:
271 case CLKCFG_FSB_1333
:
273 /* these two are just a guess; one of them might be right */
274 case CLKCFG_FSB_1600
:
275 case CLKCFG_FSB_1600_ALT
:
283 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
284 uint8_t *send
, int send_bytes
,
285 uint8_t *recv
, int recv_size
)
287 uint32_t output_reg
= intel_dp
->output_reg
;
288 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
290 uint32_t ch_ctl
= output_reg
+ 0x10;
291 uint32_t ch_data
= ch_ctl
+ 4;
295 uint32_t aux_clock_divider
;
298 /* The clock divider is based off the hrawclk,
299 * and would like to run at 2MHz. So, take the
300 * hrawclk value and divide by 2 and use that
302 * Note that PCH attached eDP panels should use a 125MHz input
305 if (is_edp(intel_dp
) && !is_pch_edp(intel_dp
)) {
307 aux_clock_divider
= 200; /* SNB eDP input clock at 400Mhz */
309 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
310 } else if (HAS_PCH_SPLIT(dev
))
311 aux_clock_divider
= 62; /* IRL input clock fixed at 125Mhz */
313 aux_clock_divider
= intel_hrawclk(dev
) / 2;
320 /* Try to wait for any previous AUX channel activity */
321 for (try = 0; try < 3; try++) {
322 status
= I915_READ(ch_ctl
);
323 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
329 WARN(1, "dp_aux_ch not started status 0x%08x\n",
334 /* Must try at least 3 times according to DP spec */
335 for (try = 0; try < 5; try++) {
336 /* Load the send data into the aux channel data registers */
337 for (i
= 0; i
< send_bytes
; i
+= 4)
338 I915_WRITE(ch_data
+ i
,
339 pack_aux(send
+ i
, send_bytes
- i
));
341 /* Send the command and wait for it to complete */
343 DP_AUX_CH_CTL_SEND_BUSY
|
344 DP_AUX_CH_CTL_TIME_OUT_400us
|
345 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
346 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
347 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
349 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
350 DP_AUX_CH_CTL_RECEIVE_ERROR
);
352 status
= I915_READ(ch_ctl
);
353 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
358 /* Clear done status and any errors */
362 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
363 DP_AUX_CH_CTL_RECEIVE_ERROR
);
364 if (status
& DP_AUX_CH_CTL_DONE
)
368 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
369 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
373 /* Check for timeout or receive error.
374 * Timeouts occur when the sink is not connected
376 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
377 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
381 /* Timeouts occur when the device isn't connected, so they're
382 * "normal" -- don't fill the kernel log with these */
383 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
384 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
388 /* Unload any bytes sent back from the other side */
389 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
390 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
391 if (recv_bytes
> recv_size
)
392 recv_bytes
= recv_size
;
394 for (i
= 0; i
< recv_bytes
; i
+= 4)
395 unpack_aux(I915_READ(ch_data
+ i
),
396 recv
+ i
, recv_bytes
- i
);
401 /* Write data to the aux channel in native mode */
403 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
404 uint16_t address
, uint8_t *send
, int send_bytes
)
413 msg
[0] = AUX_NATIVE_WRITE
<< 4;
414 msg
[1] = address
>> 8;
415 msg
[2] = address
& 0xff;
416 msg
[3] = send_bytes
- 1;
417 memcpy(&msg
[4], send
, send_bytes
);
418 msg_bytes
= send_bytes
+ 4;
420 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
423 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
425 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
433 /* Write a single byte to the aux channel in native mode */
435 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
436 uint16_t address
, uint8_t byte
)
438 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
441 /* read bytes from a native aux channel */
443 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
444 uint16_t address
, uint8_t *recv
, int recv_bytes
)
453 msg
[0] = AUX_NATIVE_READ
<< 4;
454 msg
[1] = address
>> 8;
455 msg
[2] = address
& 0xff;
456 msg
[3] = recv_bytes
- 1;
459 reply_bytes
= recv_bytes
+ 1;
462 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
469 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
470 memcpy(recv
, reply
+ 1, ret
- 1);
473 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
481 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
482 uint8_t write_byte
, uint8_t *read_byte
)
484 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
485 struct intel_dp
*intel_dp
= container_of(adapter
,
488 uint16_t address
= algo_data
->address
;
496 /* Set up the command byte */
497 if (mode
& MODE_I2C_READ
)
498 msg
[0] = AUX_I2C_READ
<< 4;
500 msg
[0] = AUX_I2C_WRITE
<< 4;
502 if (!(mode
& MODE_I2C_STOP
))
503 msg
[0] |= AUX_I2C_MOT
<< 4;
505 msg
[1] = address
>> 8;
526 for (retry
= 0; retry
< 5; retry
++) {
527 ret
= intel_dp_aux_ch(intel_dp
,
531 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
535 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
536 case AUX_NATIVE_REPLY_ACK
:
537 /* I2C-over-AUX Reply field is only valid
538 * when paired with AUX ACK.
541 case AUX_NATIVE_REPLY_NACK
:
542 DRM_DEBUG_KMS("aux_ch native nack\n");
544 case AUX_NATIVE_REPLY_DEFER
:
548 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
553 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
554 case AUX_I2C_REPLY_ACK
:
555 if (mode
== MODE_I2C_READ
) {
556 *read_byte
= reply
[1];
558 return reply_bytes
- 1;
559 case AUX_I2C_REPLY_NACK
:
560 DRM_DEBUG_KMS("aux_i2c nack\n");
562 case AUX_I2C_REPLY_DEFER
:
563 DRM_DEBUG_KMS("aux_i2c defer\n");
567 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
572 DRM_ERROR("too many retries, giving up\n");
577 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
578 struct intel_connector
*intel_connector
, const char *name
)
580 DRM_DEBUG_KMS("i2c_init %s\n", name
);
581 intel_dp
->algo
.running
= false;
582 intel_dp
->algo
.address
= 0;
583 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
585 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
586 intel_dp
->adapter
.owner
= THIS_MODULE
;
587 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
588 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
589 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
590 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
591 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
593 return i2c_dp_aux_add_bus(&intel_dp
->adapter
);
597 intel_dp_mode_fixup(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
598 struct drm_display_mode
*adjusted_mode
)
600 struct drm_device
*dev
= encoder
->dev
;
601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
602 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
603 int lane_count
, clock
;
604 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
605 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
606 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
608 if (is_edp(intel_dp
) && dev_priv
->panel_fixed_mode
) {
609 intel_fixed_panel_mode(dev_priv
->panel_fixed_mode
, adjusted_mode
);
610 intel_pch_panel_fitting(dev
, DRM_MODE_SCALE_FULLSCREEN
,
611 mode
, adjusted_mode
);
613 * the mode->clock is used to calculate the Data&Link M/N
614 * of the pipe. For the eDP the fixed clock should be used.
616 mode
->clock
= dev_priv
->panel_fixed_mode
->clock
;
619 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
620 for (clock
= 0; clock
<= max_clock
; clock
++) {
621 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
623 if (intel_dp_link_required(encoder
->dev
, intel_dp
, mode
->clock
)
625 intel_dp
->link_bw
= bws
[clock
];
626 intel_dp
->lane_count
= lane_count
;
627 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
628 DRM_DEBUG_KMS("Display port link bw %02x lane "
629 "count %d clock %d\n",
630 intel_dp
->link_bw
, intel_dp
->lane_count
,
631 adjusted_mode
->clock
);
637 if (is_edp(intel_dp
)) {
638 /* okay we failed just pick the highest */
639 intel_dp
->lane_count
= max_lane_count
;
640 intel_dp
->link_bw
= bws
[max_clock
];
641 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
642 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
643 "count %d clock %d\n",
644 intel_dp
->link_bw
, intel_dp
->lane_count
,
645 adjusted_mode
->clock
);
653 struct intel_dp_m_n
{
662 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
664 while (*num
> 0xffffff || *den
> 0xffffff) {
671 intel_dp_compute_m_n(int bpp
,
675 struct intel_dp_m_n
*m_n
)
678 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
679 m_n
->gmch_n
= link_clock
* nlanes
;
680 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
681 m_n
->link_m
= pixel_clock
;
682 m_n
->link_n
= link_clock
;
683 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
687 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
688 struct drm_display_mode
*adjusted_mode
)
690 struct drm_device
*dev
= crtc
->dev
;
691 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
692 struct drm_encoder
*encoder
;
693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
694 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
696 struct intel_dp_m_n m_n
;
697 int pipe
= intel_crtc
->pipe
;
700 * Find the lane count in the intel_encoder private
702 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
703 struct intel_dp
*intel_dp
;
705 if (encoder
->crtc
!= crtc
)
708 intel_dp
= enc_to_intel_dp(encoder
);
709 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
710 lane_count
= intel_dp
->lane_count
;
712 } else if (is_edp(intel_dp
)) {
713 lane_count
= dev_priv
->edp
.lanes
;
719 * Compute the GMCH and Link ratios. The '3' here is
720 * the number of bytes_per_pixel post-LUT, which we always
721 * set up for 8-bits of R/G/B, or 3 bytes total.
723 intel_dp_compute_m_n(intel_crtc
->bpp
, lane_count
,
724 mode
->clock
, adjusted_mode
->clock
, &m_n
);
726 if (HAS_PCH_SPLIT(dev
)) {
727 I915_WRITE(TRANSDATA_M1(pipe
),
728 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
730 I915_WRITE(TRANSDATA_N1(pipe
), m_n
.gmch_n
);
731 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
.link_m
);
732 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
.link_n
);
734 I915_WRITE(PIPE_GMCH_DATA_M(pipe
),
735 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
737 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
738 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
739 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
744 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
745 struct drm_display_mode
*adjusted_mode
)
747 struct drm_device
*dev
= encoder
->dev
;
748 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
749 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
750 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
752 intel_dp
->DP
= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
753 intel_dp
->DP
|= intel_dp
->color_range
;
755 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
756 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
757 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
758 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
760 if (HAS_PCH_CPT(dev
) && !is_edp(intel_dp
))
761 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
763 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
765 switch (intel_dp
->lane_count
) {
767 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
770 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
773 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
776 if (intel_dp
->has_audio
) {
777 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
778 pipe_name(intel_crtc
->pipe
));
779 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
780 intel_write_eld(encoder
, adjusted_mode
);
783 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
784 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
785 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
786 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
789 * Check for DPCD version > 1.1 and enhanced framing support
791 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
792 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
793 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
794 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
797 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
798 if (intel_crtc
->pipe
== 1 && !HAS_PCH_CPT(dev
))
799 intel_dp
->DP
|= DP_PIPEB_SELECT
;
801 if (is_edp(intel_dp
) && !is_pch_edp(intel_dp
)) {
802 /* don't miss out required setting for eDP */
803 intel_dp
->DP
|= DP_PLL_ENABLE
;
804 if (adjusted_mode
->clock
< 200000)
805 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
807 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
811 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
813 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
818 * If the panel wasn't on, make sure there's not a currently
819 * active PP sequence before enabling AUX VDD.
821 if (!(I915_READ(PCH_PP_STATUS
) & PP_ON
))
822 msleep(dev_priv
->panel_t3
);
824 pp
= I915_READ(PCH_PP_CONTROL
);
826 I915_WRITE(PCH_PP_CONTROL
, pp
);
827 POSTING_READ(PCH_PP_CONTROL
);
830 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
)
832 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
836 pp
= I915_READ(PCH_PP_CONTROL
);
837 pp
&= ~EDP_FORCE_VDD
;
838 I915_WRITE(PCH_PP_CONTROL
, pp
);
839 POSTING_READ(PCH_PP_CONTROL
);
841 /* Make sure sequencer is idle before allowing subsequent activity */
842 msleep(dev_priv
->panel_t12
);
845 /* Returns true if the panel was already on when called */
846 static bool ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
848 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
850 u32 pp
, idle_on_mask
= PP_ON
| PP_SEQUENCE_STATE_ON_IDLE
;
852 if (I915_READ(PCH_PP_STATUS
) & PP_ON
)
855 pp
= I915_READ(PCH_PP_CONTROL
);
857 /* ILK workaround: disable reset around power sequence */
858 pp
&= ~PANEL_POWER_RESET
;
859 I915_WRITE(PCH_PP_CONTROL
, pp
);
860 POSTING_READ(PCH_PP_CONTROL
);
862 pp
|= PANEL_UNLOCK_REGS
| POWER_TARGET_ON
;
863 I915_WRITE(PCH_PP_CONTROL
, pp
);
864 POSTING_READ(PCH_PP_CONTROL
);
866 if (wait_for((I915_READ(PCH_PP_STATUS
) & idle_on_mask
) == idle_on_mask
,
868 DRM_ERROR("panel on wait timed out: 0x%08x\n",
869 I915_READ(PCH_PP_STATUS
));
871 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
872 I915_WRITE(PCH_PP_CONTROL
, pp
);
873 POSTING_READ(PCH_PP_CONTROL
);
878 static void ironlake_edp_panel_off(struct drm_device
*dev
)
880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
881 u32 pp
, idle_off_mask
= PP_ON
| PP_SEQUENCE_MASK
|
882 PP_CYCLE_DELAY_ACTIVE
| PP_SEQUENCE_STATE_MASK
;
884 pp
= I915_READ(PCH_PP_CONTROL
);
886 /* ILK workaround: disable reset around power sequence */
887 pp
&= ~PANEL_POWER_RESET
;
888 I915_WRITE(PCH_PP_CONTROL
, pp
);
889 POSTING_READ(PCH_PP_CONTROL
);
891 pp
&= ~POWER_TARGET_ON
;
892 I915_WRITE(PCH_PP_CONTROL
, pp
);
893 POSTING_READ(PCH_PP_CONTROL
);
895 if (wait_for((I915_READ(PCH_PP_STATUS
) & idle_off_mask
) == 0, 5000))
896 DRM_ERROR("panel off wait timed out: 0x%08x\n",
897 I915_READ(PCH_PP_STATUS
));
899 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
900 I915_WRITE(PCH_PP_CONTROL
, pp
);
901 POSTING_READ(PCH_PP_CONTROL
);
904 static void ironlake_edp_backlight_on(struct drm_device
*dev
)
906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
911 * If we enable the backlight right away following a panel power
912 * on, we may see slight flicker as the panel syncs with the eDP
913 * link. So delay a bit to make sure the image is solid before
914 * allowing it to appear.
917 pp
= I915_READ(PCH_PP_CONTROL
);
918 pp
|= EDP_BLC_ENABLE
;
919 I915_WRITE(PCH_PP_CONTROL
, pp
);
922 static void ironlake_edp_backlight_off(struct drm_device
*dev
)
924 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
928 pp
= I915_READ(PCH_PP_CONTROL
);
929 pp
&= ~EDP_BLC_ENABLE
;
930 I915_WRITE(PCH_PP_CONTROL
, pp
);
933 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
)
935 struct drm_device
*dev
= encoder
->dev
;
936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
940 dpa_ctl
= I915_READ(DP_A
);
941 dpa_ctl
|= DP_PLL_ENABLE
;
942 I915_WRITE(DP_A
, dpa_ctl
);
947 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
)
949 struct drm_device
*dev
= encoder
->dev
;
950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
953 dpa_ctl
= I915_READ(DP_A
);
954 dpa_ctl
&= ~DP_PLL_ENABLE
;
955 I915_WRITE(DP_A
, dpa_ctl
);
960 /* If the sink supports it, try to set the power state appropriately */
961 static void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
965 /* Should have a valid DPCD by this point */
966 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
969 if (mode
!= DRM_MODE_DPMS_ON
) {
970 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
973 DRM_DEBUG_DRIVER("failed to write sink power state\n");
976 * When turning on, we need to retry for 1ms to give the sink
979 for (i
= 0; i
< 3; i
++) {
980 ret
= intel_dp_aux_native_write_1(intel_dp
,
990 static void intel_dp_prepare(struct drm_encoder
*encoder
)
992 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
993 struct drm_device
*dev
= encoder
->dev
;
995 /* Wake up the sink first */
996 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
998 if (is_edp(intel_dp
)) {
999 ironlake_edp_backlight_off(dev
);
1000 ironlake_edp_panel_off(dev
);
1001 if (!is_pch_edp(intel_dp
))
1002 ironlake_edp_pll_on(encoder
);
1004 ironlake_edp_pll_off(encoder
);
1006 intel_dp_link_down(intel_dp
);
1009 static void intel_dp_commit(struct drm_encoder
*encoder
)
1011 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1012 struct drm_device
*dev
= encoder
->dev
;
1014 if (is_edp(intel_dp
))
1015 ironlake_edp_panel_vdd_on(intel_dp
);
1017 intel_dp_start_link_train(intel_dp
);
1019 if (is_edp(intel_dp
)) {
1020 ironlake_edp_panel_on(intel_dp
);
1021 ironlake_edp_panel_vdd_off(intel_dp
);
1024 intel_dp_complete_link_train(intel_dp
);
1026 if (is_edp(intel_dp
))
1027 ironlake_edp_backlight_on(dev
);
1029 intel_dp
->dpms_mode
= DRM_MODE_DPMS_ON
;
1033 intel_dp_dpms(struct drm_encoder
*encoder
, int mode
)
1035 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1036 struct drm_device
*dev
= encoder
->dev
;
1037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1038 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1040 if (mode
!= DRM_MODE_DPMS_ON
) {
1041 if (is_edp(intel_dp
))
1042 ironlake_edp_backlight_off(dev
);
1043 intel_dp_sink_dpms(intel_dp
, mode
);
1044 intel_dp_link_down(intel_dp
);
1045 if (is_edp(intel_dp
))
1046 ironlake_edp_panel_off(dev
);
1047 if (is_edp(intel_dp
) && !is_pch_edp(intel_dp
))
1048 ironlake_edp_pll_off(encoder
);
1050 if (is_edp(intel_dp
))
1051 ironlake_edp_panel_vdd_on(intel_dp
);
1052 intel_dp_sink_dpms(intel_dp
, mode
);
1053 if (!(dp_reg
& DP_PORT_EN
)) {
1054 intel_dp_start_link_train(intel_dp
);
1055 if (is_edp(intel_dp
)) {
1056 ironlake_edp_panel_on(intel_dp
);
1057 ironlake_edp_panel_vdd_off(intel_dp
);
1059 intel_dp_complete_link_train(intel_dp
);
1061 if (is_edp(intel_dp
))
1062 ironlake_edp_backlight_on(dev
);
1064 intel_dp
->dpms_mode
= mode
;
1068 * Native read with retry for link status and receiver capability reads for
1069 * cases where the sink may still be asleep.
1072 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1073 uint8_t *recv
, int recv_bytes
)
1078 * Sinks are *supposed* to come up within 1ms from an off state,
1079 * but we're also supposed to retry 3 times per the spec.
1081 for (i
= 0; i
< 3; i
++) {
1082 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1084 if (ret
== recv_bytes
)
1093 * Fetch AUX CH registers 0x202 - 0x207 which contain
1094 * link status information
1097 intel_dp_get_link_status(struct intel_dp
*intel_dp
)
1099 return intel_dp_aux_native_read_retry(intel_dp
,
1101 intel_dp
->link_status
,
1102 DP_LINK_STATUS_SIZE
);
1106 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1109 return link_status
[r
- DP_LANE0_1_STATUS
];
1113 intel_get_adjust_request_voltage(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1116 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
1117 int s
= ((lane
& 1) ?
1118 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
1119 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
1120 uint8_t l
= intel_dp_link_status(link_status
, i
);
1122 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
1126 intel_get_adjust_request_pre_emphasis(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1129 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
1130 int s
= ((lane
& 1) ?
1131 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
1132 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
1133 uint8_t l
= intel_dp_link_status(link_status
, i
);
1135 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1140 static char *voltage_names
[] = {
1141 "0.4V", "0.6V", "0.8V", "1.2V"
1143 static char *pre_emph_names
[] = {
1144 "0dB", "3.5dB", "6dB", "9.5dB"
1146 static char *link_train_names
[] = {
1147 "pattern 1", "pattern 2", "idle", "off"
1152 * These are source-specific values; current Intel hardware supports
1153 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1155 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1158 intel_dp_pre_emphasis_max(uint8_t voltage_swing
)
1160 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1161 case DP_TRAIN_VOLTAGE_SWING_400
:
1162 return DP_TRAIN_PRE_EMPHASIS_6
;
1163 case DP_TRAIN_VOLTAGE_SWING_600
:
1164 return DP_TRAIN_PRE_EMPHASIS_6
;
1165 case DP_TRAIN_VOLTAGE_SWING_800
:
1166 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1167 case DP_TRAIN_VOLTAGE_SWING_1200
:
1169 return DP_TRAIN_PRE_EMPHASIS_0
;
1174 intel_get_adjust_train(struct intel_dp
*intel_dp
)
1180 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1181 uint8_t this_v
= intel_get_adjust_request_voltage(intel_dp
->link_status
, lane
);
1182 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(intel_dp
->link_status
, lane
);
1190 if (v
>= I830_DP_VOLTAGE_MAX
)
1191 v
= I830_DP_VOLTAGE_MAX
| DP_TRAIN_MAX_SWING_REACHED
;
1193 if (p
>= intel_dp_pre_emphasis_max(v
))
1194 p
= intel_dp_pre_emphasis_max(v
) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1196 for (lane
= 0; lane
< 4; lane
++)
1197 intel_dp
->train_set
[lane
] = v
| p
;
1201 intel_dp_signal_levels(uint8_t train_set
, int lane_count
)
1203 uint32_t signal_levels
= 0;
1205 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1206 case DP_TRAIN_VOLTAGE_SWING_400
:
1208 signal_levels
|= DP_VOLTAGE_0_4
;
1210 case DP_TRAIN_VOLTAGE_SWING_600
:
1211 signal_levels
|= DP_VOLTAGE_0_6
;
1213 case DP_TRAIN_VOLTAGE_SWING_800
:
1214 signal_levels
|= DP_VOLTAGE_0_8
;
1216 case DP_TRAIN_VOLTAGE_SWING_1200
:
1217 signal_levels
|= DP_VOLTAGE_1_2
;
1220 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1221 case DP_TRAIN_PRE_EMPHASIS_0
:
1223 signal_levels
|= DP_PRE_EMPHASIS_0
;
1225 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1226 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1228 case DP_TRAIN_PRE_EMPHASIS_6
:
1229 signal_levels
|= DP_PRE_EMPHASIS_6
;
1231 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1232 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1235 return signal_levels
;
1238 /* Gen6's DP voltage swing and pre-emphasis control */
1240 intel_gen6_edp_signal_levels(uint8_t train_set
)
1242 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1243 DP_TRAIN_PRE_EMPHASIS_MASK
);
1244 switch (signal_levels
) {
1245 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1246 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1247 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1248 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1249 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1250 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1251 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1252 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1253 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1254 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1255 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1256 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1257 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1258 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1260 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1261 "0x%x\n", signal_levels
);
1262 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1267 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1270 int i
= DP_LANE0_1_STATUS
+ (lane
>> 1);
1271 int s
= (lane
& 1) * 4;
1272 uint8_t l
= intel_dp_link_status(link_status
, i
);
1274 return (l
>> s
) & 0xf;
1277 /* Check for clock recovery is done on all channels */
1279 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1282 uint8_t lane_status
;
1284 for (lane
= 0; lane
< lane_count
; lane
++) {
1285 lane_status
= intel_get_lane_status(link_status
, lane
);
1286 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1292 /* Check to see if channel eq is done on all channels */
1293 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1294 DP_LANE_CHANNEL_EQ_DONE|\
1295 DP_LANE_SYMBOL_LOCKED)
1297 intel_channel_eq_ok(struct intel_dp
*intel_dp
)
1300 uint8_t lane_status
;
1303 lane_align
= intel_dp_link_status(intel_dp
->link_status
,
1304 DP_LANE_ALIGN_STATUS_UPDATED
);
1305 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1307 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1308 lane_status
= intel_get_lane_status(intel_dp
->link_status
, lane
);
1309 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1316 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1317 uint32_t dp_reg_value
,
1318 uint8_t dp_train_pat
)
1320 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1324 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1325 POSTING_READ(intel_dp
->output_reg
);
1327 intel_dp_aux_native_write_1(intel_dp
,
1328 DP_TRAINING_PATTERN_SET
,
1331 ret
= intel_dp_aux_native_write(intel_dp
,
1332 DP_TRAINING_LANE0_SET
,
1333 intel_dp
->train_set
, 4);
1340 /* Enable corresponding port and start training pattern 1 */
1342 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1344 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1346 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_dp
->base
.base
.crtc
);
1349 bool clock_recovery
= false;
1352 uint32_t DP
= intel_dp
->DP
;
1355 * On CPT we have to enable the port in training pattern 1, which
1356 * will happen below in intel_dp_set_link_train. Otherwise, enable
1357 * the port and wait for it to become active.
1359 if (!HAS_PCH_CPT(dev
)) {
1360 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
1361 POSTING_READ(intel_dp
->output_reg
);
1362 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1365 /* Write the link configuration data */
1366 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1367 intel_dp
->link_configuration
,
1368 DP_LINK_CONFIGURATION_SIZE
);
1371 if (HAS_PCH_CPT(dev
) && !is_edp(intel_dp
))
1372 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1374 DP
&= ~DP_LINK_TRAIN_MASK
;
1375 memset(intel_dp
->train_set
, 0, 4);
1378 clock_recovery
= false;
1380 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1381 uint32_t signal_levels
;
1382 if (IS_GEN6(dev
) && is_edp(intel_dp
)) {
1383 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1384 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1386 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0], intel_dp
->lane_count
);
1387 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1390 if (HAS_PCH_CPT(dev
) && !is_edp(intel_dp
))
1391 reg
= DP
| DP_LINK_TRAIN_PAT_1_CPT
;
1393 reg
= DP
| DP_LINK_TRAIN_PAT_1
;
1395 if (!intel_dp_set_link_train(intel_dp
, reg
,
1396 DP_TRAINING_PATTERN_1
|
1397 DP_LINK_SCRAMBLING_DISABLE
))
1399 /* Set training pattern 1 */
1402 if (!intel_dp_get_link_status(intel_dp
))
1405 if (intel_clock_recovery_ok(intel_dp
->link_status
, intel_dp
->lane_count
)) {
1406 clock_recovery
= true;
1410 /* Check to see if we've tried the max voltage */
1411 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1412 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1414 if (i
== intel_dp
->lane_count
)
1417 /* Check to see if we've tried the same voltage 5 times */
1418 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1424 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1426 /* Compute new intel_dp->train_set as requested by target */
1427 intel_get_adjust_train(intel_dp
);
1434 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1436 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1438 bool channel_eq
= false;
1439 int tries
, cr_tries
;
1441 uint32_t DP
= intel_dp
->DP
;
1443 /* channel equalization */
1448 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1449 uint32_t signal_levels
;
1452 DRM_ERROR("failed to train DP, aborting\n");
1453 intel_dp_link_down(intel_dp
);
1457 if (IS_GEN6(dev
) && is_edp(intel_dp
)) {
1458 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1459 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1461 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0], intel_dp
->lane_count
);
1462 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1465 if (HAS_PCH_CPT(dev
) && !is_edp(intel_dp
))
1466 reg
= DP
| DP_LINK_TRAIN_PAT_2_CPT
;
1468 reg
= DP
| DP_LINK_TRAIN_PAT_2
;
1470 /* channel eq pattern */
1471 if (!intel_dp_set_link_train(intel_dp
, reg
,
1472 DP_TRAINING_PATTERN_2
|
1473 DP_LINK_SCRAMBLING_DISABLE
))
1477 if (!intel_dp_get_link_status(intel_dp
))
1480 /* Make sure clock is still ok */
1481 if (!intel_clock_recovery_ok(intel_dp
->link_status
, intel_dp
->lane_count
)) {
1482 intel_dp_start_link_train(intel_dp
);
1487 if (intel_channel_eq_ok(intel_dp
)) {
1492 /* Try 5 times, then try clock recovery if that fails */
1494 intel_dp_link_down(intel_dp
);
1495 intel_dp_start_link_train(intel_dp
);
1501 /* Compute new intel_dp->train_set as requested by target */
1502 intel_get_adjust_train(intel_dp
);
1506 if (HAS_PCH_CPT(dev
) && !is_edp(intel_dp
))
1507 reg
= DP
| DP_LINK_TRAIN_OFF_CPT
;
1509 reg
= DP
| DP_LINK_TRAIN_OFF
;
1511 I915_WRITE(intel_dp
->output_reg
, reg
);
1512 POSTING_READ(intel_dp
->output_reg
);
1513 intel_dp_aux_native_write_1(intel_dp
,
1514 DP_TRAINING_PATTERN_SET
, DP_TRAINING_PATTERN_DISABLE
);
1518 intel_dp_link_down(struct intel_dp
*intel_dp
)
1520 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1522 uint32_t DP
= intel_dp
->DP
;
1524 if ((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0)
1527 DRM_DEBUG_KMS("\n");
1529 if (is_edp(intel_dp
)) {
1530 DP
&= ~DP_PLL_ENABLE
;
1531 I915_WRITE(intel_dp
->output_reg
, DP
);
1532 POSTING_READ(intel_dp
->output_reg
);
1536 if (HAS_PCH_CPT(dev
) && !is_edp(intel_dp
)) {
1537 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1538 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1540 DP
&= ~DP_LINK_TRAIN_MASK
;
1541 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1543 POSTING_READ(intel_dp
->output_reg
);
1547 if (is_edp(intel_dp
))
1548 DP
|= DP_LINK_TRAIN_OFF
;
1550 if (!HAS_PCH_CPT(dev
) &&
1551 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
1552 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1554 /* Hardware workaround: leaving our transcoder select
1555 * set to transcoder B while it's off will prevent the
1556 * corresponding HDMI output on transcoder A.
1558 * Combine this with another hardware workaround:
1559 * transcoder select bit can only be cleared while the
1562 DP
&= ~DP_PIPEB_SELECT
;
1563 I915_WRITE(intel_dp
->output_reg
, DP
);
1565 /* Changes to enable or select take place the vblank
1566 * after being written.
1569 /* We can arrive here never having been attached
1570 * to a CRTC, for instance, due to inheriting
1571 * random state from the BIOS.
1573 * If the pipe is not running, play safe and
1574 * wait for the clocks to stabilise before
1577 POSTING_READ(intel_dp
->output_reg
);
1580 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
1583 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
1584 POSTING_READ(intel_dp
->output_reg
);
1588 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
1590 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
1591 sizeof(intel_dp
->dpcd
)) &&
1592 (intel_dp
->dpcd
[DP_DPCD_REV
] != 0)) {
1600 * According to DP spec
1603 * 2. Configure link according to Receiver Capabilities
1604 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1605 * 4. Check link status on receipt of hot-plug interrupt
1609 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
1611 if (intel_dp
->dpms_mode
!= DRM_MODE_DPMS_ON
)
1614 if (!intel_dp
->base
.base
.crtc
)
1617 /* Try to read receiver status if the link appears to be up */
1618 if (!intel_dp_get_link_status(intel_dp
)) {
1619 intel_dp_link_down(intel_dp
);
1623 /* Now read the DPCD to see if it's actually running */
1624 if (!intel_dp_get_dpcd(intel_dp
)) {
1625 intel_dp_link_down(intel_dp
);
1629 if (!intel_channel_eq_ok(intel_dp
)) {
1630 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1631 drm_get_encoder_name(&intel_dp
->base
.base
));
1632 intel_dp_start_link_train(intel_dp
);
1633 intel_dp_complete_link_train(intel_dp
);
1637 static enum drm_connector_status
1638 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
1640 if (intel_dp_get_dpcd(intel_dp
))
1641 return connector_status_connected
;
1642 return connector_status_disconnected
;
1645 static enum drm_connector_status
1646 ironlake_dp_detect(struct intel_dp
*intel_dp
)
1648 enum drm_connector_status status
;
1650 /* Can't disconnect eDP, but you can close the lid... */
1651 if (is_edp(intel_dp
)) {
1652 status
= intel_panel_detect(intel_dp
->base
.base
.dev
);
1653 if (status
== connector_status_unknown
)
1654 status
= connector_status_connected
;
1658 return intel_dp_detect_dpcd(intel_dp
);
1661 static enum drm_connector_status
1662 g4x_dp_detect(struct intel_dp
*intel_dp
)
1664 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1668 switch (intel_dp
->output_reg
) {
1670 bit
= DPB_HOTPLUG_INT_STATUS
;
1673 bit
= DPC_HOTPLUG_INT_STATUS
;
1676 bit
= DPD_HOTPLUG_INT_STATUS
;
1679 return connector_status_unknown
;
1682 temp
= I915_READ(PORT_HOTPLUG_STAT
);
1684 if ((temp
& bit
) == 0)
1685 return connector_status_disconnected
;
1687 return intel_dp_detect_dpcd(intel_dp
);
1691 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1693 * \return true if DP port is connected.
1694 * \return false if DP port is disconnected.
1696 static enum drm_connector_status
1697 intel_dp_detect(struct drm_connector
*connector
, bool force
)
1699 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
1700 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1701 enum drm_connector_status status
;
1702 struct edid
*edid
= NULL
;
1704 intel_dp
->has_audio
= false;
1706 if (HAS_PCH_SPLIT(dev
))
1707 status
= ironlake_dp_detect(intel_dp
);
1709 status
= g4x_dp_detect(intel_dp
);
1711 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1712 intel_dp
->dpcd
[0], intel_dp
->dpcd
[1], intel_dp
->dpcd
[2],
1713 intel_dp
->dpcd
[3], intel_dp
->dpcd
[4], intel_dp
->dpcd
[5],
1714 intel_dp
->dpcd
[6], intel_dp
->dpcd
[7]);
1716 if (status
!= connector_status_connected
)
1719 if (intel_dp
->force_audio
) {
1720 intel_dp
->has_audio
= intel_dp
->force_audio
> 0;
1722 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
1724 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
1725 connector
->display_info
.raw_edid
= NULL
;
1730 return connector_status_connected
;
1733 static int intel_dp_get_modes(struct drm_connector
*connector
)
1735 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
1736 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1740 /* We should parse the EDID data and find out if it has an audio sink
1743 ret
= intel_ddc_get_modes(connector
, &intel_dp
->adapter
);
1745 if (is_edp(intel_dp
) && !dev_priv
->panel_fixed_mode
) {
1746 struct drm_display_mode
*newmode
;
1747 list_for_each_entry(newmode
, &connector
->probed_modes
,
1749 if (newmode
->type
& DRM_MODE_TYPE_PREFERRED
) {
1750 dev_priv
->panel_fixed_mode
=
1751 drm_mode_duplicate(dev
, newmode
);
1760 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1761 if (is_edp(intel_dp
)) {
1762 if (dev_priv
->panel_fixed_mode
!= NULL
) {
1763 struct drm_display_mode
*mode
;
1764 mode
= drm_mode_duplicate(dev
, dev_priv
->panel_fixed_mode
);
1765 drm_mode_probed_add(connector
, mode
);
1773 intel_dp_detect_audio(struct drm_connector
*connector
)
1775 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
1777 bool has_audio
= false;
1779 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
1781 has_audio
= drm_detect_monitor_audio(edid
);
1783 connector
->display_info
.raw_edid
= NULL
;
1791 intel_dp_set_property(struct drm_connector
*connector
,
1792 struct drm_property
*property
,
1795 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
1796 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
1799 ret
= drm_connector_property_set_value(connector
, property
, val
);
1803 if (property
== dev_priv
->force_audio_property
) {
1807 if (i
== intel_dp
->force_audio
)
1810 intel_dp
->force_audio
= i
;
1813 has_audio
= intel_dp_detect_audio(connector
);
1817 if (has_audio
== intel_dp
->has_audio
)
1820 intel_dp
->has_audio
= has_audio
;
1824 if (property
== dev_priv
->broadcast_rgb_property
) {
1825 if (val
== !!intel_dp
->color_range
)
1828 intel_dp
->color_range
= val
? DP_COLOR_RANGE_16_235
: 0;
1835 if (intel_dp
->base
.base
.crtc
) {
1836 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1837 drm_crtc_helper_set_mode(crtc
, &crtc
->mode
,
1846 intel_dp_destroy(struct drm_connector
*connector
)
1848 struct drm_device
*dev
= connector
->dev
;
1850 if (intel_dpd_is_edp(dev
))
1851 intel_panel_destroy_backlight(dev
);
1853 drm_sysfs_connector_remove(connector
);
1854 drm_connector_cleanup(connector
);
1858 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
1860 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1862 i2c_del_adapter(&intel_dp
->adapter
);
1863 drm_encoder_cleanup(encoder
);
1867 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
1868 .dpms
= intel_dp_dpms
,
1869 .mode_fixup
= intel_dp_mode_fixup
,
1870 .prepare
= intel_dp_prepare
,
1871 .mode_set
= intel_dp_mode_set
,
1872 .commit
= intel_dp_commit
,
1875 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
1876 .dpms
= drm_helper_connector_dpms
,
1877 .detect
= intel_dp_detect
,
1878 .fill_modes
= drm_helper_probe_single_connector_modes
,
1879 .set_property
= intel_dp_set_property
,
1880 .destroy
= intel_dp_destroy
,
1883 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
1884 .get_modes
= intel_dp_get_modes
,
1885 .mode_valid
= intel_dp_mode_valid
,
1886 .best_encoder
= intel_best_encoder
,
1889 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
1890 .destroy
= intel_dp_encoder_destroy
,
1894 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
1896 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
1898 intel_dp_check_link_status(intel_dp
);
1901 /* Return which DP Port should be selected for Transcoder DP control */
1903 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
1905 struct drm_device
*dev
= crtc
->dev
;
1906 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
1907 struct drm_encoder
*encoder
;
1909 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
1910 struct intel_dp
*intel_dp
;
1912 if (encoder
->crtc
!= crtc
)
1915 intel_dp
= enc_to_intel_dp(encoder
);
1916 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
)
1917 return intel_dp
->output_reg
;
1923 /* check the VBT to see whether the eDP is on DP-D port */
1924 bool intel_dpd_is_edp(struct drm_device
*dev
)
1926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1927 struct child_device_config
*p_child
;
1930 if (!dev_priv
->child_dev_num
)
1933 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
1934 p_child
= dev_priv
->child_dev
+ i
;
1936 if (p_child
->dvo_port
== PORT_IDPD
&&
1937 p_child
->device_type
== DEVICE_TYPE_eDP
)
1944 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
1946 intel_attach_force_audio_property(connector
);
1947 intel_attach_broadcast_rgb_property(connector
);
1951 intel_dp_init(struct drm_device
*dev
, int output_reg
)
1953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1954 struct drm_connector
*connector
;
1955 struct intel_dp
*intel_dp
;
1956 struct intel_encoder
*intel_encoder
;
1957 struct intel_connector
*intel_connector
;
1958 const char *name
= NULL
;
1961 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
1965 intel_dp
->output_reg
= output_reg
;
1966 intel_dp
->dpms_mode
= -1;
1968 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1969 if (!intel_connector
) {
1973 intel_encoder
= &intel_dp
->base
;
1975 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
1976 if (intel_dpd_is_edp(dev
))
1977 intel_dp
->is_pch_edp
= true;
1979 if (output_reg
== DP_A
|| is_pch_edp(intel_dp
)) {
1980 type
= DRM_MODE_CONNECTOR_eDP
;
1981 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
1983 type
= DRM_MODE_CONNECTOR_DisplayPort
;
1984 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
1987 connector
= &intel_connector
->base
;
1988 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
1989 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
1991 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
1993 if (output_reg
== DP_B
|| output_reg
== PCH_DP_B
)
1994 intel_encoder
->clone_mask
= (1 << INTEL_DP_B_CLONE_BIT
);
1995 else if (output_reg
== DP_C
|| output_reg
== PCH_DP_C
)
1996 intel_encoder
->clone_mask
= (1 << INTEL_DP_C_CLONE_BIT
);
1997 else if (output_reg
== DP_D
|| output_reg
== PCH_DP_D
)
1998 intel_encoder
->clone_mask
= (1 << INTEL_DP_D_CLONE_BIT
);
2000 if (is_edp(intel_dp
))
2001 intel_encoder
->clone_mask
= (1 << INTEL_EDP_CLONE_BIT
);
2003 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
2004 connector
->interlace_allowed
= true;
2005 connector
->doublescan_allowed
= 0;
2007 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2008 DRM_MODE_ENCODER_TMDS
);
2009 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
2011 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2012 drm_sysfs_connector_add(connector
);
2014 /* Set up the DDC bus. */
2015 switch (output_reg
) {
2021 dev_priv
->hotplug_supported_mask
|=
2022 HDMIB_HOTPLUG_INT_STATUS
;
2027 dev_priv
->hotplug_supported_mask
|=
2028 HDMIC_HOTPLUG_INT_STATUS
;
2033 dev_priv
->hotplug_supported_mask
|=
2034 HDMID_HOTPLUG_INT_STATUS
;
2039 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2041 /* Cache some DPCD data in the eDP case */
2042 if (is_edp(intel_dp
)) {
2046 pp_on
= I915_READ(PCH_PP_ON_DELAYS
);
2047 pp_div
= I915_READ(PCH_PP_DIVISOR
);
2049 /* Get T3 & T12 values (note: VESA not bspec terminology) */
2050 dev_priv
->panel_t3
= (pp_on
& 0x1fff0000) >> 16;
2051 dev_priv
->panel_t3
/= 10; /* t3 in 100us units */
2052 dev_priv
->panel_t12
= pp_div
& 0xf;
2053 dev_priv
->panel_t12
*= 100; /* t12 in 100ms units */
2055 ironlake_edp_panel_vdd_on(intel_dp
);
2056 ret
= intel_dp_get_dpcd(intel_dp
);
2057 ironlake_edp_panel_vdd_off(intel_dp
);
2059 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2060 dev_priv
->no_aux_handshake
=
2061 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2062 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2064 /* if this fails, presume the device is a ghost */
2065 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2066 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2067 intel_dp_destroy(&intel_connector
->base
);
2072 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2074 if (is_edp(intel_dp
)) {
2075 /* initialize panel mode from VBT if available for eDP */
2076 if (dev_priv
->lfp_lvds_vbt_mode
) {
2077 dev_priv
->panel_fixed_mode
=
2078 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2079 if (dev_priv
->panel_fixed_mode
) {
2080 dev_priv
->panel_fixed_mode
->type
|=
2081 DRM_MODE_TYPE_PREFERRED
;
2084 dev_priv
->int_edp_connector
= connector
;
2085 intel_panel_setup_backlight(dev
);
2088 intel_dp_add_properties(intel_dp
, connector
);
2090 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2091 * 0xd. Failure to do so will result in spurious interrupts being
2092 * generated on the port when a cable is not attached.
2094 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2095 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2096 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);