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drm/i915: pass ELD to HDMI/DP audio driver
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
blobf0e5f9f32aa8ebdc0e962f6d3f915a772a2cf0b6
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41
42 #include "drm_crtc_helper.h"
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
50
51 typedef struct {
52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
61 } intel_clock_t;
62
63 typedef struct {
64 int min, max;
65 } intel_range_t;
66
67 typedef struct {
68 int dot_limit;
69 int p2_slow, p2_fast;
70 } intel_p2_t;
71
72 #define INTEL_P2_NUM 2
73 typedef struct intel_limit intel_limit_t;
74 struct intel_limit {
75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *);
79 };
80
81 /* FDI */
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
84 static bool
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *best_clock);
90
91 static bool
92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *best_clock);
94 static bool
95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *best_clock);
97
98 static inline u32 /* units of 100MHz */
99 intel_fdi_link_freq(struct drm_device *dev)
100 {
101 if (IS_GEN5(dev)) {
102 struct drm_i915_private *dev_priv = dev->dev_private;
103 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
104 } else
105 return 27;
106 }
107
108 static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 2 },
119 .find_pll = intel_find_best_PLL,
120 };
121
122 static const intel_limit_t intel_limits_i8xx_lvds = {
123 .dot = { .min = 25000, .max = 350000 },
124 .vco = { .min = 930000, .max = 1400000 },
125 .n = { .min = 3, .max = 16 },
126 .m = { .min = 96, .max = 140 },
127 .m1 = { .min = 18, .max = 26 },
128 .m2 = { .min = 6, .max = 16 },
129 .p = { .min = 4, .max = 128 },
130 .p1 = { .min = 1, .max = 6 },
131 .p2 = { .dot_limit = 165000,
132 .p2_slow = 14, .p2_fast = 7 },
133 .find_pll = intel_find_best_PLL,
134 };
135
136 static const intel_limit_t intel_limits_i9xx_sdvo = {
137 .dot = { .min = 20000, .max = 400000 },
138 .vco = { .min = 1400000, .max = 2800000 },
139 .n = { .min = 1, .max = 6 },
140 .m = { .min = 70, .max = 120 },
141 .m1 = { .min = 10, .max = 22 },
142 .m2 = { .min = 5, .max = 9 },
143 .p = { .min = 5, .max = 80 },
144 .p1 = { .min = 1, .max = 8 },
145 .p2 = { .dot_limit = 200000,
146 .p2_slow = 10, .p2_fast = 5 },
147 .find_pll = intel_find_best_PLL,
148 };
149
150 static const intel_limit_t intel_limits_i9xx_lvds = {
151 .dot = { .min = 20000, .max = 400000 },
152 .vco = { .min = 1400000, .max = 2800000 },
153 .n = { .min = 1, .max = 6 },
154 .m = { .min = 70, .max = 120 },
155 .m1 = { .min = 10, .max = 22 },
156 .m2 = { .min = 5, .max = 9 },
157 .p = { .min = 7, .max = 98 },
158 .p1 = { .min = 1, .max = 8 },
159 .p2 = { .dot_limit = 112000,
160 .p2_slow = 14, .p2_fast = 7 },
161 .find_pll = intel_find_best_PLL,
162 };
163
164
165 static const intel_limit_t intel_limits_g4x_sdvo = {
166 .dot = { .min = 25000, .max = 270000 },
167 .vco = { .min = 1750000, .max = 3500000},
168 .n = { .min = 1, .max = 4 },
169 .m = { .min = 104, .max = 138 },
170 .m1 = { .min = 17, .max = 23 },
171 .m2 = { .min = 5, .max = 11 },
172 .p = { .min = 10, .max = 30 },
173 .p1 = { .min = 1, .max = 3},
174 .p2 = { .dot_limit = 270000,
175 .p2_slow = 10,
176 .p2_fast = 10
177 },
178 .find_pll = intel_g4x_find_best_PLL,
179 };
180
181 static const intel_limit_t intel_limits_g4x_hdmi = {
182 .dot = { .min = 22000, .max = 400000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 16, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 5, .max = 80 },
189 .p1 = { .min = 1, .max = 8},
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 10, .p2_fast = 5 },
192 .find_pll = intel_g4x_find_best_PLL,
193 };
194
195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
196 .dot = { .min = 20000, .max = 115000 },
197 .vco = { .min = 1750000, .max = 3500000 },
198 .n = { .min = 1, .max = 3 },
199 .m = { .min = 104, .max = 138 },
200 .m1 = { .min = 17, .max = 23 },
201 .m2 = { .min = 5, .max = 11 },
202 .p = { .min = 28, .max = 112 },
203 .p1 = { .min = 2, .max = 8 },
204 .p2 = { .dot_limit = 0,
205 .p2_slow = 14, .p2_fast = 14
206 },
207 .find_pll = intel_g4x_find_best_PLL,
208 };
209
210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
211 .dot = { .min = 80000, .max = 224000 },
212 .vco = { .min = 1750000, .max = 3500000 },
213 .n = { .min = 1, .max = 3 },
214 .m = { .min = 104, .max = 138 },
215 .m1 = { .min = 17, .max = 23 },
216 .m2 = { .min = 5, .max = 11 },
217 .p = { .min = 14, .max = 42 },
218 .p1 = { .min = 2, .max = 6 },
219 .p2 = { .dot_limit = 0,
220 .p2_slow = 7, .p2_fast = 7
221 },
222 .find_pll = intel_g4x_find_best_PLL,
223 };
224
225 static const intel_limit_t intel_limits_g4x_display_port = {
226 .dot = { .min = 161670, .max = 227000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 2 },
229 .m = { .min = 97, .max = 108 },
230 .m1 = { .min = 0x10, .max = 0x12 },
231 .m2 = { .min = 0x05, .max = 0x06 },
232 .p = { .min = 10, .max = 20 },
233 .p1 = { .min = 1, .max = 2},
234 .p2 = { .dot_limit = 0,
235 .p2_slow = 10, .p2_fast = 10 },
236 .find_pll = intel_find_pll_g4x_dp,
237 };
238
239 static const intel_limit_t intel_limits_pineview_sdvo = {
240 .dot = { .min = 20000, .max = 400000},
241 .vco = { .min = 1700000, .max = 3500000 },
242 /* Pineview's Ncounter is a ring counter */
243 .n = { .min = 3, .max = 6 },
244 .m = { .min = 2, .max = 256 },
245 /* Pineview only has one combined m divider, which we treat as m2. */
246 .m1 = { .min = 0, .max = 0 },
247 .m2 = { .min = 0, .max = 254 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8 },
250 .p2 = { .dot_limit = 200000,
251 .p2_slow = 10, .p2_fast = 5 },
252 .find_pll = intel_find_best_PLL,
253 };
254
255 static const intel_limit_t intel_limits_pineview_lvds = {
256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1700000, .max = 3500000 },
258 .n = { .min = 3, .max = 6 },
259 .m = { .min = 2, .max = 256 },
260 .m1 = { .min = 0, .max = 0 },
261 .m2 = { .min = 0, .max = 254 },
262 .p = { .min = 7, .max = 112 },
263 .p1 = { .min = 1, .max = 8 },
264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 14 },
266 .find_pll = intel_find_best_PLL,
267 };
268
269 /* Ironlake / Sandybridge
270 *
271 * We calculate clock using (register_value + 2) for N/M1/M2, so here
272 * the range value for them is (actual_value - 2).
273 */
274 static const intel_limit_t intel_limits_ironlake_dac = {
275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 5 },
278 .m = { .min = 79, .max = 127 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 10, .p2_fast = 5 },
285 .find_pll = intel_g4x_find_best_PLL,
286 };
287
288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 1760000, .max = 3510000 },
291 .n = { .min = 1, .max = 3 },
292 .m = { .min = 79, .max = 118 },
293 .m1 = { .min = 12, .max = 22 },
294 .m2 = { .min = 5, .max = 9 },
295 .p = { .min = 28, .max = 112 },
296 .p1 = { .min = 2, .max = 8 },
297 .p2 = { .dot_limit = 225000,
298 .p2_slow = 14, .p2_fast = 14 },
299 .find_pll = intel_g4x_find_best_PLL,
300 };
301
302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 56 },
310 .p1 = { .min = 2, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
313 .find_pll = intel_g4x_find_best_PLL,
314 };
315
316 /* LVDS 100mhz refclk limits. */
317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 2 },
321 .m = { .min = 79, .max = 126 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
328 .find_pll = intel_g4x_find_best_PLL,
329 };
330
331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 126 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 42 },
339 .p1 = { .min = 2, .max = 6 },
340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
342 .find_pll = intel_g4x_find_best_PLL,
343 };
344
345 static const intel_limit_t intel_limits_ironlake_display_port = {
346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000},
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 81, .max = 90 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 10, .max = 20 },
353 .p1 = { .min = 1, .max = 2},
354 .p2 = { .dot_limit = 0,
355 .p2_slow = 10, .p2_fast = 10 },
356 .find_pll = intel_find_pll_ironlake_dp,
357 };
358
359 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
360 int refclk)
361 {
362 struct drm_device *dev = crtc->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
364 const intel_limit_t *limit;
365
366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
367 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
368 LVDS_CLKB_POWER_UP) {
369 /* LVDS dual channel */
370 if (refclk == 100000)
371 limit = &intel_limits_ironlake_dual_lvds_100m;
372 else
373 limit = &intel_limits_ironlake_dual_lvds;
374 } else {
375 if (refclk == 100000)
376 limit = &intel_limits_ironlake_single_lvds_100m;
377 else
378 limit = &intel_limits_ironlake_single_lvds;
379 }
380 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
381 HAS_eDP)
382 limit = &intel_limits_ironlake_display_port;
383 else
384 limit = &intel_limits_ironlake_dac;
385
386 return limit;
387 }
388
389 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
390 {
391 struct drm_device *dev = crtc->dev;
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 const intel_limit_t *limit;
394
395 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
396 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
397 LVDS_CLKB_POWER_UP)
398 /* LVDS with dual channel */
399 limit = &intel_limits_g4x_dual_channel_lvds;
400 else
401 /* LVDS with dual channel */
402 limit = &intel_limits_g4x_single_channel_lvds;
403 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
404 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
405 limit = &intel_limits_g4x_hdmi;
406 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
407 limit = &intel_limits_g4x_sdvo;
408 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
409 limit = &intel_limits_g4x_display_port;
410 } else /* The option is for other outputs */
411 limit = &intel_limits_i9xx_sdvo;
412
413 return limit;
414 }
415
416 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
417 {
418 struct drm_device *dev = crtc->dev;
419 const intel_limit_t *limit;
420
421 if (HAS_PCH_SPLIT(dev))
422 limit = intel_ironlake_limit(crtc, refclk);
423 else if (IS_G4X(dev)) {
424 limit = intel_g4x_limit(crtc);
425 } else if (IS_PINEVIEW(dev)) {
426 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
427 limit = &intel_limits_pineview_lvds;
428 else
429 limit = &intel_limits_pineview_sdvo;
430 } else if (!IS_GEN2(dev)) {
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
432 limit = &intel_limits_i9xx_lvds;
433 else
434 limit = &intel_limits_i9xx_sdvo;
435 } else {
436 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
437 limit = &intel_limits_i8xx_lvds;
438 else
439 limit = &intel_limits_i8xx_dvo;
440 }
441 return limit;
442 }
443
444 /* m1 is reserved as 0 in Pineview, n is a ring counter */
445 static void pineview_clock(int refclk, intel_clock_t *clock)
446 {
447 clock->m = clock->m2 + 2;
448 clock->p = clock->p1 * clock->p2;
449 clock->vco = refclk * clock->m / clock->n;
450 clock->dot = clock->vco / clock->p;
451 }
452
453 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
454 {
455 if (IS_PINEVIEW(dev)) {
456 pineview_clock(refclk, clock);
457 return;
458 }
459 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
460 clock->p = clock->p1 * clock->p2;
461 clock->vco = refclk * clock->m / (clock->n + 2);
462 clock->dot = clock->vco / clock->p;
463 }
464
465 /**
466 * Returns whether any output on the specified pipe is of the specified type
467 */
468 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
469 {
470 struct drm_device *dev = crtc->dev;
471 struct drm_mode_config *mode_config = &dev->mode_config;
472 struct intel_encoder *encoder;
473
474 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
475 if (encoder->base.crtc == crtc && encoder->type == type)
476 return true;
477
478 return false;
479 }
480
481 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
482 /**
483 * Returns whether the given set of divisors are valid for a given refclk with
484 * the given connectors.
485 */
486
487 static bool intel_PLL_is_valid(struct drm_device *dev,
488 const intel_limit_t *limit,
489 const intel_clock_t *clock)
490 {
491 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
492 INTELPllInvalid("p1 out of range\n");
493 if (clock->p < limit->p.min || limit->p.max < clock->p)
494 INTELPllInvalid("p out of range\n");
495 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
496 INTELPllInvalid("m2 out of range\n");
497 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
498 INTELPllInvalid("m1 out of range\n");
499 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
500 INTELPllInvalid("m1 <= m2\n");
501 if (clock->m < limit->m.min || limit->m.max < clock->m)
502 INTELPllInvalid("m out of range\n");
503 if (clock->n < limit->n.min || limit->n.max < clock->n)
504 INTELPllInvalid("n out of range\n");
505 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
506 INTELPllInvalid("vco out of range\n");
507 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
508 * connector, etc., rather than just a single range.
509 */
510 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
511 INTELPllInvalid("dot out of range\n");
512
513 return true;
514 }
515
516 static bool
517 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
518 int target, int refclk, intel_clock_t *best_clock)
519
520 {
521 struct drm_device *dev = crtc->dev;
522 struct drm_i915_private *dev_priv = dev->dev_private;
523 intel_clock_t clock;
524 int err = target;
525
526 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
527 (I915_READ(LVDS)) != 0) {
528 /*
529 * For LVDS, if the panel is on, just rely on its current
530 * settings for dual-channel. We haven't figured out how to
531 * reliably set up different single/dual channel state, if we
532 * even can.
533 */
534 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
535 LVDS_CLKB_POWER_UP)
536 clock.p2 = limit->p2.p2_fast;
537 else
538 clock.p2 = limit->p2.p2_slow;
539 } else {
540 if (target < limit->p2.dot_limit)
541 clock.p2 = limit->p2.p2_slow;
542 else
543 clock.p2 = limit->p2.p2_fast;
544 }
545
546 memset(best_clock, 0, sizeof(*best_clock));
547
548 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
549 clock.m1++) {
550 for (clock.m2 = limit->m2.min;
551 clock.m2 <= limit->m2.max; clock.m2++) {
552 /* m1 is always 0 in Pineview */
553 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
554 break;
555 for (clock.n = limit->n.min;
556 clock.n <= limit->n.max; clock.n++) {
557 for (clock.p1 = limit->p1.min;
558 clock.p1 <= limit->p1.max; clock.p1++) {
559 int this_err;
560
561 intel_clock(dev, refclk, &clock);
562 if (!intel_PLL_is_valid(dev, limit,
563 &clock))
564 continue;
565
566 this_err = abs(clock.dot - target);
567 if (this_err < err) {
568 *best_clock = clock;
569 err = this_err;
570 }
571 }
572 }
573 }
574 }
575
576 return (err != target);
577 }
578
579 static bool
580 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
581 int target, int refclk, intel_clock_t *best_clock)
582 {
583 struct drm_device *dev = crtc->dev;
584 struct drm_i915_private *dev_priv = dev->dev_private;
585 intel_clock_t clock;
586 int max_n;
587 bool found;
588 /* approximately equals target * 0.00585 */
589 int err_most = (target >> 8) + (target >> 9);
590 found = false;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 int lvds_reg;
594
595 if (HAS_PCH_SPLIT(dev))
596 lvds_reg = PCH_LVDS;
597 else
598 lvds_reg = LVDS;
599 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
600 LVDS_CLKB_POWER_UP)
601 clock.p2 = limit->p2.p2_fast;
602 else
603 clock.p2 = limit->p2.p2_slow;
604 } else {
605 if (target < limit->p2.dot_limit)
606 clock.p2 = limit->p2.p2_slow;
607 else
608 clock.p2 = limit->p2.p2_fast;
609 }
610
611 memset(best_clock, 0, sizeof(*best_clock));
612 max_n = limit->n.max;
613 /* based on hardware requirement, prefer smaller n to precision */
614 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
615 /* based on hardware requirement, prefere larger m1,m2 */
616 for (clock.m1 = limit->m1.max;
617 clock.m1 >= limit->m1.min; clock.m1--) {
618 for (clock.m2 = limit->m2.max;
619 clock.m2 >= limit->m2.min; clock.m2--) {
620 for (clock.p1 = limit->p1.max;
621 clock.p1 >= limit->p1.min; clock.p1--) {
622 int this_err;
623
624 intel_clock(dev, refclk, &clock);
625 if (!intel_PLL_is_valid(dev, limit,
626 &clock))
627 continue;
628
629 this_err = abs(clock.dot - target);
630 if (this_err < err_most) {
631 *best_clock = clock;
632 err_most = this_err;
633 max_n = clock.n;
634 found = true;
635 }
636 }
637 }
638 }
639 }
640 return found;
641 }
642
643 static bool
644 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int target, int refclk, intel_clock_t *best_clock)
646 {
647 struct drm_device *dev = crtc->dev;
648 intel_clock_t clock;
649
650 if (target < 200000) {
651 clock.n = 1;
652 clock.p1 = 2;
653 clock.p2 = 10;
654 clock.m1 = 12;
655 clock.m2 = 9;
656 } else {
657 clock.n = 2;
658 clock.p1 = 1;
659 clock.p2 = 10;
660 clock.m1 = 14;
661 clock.m2 = 8;
662 }
663 intel_clock(dev, refclk, &clock);
664 memcpy(best_clock, &clock, sizeof(intel_clock_t));
665 return true;
666 }
667
668 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
669 static bool
670 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
671 int target, int refclk, intel_clock_t *best_clock)
672 {
673 intel_clock_t clock;
674 if (target < 200000) {
675 clock.p1 = 2;
676 clock.p2 = 10;
677 clock.n = 2;
678 clock.m1 = 23;
679 clock.m2 = 8;
680 } else {
681 clock.p1 = 1;
682 clock.p2 = 10;
683 clock.n = 1;
684 clock.m1 = 14;
685 clock.m2 = 2;
686 }
687 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
688 clock.p = (clock.p1 * clock.p2);
689 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
690 clock.vco = 0;
691 memcpy(best_clock, &clock, sizeof(intel_clock_t));
692 return true;
693 }
694
695 /**
696 * intel_wait_for_vblank - wait for vblank on a given pipe
697 * @dev: drm device
698 * @pipe: pipe to wait for
699 *
700 * Wait for vblank to occur on a given pipe. Needed for various bits of
701 * mode setting code.
702 */
703 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
704 {
705 struct drm_i915_private *dev_priv = dev->dev_private;
706 int pipestat_reg = PIPESTAT(pipe);
707
708 /* Clear existing vblank status. Note this will clear any other
709 * sticky status fields as well.
710 *
711 * This races with i915_driver_irq_handler() with the result
712 * that either function could miss a vblank event. Here it is not
713 * fatal, as we will either wait upon the next vblank interrupt or
714 * timeout. Generally speaking intel_wait_for_vblank() is only
715 * called during modeset at which time the GPU should be idle and
716 * should *not* be performing page flips and thus not waiting on
717 * vblanks...
718 * Currently, the result of us stealing a vblank from the irq
719 * handler is that a single frame will be skipped during swapbuffers.
720 */
721 I915_WRITE(pipestat_reg,
722 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
723
724 /* Wait for vblank interrupt bit to set */
725 if (wait_for(I915_READ(pipestat_reg) &
726 PIPE_VBLANK_INTERRUPT_STATUS,
727 50))
728 DRM_DEBUG_KMS("vblank wait timed out\n");
729 }
730
731 /*
732 * intel_wait_for_pipe_off - wait for pipe to turn off
733 * @dev: drm device
734 * @pipe: pipe to wait for
735 *
736 * After disabling a pipe, we can't wait for vblank in the usual way,
737 * spinning on the vblank interrupt status bit, since we won't actually
738 * see an interrupt when the pipe is disabled.
739 *
740 * On Gen4 and above:
741 * wait for the pipe register state bit to turn off
742 *
743 * Otherwise:
744 * wait for the display line value to settle (it usually
745 * ends up stopping at the start of the next frame).
746 *
747 */
748 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
749 {
750 struct drm_i915_private *dev_priv = dev->dev_private;
751
752 if (INTEL_INFO(dev)->gen >= 4) {
753 int reg = PIPECONF(pipe);
754
755 /* Wait for the Pipe State to go off */
756 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
757 100))
758 DRM_DEBUG_KMS("pipe_off wait timed out\n");
759 } else {
760 u32 last_line;
761 int reg = PIPEDSL(pipe);
762 unsigned long timeout = jiffies + msecs_to_jiffies(100);
763
764 /* Wait for the display line to settle */
765 do {
766 last_line = I915_READ(reg) & DSL_LINEMASK;
767 mdelay(5);
768 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
769 time_after(timeout, jiffies));
770 if (time_after(jiffies, timeout))
771 DRM_DEBUG_KMS("pipe_off wait timed out\n");
772 }
773 }
774
775 static const char *state_string(bool enabled)
776 {
777 return enabled ? "on" : "off";
778 }
779
780 /* Only for pre-ILK configs */
781 static void assert_pll(struct drm_i915_private *dev_priv,
782 enum pipe pipe, bool state)
783 {
784 int reg;
785 u32 val;
786 bool cur_state;
787
788 reg = DPLL(pipe);
789 val = I915_READ(reg);
790 cur_state = !!(val & DPLL_VCO_ENABLE);
791 WARN(cur_state != state,
792 "PLL state assertion failure (expected %s, current %s)\n",
793 state_string(state), state_string(cur_state));
794 }
795 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
796 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
797
798 /* For ILK+ */
799 static void assert_pch_pll(struct drm_i915_private *dev_priv,
800 enum pipe pipe, bool state)
801 {
802 int reg;
803 u32 val;
804 bool cur_state;
805
806 reg = PCH_DPLL(pipe);
807 val = I915_READ(reg);
808 cur_state = !!(val & DPLL_VCO_ENABLE);
809 WARN(cur_state != state,
810 "PCH PLL state assertion failure (expected %s, current %s)\n",
811 state_string(state), state_string(cur_state));
812 }
813 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
814 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
815
816 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
817 enum pipe pipe, bool state)
818 {
819 int reg;
820 u32 val;
821 bool cur_state;
822
823 reg = FDI_TX_CTL(pipe);
824 val = I915_READ(reg);
825 cur_state = !!(val & FDI_TX_ENABLE);
826 WARN(cur_state != state,
827 "FDI TX state assertion failure (expected %s, current %s)\n",
828 state_string(state), state_string(cur_state));
829 }
830 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
831 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
832
833 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
834 enum pipe pipe, bool state)
835 {
836 int reg;
837 u32 val;
838 bool cur_state;
839
840 reg = FDI_RX_CTL(pipe);
841 val = I915_READ(reg);
842 cur_state = !!(val & FDI_RX_ENABLE);
843 WARN(cur_state != state,
844 "FDI RX state assertion failure (expected %s, current %s)\n",
845 state_string(state), state_string(cur_state));
846 }
847 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
848 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
849
850 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
851 enum pipe pipe)
852 {
853 int reg;
854 u32 val;
855
856 /* ILK FDI PLL is always enabled */
857 if (dev_priv->info->gen == 5)
858 return;
859
860 reg = FDI_TX_CTL(pipe);
861 val = I915_READ(reg);
862 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
863 }
864
865 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
866 enum pipe pipe)
867 {
868 int reg;
869 u32 val;
870
871 reg = FDI_RX_CTL(pipe);
872 val = I915_READ(reg);
873 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
874 }
875
876 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878 {
879 int pp_reg, lvds_reg;
880 u32 val;
881 enum pipe panel_pipe = PIPE_A;
882 bool locked = true;
883
884 if (HAS_PCH_SPLIT(dev_priv->dev)) {
885 pp_reg = PCH_PP_CONTROL;
886 lvds_reg = PCH_LVDS;
887 } else {
888 pp_reg = PP_CONTROL;
889 lvds_reg = LVDS;
890 }
891
892 val = I915_READ(pp_reg);
893 if (!(val & PANEL_POWER_ON) ||
894 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
895 locked = false;
896
897 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
898 panel_pipe = PIPE_B;
899
900 WARN(panel_pipe == pipe && locked,
901 "panel assertion failure, pipe %c regs locked\n",
902 pipe_name(pipe));
903 }
904
905 static void assert_pipe(struct drm_i915_private *dev_priv,
906 enum pipe pipe, bool state)
907 {
908 int reg;
909 u32 val;
910 bool cur_state;
911
912 reg = PIPECONF(pipe);
913 val = I915_READ(reg);
914 cur_state = !!(val & PIPECONF_ENABLE);
915 WARN(cur_state != state,
916 "pipe %c assertion failure (expected %s, current %s)\n",
917 pipe_name(pipe), state_string(state), state_string(cur_state));
918 }
919 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
920 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
921
922 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
923 enum plane plane)
924 {
925 int reg;
926 u32 val;
927
928 reg = DSPCNTR(plane);
929 val = I915_READ(reg);
930 WARN(!(val & DISPLAY_PLANE_ENABLE),
931 "plane %c assertion failure, should be active but is disabled\n",
932 plane_name(plane));
933 }
934
935 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
936 enum pipe pipe)
937 {
938 int reg, i;
939 u32 val;
940 int cur_pipe;
941
942 /* Planes are fixed to pipes on ILK+ */
943 if (HAS_PCH_SPLIT(dev_priv->dev))
944 return;
945
946 /* Need to check both planes against the pipe */
947 for (i = 0; i < 2; i++) {
948 reg = DSPCNTR(i);
949 val = I915_READ(reg);
950 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
951 DISPPLANE_SEL_PIPE_SHIFT;
952 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
953 "plane %c assertion failure, should be off on pipe %c but is still active\n",
954 plane_name(i), pipe_name(pipe));
955 }
956 }
957
958 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
959 {
960 u32 val;
961 bool enabled;
962
963 val = I915_READ(PCH_DREF_CONTROL);
964 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
965 DREF_SUPERSPREAD_SOURCE_MASK));
966 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
967 }
968
969 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
970 enum pipe pipe)
971 {
972 int reg;
973 u32 val;
974 bool enabled;
975
976 reg = TRANSCONF(pipe);
977 val = I915_READ(reg);
978 enabled = !!(val & TRANS_ENABLE);
979 WARN(enabled,
980 "transcoder assertion failed, should be off on pipe %c but is still active\n",
981 pipe_name(pipe));
982 }
983
984 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
985 enum pipe pipe, u32 port_sel, u32 val)
986 {
987 if ((val & DP_PORT_EN) == 0)
988 return false;
989
990 if (HAS_PCH_CPT(dev_priv->dev)) {
991 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
992 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
993 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
994 return false;
995 } else {
996 if ((val & DP_PIPE_MASK) != (pipe << 30))
997 return false;
998 }
999 return true;
1000 }
1001
1002 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1003 enum pipe pipe, u32 val)
1004 {
1005 if ((val & PORT_ENABLE) == 0)
1006 return false;
1007
1008 if (HAS_PCH_CPT(dev_priv->dev)) {
1009 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1010 return false;
1011 } else {
1012 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1013 return false;
1014 }
1015 return true;
1016 }
1017
1018 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1019 enum pipe pipe, u32 val)
1020 {
1021 if ((val & LVDS_PORT_EN) == 0)
1022 return false;
1023
1024 if (HAS_PCH_CPT(dev_priv->dev)) {
1025 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1026 return false;
1027 } else {
1028 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1029 return false;
1030 }
1031 return true;
1032 }
1033
1034 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1035 enum pipe pipe, u32 val)
1036 {
1037 if ((val & ADPA_DAC_ENABLE) == 0)
1038 return false;
1039 if (HAS_PCH_CPT(dev_priv->dev)) {
1040 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1041 return false;
1042 } else {
1043 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1044 return false;
1045 }
1046 return true;
1047 }
1048
1049 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1050 enum pipe pipe, int reg, u32 port_sel)
1051 {
1052 u32 val = I915_READ(reg);
1053 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1054 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1055 reg, pipe_name(pipe));
1056 }
1057
1058 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, int reg)
1060 {
1061 u32 val = I915_READ(reg);
1062 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1063 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1064 reg, pipe_name(pipe));
1065 }
1066
1067 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1068 enum pipe pipe)
1069 {
1070 int reg;
1071 u32 val;
1072
1073 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1074 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1075 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1076
1077 reg = PCH_ADPA;
1078 val = I915_READ(reg);
1079 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1080 "PCH VGA enabled on transcoder %c, should be disabled\n",
1081 pipe_name(pipe));
1082
1083 reg = PCH_LVDS;
1084 val = I915_READ(reg);
1085 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1086 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1087 pipe_name(pipe));
1088
1089 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1090 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1091 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1092 }
1093
1094 /**
1095 * intel_enable_pll - enable a PLL
1096 * @dev_priv: i915 private structure
1097 * @pipe: pipe PLL to enable
1098 *
1099 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1100 * make sure the PLL reg is writable first though, since the panel write
1101 * protect mechanism may be enabled.
1102 *
1103 * Note! This is for pre-ILK only.
1104 */
1105 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1106 {
1107 int reg;
1108 u32 val;
1109
1110 /* No really, not for ILK+ */
1111 BUG_ON(dev_priv->info->gen >= 5);
1112
1113 /* PLL is protected by panel, make sure we can write it */
1114 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1115 assert_panel_unlocked(dev_priv, pipe);
1116
1117 reg = DPLL(pipe);
1118 val = I915_READ(reg);
1119 val |= DPLL_VCO_ENABLE;
1120
1121 /* We do this three times for luck */
1122 I915_WRITE(reg, val);
1123 POSTING_READ(reg);
1124 udelay(150); /* wait for warmup */
1125 I915_WRITE(reg, val);
1126 POSTING_READ(reg);
1127 udelay(150); /* wait for warmup */
1128 I915_WRITE(reg, val);
1129 POSTING_READ(reg);
1130 udelay(150); /* wait for warmup */
1131 }
1132
1133 /**
1134 * intel_disable_pll - disable a PLL
1135 * @dev_priv: i915 private structure
1136 * @pipe: pipe PLL to disable
1137 *
1138 * Disable the PLL for @pipe, making sure the pipe is off first.
1139 *
1140 * Note! This is for pre-ILK only.
1141 */
1142 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1143 {
1144 int reg;
1145 u32 val;
1146
1147 /* Don't disable pipe A or pipe A PLLs if needed */
1148 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1149 return;
1150
1151 /* Make sure the pipe isn't still relying on us */
1152 assert_pipe_disabled(dev_priv, pipe);
1153
1154 reg = DPLL(pipe);
1155 val = I915_READ(reg);
1156 val &= ~DPLL_VCO_ENABLE;
1157 I915_WRITE(reg, val);
1158 POSTING_READ(reg);
1159 }
1160
1161 /**
1162 * intel_enable_pch_pll - enable PCH PLL
1163 * @dev_priv: i915 private structure
1164 * @pipe: pipe PLL to enable
1165 *
1166 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1167 * drives the transcoder clock.
1168 */
1169 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171 {
1172 int reg;
1173 u32 val;
1174
1175 /* PCH only available on ILK+ */
1176 BUG_ON(dev_priv->info->gen < 5);
1177
1178 /* PCH refclock must be enabled first */
1179 assert_pch_refclk_enabled(dev_priv);
1180
1181 reg = PCH_DPLL(pipe);
1182 val = I915_READ(reg);
1183 val |= DPLL_VCO_ENABLE;
1184 I915_WRITE(reg, val);
1185 POSTING_READ(reg);
1186 udelay(200);
1187 }
1188
1189 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1190 enum pipe pipe)
1191 {
1192 int reg;
1193 u32 val;
1194
1195 /* PCH only available on ILK+ */
1196 BUG_ON(dev_priv->info->gen < 5);
1197
1198 /* Make sure transcoder isn't still depending on us */
1199 assert_transcoder_disabled(dev_priv, pipe);
1200
1201 reg = PCH_DPLL(pipe);
1202 val = I915_READ(reg);
1203 val &= ~DPLL_VCO_ENABLE;
1204 I915_WRITE(reg, val);
1205 POSTING_READ(reg);
1206 udelay(200);
1207 }
1208
1209 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211 {
1212 int reg;
1213 u32 val;
1214
1215 /* PCH only available on ILK+ */
1216 BUG_ON(dev_priv->info->gen < 5);
1217
1218 /* Make sure PCH DPLL is enabled */
1219 assert_pch_pll_enabled(dev_priv, pipe);
1220
1221 /* FDI must be feeding us bits for PCH ports */
1222 assert_fdi_tx_enabled(dev_priv, pipe);
1223 assert_fdi_rx_enabled(dev_priv, pipe);
1224
1225 reg = TRANSCONF(pipe);
1226 val = I915_READ(reg);
1227
1228 if (HAS_PCH_IBX(dev_priv->dev)) {
1229 /*
1230 * make the BPC in transcoder be consistent with
1231 * that in pipeconf reg.
1232 */
1233 val &= ~PIPE_BPC_MASK;
1234 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1235 }
1236 I915_WRITE(reg, val | TRANS_ENABLE);
1237 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1238 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1239 }
1240
1241 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1242 enum pipe pipe)
1243 {
1244 int reg;
1245 u32 val;
1246
1247 /* FDI relies on the transcoder */
1248 assert_fdi_tx_disabled(dev_priv, pipe);
1249 assert_fdi_rx_disabled(dev_priv, pipe);
1250
1251 /* Ports must be off as well */
1252 assert_pch_ports_disabled(dev_priv, pipe);
1253
1254 reg = TRANSCONF(pipe);
1255 val = I915_READ(reg);
1256 val &= ~TRANS_ENABLE;
1257 I915_WRITE(reg, val);
1258 /* wait for PCH transcoder off, transcoder state */
1259 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1260 DRM_ERROR("failed to disable transcoder\n");
1261 }
1262
1263 /**
1264 * intel_enable_pipe - enable a pipe, asserting requirements
1265 * @dev_priv: i915 private structure
1266 * @pipe: pipe to enable
1267 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1268 *
1269 * Enable @pipe, making sure that various hardware specific requirements
1270 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1271 *
1272 * @pipe should be %PIPE_A or %PIPE_B.
1273 *
1274 * Will wait until the pipe is actually running (i.e. first vblank) before
1275 * returning.
1276 */
1277 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1278 bool pch_port)
1279 {
1280 int reg;
1281 u32 val;
1282
1283 /*
1284 * A pipe without a PLL won't actually be able to drive bits from
1285 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1286 * need the check.
1287 */
1288 if (!HAS_PCH_SPLIT(dev_priv->dev))
1289 assert_pll_enabled(dev_priv, pipe);
1290 else {
1291 if (pch_port) {
1292 /* if driving the PCH, we need FDI enabled */
1293 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1294 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1295 }
1296 /* FIXME: assert CPU port conditions for SNB+ */
1297 }
1298
1299 reg = PIPECONF(pipe);
1300 val = I915_READ(reg);
1301 if (val & PIPECONF_ENABLE)
1302 return;
1303
1304 I915_WRITE(reg, val | PIPECONF_ENABLE);
1305 intel_wait_for_vblank(dev_priv->dev, pipe);
1306 }
1307
1308 /**
1309 * intel_disable_pipe - disable a pipe, asserting requirements
1310 * @dev_priv: i915 private structure
1311 * @pipe: pipe to disable
1312 *
1313 * Disable @pipe, making sure that various hardware specific requirements
1314 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1315 *
1316 * @pipe should be %PIPE_A or %PIPE_B.
1317 *
1318 * Will wait until the pipe has shut down before returning.
1319 */
1320 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1321 enum pipe pipe)
1322 {
1323 int reg;
1324 u32 val;
1325
1326 /*
1327 * Make sure planes won't keep trying to pump pixels to us,
1328 * or we might hang the display.
1329 */
1330 assert_planes_disabled(dev_priv, pipe);
1331
1332 /* Don't disable pipe A or pipe A PLLs if needed */
1333 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1334 return;
1335
1336 reg = PIPECONF(pipe);
1337 val = I915_READ(reg);
1338 if ((val & PIPECONF_ENABLE) == 0)
1339 return;
1340
1341 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1342 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1343 }
1344
1345 /*
1346 * Plane regs are double buffered, going from enabled->disabled needs a
1347 * trigger in order to latch. The display address reg provides this.
1348 */
1349 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane)
1351 {
1352 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1353 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1354 }
1355
1356 /**
1357 * intel_enable_plane - enable a display plane on a given pipe
1358 * @dev_priv: i915 private structure
1359 * @plane: plane to enable
1360 * @pipe: pipe being fed
1361 *
1362 * Enable @plane on @pipe, making sure that @pipe is running first.
1363 */
1364 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1365 enum plane plane, enum pipe pipe)
1366 {
1367 int reg;
1368 u32 val;
1369
1370 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1371 assert_pipe_enabled(dev_priv, pipe);
1372
1373 reg = DSPCNTR(plane);
1374 val = I915_READ(reg);
1375 if (val & DISPLAY_PLANE_ENABLE)
1376 return;
1377
1378 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1379 intel_flush_display_plane(dev_priv, plane);
1380 intel_wait_for_vblank(dev_priv->dev, pipe);
1381 }
1382
1383 /**
1384 * intel_disable_plane - disable a display plane
1385 * @dev_priv: i915 private structure
1386 * @plane: plane to disable
1387 * @pipe: pipe consuming the data
1388 *
1389 * Disable @plane; should be an independent operation.
1390 */
1391 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1392 enum plane plane, enum pipe pipe)
1393 {
1394 int reg;
1395 u32 val;
1396
1397 reg = DSPCNTR(plane);
1398 val = I915_READ(reg);
1399 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1400 return;
1401
1402 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1403 intel_flush_display_plane(dev_priv, plane);
1404 intel_wait_for_vblank(dev_priv->dev, pipe);
1405 }
1406
1407 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1408 enum pipe pipe, int reg, u32 port_sel)
1409 {
1410 u32 val = I915_READ(reg);
1411 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1412 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1413 I915_WRITE(reg, val & ~DP_PORT_EN);
1414 }
1415 }
1416
1417 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1418 enum pipe pipe, int reg)
1419 {
1420 u32 val = I915_READ(reg);
1421 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1422 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1423 reg, pipe);
1424 I915_WRITE(reg, val & ~PORT_ENABLE);
1425 }
1426 }
1427
1428 /* Disable any ports connected to this transcoder */
1429 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1430 enum pipe pipe)
1431 {
1432 u32 reg, val;
1433
1434 val = I915_READ(PCH_PP_CONTROL);
1435 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1436
1437 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1438 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1439 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1440
1441 reg = PCH_ADPA;
1442 val = I915_READ(reg);
1443 if (adpa_pipe_enabled(dev_priv, val, pipe))
1444 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1445
1446 reg = PCH_LVDS;
1447 val = I915_READ(reg);
1448 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1449 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1450 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1451 POSTING_READ(reg);
1452 udelay(100);
1453 }
1454
1455 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1456 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1457 disable_pch_hdmi(dev_priv, pipe, HDMID);
1458 }
1459
1460 static void i8xx_disable_fbc(struct drm_device *dev)
1461 {
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463 u32 fbc_ctl;
1464
1465 /* Disable compression */
1466 fbc_ctl = I915_READ(FBC_CONTROL);
1467 if ((fbc_ctl & FBC_CTL_EN) == 0)
1468 return;
1469
1470 fbc_ctl &= ~FBC_CTL_EN;
1471 I915_WRITE(FBC_CONTROL, fbc_ctl);
1472
1473 /* Wait for compressing bit to clear */
1474 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1475 DRM_DEBUG_KMS("FBC idle timed out\n");
1476 return;
1477 }
1478
1479 DRM_DEBUG_KMS("disabled FBC\n");
1480 }
1481
1482 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1483 {
1484 struct drm_device *dev = crtc->dev;
1485 struct drm_i915_private *dev_priv = dev->dev_private;
1486 struct drm_framebuffer *fb = crtc->fb;
1487 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1488 struct drm_i915_gem_object *obj = intel_fb->obj;
1489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1490 int cfb_pitch;
1491 int plane, i;
1492 u32 fbc_ctl, fbc_ctl2;
1493
1494 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1495 if (fb->pitch < cfb_pitch)
1496 cfb_pitch = fb->pitch;
1497
1498 /* FBC_CTL wants 64B units */
1499 cfb_pitch = (cfb_pitch / 64) - 1;
1500 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1501
1502 /* Clear old tags */
1503 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1504 I915_WRITE(FBC_TAG + (i * 4), 0);
1505
1506 /* Set it up... */
1507 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1508 fbc_ctl2 |= plane;
1509 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1510 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1511
1512 /* enable it... */
1513 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1514 if (IS_I945GM(dev))
1515 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1516 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1517 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1518 fbc_ctl |= obj->fence_reg;
1519 I915_WRITE(FBC_CONTROL, fbc_ctl);
1520
1521 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1522 cfb_pitch, crtc->y, intel_crtc->plane);
1523 }
1524
1525 static bool i8xx_fbc_enabled(struct drm_device *dev)
1526 {
1527 struct drm_i915_private *dev_priv = dev->dev_private;
1528
1529 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1530 }
1531
1532 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1533 {
1534 struct drm_device *dev = crtc->dev;
1535 struct drm_i915_private *dev_priv = dev->dev_private;
1536 struct drm_framebuffer *fb = crtc->fb;
1537 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1538 struct drm_i915_gem_object *obj = intel_fb->obj;
1539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1540 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1541 unsigned long stall_watermark = 200;
1542 u32 dpfc_ctl;
1543
1544 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1545 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1546 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1547
1548 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1549 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1550 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1551 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1552
1553 /* enable it... */
1554 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1555
1556 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1557 }
1558
1559 static void g4x_disable_fbc(struct drm_device *dev)
1560 {
1561 struct drm_i915_private *dev_priv = dev->dev_private;
1562 u32 dpfc_ctl;
1563
1564 /* Disable compression */
1565 dpfc_ctl = I915_READ(DPFC_CONTROL);
1566 if (dpfc_ctl & DPFC_CTL_EN) {
1567 dpfc_ctl &= ~DPFC_CTL_EN;
1568 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1569
1570 DRM_DEBUG_KMS("disabled FBC\n");
1571 }
1572 }
1573
1574 static bool g4x_fbc_enabled(struct drm_device *dev)
1575 {
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1577
1578 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1579 }
1580
1581 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1582 {
1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584 u32 blt_ecoskpd;
1585
1586 /* Make sure blitter notifies FBC of writes */
1587 gen6_gt_force_wake_get(dev_priv);
1588 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1589 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1590 GEN6_BLITTER_LOCK_SHIFT;
1591 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1592 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1593 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1594 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1595 GEN6_BLITTER_LOCK_SHIFT);
1596 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1597 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1598 gen6_gt_force_wake_put(dev_priv);
1599 }
1600
1601 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1602 {
1603 struct drm_device *dev = crtc->dev;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 struct drm_framebuffer *fb = crtc->fb;
1606 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1607 struct drm_i915_gem_object *obj = intel_fb->obj;
1608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1609 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1610 unsigned long stall_watermark = 200;
1611 u32 dpfc_ctl;
1612
1613 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1614 dpfc_ctl &= DPFC_RESERVED;
1615 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1616 /* Set persistent mode for front-buffer rendering, ala X. */
1617 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1618 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1619 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1620
1621 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1622 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1623 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1624 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1625 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1626 /* enable it... */
1627 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1628
1629 if (IS_GEN6(dev)) {
1630 I915_WRITE(SNB_DPFC_CTL_SA,
1631 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1632 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1633 sandybridge_blit_fbc_update(dev);
1634 }
1635
1636 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1637 }
1638
1639 static void ironlake_disable_fbc(struct drm_device *dev)
1640 {
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 u32 dpfc_ctl;
1643
1644 /* Disable compression */
1645 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1646 if (dpfc_ctl & DPFC_CTL_EN) {
1647 dpfc_ctl &= ~DPFC_CTL_EN;
1648 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1649
1650 DRM_DEBUG_KMS("disabled FBC\n");
1651 }
1652 }
1653
1654 static bool ironlake_fbc_enabled(struct drm_device *dev)
1655 {
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657
1658 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1659 }
1660
1661 bool intel_fbc_enabled(struct drm_device *dev)
1662 {
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664
1665 if (!dev_priv->display.fbc_enabled)
1666 return false;
1667
1668 return dev_priv->display.fbc_enabled(dev);
1669 }
1670
1671 static void intel_fbc_work_fn(struct work_struct *__work)
1672 {
1673 struct intel_fbc_work *work =
1674 container_of(to_delayed_work(__work),
1675 struct intel_fbc_work, work);
1676 struct drm_device *dev = work->crtc->dev;
1677 struct drm_i915_private *dev_priv = dev->dev_private;
1678
1679 mutex_lock(&dev->struct_mutex);
1680 if (work == dev_priv->fbc_work) {
1681 /* Double check that we haven't switched fb without cancelling
1682 * the prior work.
1683 */
1684 if (work->crtc->fb == work->fb) {
1685 dev_priv->display.enable_fbc(work->crtc,
1686 work->interval);
1687
1688 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1689 dev_priv->cfb_fb = work->crtc->fb->base.id;
1690 dev_priv->cfb_y = work->crtc->y;
1691 }
1692
1693 dev_priv->fbc_work = NULL;
1694 }
1695 mutex_unlock(&dev->struct_mutex);
1696
1697 kfree(work);
1698 }
1699
1700 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1701 {
1702 if (dev_priv->fbc_work == NULL)
1703 return;
1704
1705 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1706
1707 /* Synchronisation is provided by struct_mutex and checking of
1708 * dev_priv->fbc_work, so we can perform the cancellation
1709 * entirely asynchronously.
1710 */
1711 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1712 /* tasklet was killed before being run, clean up */
1713 kfree(dev_priv->fbc_work);
1714
1715 /* Mark the work as no longer wanted so that if it does
1716 * wake-up (because the work was already running and waiting
1717 * for our mutex), it will discover that is no longer
1718 * necessary to run.
1719 */
1720 dev_priv->fbc_work = NULL;
1721 }
1722
1723 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1724 {
1725 struct intel_fbc_work *work;
1726 struct drm_device *dev = crtc->dev;
1727 struct drm_i915_private *dev_priv = dev->dev_private;
1728
1729 if (!dev_priv->display.enable_fbc)
1730 return;
1731
1732 intel_cancel_fbc_work(dev_priv);
1733
1734 work = kzalloc(sizeof *work, GFP_KERNEL);
1735 if (work == NULL) {
1736 dev_priv->display.enable_fbc(crtc, interval);
1737 return;
1738 }
1739
1740 work->crtc = crtc;
1741 work->fb = crtc->fb;
1742 work->interval = interval;
1743 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1744
1745 dev_priv->fbc_work = work;
1746
1747 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1748
1749 /* Delay the actual enabling to let pageflipping cease and the
1750 * display to settle before starting the compression. Note that
1751 * this delay also serves a second purpose: it allows for a
1752 * vblank to pass after disabling the FBC before we attempt
1753 * to modify the control registers.
1754 *
1755 * A more complicated solution would involve tracking vblanks
1756 * following the termination of the page-flipping sequence
1757 * and indeed performing the enable as a co-routine and not
1758 * waiting synchronously upon the vblank.
1759 */
1760 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1761 }
1762
1763 void intel_disable_fbc(struct drm_device *dev)
1764 {
1765 struct drm_i915_private *dev_priv = dev->dev_private;
1766
1767 intel_cancel_fbc_work(dev_priv);
1768
1769 if (!dev_priv->display.disable_fbc)
1770 return;
1771
1772 dev_priv->display.disable_fbc(dev);
1773 dev_priv->cfb_plane = -1;
1774 }
1775
1776 /**
1777 * intel_update_fbc - enable/disable FBC as needed
1778 * @dev: the drm_device
1779 *
1780 * Set up the framebuffer compression hardware at mode set time. We
1781 * enable it if possible:
1782 * - plane A only (on pre-965)
1783 * - no pixel mulitply/line duplication
1784 * - no alpha buffer discard
1785 * - no dual wide
1786 * - framebuffer <= 2048 in width, 1536 in height
1787 *
1788 * We can't assume that any compression will take place (worst case),
1789 * so the compressed buffer has to be the same size as the uncompressed
1790 * one. It also must reside (along with the line length buffer) in
1791 * stolen memory.
1792 *
1793 * We need to enable/disable FBC on a global basis.
1794 */
1795 static void intel_update_fbc(struct drm_device *dev)
1796 {
1797 struct drm_i915_private *dev_priv = dev->dev_private;
1798 struct drm_crtc *crtc = NULL, *tmp_crtc;
1799 struct intel_crtc *intel_crtc;
1800 struct drm_framebuffer *fb;
1801 struct intel_framebuffer *intel_fb;
1802 struct drm_i915_gem_object *obj;
1803
1804 DRM_DEBUG_KMS("\n");
1805
1806 if (!i915_powersave)
1807 return;
1808
1809 if (!I915_HAS_FBC(dev))
1810 return;
1811
1812 /*
1813 * If FBC is already on, we just have to verify that we can
1814 * keep it that way...
1815 * Need to disable if:
1816 * - more than one pipe is active
1817 * - changing FBC params (stride, fence, mode)
1818 * - new fb is too large to fit in compressed buffer
1819 * - going to an unsupported config (interlace, pixel multiply, etc.)
1820 */
1821 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1822 if (tmp_crtc->enabled && tmp_crtc->fb) {
1823 if (crtc) {
1824 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1825 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1826 goto out_disable;
1827 }
1828 crtc = tmp_crtc;
1829 }
1830 }
1831
1832 if (!crtc || crtc->fb == NULL) {
1833 DRM_DEBUG_KMS("no output, disabling\n");
1834 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1835 goto out_disable;
1836 }
1837
1838 intel_crtc = to_intel_crtc(crtc);
1839 fb = crtc->fb;
1840 intel_fb = to_intel_framebuffer(fb);
1841 obj = intel_fb->obj;
1842
1843 if (!i915_enable_fbc) {
1844 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1845 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1846 goto out_disable;
1847 }
1848 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1849 DRM_DEBUG_KMS("framebuffer too large, disabling "
1850 "compression\n");
1851 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1852 goto out_disable;
1853 }
1854 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1855 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1856 DRM_DEBUG_KMS("mode incompatible with compression, "
1857 "disabling\n");
1858 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1859 goto out_disable;
1860 }
1861 if ((crtc->mode.hdisplay > 2048) ||
1862 (crtc->mode.vdisplay > 1536)) {
1863 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1864 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1865 goto out_disable;
1866 }
1867 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1868 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1869 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1870 goto out_disable;
1871 }
1872
1873 /* The use of a CPU fence is mandatory in order to detect writes
1874 * by the CPU to the scanout and trigger updates to the FBC.
1875 */
1876 if (obj->tiling_mode != I915_TILING_X ||
1877 obj->fence_reg == I915_FENCE_REG_NONE) {
1878 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1879 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1880 goto out_disable;
1881 }
1882
1883 /* If the kernel debugger is active, always disable compression */
1884 if (in_dbg_master())
1885 goto out_disable;
1886
1887 /* If the scanout has not changed, don't modify the FBC settings.
1888 * Note that we make the fundamental assumption that the fb->obj
1889 * cannot be unpinned (and have its GTT offset and fence revoked)
1890 * without first being decoupled from the scanout and FBC disabled.
1891 */
1892 if (dev_priv->cfb_plane == intel_crtc->plane &&
1893 dev_priv->cfb_fb == fb->base.id &&
1894 dev_priv->cfb_y == crtc->y)
1895 return;
1896
1897 if (intel_fbc_enabled(dev)) {
1898 /* We update FBC along two paths, after changing fb/crtc
1899 * configuration (modeswitching) and after page-flipping
1900 * finishes. For the latter, we know that not only did
1901 * we disable the FBC at the start of the page-flip
1902 * sequence, but also more than one vblank has passed.
1903 *
1904 * For the former case of modeswitching, it is possible
1905 * to switch between two FBC valid configurations
1906 * instantaneously so we do need to disable the FBC
1907 * before we can modify its control registers. We also
1908 * have to wait for the next vblank for that to take
1909 * effect. However, since we delay enabling FBC we can
1910 * assume that a vblank has passed since disabling and
1911 * that we can safely alter the registers in the deferred
1912 * callback.
1913 *
1914 * In the scenario that we go from a valid to invalid
1915 * and then back to valid FBC configuration we have
1916 * no strict enforcement that a vblank occurred since
1917 * disabling the FBC. However, along all current pipe
1918 * disabling paths we do need to wait for a vblank at
1919 * some point. And we wait before enabling FBC anyway.
1920 */
1921 DRM_DEBUG_KMS("disabling active FBC for update\n");
1922 intel_disable_fbc(dev);
1923 }
1924
1925 intel_enable_fbc(crtc, 500);
1926 return;
1927
1928 out_disable:
1929 /* Multiple disables should be harmless */
1930 if (intel_fbc_enabled(dev)) {
1931 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1932 intel_disable_fbc(dev);
1933 }
1934 }
1935
1936 int
1937 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1938 struct drm_i915_gem_object *obj,
1939 struct intel_ring_buffer *pipelined)
1940 {
1941 struct drm_i915_private *dev_priv = dev->dev_private;
1942 u32 alignment;
1943 int ret;
1944
1945 switch (obj->tiling_mode) {
1946 case I915_TILING_NONE:
1947 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1948 alignment = 128 * 1024;
1949 else if (INTEL_INFO(dev)->gen >= 4)
1950 alignment = 4 * 1024;
1951 else
1952 alignment = 64 * 1024;
1953 break;
1954 case I915_TILING_X:
1955 /* pin() will align the object as required by fence */
1956 alignment = 0;
1957 break;
1958 case I915_TILING_Y:
1959 /* FIXME: Is this true? */
1960 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1961 return -EINVAL;
1962 default:
1963 BUG();
1964 }
1965
1966 dev_priv->mm.interruptible = false;
1967 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1968 if (ret)
1969 goto err_interruptible;
1970
1971 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1972 * fence, whereas 965+ only requires a fence if using
1973 * framebuffer compression. For simplicity, we always install
1974 * a fence as the cost is not that onerous.
1975 */
1976 if (obj->tiling_mode != I915_TILING_NONE) {
1977 ret = i915_gem_object_get_fence(obj, pipelined);
1978 if (ret)
1979 goto err_unpin;
1980 }
1981
1982 dev_priv->mm.interruptible = true;
1983 return 0;
1984
1985 err_unpin:
1986 i915_gem_object_unpin(obj);
1987 err_interruptible:
1988 dev_priv->mm.interruptible = true;
1989 return ret;
1990 }
1991
1992 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1993 int x, int y)
1994 {
1995 struct drm_device *dev = crtc->dev;
1996 struct drm_i915_private *dev_priv = dev->dev_private;
1997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1998 struct intel_framebuffer *intel_fb;
1999 struct drm_i915_gem_object *obj;
2000 int plane = intel_crtc->plane;
2001 unsigned long Start, Offset;
2002 u32 dspcntr;
2003 u32 reg;
2004
2005 switch (plane) {
2006 case 0:
2007 case 1:
2008 break;
2009 default:
2010 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2011 return -EINVAL;
2012 }
2013
2014 intel_fb = to_intel_framebuffer(fb);
2015 obj = intel_fb->obj;
2016
2017 reg = DSPCNTR(plane);
2018 dspcntr = I915_READ(reg);
2019 /* Mask out pixel format bits in case we change it */
2020 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2021 switch (fb->bits_per_pixel) {
2022 case 8:
2023 dspcntr |= DISPPLANE_8BPP;
2024 break;
2025 case 16:
2026 if (fb->depth == 15)
2027 dspcntr |= DISPPLANE_15_16BPP;
2028 else
2029 dspcntr |= DISPPLANE_16BPP;
2030 break;
2031 case 24:
2032 case 32:
2033 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2034 break;
2035 default:
2036 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2037 return -EINVAL;
2038 }
2039 if (INTEL_INFO(dev)->gen >= 4) {
2040 if (obj->tiling_mode != I915_TILING_NONE)
2041 dspcntr |= DISPPLANE_TILED;
2042 else
2043 dspcntr &= ~DISPPLANE_TILED;
2044 }
2045
2046 I915_WRITE(reg, dspcntr);
2047
2048 Start = obj->gtt_offset;
2049 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2050
2051 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2052 Start, Offset, x, y, fb->pitch);
2053 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2054 if (INTEL_INFO(dev)->gen >= 4) {
2055 I915_WRITE(DSPSURF(plane), Start);
2056 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2057 I915_WRITE(DSPADDR(plane), Offset);
2058 } else
2059 I915_WRITE(DSPADDR(plane), Start + Offset);
2060 POSTING_READ(reg);
2061
2062 return 0;
2063 }
2064
2065 static int ironlake_update_plane(struct drm_crtc *crtc,
2066 struct drm_framebuffer *fb, int x, int y)
2067 {
2068 struct drm_device *dev = crtc->dev;
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2071 struct intel_framebuffer *intel_fb;
2072 struct drm_i915_gem_object *obj;
2073 int plane = intel_crtc->plane;
2074 unsigned long Start, Offset;
2075 u32 dspcntr;
2076 u32 reg;
2077
2078 switch (plane) {
2079 case 0:
2080 case 1:
2081 break;
2082 default:
2083 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2084 return -EINVAL;
2085 }
2086
2087 intel_fb = to_intel_framebuffer(fb);
2088 obj = intel_fb->obj;
2089
2090 reg = DSPCNTR(plane);
2091 dspcntr = I915_READ(reg);
2092 /* Mask out pixel format bits in case we change it */
2093 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2094 switch (fb->bits_per_pixel) {
2095 case 8:
2096 dspcntr |= DISPPLANE_8BPP;
2097 break;
2098 case 16:
2099 if (fb->depth != 16)
2100 return -EINVAL;
2101
2102 dspcntr |= DISPPLANE_16BPP;
2103 break;
2104 case 24:
2105 case 32:
2106 if (fb->depth == 24)
2107 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2108 else if (fb->depth == 30)
2109 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2110 else
2111 return -EINVAL;
2112 break;
2113 default:
2114 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2115 return -EINVAL;
2116 }
2117
2118 if (obj->tiling_mode != I915_TILING_NONE)
2119 dspcntr |= DISPPLANE_TILED;
2120 else
2121 dspcntr &= ~DISPPLANE_TILED;
2122
2123 /* must disable */
2124 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2125
2126 I915_WRITE(reg, dspcntr);
2127
2128 Start = obj->gtt_offset;
2129 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2130
2131 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2132 Start, Offset, x, y, fb->pitch);
2133 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2134 I915_WRITE(DSPSURF(plane), Start);
2135 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2136 I915_WRITE(DSPADDR(plane), Offset);
2137 POSTING_READ(reg);
2138
2139 return 0;
2140 }
2141
2142 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2143 static int
2144 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2145 int x, int y, enum mode_set_atomic state)
2146 {
2147 struct drm_device *dev = crtc->dev;
2148 struct drm_i915_private *dev_priv = dev->dev_private;
2149 int ret;
2150
2151 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2152 if (ret)
2153 return ret;
2154
2155 intel_update_fbc(dev);
2156 intel_increase_pllclock(crtc);
2157
2158 return 0;
2159 }
2160
2161 static int
2162 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2163 struct drm_framebuffer *old_fb)
2164 {
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_master_private *master_priv;
2167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2168 int ret;
2169
2170 /* no fb bound */
2171 if (!crtc->fb) {
2172 DRM_ERROR("No FB bound\n");
2173 return 0;
2174 }
2175
2176 switch (intel_crtc->plane) {
2177 case 0:
2178 case 1:
2179 break;
2180 default:
2181 DRM_ERROR("no plane for crtc\n");
2182 return -EINVAL;
2183 }
2184
2185 mutex_lock(&dev->struct_mutex);
2186 ret = intel_pin_and_fence_fb_obj(dev,
2187 to_intel_framebuffer(crtc->fb)->obj,
2188 NULL);
2189 if (ret != 0) {
2190 mutex_unlock(&dev->struct_mutex);
2191 DRM_ERROR("pin & fence failed\n");
2192 return ret;
2193 }
2194
2195 if (old_fb) {
2196 struct drm_i915_private *dev_priv = dev->dev_private;
2197 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2198
2199 wait_event(dev_priv->pending_flip_queue,
2200 atomic_read(&dev_priv->mm.wedged) ||
2201 atomic_read(&obj->pending_flip) == 0);
2202
2203 /* Big Hammer, we also need to ensure that any pending
2204 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2205 * current scanout is retired before unpinning the old
2206 * framebuffer.
2207 *
2208 * This should only fail upon a hung GPU, in which case we
2209 * can safely continue.
2210 */
2211 ret = i915_gem_object_finish_gpu(obj);
2212 (void) ret;
2213 }
2214
2215 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2216 LEAVE_ATOMIC_MODE_SET);
2217 if (ret) {
2218 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2219 mutex_unlock(&dev->struct_mutex);
2220 DRM_ERROR("failed to update base address\n");
2221 return ret;
2222 }
2223
2224 if (old_fb) {
2225 intel_wait_for_vblank(dev, intel_crtc->pipe);
2226 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2227 }
2228
2229 mutex_unlock(&dev->struct_mutex);
2230
2231 if (!dev->primary->master)
2232 return 0;
2233
2234 master_priv = dev->primary->master->driver_priv;
2235 if (!master_priv->sarea_priv)
2236 return 0;
2237
2238 if (intel_crtc->pipe) {
2239 master_priv->sarea_priv->pipeB_x = x;
2240 master_priv->sarea_priv->pipeB_y = y;
2241 } else {
2242 master_priv->sarea_priv->pipeA_x = x;
2243 master_priv->sarea_priv->pipeA_y = y;
2244 }
2245
2246 return 0;
2247 }
2248
2249 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2250 {
2251 struct drm_device *dev = crtc->dev;
2252 struct drm_i915_private *dev_priv = dev->dev_private;
2253 u32 dpa_ctl;
2254
2255 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2256 dpa_ctl = I915_READ(DP_A);
2257 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2258
2259 if (clock < 200000) {
2260 u32 temp;
2261 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2262 /* workaround for 160Mhz:
2263 1) program 0x4600c bits 15:0 = 0x8124
2264 2) program 0x46010 bit 0 = 1
2265 3) program 0x46034 bit 24 = 1
2266 4) program 0x64000 bit 14 = 1
2267 */
2268 temp = I915_READ(0x4600c);
2269 temp &= 0xffff0000;
2270 I915_WRITE(0x4600c, temp | 0x8124);
2271
2272 temp = I915_READ(0x46010);
2273 I915_WRITE(0x46010, temp | 1);
2274
2275 temp = I915_READ(0x46034);
2276 I915_WRITE(0x46034, temp | (1 << 24));
2277 } else {
2278 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2279 }
2280 I915_WRITE(DP_A, dpa_ctl);
2281
2282 POSTING_READ(DP_A);
2283 udelay(500);
2284 }
2285
2286 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2287 {
2288 struct drm_device *dev = crtc->dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291 int pipe = intel_crtc->pipe;
2292 u32 reg, temp;
2293
2294 /* enable normal train */
2295 reg = FDI_TX_CTL(pipe);
2296 temp = I915_READ(reg);
2297 if (IS_IVYBRIDGE(dev)) {
2298 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2299 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2300 } else {
2301 temp &= ~FDI_LINK_TRAIN_NONE;
2302 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2303 }
2304 I915_WRITE(reg, temp);
2305
2306 reg = FDI_RX_CTL(pipe);
2307 temp = I915_READ(reg);
2308 if (HAS_PCH_CPT(dev)) {
2309 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2310 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2311 } else {
2312 temp &= ~FDI_LINK_TRAIN_NONE;
2313 temp |= FDI_LINK_TRAIN_NONE;
2314 }
2315 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2316
2317 /* wait one idle pattern time */
2318 POSTING_READ(reg);
2319 udelay(1000);
2320
2321 /* IVB wants error correction enabled */
2322 if (IS_IVYBRIDGE(dev))
2323 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2324 FDI_FE_ERRC_ENABLE);
2325 }
2326
2327 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2328 {
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330 u32 flags = I915_READ(SOUTH_CHICKEN1);
2331
2332 flags |= FDI_PHASE_SYNC_OVR(pipe);
2333 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2334 flags |= FDI_PHASE_SYNC_EN(pipe);
2335 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2336 POSTING_READ(SOUTH_CHICKEN1);
2337 }
2338
2339 /* The FDI link training functions for ILK/Ibexpeak. */
2340 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2341 {
2342 struct drm_device *dev = crtc->dev;
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2345 int pipe = intel_crtc->pipe;
2346 int plane = intel_crtc->plane;
2347 u32 reg, temp, tries;
2348
2349 /* FDI needs bits from pipe & plane first */
2350 assert_pipe_enabled(dev_priv, pipe);
2351 assert_plane_enabled(dev_priv, plane);
2352
2353 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2354 for train result */
2355 reg = FDI_RX_IMR(pipe);
2356 temp = I915_READ(reg);
2357 temp &= ~FDI_RX_SYMBOL_LOCK;
2358 temp &= ~FDI_RX_BIT_LOCK;
2359 I915_WRITE(reg, temp);
2360 I915_READ(reg);
2361 udelay(150);
2362
2363 /* enable CPU FDI TX and PCH FDI RX */
2364 reg = FDI_TX_CTL(pipe);
2365 temp = I915_READ(reg);
2366 temp &= ~(7 << 19);
2367 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2368 temp &= ~FDI_LINK_TRAIN_NONE;
2369 temp |= FDI_LINK_TRAIN_PATTERN_1;
2370 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2371
2372 reg = FDI_RX_CTL(pipe);
2373 temp = I915_READ(reg);
2374 temp &= ~FDI_LINK_TRAIN_NONE;
2375 temp |= FDI_LINK_TRAIN_PATTERN_1;
2376 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2377
2378 POSTING_READ(reg);
2379 udelay(150);
2380
2381 /* Ironlake workaround, enable clock pointer after FDI enable*/
2382 if (HAS_PCH_IBX(dev)) {
2383 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2384 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2385 FDI_RX_PHASE_SYNC_POINTER_EN);
2386 }
2387
2388 reg = FDI_RX_IIR(pipe);
2389 for (tries = 0; tries < 5; tries++) {
2390 temp = I915_READ(reg);
2391 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2392
2393 if ((temp & FDI_RX_BIT_LOCK)) {
2394 DRM_DEBUG_KMS("FDI train 1 done.\n");
2395 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2396 break;
2397 }
2398 }
2399 if (tries == 5)
2400 DRM_ERROR("FDI train 1 fail!\n");
2401
2402 /* Train 2 */
2403 reg = FDI_TX_CTL(pipe);
2404 temp = I915_READ(reg);
2405 temp &= ~FDI_LINK_TRAIN_NONE;
2406 temp |= FDI_LINK_TRAIN_PATTERN_2;
2407 I915_WRITE(reg, temp);
2408
2409 reg = FDI_RX_CTL(pipe);
2410 temp = I915_READ(reg);
2411 temp &= ~FDI_LINK_TRAIN_NONE;
2412 temp |= FDI_LINK_TRAIN_PATTERN_2;
2413 I915_WRITE(reg, temp);
2414
2415 POSTING_READ(reg);
2416 udelay(150);
2417
2418 reg = FDI_RX_IIR(pipe);
2419 for (tries = 0; tries < 5; tries++) {
2420 temp = I915_READ(reg);
2421 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2422
2423 if (temp & FDI_RX_SYMBOL_LOCK) {
2424 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2425 DRM_DEBUG_KMS("FDI train 2 done.\n");
2426 break;
2427 }
2428 }
2429 if (tries == 5)
2430 DRM_ERROR("FDI train 2 fail!\n");
2431
2432 DRM_DEBUG_KMS("FDI train done\n");
2433
2434 }
2435
2436 static const int snb_b_fdi_train_param[] = {
2437 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2438 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2439 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2440 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2441 };
2442
2443 /* The FDI link training functions for SNB/Cougarpoint. */
2444 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2445 {
2446 struct drm_device *dev = crtc->dev;
2447 struct drm_i915_private *dev_priv = dev->dev_private;
2448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2449 int pipe = intel_crtc->pipe;
2450 u32 reg, temp, i;
2451
2452 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2453 for train result */
2454 reg = FDI_RX_IMR(pipe);
2455 temp = I915_READ(reg);
2456 temp &= ~FDI_RX_SYMBOL_LOCK;
2457 temp &= ~FDI_RX_BIT_LOCK;
2458 I915_WRITE(reg, temp);
2459
2460 POSTING_READ(reg);
2461 udelay(150);
2462
2463 /* enable CPU FDI TX and PCH FDI RX */
2464 reg = FDI_TX_CTL(pipe);
2465 temp = I915_READ(reg);
2466 temp &= ~(7 << 19);
2467 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2468 temp &= ~FDI_LINK_TRAIN_NONE;
2469 temp |= FDI_LINK_TRAIN_PATTERN_1;
2470 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2471 /* SNB-B */
2472 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2473 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2474
2475 reg = FDI_RX_CTL(pipe);
2476 temp = I915_READ(reg);
2477 if (HAS_PCH_CPT(dev)) {
2478 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2479 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2480 } else {
2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_1;
2483 }
2484 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2485
2486 POSTING_READ(reg);
2487 udelay(150);
2488
2489 if (HAS_PCH_CPT(dev))
2490 cpt_phase_pointer_enable(dev, pipe);
2491
2492 for (i = 0; i < 4; i++) {
2493 reg = FDI_TX_CTL(pipe);
2494 temp = I915_READ(reg);
2495 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2496 temp |= snb_b_fdi_train_param[i];
2497 I915_WRITE(reg, temp);
2498
2499 POSTING_READ(reg);
2500 udelay(500);
2501
2502 reg = FDI_RX_IIR(pipe);
2503 temp = I915_READ(reg);
2504 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2505
2506 if (temp & FDI_RX_BIT_LOCK) {
2507 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2508 DRM_DEBUG_KMS("FDI train 1 done.\n");
2509 break;
2510 }
2511 }
2512 if (i == 4)
2513 DRM_ERROR("FDI train 1 fail!\n");
2514
2515 /* Train 2 */
2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_LINK_TRAIN_NONE;
2519 temp |= FDI_LINK_TRAIN_PATTERN_2;
2520 if (IS_GEN6(dev)) {
2521 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2522 /* SNB-B */
2523 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2524 }
2525 I915_WRITE(reg, temp);
2526
2527 reg = FDI_RX_CTL(pipe);
2528 temp = I915_READ(reg);
2529 if (HAS_PCH_CPT(dev)) {
2530 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2531 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2532 } else {
2533 temp &= ~FDI_LINK_TRAIN_NONE;
2534 temp |= FDI_LINK_TRAIN_PATTERN_2;
2535 }
2536 I915_WRITE(reg, temp);
2537
2538 POSTING_READ(reg);
2539 udelay(150);
2540
2541 for (i = 0; i < 4; i++) {
2542 reg = FDI_TX_CTL(pipe);
2543 temp = I915_READ(reg);
2544 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2545 temp |= snb_b_fdi_train_param[i];
2546 I915_WRITE(reg, temp);
2547
2548 POSTING_READ(reg);
2549 udelay(500);
2550
2551 reg = FDI_RX_IIR(pipe);
2552 temp = I915_READ(reg);
2553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2554
2555 if (temp & FDI_RX_SYMBOL_LOCK) {
2556 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2557 DRM_DEBUG_KMS("FDI train 2 done.\n");
2558 break;
2559 }
2560 }
2561 if (i == 4)
2562 DRM_ERROR("FDI train 2 fail!\n");
2563
2564 DRM_DEBUG_KMS("FDI train done.\n");
2565 }
2566
2567 /* Manual link training for Ivy Bridge A0 parts */
2568 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2569 {
2570 struct drm_device *dev = crtc->dev;
2571 struct drm_i915_private *dev_priv = dev->dev_private;
2572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2573 int pipe = intel_crtc->pipe;
2574 u32 reg, temp, i;
2575
2576 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2577 for train result */
2578 reg = FDI_RX_IMR(pipe);
2579 temp = I915_READ(reg);
2580 temp &= ~FDI_RX_SYMBOL_LOCK;
2581 temp &= ~FDI_RX_BIT_LOCK;
2582 I915_WRITE(reg, temp);
2583
2584 POSTING_READ(reg);
2585 udelay(150);
2586
2587 /* enable CPU FDI TX and PCH FDI RX */
2588 reg = FDI_TX_CTL(pipe);
2589 temp = I915_READ(reg);
2590 temp &= ~(7 << 19);
2591 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2592 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2593 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2594 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2595 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2596 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2597
2598 reg = FDI_RX_CTL(pipe);
2599 temp = I915_READ(reg);
2600 temp &= ~FDI_LINK_TRAIN_AUTO;
2601 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2602 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2603 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2604
2605 POSTING_READ(reg);
2606 udelay(150);
2607
2608 if (HAS_PCH_CPT(dev))
2609 cpt_phase_pointer_enable(dev, pipe);
2610
2611 for (i = 0; i < 4; i++) {
2612 reg = FDI_TX_CTL(pipe);
2613 temp = I915_READ(reg);
2614 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2615 temp |= snb_b_fdi_train_param[i];
2616 I915_WRITE(reg, temp);
2617
2618 POSTING_READ(reg);
2619 udelay(500);
2620
2621 reg = FDI_RX_IIR(pipe);
2622 temp = I915_READ(reg);
2623 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2624
2625 if (temp & FDI_RX_BIT_LOCK ||
2626 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2627 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2628 DRM_DEBUG_KMS("FDI train 1 done.\n");
2629 break;
2630 }
2631 }
2632 if (i == 4)
2633 DRM_ERROR("FDI train 1 fail!\n");
2634
2635 /* Train 2 */
2636 reg = FDI_TX_CTL(pipe);
2637 temp = I915_READ(reg);
2638 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2639 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2640 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2642 I915_WRITE(reg, temp);
2643
2644 reg = FDI_RX_CTL(pipe);
2645 temp = I915_READ(reg);
2646 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2647 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2648 I915_WRITE(reg, temp);
2649
2650 POSTING_READ(reg);
2651 udelay(150);
2652
2653 for (i = 0; i < 4; i++) {
2654 reg = FDI_TX_CTL(pipe);
2655 temp = I915_READ(reg);
2656 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2657 temp |= snb_b_fdi_train_param[i];
2658 I915_WRITE(reg, temp);
2659
2660 POSTING_READ(reg);
2661 udelay(500);
2662
2663 reg = FDI_RX_IIR(pipe);
2664 temp = I915_READ(reg);
2665 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2666
2667 if (temp & FDI_RX_SYMBOL_LOCK) {
2668 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2669 DRM_DEBUG_KMS("FDI train 2 done.\n");
2670 break;
2671 }
2672 }
2673 if (i == 4)
2674 DRM_ERROR("FDI train 2 fail!\n");
2675
2676 DRM_DEBUG_KMS("FDI train done.\n");
2677 }
2678
2679 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2680 {
2681 struct drm_device *dev = crtc->dev;
2682 struct drm_i915_private *dev_priv = dev->dev_private;
2683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2684 int pipe = intel_crtc->pipe;
2685 u32 reg, temp;
2686
2687 /* Write the TU size bits so error detection works */
2688 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2689 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2690
2691 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2692 reg = FDI_RX_CTL(pipe);
2693 temp = I915_READ(reg);
2694 temp &= ~((0x7 << 19) | (0x7 << 16));
2695 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2696 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2697 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2698
2699 POSTING_READ(reg);
2700 udelay(200);
2701
2702 /* Switch from Rawclk to PCDclk */
2703 temp = I915_READ(reg);
2704 I915_WRITE(reg, temp | FDI_PCDCLK);
2705
2706 POSTING_READ(reg);
2707 udelay(200);
2708
2709 /* Enable CPU FDI TX PLL, always on for Ironlake */
2710 reg = FDI_TX_CTL(pipe);
2711 temp = I915_READ(reg);
2712 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2713 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2714
2715 POSTING_READ(reg);
2716 udelay(100);
2717 }
2718 }
2719
2720 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2721 {
2722 struct drm_i915_private *dev_priv = dev->dev_private;
2723 u32 flags = I915_READ(SOUTH_CHICKEN1);
2724
2725 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2726 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2727 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2728 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2729 POSTING_READ(SOUTH_CHICKEN1);
2730 }
2731 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2732 {
2733 struct drm_device *dev = crtc->dev;
2734 struct drm_i915_private *dev_priv = dev->dev_private;
2735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2736 int pipe = intel_crtc->pipe;
2737 u32 reg, temp;
2738
2739 /* disable CPU FDI tx and PCH FDI rx */
2740 reg = FDI_TX_CTL(pipe);
2741 temp = I915_READ(reg);
2742 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2743 POSTING_READ(reg);
2744
2745 reg = FDI_RX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 temp &= ~(0x7 << 16);
2748 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2749 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2750
2751 POSTING_READ(reg);
2752 udelay(100);
2753
2754 /* Ironlake workaround, disable clock pointer after downing FDI */
2755 if (HAS_PCH_IBX(dev)) {
2756 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2757 I915_WRITE(FDI_RX_CHICKEN(pipe),
2758 I915_READ(FDI_RX_CHICKEN(pipe) &
2759 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2760 } else if (HAS_PCH_CPT(dev)) {
2761 cpt_phase_pointer_disable(dev, pipe);
2762 }
2763
2764 /* still set train pattern 1 */
2765 reg = FDI_TX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~FDI_LINK_TRAIN_NONE;
2768 temp |= FDI_LINK_TRAIN_PATTERN_1;
2769 I915_WRITE(reg, temp);
2770
2771 reg = FDI_RX_CTL(pipe);
2772 temp = I915_READ(reg);
2773 if (HAS_PCH_CPT(dev)) {
2774 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2775 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2776 } else {
2777 temp &= ~FDI_LINK_TRAIN_NONE;
2778 temp |= FDI_LINK_TRAIN_PATTERN_1;
2779 }
2780 /* BPC in FDI rx is consistent with that in PIPECONF */
2781 temp &= ~(0x07 << 16);
2782 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2783 I915_WRITE(reg, temp);
2784
2785 POSTING_READ(reg);
2786 udelay(100);
2787 }
2788
2789 /*
2790 * When we disable a pipe, we need to clear any pending scanline wait events
2791 * to avoid hanging the ring, which we assume we are waiting on.
2792 */
2793 static void intel_clear_scanline_wait(struct drm_device *dev)
2794 {
2795 struct drm_i915_private *dev_priv = dev->dev_private;
2796 struct intel_ring_buffer *ring;
2797 u32 tmp;
2798
2799 if (IS_GEN2(dev))
2800 /* Can't break the hang on i8xx */
2801 return;
2802
2803 ring = LP_RING(dev_priv);
2804 tmp = I915_READ_CTL(ring);
2805 if (tmp & RING_WAIT)
2806 I915_WRITE_CTL(ring, tmp);
2807 }
2808
2809 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2810 {
2811 struct drm_i915_gem_object *obj;
2812 struct drm_i915_private *dev_priv;
2813
2814 if (crtc->fb == NULL)
2815 return;
2816
2817 obj = to_intel_framebuffer(crtc->fb)->obj;
2818 dev_priv = crtc->dev->dev_private;
2819 wait_event(dev_priv->pending_flip_queue,
2820 atomic_read(&obj->pending_flip) == 0);
2821 }
2822
2823 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2824 {
2825 struct drm_device *dev = crtc->dev;
2826 struct drm_mode_config *mode_config = &dev->mode_config;
2827 struct intel_encoder *encoder;
2828
2829 /*
2830 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2831 * must be driven by its own crtc; no sharing is possible.
2832 */
2833 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2834 if (encoder->base.crtc != crtc)
2835 continue;
2836
2837 switch (encoder->type) {
2838 case INTEL_OUTPUT_EDP:
2839 if (!intel_encoder_is_pch_edp(&encoder->base))
2840 return false;
2841 continue;
2842 }
2843 }
2844
2845 return true;
2846 }
2847
2848 /*
2849 * Enable PCH resources required for PCH ports:
2850 * - PCH PLLs
2851 * - FDI training & RX/TX
2852 * - update transcoder timings
2853 * - DP transcoding bits
2854 * - transcoder
2855 */
2856 static void ironlake_pch_enable(struct drm_crtc *crtc)
2857 {
2858 struct drm_device *dev = crtc->dev;
2859 struct drm_i915_private *dev_priv = dev->dev_private;
2860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2861 int pipe = intel_crtc->pipe;
2862 u32 reg, temp;
2863
2864 /* For PCH output, training FDI link */
2865 dev_priv->display.fdi_link_train(crtc);
2866
2867 intel_enable_pch_pll(dev_priv, pipe);
2868
2869 if (HAS_PCH_CPT(dev)) {
2870 /* Be sure PCH DPLL SEL is set */
2871 temp = I915_READ(PCH_DPLL_SEL);
2872 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2873 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2874 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2875 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2876 I915_WRITE(PCH_DPLL_SEL, temp);
2877 }
2878
2879 /* set transcoder timing, panel must allow it */
2880 assert_panel_unlocked(dev_priv, pipe);
2881 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2882 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2883 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2884
2885 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2886 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2887 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2888
2889 intel_fdi_normal_train(crtc);
2890
2891 /* For PCH DP, enable TRANS_DP_CTL */
2892 if (HAS_PCH_CPT(dev) &&
2893 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2894 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2895 reg = TRANS_DP_CTL(pipe);
2896 temp = I915_READ(reg);
2897 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2898 TRANS_DP_SYNC_MASK |
2899 TRANS_DP_BPC_MASK);
2900 temp |= (TRANS_DP_OUTPUT_ENABLE |
2901 TRANS_DP_ENH_FRAMING);
2902 temp |= bpc << 9; /* same format but at 11:9 */
2903
2904 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2905 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2906 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2907 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2908
2909 switch (intel_trans_dp_port_sel(crtc)) {
2910 case PCH_DP_B:
2911 temp |= TRANS_DP_PORT_SEL_B;
2912 break;
2913 case PCH_DP_C:
2914 temp |= TRANS_DP_PORT_SEL_C;
2915 break;
2916 case PCH_DP_D:
2917 temp |= TRANS_DP_PORT_SEL_D;
2918 break;
2919 default:
2920 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2921 temp |= TRANS_DP_PORT_SEL_B;
2922 break;
2923 }
2924
2925 I915_WRITE(reg, temp);
2926 }
2927
2928 intel_enable_transcoder(dev_priv, pipe);
2929 }
2930
2931 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2932 {
2933 struct drm_device *dev = crtc->dev;
2934 struct drm_i915_private *dev_priv = dev->dev_private;
2935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2936 int pipe = intel_crtc->pipe;
2937 int plane = intel_crtc->plane;
2938 u32 temp;
2939 bool is_pch_port;
2940
2941 if (intel_crtc->active)
2942 return;
2943
2944 intel_crtc->active = true;
2945 intel_update_watermarks(dev);
2946
2947 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2948 temp = I915_READ(PCH_LVDS);
2949 if ((temp & LVDS_PORT_EN) == 0)
2950 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2951 }
2952
2953 is_pch_port = intel_crtc_driving_pch(crtc);
2954
2955 if (is_pch_port)
2956 ironlake_fdi_pll_enable(crtc);
2957 else
2958 ironlake_fdi_disable(crtc);
2959
2960 /* Enable panel fitting for LVDS */
2961 if (dev_priv->pch_pf_size &&
2962 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2963 /* Force use of hard-coded filter coefficients
2964 * as some pre-programmed values are broken,
2965 * e.g. x201.
2966 */
2967 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2968 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2969 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2970 }
2971
2972 /*
2973 * On ILK+ LUT must be loaded before the pipe is running but with
2974 * clocks enabled
2975 */
2976 intel_crtc_load_lut(crtc);
2977
2978 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2979 intel_enable_plane(dev_priv, plane, pipe);
2980
2981 if (is_pch_port)
2982 ironlake_pch_enable(crtc);
2983
2984 mutex_lock(&dev->struct_mutex);
2985 intel_update_fbc(dev);
2986 mutex_unlock(&dev->struct_mutex);
2987
2988 intel_crtc_update_cursor(crtc, true);
2989 }
2990
2991 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2992 {
2993 struct drm_device *dev = crtc->dev;
2994 struct drm_i915_private *dev_priv = dev->dev_private;
2995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2996 int pipe = intel_crtc->pipe;
2997 int plane = intel_crtc->plane;
2998 u32 reg, temp;
2999
3000 if (!intel_crtc->active)
3001 return;
3002
3003 intel_crtc_wait_for_pending_flips(crtc);
3004 drm_vblank_off(dev, pipe);
3005 intel_crtc_update_cursor(crtc, false);
3006
3007 intel_disable_plane(dev_priv, plane, pipe);
3008
3009 if (dev_priv->cfb_plane == plane)
3010 intel_disable_fbc(dev);
3011
3012 intel_disable_pipe(dev_priv, pipe);
3013
3014 /* Disable PF */
3015 I915_WRITE(PF_CTL(pipe), 0);
3016 I915_WRITE(PF_WIN_SZ(pipe), 0);
3017
3018 ironlake_fdi_disable(crtc);
3019
3020 /* This is a horrible layering violation; we should be doing this in
3021 * the connector/encoder ->prepare instead, but we don't always have
3022 * enough information there about the config to know whether it will
3023 * actually be necessary or just cause undesired flicker.
3024 */
3025 intel_disable_pch_ports(dev_priv, pipe);
3026
3027 intel_disable_transcoder(dev_priv, pipe);
3028
3029 if (HAS_PCH_CPT(dev)) {
3030 /* disable TRANS_DP_CTL */
3031 reg = TRANS_DP_CTL(pipe);
3032 temp = I915_READ(reg);
3033 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3034 temp |= TRANS_DP_PORT_SEL_NONE;
3035 I915_WRITE(reg, temp);
3036
3037 /* disable DPLL_SEL */
3038 temp = I915_READ(PCH_DPLL_SEL);
3039 switch (pipe) {
3040 case 0:
3041 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3042 break;
3043 case 1:
3044 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3045 break;
3046 case 2:
3047 /* FIXME: manage transcoder PLLs? */
3048 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3049 break;
3050 default:
3051 BUG(); /* wtf */
3052 }
3053 I915_WRITE(PCH_DPLL_SEL, temp);
3054 }
3055
3056 /* disable PCH DPLL */
3057 intel_disable_pch_pll(dev_priv, pipe);
3058
3059 /* Switch from PCDclk to Rawclk */
3060 reg = FDI_RX_CTL(pipe);
3061 temp = I915_READ(reg);
3062 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3063
3064 /* Disable CPU FDI TX PLL */
3065 reg = FDI_TX_CTL(pipe);
3066 temp = I915_READ(reg);
3067 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3068
3069 POSTING_READ(reg);
3070 udelay(100);
3071
3072 reg = FDI_RX_CTL(pipe);
3073 temp = I915_READ(reg);
3074 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3075
3076 /* Wait for the clocks to turn off. */
3077 POSTING_READ(reg);
3078 udelay(100);
3079
3080 intel_crtc->active = false;
3081 intel_update_watermarks(dev);
3082
3083 mutex_lock(&dev->struct_mutex);
3084 intel_update_fbc(dev);
3085 intel_clear_scanline_wait(dev);
3086 mutex_unlock(&dev->struct_mutex);
3087 }
3088
3089 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3090 {
3091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3092 int pipe = intel_crtc->pipe;
3093 int plane = intel_crtc->plane;
3094
3095 /* XXX: When our outputs are all unaware of DPMS modes other than off
3096 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3097 */
3098 switch (mode) {
3099 case DRM_MODE_DPMS_ON:
3100 case DRM_MODE_DPMS_STANDBY:
3101 case DRM_MODE_DPMS_SUSPEND:
3102 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3103 ironlake_crtc_enable(crtc);
3104 break;
3105
3106 case DRM_MODE_DPMS_OFF:
3107 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3108 ironlake_crtc_disable(crtc);
3109 break;
3110 }
3111 }
3112
3113 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3114 {
3115 if (!enable && intel_crtc->overlay) {
3116 struct drm_device *dev = intel_crtc->base.dev;
3117 struct drm_i915_private *dev_priv = dev->dev_private;
3118
3119 mutex_lock(&dev->struct_mutex);
3120 dev_priv->mm.interruptible = false;
3121 (void) intel_overlay_switch_off(intel_crtc->overlay);
3122 dev_priv->mm.interruptible = true;
3123 mutex_unlock(&dev->struct_mutex);
3124 }
3125
3126 /* Let userspace switch the overlay on again. In most cases userspace
3127 * has to recompute where to put it anyway.
3128 */
3129 }
3130
3131 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3132 {
3133 struct drm_device *dev = crtc->dev;
3134 struct drm_i915_private *dev_priv = dev->dev_private;
3135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3136 int pipe = intel_crtc->pipe;
3137 int plane = intel_crtc->plane;
3138
3139 if (intel_crtc->active)
3140 return;
3141
3142 intel_crtc->active = true;
3143 intel_update_watermarks(dev);
3144
3145 intel_enable_pll(dev_priv, pipe);
3146 intel_enable_pipe(dev_priv, pipe, false);
3147 intel_enable_plane(dev_priv, plane, pipe);
3148
3149 intel_crtc_load_lut(crtc);
3150 intel_update_fbc(dev);
3151
3152 /* Give the overlay scaler a chance to enable if it's on this pipe */
3153 intel_crtc_dpms_overlay(intel_crtc, true);
3154 intel_crtc_update_cursor(crtc, true);
3155 }
3156
3157 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3158 {
3159 struct drm_device *dev = crtc->dev;
3160 struct drm_i915_private *dev_priv = dev->dev_private;
3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162 int pipe = intel_crtc->pipe;
3163 int plane = intel_crtc->plane;
3164
3165 if (!intel_crtc->active)
3166 return;
3167
3168 /* Give the overlay scaler a chance to disable if it's on this pipe */
3169 intel_crtc_wait_for_pending_flips(crtc);
3170 drm_vblank_off(dev, pipe);
3171 intel_crtc_dpms_overlay(intel_crtc, false);
3172 intel_crtc_update_cursor(crtc, false);
3173
3174 if (dev_priv->cfb_plane == plane)
3175 intel_disable_fbc(dev);
3176
3177 intel_disable_plane(dev_priv, plane, pipe);
3178 intel_disable_pipe(dev_priv, pipe);
3179 intel_disable_pll(dev_priv, pipe);
3180
3181 intel_crtc->active = false;
3182 intel_update_fbc(dev);
3183 intel_update_watermarks(dev);
3184 intel_clear_scanline_wait(dev);
3185 }
3186
3187 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3188 {
3189 /* XXX: When our outputs are all unaware of DPMS modes other than off
3190 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3191 */
3192 switch (mode) {
3193 case DRM_MODE_DPMS_ON:
3194 case DRM_MODE_DPMS_STANDBY:
3195 case DRM_MODE_DPMS_SUSPEND:
3196 i9xx_crtc_enable(crtc);
3197 break;
3198 case DRM_MODE_DPMS_OFF:
3199 i9xx_crtc_disable(crtc);
3200 break;
3201 }
3202 }
3203
3204 /**
3205 * Sets the power management mode of the pipe and plane.
3206 */
3207 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3208 {
3209 struct drm_device *dev = crtc->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct drm_i915_master_private *master_priv;
3212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3213 int pipe = intel_crtc->pipe;
3214 bool enabled;
3215
3216 if (intel_crtc->dpms_mode == mode)
3217 return;
3218
3219 intel_crtc->dpms_mode = mode;
3220
3221 dev_priv->display.dpms(crtc, mode);
3222
3223 if (!dev->primary->master)
3224 return;
3225
3226 master_priv = dev->primary->master->driver_priv;
3227 if (!master_priv->sarea_priv)
3228 return;
3229
3230 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3231
3232 switch (pipe) {
3233 case 0:
3234 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3235 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3236 break;
3237 case 1:
3238 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3239 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3240 break;
3241 default:
3242 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3243 break;
3244 }
3245 }
3246
3247 static void intel_crtc_disable(struct drm_crtc *crtc)
3248 {
3249 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3250 struct drm_device *dev = crtc->dev;
3251
3252 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3253
3254 if (crtc->fb) {
3255 mutex_lock(&dev->struct_mutex);
3256 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3257 mutex_unlock(&dev->struct_mutex);
3258 }
3259 }
3260
3261 /* Prepare for a mode set.
3262 *
3263 * Note we could be a lot smarter here. We need to figure out which outputs
3264 * will be enabled, which disabled (in short, how the config will changes)
3265 * and perform the minimum necessary steps to accomplish that, e.g. updating
3266 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3267 * panel fitting is in the proper state, etc.
3268 */
3269 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3270 {
3271 i9xx_crtc_disable(crtc);
3272 }
3273
3274 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3275 {
3276 i9xx_crtc_enable(crtc);
3277 }
3278
3279 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3280 {
3281 ironlake_crtc_disable(crtc);
3282 }
3283
3284 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3285 {
3286 ironlake_crtc_enable(crtc);
3287 }
3288
3289 void intel_encoder_prepare(struct drm_encoder *encoder)
3290 {
3291 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3292 /* lvds has its own version of prepare see intel_lvds_prepare */
3293 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3294 }
3295
3296 void intel_encoder_commit(struct drm_encoder *encoder)
3297 {
3298 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3299 /* lvds has its own version of commit see intel_lvds_commit */
3300 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3301 }
3302
3303 void intel_encoder_destroy(struct drm_encoder *encoder)
3304 {
3305 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3306
3307 drm_encoder_cleanup(encoder);
3308 kfree(intel_encoder);
3309 }
3310
3311 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3312 struct drm_display_mode *mode,
3313 struct drm_display_mode *adjusted_mode)
3314 {
3315 struct drm_device *dev = crtc->dev;
3316
3317 if (HAS_PCH_SPLIT(dev)) {
3318 /* FDI link clock is fixed at 2.7G */
3319 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3320 return false;
3321 }
3322
3323 /* XXX some encoders set the crtcinfo, others don't.
3324 * Obviously we need some form of conflict resolution here...
3325 */
3326 if (adjusted_mode->crtc_htotal == 0)
3327 drm_mode_set_crtcinfo(adjusted_mode, 0);
3328
3329 return true;
3330 }
3331
3332 static int i945_get_display_clock_speed(struct drm_device *dev)
3333 {
3334 return 400000;
3335 }
3336
3337 static int i915_get_display_clock_speed(struct drm_device *dev)
3338 {
3339 return 333000;
3340 }
3341
3342 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3343 {
3344 return 200000;
3345 }
3346
3347 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3348 {
3349 u16 gcfgc = 0;
3350
3351 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3352
3353 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3354 return 133000;
3355 else {
3356 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3357 case GC_DISPLAY_CLOCK_333_MHZ:
3358 return 333000;
3359 default:
3360 case GC_DISPLAY_CLOCK_190_200_MHZ:
3361 return 190000;
3362 }
3363 }
3364 }
3365
3366 static int i865_get_display_clock_speed(struct drm_device *dev)
3367 {
3368 return 266000;
3369 }
3370
3371 static int i855_get_display_clock_speed(struct drm_device *dev)
3372 {
3373 u16 hpllcc = 0;
3374 /* Assume that the hardware is in the high speed state. This
3375 * should be the default.
3376 */
3377 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3378 case GC_CLOCK_133_200:
3379 case GC_CLOCK_100_200:
3380 return 200000;
3381 case GC_CLOCK_166_250:
3382 return 250000;
3383 case GC_CLOCK_100_133:
3384 return 133000;
3385 }
3386
3387 /* Shouldn't happen */
3388 return 0;
3389 }
3390
3391 static int i830_get_display_clock_speed(struct drm_device *dev)
3392 {
3393 return 133000;
3394 }
3395
3396 struct fdi_m_n {
3397 u32 tu;
3398 u32 gmch_m;
3399 u32 gmch_n;
3400 u32 link_m;
3401 u32 link_n;
3402 };
3403
3404 static void
3405 fdi_reduce_ratio(u32 *num, u32 *den)
3406 {
3407 while (*num > 0xffffff || *den > 0xffffff) {
3408 *num >>= 1;
3409 *den >>= 1;
3410 }
3411 }
3412
3413 static void
3414 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3415 int link_clock, struct fdi_m_n *m_n)
3416 {
3417 m_n->tu = 64; /* default size */
3418
3419 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3420 m_n->gmch_m = bits_per_pixel * pixel_clock;
3421 m_n->gmch_n = link_clock * nlanes * 8;
3422 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3423
3424 m_n->link_m = pixel_clock;
3425 m_n->link_n = link_clock;
3426 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3427 }
3428
3429
3430 struct intel_watermark_params {
3431 unsigned long fifo_size;
3432 unsigned long max_wm;
3433 unsigned long default_wm;
3434 unsigned long guard_size;
3435 unsigned long cacheline_size;
3436 };
3437
3438 /* Pineview has different values for various configs */
3439 static const struct intel_watermark_params pineview_display_wm = {
3440 PINEVIEW_DISPLAY_FIFO,
3441 PINEVIEW_MAX_WM,
3442 PINEVIEW_DFT_WM,
3443 PINEVIEW_GUARD_WM,
3444 PINEVIEW_FIFO_LINE_SIZE
3445 };
3446 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3447 PINEVIEW_DISPLAY_FIFO,
3448 PINEVIEW_MAX_WM,
3449 PINEVIEW_DFT_HPLLOFF_WM,
3450 PINEVIEW_GUARD_WM,
3451 PINEVIEW_FIFO_LINE_SIZE
3452 };
3453 static const struct intel_watermark_params pineview_cursor_wm = {
3454 PINEVIEW_CURSOR_FIFO,
3455 PINEVIEW_CURSOR_MAX_WM,
3456 PINEVIEW_CURSOR_DFT_WM,
3457 PINEVIEW_CURSOR_GUARD_WM,
3458 PINEVIEW_FIFO_LINE_SIZE,
3459 };
3460 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3461 PINEVIEW_CURSOR_FIFO,
3462 PINEVIEW_CURSOR_MAX_WM,
3463 PINEVIEW_CURSOR_DFT_WM,
3464 PINEVIEW_CURSOR_GUARD_WM,
3465 PINEVIEW_FIFO_LINE_SIZE
3466 };
3467 static const struct intel_watermark_params g4x_wm_info = {
3468 G4X_FIFO_SIZE,
3469 G4X_MAX_WM,
3470 G4X_MAX_WM,
3471 2,
3472 G4X_FIFO_LINE_SIZE,
3473 };
3474 static const struct intel_watermark_params g4x_cursor_wm_info = {
3475 I965_CURSOR_FIFO,
3476 I965_CURSOR_MAX_WM,
3477 I965_CURSOR_DFT_WM,
3478 2,
3479 G4X_FIFO_LINE_SIZE,
3480 };
3481 static const struct intel_watermark_params i965_cursor_wm_info = {
3482 I965_CURSOR_FIFO,
3483 I965_CURSOR_MAX_WM,
3484 I965_CURSOR_DFT_WM,
3485 2,
3486 I915_FIFO_LINE_SIZE,
3487 };
3488 static const struct intel_watermark_params i945_wm_info = {
3489 I945_FIFO_SIZE,
3490 I915_MAX_WM,
3491 1,
3492 2,
3493 I915_FIFO_LINE_SIZE
3494 };
3495 static const struct intel_watermark_params i915_wm_info = {
3496 I915_FIFO_SIZE,
3497 I915_MAX_WM,
3498 1,
3499 2,
3500 I915_FIFO_LINE_SIZE
3501 };
3502 static const struct intel_watermark_params i855_wm_info = {
3503 I855GM_FIFO_SIZE,
3504 I915_MAX_WM,
3505 1,
3506 2,
3507 I830_FIFO_LINE_SIZE
3508 };
3509 static const struct intel_watermark_params i830_wm_info = {
3510 I830_FIFO_SIZE,
3511 I915_MAX_WM,
3512 1,
3513 2,
3514 I830_FIFO_LINE_SIZE
3515 };
3516
3517 static const struct intel_watermark_params ironlake_display_wm_info = {
3518 ILK_DISPLAY_FIFO,
3519 ILK_DISPLAY_MAXWM,
3520 ILK_DISPLAY_DFTWM,
3521 2,
3522 ILK_FIFO_LINE_SIZE
3523 };
3524 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3525 ILK_CURSOR_FIFO,
3526 ILK_CURSOR_MAXWM,
3527 ILK_CURSOR_DFTWM,
3528 2,
3529 ILK_FIFO_LINE_SIZE
3530 };
3531 static const struct intel_watermark_params ironlake_display_srwm_info = {
3532 ILK_DISPLAY_SR_FIFO,
3533 ILK_DISPLAY_MAX_SRWM,
3534 ILK_DISPLAY_DFT_SRWM,
3535 2,
3536 ILK_FIFO_LINE_SIZE
3537 };
3538 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3539 ILK_CURSOR_SR_FIFO,
3540 ILK_CURSOR_MAX_SRWM,
3541 ILK_CURSOR_DFT_SRWM,
3542 2,
3543 ILK_FIFO_LINE_SIZE
3544 };
3545
3546 static const struct intel_watermark_params sandybridge_display_wm_info = {
3547 SNB_DISPLAY_FIFO,
3548 SNB_DISPLAY_MAXWM,
3549 SNB_DISPLAY_DFTWM,
3550 2,
3551 SNB_FIFO_LINE_SIZE
3552 };
3553 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3554 SNB_CURSOR_FIFO,
3555 SNB_CURSOR_MAXWM,
3556 SNB_CURSOR_DFTWM,
3557 2,
3558 SNB_FIFO_LINE_SIZE
3559 };
3560 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3561 SNB_DISPLAY_SR_FIFO,
3562 SNB_DISPLAY_MAX_SRWM,
3563 SNB_DISPLAY_DFT_SRWM,
3564 2,
3565 SNB_FIFO_LINE_SIZE
3566 };
3567 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3568 SNB_CURSOR_SR_FIFO,
3569 SNB_CURSOR_MAX_SRWM,
3570 SNB_CURSOR_DFT_SRWM,
3571 2,
3572 SNB_FIFO_LINE_SIZE
3573 };
3574
3575
3576 /**
3577 * intel_calculate_wm - calculate watermark level
3578 * @clock_in_khz: pixel clock
3579 * @wm: chip FIFO params
3580 * @pixel_size: display pixel size
3581 * @latency_ns: memory latency for the platform
3582 *
3583 * Calculate the watermark level (the level at which the display plane will
3584 * start fetching from memory again). Each chip has a different display
3585 * FIFO size and allocation, so the caller needs to figure that out and pass
3586 * in the correct intel_watermark_params structure.
3587 *
3588 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3589 * on the pixel size. When it reaches the watermark level, it'll start
3590 * fetching FIFO line sized based chunks from memory until the FIFO fills
3591 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3592 * will occur, and a display engine hang could result.
3593 */
3594 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3595 const struct intel_watermark_params *wm,
3596 int fifo_size,
3597 int pixel_size,
3598 unsigned long latency_ns)
3599 {
3600 long entries_required, wm_size;
3601
3602 /*
3603 * Note: we need to make sure we don't overflow for various clock &
3604 * latency values.
3605 * clocks go from a few thousand to several hundred thousand.
3606 * latency is usually a few thousand
3607 */
3608 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3609 1000;
3610 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3611
3612 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3613
3614 wm_size = fifo_size - (entries_required + wm->guard_size);
3615
3616 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3617
3618 /* Don't promote wm_size to unsigned... */
3619 if (wm_size > (long)wm->max_wm)
3620 wm_size = wm->max_wm;
3621 if (wm_size <= 0)
3622 wm_size = wm->default_wm;
3623 return wm_size;
3624 }
3625
3626 struct cxsr_latency {
3627 int is_desktop;
3628 int is_ddr3;
3629 unsigned long fsb_freq;
3630 unsigned long mem_freq;
3631 unsigned long display_sr;
3632 unsigned long display_hpll_disable;
3633 unsigned long cursor_sr;
3634 unsigned long cursor_hpll_disable;
3635 };
3636
3637 static const struct cxsr_latency cxsr_latency_table[] = {
3638 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3639 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3640 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3641 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3642 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3643
3644 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3645 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3646 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3647 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3648 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3649
3650 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3651 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3652 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3653 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3654 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3655
3656 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3657 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3658 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3659 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3660 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3661
3662 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3663 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3664 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3665 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3666 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3667
3668 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3669 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3670 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3671 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3672 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3673 };
3674
3675 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3676 int is_ddr3,
3677 int fsb,
3678 int mem)
3679 {
3680 const struct cxsr_latency *latency;
3681 int i;
3682
3683 if (fsb == 0 || mem == 0)
3684 return NULL;
3685
3686 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3687 latency = &cxsr_latency_table[i];
3688 if (is_desktop == latency->is_desktop &&
3689 is_ddr3 == latency->is_ddr3 &&
3690 fsb == latency->fsb_freq && mem == latency->mem_freq)
3691 return latency;
3692 }
3693
3694 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3695
3696 return NULL;
3697 }
3698
3699 static void pineview_disable_cxsr(struct drm_device *dev)
3700 {
3701 struct drm_i915_private *dev_priv = dev->dev_private;
3702
3703 /* deactivate cxsr */
3704 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3705 }
3706
3707 /*
3708 * Latency for FIFO fetches is dependent on several factors:
3709 * - memory configuration (speed, channels)
3710 * - chipset
3711 * - current MCH state
3712 * It can be fairly high in some situations, so here we assume a fairly
3713 * pessimal value. It's a tradeoff between extra memory fetches (if we
3714 * set this value too high, the FIFO will fetch frequently to stay full)
3715 * and power consumption (set it too low to save power and we might see
3716 * FIFO underruns and display "flicker").
3717 *
3718 * A value of 5us seems to be a good balance; safe for very low end
3719 * platforms but not overly aggressive on lower latency configs.
3720 */
3721 static const int latency_ns = 5000;
3722
3723 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3724 {
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726 uint32_t dsparb = I915_READ(DSPARB);
3727 int size;
3728
3729 size = dsparb & 0x7f;
3730 if (plane)
3731 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3732
3733 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3734 plane ? "B" : "A", size);
3735
3736 return size;
3737 }
3738
3739 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3740 {
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 uint32_t dsparb = I915_READ(DSPARB);
3743 int size;
3744
3745 size = dsparb & 0x1ff;
3746 if (plane)
3747 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3748 size >>= 1; /* Convert to cachelines */
3749
3750 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3751 plane ? "B" : "A", size);
3752
3753 return size;
3754 }
3755
3756 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3757 {
3758 struct drm_i915_private *dev_priv = dev->dev_private;
3759 uint32_t dsparb = I915_READ(DSPARB);
3760 int size;
3761
3762 size = dsparb & 0x7f;
3763 size >>= 2; /* Convert to cachelines */
3764
3765 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3766 plane ? "B" : "A",
3767 size);
3768
3769 return size;
3770 }
3771
3772 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3773 {
3774 struct drm_i915_private *dev_priv = dev->dev_private;
3775 uint32_t dsparb = I915_READ(DSPARB);
3776 int size;
3777
3778 size = dsparb & 0x7f;
3779 size >>= 1; /* Convert to cachelines */
3780
3781 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3782 plane ? "B" : "A", size);
3783
3784 return size;
3785 }
3786
3787 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3788 {
3789 struct drm_crtc *crtc, *enabled = NULL;
3790
3791 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3792 if (crtc->enabled && crtc->fb) {
3793 if (enabled)
3794 return NULL;
3795 enabled = crtc;
3796 }
3797 }
3798
3799 return enabled;
3800 }
3801
3802 static void pineview_update_wm(struct drm_device *dev)
3803 {
3804 struct drm_i915_private *dev_priv = dev->dev_private;
3805 struct drm_crtc *crtc;
3806 const struct cxsr_latency *latency;
3807 u32 reg;
3808 unsigned long wm;
3809
3810 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3811 dev_priv->fsb_freq, dev_priv->mem_freq);
3812 if (!latency) {
3813 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3814 pineview_disable_cxsr(dev);
3815 return;
3816 }
3817
3818 crtc = single_enabled_crtc(dev);
3819 if (crtc) {
3820 int clock = crtc->mode.clock;
3821 int pixel_size = crtc->fb->bits_per_pixel / 8;
3822
3823 /* Display SR */
3824 wm = intel_calculate_wm(clock, &pineview_display_wm,
3825 pineview_display_wm.fifo_size,
3826 pixel_size, latency->display_sr);
3827 reg = I915_READ(DSPFW1);
3828 reg &= ~DSPFW_SR_MASK;
3829 reg |= wm << DSPFW_SR_SHIFT;
3830 I915_WRITE(DSPFW1, reg);
3831 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3832
3833 /* cursor SR */
3834 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3835 pineview_display_wm.fifo_size,
3836 pixel_size, latency->cursor_sr);
3837 reg = I915_READ(DSPFW3);
3838 reg &= ~DSPFW_CURSOR_SR_MASK;
3839 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3840 I915_WRITE(DSPFW3, reg);
3841
3842 /* Display HPLL off SR */
3843 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3844 pineview_display_hplloff_wm.fifo_size,
3845 pixel_size, latency->display_hpll_disable);
3846 reg = I915_READ(DSPFW3);
3847 reg &= ~DSPFW_HPLL_SR_MASK;
3848 reg |= wm & DSPFW_HPLL_SR_MASK;
3849 I915_WRITE(DSPFW3, reg);
3850
3851 /* cursor HPLL off SR */
3852 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3853 pineview_display_hplloff_wm.fifo_size,
3854 pixel_size, latency->cursor_hpll_disable);
3855 reg = I915_READ(DSPFW3);
3856 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3857 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3858 I915_WRITE(DSPFW3, reg);
3859 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3860
3861 /* activate cxsr */
3862 I915_WRITE(DSPFW3,
3863 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3864 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3865 } else {
3866 pineview_disable_cxsr(dev);
3867 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3868 }
3869 }
3870
3871 static bool g4x_compute_wm0(struct drm_device *dev,
3872 int plane,
3873 const struct intel_watermark_params *display,
3874 int display_latency_ns,
3875 const struct intel_watermark_params *cursor,
3876 int cursor_latency_ns,
3877 int *plane_wm,
3878 int *cursor_wm)
3879 {
3880 struct drm_crtc *crtc;
3881 int htotal, hdisplay, clock, pixel_size;
3882 int line_time_us, line_count;
3883 int entries, tlb_miss;
3884
3885 crtc = intel_get_crtc_for_plane(dev, plane);
3886 if (crtc->fb == NULL || !crtc->enabled) {
3887 *cursor_wm = cursor->guard_size;
3888 *plane_wm = display->guard_size;
3889 return false;
3890 }
3891
3892 htotal = crtc->mode.htotal;
3893 hdisplay = crtc->mode.hdisplay;
3894 clock = crtc->mode.clock;
3895 pixel_size = crtc->fb->bits_per_pixel / 8;
3896
3897 /* Use the small buffer method to calculate plane watermark */
3898 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3899 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3900 if (tlb_miss > 0)
3901 entries += tlb_miss;
3902 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3903 *plane_wm = entries + display->guard_size;
3904 if (*plane_wm > (int)display->max_wm)
3905 *plane_wm = display->max_wm;
3906
3907 /* Use the large buffer method to calculate cursor watermark */
3908 line_time_us = ((htotal * 1000) / clock);
3909 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3910 entries = line_count * 64 * pixel_size;
3911 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3912 if (tlb_miss > 0)
3913 entries += tlb_miss;
3914 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3915 *cursor_wm = entries + cursor->guard_size;
3916 if (*cursor_wm > (int)cursor->max_wm)
3917 *cursor_wm = (int)cursor->max_wm;
3918
3919 return true;
3920 }
3921
3922 /*
3923 * Check the wm result.
3924 *
3925 * If any calculated watermark values is larger than the maximum value that
3926 * can be programmed into the associated watermark register, that watermark
3927 * must be disabled.
3928 */
3929 static bool g4x_check_srwm(struct drm_device *dev,
3930 int display_wm, int cursor_wm,
3931 const struct intel_watermark_params *display,
3932 const struct intel_watermark_params *cursor)
3933 {
3934 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3935 display_wm, cursor_wm);
3936
3937 if (display_wm > display->max_wm) {
3938 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3939 display_wm, display->max_wm);
3940 return false;
3941 }
3942
3943 if (cursor_wm > cursor->max_wm) {
3944 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3945 cursor_wm, cursor->max_wm);
3946 return false;
3947 }
3948
3949 if (!(display_wm || cursor_wm)) {
3950 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3951 return false;
3952 }
3953
3954 return true;
3955 }
3956
3957 static bool g4x_compute_srwm(struct drm_device *dev,
3958 int plane,
3959 int latency_ns,
3960 const struct intel_watermark_params *display,
3961 const struct intel_watermark_params *cursor,
3962 int *display_wm, int *cursor_wm)
3963 {
3964 struct drm_crtc *crtc;
3965 int hdisplay, htotal, pixel_size, clock;
3966 unsigned long line_time_us;
3967 int line_count, line_size;
3968 int small, large;
3969 int entries;
3970
3971 if (!latency_ns) {
3972 *display_wm = *cursor_wm = 0;
3973 return false;
3974 }
3975
3976 crtc = intel_get_crtc_for_plane(dev, plane);
3977 hdisplay = crtc->mode.hdisplay;
3978 htotal = crtc->mode.htotal;
3979 clock = crtc->mode.clock;
3980 pixel_size = crtc->fb->bits_per_pixel / 8;
3981
3982 line_time_us = (htotal * 1000) / clock;
3983 line_count = (latency_ns / line_time_us + 1000) / 1000;
3984 line_size = hdisplay * pixel_size;
3985
3986 /* Use the minimum of the small and large buffer method for primary */
3987 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3988 large = line_count * line_size;
3989
3990 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3991 *display_wm = entries + display->guard_size;
3992
3993 /* calculate the self-refresh watermark for display cursor */
3994 entries = line_count * pixel_size * 64;
3995 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3996 *cursor_wm = entries + cursor->guard_size;
3997
3998 return g4x_check_srwm(dev,
3999 *display_wm, *cursor_wm,
4000 display, cursor);
4001 }
4002
4003 #define single_plane_enabled(mask) is_power_of_2(mask)
4004
4005 static void g4x_update_wm(struct drm_device *dev)
4006 {
4007 static const int sr_latency_ns = 12000;
4008 struct drm_i915_private *dev_priv = dev->dev_private;
4009 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4010 int plane_sr, cursor_sr;
4011 unsigned int enabled = 0;
4012
4013 if (g4x_compute_wm0(dev, 0,
4014 &g4x_wm_info, latency_ns,
4015 &g4x_cursor_wm_info, latency_ns,
4016 &planea_wm, &cursora_wm))
4017 enabled |= 1;
4018
4019 if (g4x_compute_wm0(dev, 1,
4020 &g4x_wm_info, latency_ns,
4021 &g4x_cursor_wm_info, latency_ns,
4022 &planeb_wm, &cursorb_wm))
4023 enabled |= 2;
4024
4025 plane_sr = cursor_sr = 0;
4026 if (single_plane_enabled(enabled) &&
4027 g4x_compute_srwm(dev, ffs(enabled) - 1,
4028 sr_latency_ns,
4029 &g4x_wm_info,
4030 &g4x_cursor_wm_info,
4031 &plane_sr, &cursor_sr))
4032 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4033 else
4034 I915_WRITE(FW_BLC_SELF,
4035 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4036
4037 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4038 planea_wm, cursora_wm,
4039 planeb_wm, cursorb_wm,
4040 plane_sr, cursor_sr);
4041
4042 I915_WRITE(DSPFW1,
4043 (plane_sr << DSPFW_SR_SHIFT) |
4044 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4045 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4046 planea_wm);
4047 I915_WRITE(DSPFW2,
4048 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4049 (cursora_wm << DSPFW_CURSORA_SHIFT));
4050 /* HPLL off in SR has some issues on G4x... disable it */
4051 I915_WRITE(DSPFW3,
4052 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4053 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4054 }
4055
4056 static void i965_update_wm(struct drm_device *dev)
4057 {
4058 struct drm_i915_private *dev_priv = dev->dev_private;
4059 struct drm_crtc *crtc;
4060 int srwm = 1;
4061 int cursor_sr = 16;
4062
4063 /* Calc sr entries for one plane configs */
4064 crtc = single_enabled_crtc(dev);
4065 if (crtc) {
4066 /* self-refresh has much higher latency */
4067 static const int sr_latency_ns = 12000;
4068 int clock = crtc->mode.clock;
4069 int htotal = crtc->mode.htotal;
4070 int hdisplay = crtc->mode.hdisplay;
4071 int pixel_size = crtc->fb->bits_per_pixel / 8;
4072 unsigned long line_time_us;
4073 int entries;
4074
4075 line_time_us = ((htotal * 1000) / clock);
4076
4077 /* Use ns/us then divide to preserve precision */
4078 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4079 pixel_size * hdisplay;
4080 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4081 srwm = I965_FIFO_SIZE - entries;
4082 if (srwm < 0)
4083 srwm = 1;
4084 srwm &= 0x1ff;
4085 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4086 entries, srwm);
4087
4088 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4089 pixel_size * 64;
4090 entries = DIV_ROUND_UP(entries,
4091 i965_cursor_wm_info.cacheline_size);
4092 cursor_sr = i965_cursor_wm_info.fifo_size -
4093 (entries + i965_cursor_wm_info.guard_size);
4094
4095 if (cursor_sr > i965_cursor_wm_info.max_wm)
4096 cursor_sr = i965_cursor_wm_info.max_wm;
4097
4098 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4099 "cursor %d\n", srwm, cursor_sr);
4100
4101 if (IS_CRESTLINE(dev))
4102 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4103 } else {
4104 /* Turn off self refresh if both pipes are enabled */
4105 if (IS_CRESTLINE(dev))
4106 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4107 & ~FW_BLC_SELF_EN);
4108 }
4109
4110 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4111 srwm);
4112
4113 /* 965 has limitations... */
4114 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4115 (8 << 16) | (8 << 8) | (8 << 0));
4116 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4117 /* update cursor SR watermark */
4118 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4119 }
4120
4121 static void i9xx_update_wm(struct drm_device *dev)
4122 {
4123 struct drm_i915_private *dev_priv = dev->dev_private;
4124 const struct intel_watermark_params *wm_info;
4125 uint32_t fwater_lo;
4126 uint32_t fwater_hi;
4127 int cwm, srwm = 1;
4128 int fifo_size;
4129 int planea_wm, planeb_wm;
4130 struct drm_crtc *crtc, *enabled = NULL;
4131
4132 if (IS_I945GM(dev))
4133 wm_info = &i945_wm_info;
4134 else if (!IS_GEN2(dev))
4135 wm_info = &i915_wm_info;
4136 else
4137 wm_info = &i855_wm_info;
4138
4139 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4140 crtc = intel_get_crtc_for_plane(dev, 0);
4141 if (crtc->enabled && crtc->fb) {
4142 planea_wm = intel_calculate_wm(crtc->mode.clock,
4143 wm_info, fifo_size,
4144 crtc->fb->bits_per_pixel / 8,
4145 latency_ns);
4146 enabled = crtc;
4147 } else
4148 planea_wm = fifo_size - wm_info->guard_size;
4149
4150 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4151 crtc = intel_get_crtc_for_plane(dev, 1);
4152 if (crtc->enabled && crtc->fb) {
4153 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4154 wm_info, fifo_size,
4155 crtc->fb->bits_per_pixel / 8,
4156 latency_ns);
4157 if (enabled == NULL)
4158 enabled = crtc;
4159 else
4160 enabled = NULL;
4161 } else
4162 planeb_wm = fifo_size - wm_info->guard_size;
4163
4164 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4165
4166 /*
4167 * Overlay gets an aggressive default since video jitter is bad.
4168 */
4169 cwm = 2;
4170
4171 /* Play safe and disable self-refresh before adjusting watermarks. */
4172 if (IS_I945G(dev) || IS_I945GM(dev))
4173 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4174 else if (IS_I915GM(dev))
4175 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4176
4177 /* Calc sr entries for one plane configs */
4178 if (HAS_FW_BLC(dev) && enabled) {
4179 /* self-refresh has much higher latency */
4180 static const int sr_latency_ns = 6000;
4181 int clock = enabled->mode.clock;
4182 int htotal = enabled->mode.htotal;
4183 int hdisplay = enabled->mode.hdisplay;
4184 int pixel_size = enabled->fb->bits_per_pixel / 8;
4185 unsigned long line_time_us;
4186 int entries;
4187
4188 line_time_us = (htotal * 1000) / clock;
4189
4190 /* Use ns/us then divide to preserve precision */
4191 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4192 pixel_size * hdisplay;
4193 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4194 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4195 srwm = wm_info->fifo_size - entries;
4196 if (srwm < 0)
4197 srwm = 1;
4198
4199 if (IS_I945G(dev) || IS_I945GM(dev))
4200 I915_WRITE(FW_BLC_SELF,
4201 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4202 else if (IS_I915GM(dev))
4203 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4204 }
4205
4206 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4207 planea_wm, planeb_wm, cwm, srwm);
4208
4209 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4210 fwater_hi = (cwm & 0x1f);
4211
4212 /* Set request length to 8 cachelines per fetch */
4213 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4214 fwater_hi = fwater_hi | (1 << 8);
4215
4216 I915_WRITE(FW_BLC, fwater_lo);
4217 I915_WRITE(FW_BLC2, fwater_hi);
4218
4219 if (HAS_FW_BLC(dev)) {
4220 if (enabled) {
4221 if (IS_I945G(dev) || IS_I945GM(dev))
4222 I915_WRITE(FW_BLC_SELF,
4223 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4224 else if (IS_I915GM(dev))
4225 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4226 DRM_DEBUG_KMS("memory self refresh enabled\n");
4227 } else
4228 DRM_DEBUG_KMS("memory self refresh disabled\n");
4229 }
4230 }
4231
4232 static void i830_update_wm(struct drm_device *dev)
4233 {
4234 struct drm_i915_private *dev_priv = dev->dev_private;
4235 struct drm_crtc *crtc;
4236 uint32_t fwater_lo;
4237 int planea_wm;
4238
4239 crtc = single_enabled_crtc(dev);
4240 if (crtc == NULL)
4241 return;
4242
4243 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4244 dev_priv->display.get_fifo_size(dev, 0),
4245 crtc->fb->bits_per_pixel / 8,
4246 latency_ns);
4247 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4248 fwater_lo |= (3<<8) | planea_wm;
4249
4250 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4251
4252 I915_WRITE(FW_BLC, fwater_lo);
4253 }
4254
4255 #define ILK_LP0_PLANE_LATENCY 700
4256 #define ILK_LP0_CURSOR_LATENCY 1300
4257
4258 /*
4259 * Check the wm result.
4260 *
4261 * If any calculated watermark values is larger than the maximum value that
4262 * can be programmed into the associated watermark register, that watermark
4263 * must be disabled.
4264 */
4265 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4266 int fbc_wm, int display_wm, int cursor_wm,
4267 const struct intel_watermark_params *display,
4268 const struct intel_watermark_params *cursor)
4269 {
4270 struct drm_i915_private *dev_priv = dev->dev_private;
4271
4272 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4273 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4274
4275 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4276 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4277 fbc_wm, SNB_FBC_MAX_SRWM, level);
4278
4279 /* fbc has it's own way to disable FBC WM */
4280 I915_WRITE(DISP_ARB_CTL,
4281 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4282 return false;
4283 }
4284
4285 if (display_wm > display->max_wm) {
4286 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4287 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4288 return false;
4289 }
4290
4291 if (cursor_wm > cursor->max_wm) {
4292 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4293 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4294 return false;
4295 }
4296
4297 if (!(fbc_wm || display_wm || cursor_wm)) {
4298 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4299 return false;
4300 }
4301
4302 return true;
4303 }
4304
4305 /*
4306 * Compute watermark values of WM[1-3],
4307 */
4308 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4309 int latency_ns,
4310 const struct intel_watermark_params *display,
4311 const struct intel_watermark_params *cursor,
4312 int *fbc_wm, int *display_wm, int *cursor_wm)
4313 {
4314 struct drm_crtc *crtc;
4315 unsigned long line_time_us;
4316 int hdisplay, htotal, pixel_size, clock;
4317 int line_count, line_size;
4318 int small, large;
4319 int entries;
4320
4321 if (!latency_ns) {
4322 *fbc_wm = *display_wm = *cursor_wm = 0;
4323 return false;
4324 }
4325
4326 crtc = intel_get_crtc_for_plane(dev, plane);
4327 hdisplay = crtc->mode.hdisplay;
4328 htotal = crtc->mode.htotal;
4329 clock = crtc->mode.clock;
4330 pixel_size = crtc->fb->bits_per_pixel / 8;
4331
4332 line_time_us = (htotal * 1000) / clock;
4333 line_count = (latency_ns / line_time_us + 1000) / 1000;
4334 line_size = hdisplay * pixel_size;
4335
4336 /* Use the minimum of the small and large buffer method for primary */
4337 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4338 large = line_count * line_size;
4339
4340 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4341 *display_wm = entries + display->guard_size;
4342
4343 /*
4344 * Spec says:
4345 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4346 */
4347 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4348
4349 /* calculate the self-refresh watermark for display cursor */
4350 entries = line_count * pixel_size * 64;
4351 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4352 *cursor_wm = entries + cursor->guard_size;
4353
4354 return ironlake_check_srwm(dev, level,
4355 *fbc_wm, *display_wm, *cursor_wm,
4356 display, cursor);
4357 }
4358
4359 static void ironlake_update_wm(struct drm_device *dev)
4360 {
4361 struct drm_i915_private *dev_priv = dev->dev_private;
4362 int fbc_wm, plane_wm, cursor_wm;
4363 unsigned int enabled;
4364
4365 enabled = 0;
4366 if (g4x_compute_wm0(dev, 0,
4367 &ironlake_display_wm_info,
4368 ILK_LP0_PLANE_LATENCY,
4369 &ironlake_cursor_wm_info,
4370 ILK_LP0_CURSOR_LATENCY,
4371 &plane_wm, &cursor_wm)) {
4372 I915_WRITE(WM0_PIPEA_ILK,
4373 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4374 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4375 " plane %d, " "cursor: %d\n",
4376 plane_wm, cursor_wm);
4377 enabled |= 1;
4378 }
4379
4380 if (g4x_compute_wm0(dev, 1,
4381 &ironlake_display_wm_info,
4382 ILK_LP0_PLANE_LATENCY,
4383 &ironlake_cursor_wm_info,
4384 ILK_LP0_CURSOR_LATENCY,
4385 &plane_wm, &cursor_wm)) {
4386 I915_WRITE(WM0_PIPEB_ILK,
4387 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4388 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4389 " plane %d, cursor: %d\n",
4390 plane_wm, cursor_wm);
4391 enabled |= 2;
4392 }
4393
4394 /*
4395 * Calculate and update the self-refresh watermark only when one
4396 * display plane is used.
4397 */
4398 I915_WRITE(WM3_LP_ILK, 0);
4399 I915_WRITE(WM2_LP_ILK, 0);
4400 I915_WRITE(WM1_LP_ILK, 0);
4401
4402 if (!single_plane_enabled(enabled))
4403 return;
4404 enabled = ffs(enabled) - 1;
4405
4406 /* WM1 */
4407 if (!ironlake_compute_srwm(dev, 1, enabled,
4408 ILK_READ_WM1_LATENCY() * 500,
4409 &ironlake_display_srwm_info,
4410 &ironlake_cursor_srwm_info,
4411 &fbc_wm, &plane_wm, &cursor_wm))
4412 return;
4413
4414 I915_WRITE(WM1_LP_ILK,
4415 WM1_LP_SR_EN |
4416 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4417 (fbc_wm << WM1_LP_FBC_SHIFT) |
4418 (plane_wm << WM1_LP_SR_SHIFT) |
4419 cursor_wm);
4420
4421 /* WM2 */
4422 if (!ironlake_compute_srwm(dev, 2, enabled,
4423 ILK_READ_WM2_LATENCY() * 500,
4424 &ironlake_display_srwm_info,
4425 &ironlake_cursor_srwm_info,
4426 &fbc_wm, &plane_wm, &cursor_wm))
4427 return;
4428
4429 I915_WRITE(WM2_LP_ILK,
4430 WM2_LP_EN |
4431 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4432 (fbc_wm << WM1_LP_FBC_SHIFT) |
4433 (plane_wm << WM1_LP_SR_SHIFT) |
4434 cursor_wm);
4435
4436 /*
4437 * WM3 is unsupported on ILK, probably because we don't have latency
4438 * data for that power state
4439 */
4440 }
4441
4442 static void sandybridge_update_wm(struct drm_device *dev)
4443 {
4444 struct drm_i915_private *dev_priv = dev->dev_private;
4445 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4446 int fbc_wm, plane_wm, cursor_wm;
4447 unsigned int enabled;
4448
4449 enabled = 0;
4450 if (g4x_compute_wm0(dev, 0,
4451 &sandybridge_display_wm_info, latency,
4452 &sandybridge_cursor_wm_info, latency,
4453 &plane_wm, &cursor_wm)) {
4454 I915_WRITE(WM0_PIPEA_ILK,
4455 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4456 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4457 " plane %d, " "cursor: %d\n",
4458 plane_wm, cursor_wm);
4459 enabled |= 1;
4460 }
4461
4462 if (g4x_compute_wm0(dev, 1,
4463 &sandybridge_display_wm_info, latency,
4464 &sandybridge_cursor_wm_info, latency,
4465 &plane_wm, &cursor_wm)) {
4466 I915_WRITE(WM0_PIPEB_ILK,
4467 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4468 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4469 " plane %d, cursor: %d\n",
4470 plane_wm, cursor_wm);
4471 enabled |= 2;
4472 }
4473
4474 /*
4475 * Calculate and update the self-refresh watermark only when one
4476 * display plane is used.
4477 *
4478 * SNB support 3 levels of watermark.
4479 *
4480 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4481 * and disabled in the descending order
4482 *
4483 */
4484 I915_WRITE(WM3_LP_ILK, 0);
4485 I915_WRITE(WM2_LP_ILK, 0);
4486 I915_WRITE(WM1_LP_ILK, 0);
4487
4488 if (!single_plane_enabled(enabled))
4489 return;
4490 enabled = ffs(enabled) - 1;
4491
4492 /* WM1 */
4493 if (!ironlake_compute_srwm(dev, 1, enabled,
4494 SNB_READ_WM1_LATENCY() * 500,
4495 &sandybridge_display_srwm_info,
4496 &sandybridge_cursor_srwm_info,
4497 &fbc_wm, &plane_wm, &cursor_wm))
4498 return;
4499
4500 I915_WRITE(WM1_LP_ILK,
4501 WM1_LP_SR_EN |
4502 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4503 (fbc_wm << WM1_LP_FBC_SHIFT) |
4504 (plane_wm << WM1_LP_SR_SHIFT) |
4505 cursor_wm);
4506
4507 /* WM2 */
4508 if (!ironlake_compute_srwm(dev, 2, enabled,
4509 SNB_READ_WM2_LATENCY() * 500,
4510 &sandybridge_display_srwm_info,
4511 &sandybridge_cursor_srwm_info,
4512 &fbc_wm, &plane_wm, &cursor_wm))
4513 return;
4514
4515 I915_WRITE(WM2_LP_ILK,
4516 WM2_LP_EN |
4517 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4518 (fbc_wm << WM1_LP_FBC_SHIFT) |
4519 (plane_wm << WM1_LP_SR_SHIFT) |
4520 cursor_wm);
4521
4522 /* WM3 */
4523 if (!ironlake_compute_srwm(dev, 3, enabled,
4524 SNB_READ_WM3_LATENCY() * 500,
4525 &sandybridge_display_srwm_info,
4526 &sandybridge_cursor_srwm_info,
4527 &fbc_wm, &plane_wm, &cursor_wm))
4528 return;
4529
4530 I915_WRITE(WM3_LP_ILK,
4531 WM3_LP_EN |
4532 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4533 (fbc_wm << WM1_LP_FBC_SHIFT) |
4534 (plane_wm << WM1_LP_SR_SHIFT) |
4535 cursor_wm);
4536 }
4537
4538 /**
4539 * intel_update_watermarks - update FIFO watermark values based on current modes
4540 *
4541 * Calculate watermark values for the various WM regs based on current mode
4542 * and plane configuration.
4543 *
4544 * There are several cases to deal with here:
4545 * - normal (i.e. non-self-refresh)
4546 * - self-refresh (SR) mode
4547 * - lines are large relative to FIFO size (buffer can hold up to 2)
4548 * - lines are small relative to FIFO size (buffer can hold more than 2
4549 * lines), so need to account for TLB latency
4550 *
4551 * The normal calculation is:
4552 * watermark = dotclock * bytes per pixel * latency
4553 * where latency is platform & configuration dependent (we assume pessimal
4554 * values here).
4555 *
4556 * The SR calculation is:
4557 * watermark = (trunc(latency/line time)+1) * surface width *
4558 * bytes per pixel
4559 * where
4560 * line time = htotal / dotclock
4561 * surface width = hdisplay for normal plane and 64 for cursor
4562 * and latency is assumed to be high, as above.
4563 *
4564 * The final value programmed to the register should always be rounded up,
4565 * and include an extra 2 entries to account for clock crossings.
4566 *
4567 * We don't use the sprite, so we can ignore that. And on Crestline we have
4568 * to set the non-SR watermarks to 8.
4569 */
4570 static void intel_update_watermarks(struct drm_device *dev)
4571 {
4572 struct drm_i915_private *dev_priv = dev->dev_private;
4573
4574 if (dev_priv->display.update_wm)
4575 dev_priv->display.update_wm(dev);
4576 }
4577
4578 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4579 {
4580 return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4581 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4582 }
4583
4584 /**
4585 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4586 * @crtc: CRTC structure
4587 *
4588 * A pipe may be connected to one or more outputs. Based on the depth of the
4589 * attached framebuffer, choose a good color depth to use on the pipe.
4590 *
4591 * If possible, match the pipe depth to the fb depth. In some cases, this
4592 * isn't ideal, because the connected output supports a lesser or restricted
4593 * set of depths. Resolve that here:
4594 * LVDS typically supports only 6bpc, so clamp down in that case
4595 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4596 * Displays may support a restricted set as well, check EDID and clamp as
4597 * appropriate.
4598 *
4599 * RETURNS:
4600 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4601 * true if they don't match).
4602 */
4603 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4604 unsigned int *pipe_bpp)
4605 {
4606 struct drm_device *dev = crtc->dev;
4607 struct drm_i915_private *dev_priv = dev->dev_private;
4608 struct drm_encoder *encoder;
4609 struct drm_connector *connector;
4610 unsigned int display_bpc = UINT_MAX, bpc;
4611
4612 /* Walk the encoders & connectors on this crtc, get min bpc */
4613 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4614 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4615
4616 if (encoder->crtc != crtc)
4617 continue;
4618
4619 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4620 unsigned int lvds_bpc;
4621
4622 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4623 LVDS_A3_POWER_UP)
4624 lvds_bpc = 8;
4625 else
4626 lvds_bpc = 6;
4627
4628 if (lvds_bpc < display_bpc) {
4629 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4630 display_bpc = lvds_bpc;
4631 }
4632 continue;
4633 }
4634
4635 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4636 /* Use VBT settings if we have an eDP panel */
4637 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4638
4639 if (edp_bpc < display_bpc) {
4640 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4641 display_bpc = edp_bpc;
4642 }
4643 continue;
4644 }
4645
4646 /* Not one of the known troublemakers, check the EDID */
4647 list_for_each_entry(connector, &dev->mode_config.connector_list,
4648 head) {
4649 if (connector->encoder != encoder)
4650 continue;
4651
4652 /* Don't use an invalid EDID bpc value */
4653 if (connector->display_info.bpc &&
4654 connector->display_info.bpc < display_bpc) {
4655 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4656 display_bpc = connector->display_info.bpc;
4657 }
4658 }
4659
4660 /*
4661 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4662 * through, clamp it down. (Note: >12bpc will be caught below.)
4663 */
4664 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4665 if (display_bpc > 8 && display_bpc < 12) {
4666 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4667 display_bpc = 12;
4668 } else {
4669 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4670 display_bpc = 8;
4671 }
4672 }
4673 }
4674
4675 /*
4676 * We could just drive the pipe at the highest bpc all the time and
4677 * enable dithering as needed, but that costs bandwidth. So choose
4678 * the minimum value that expresses the full color range of the fb but
4679 * also stays within the max display bpc discovered above.
4680 */
4681
4682 switch (crtc->fb->depth) {
4683 case 8:
4684 bpc = 8; /* since we go through a colormap */
4685 break;
4686 case 15:
4687 case 16:
4688 bpc = 6; /* min is 18bpp */
4689 break;
4690 case 24:
4691 bpc = 8;
4692 break;
4693 case 30:
4694 bpc = 10;
4695 break;
4696 case 48:
4697 bpc = 12;
4698 break;
4699 default:
4700 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4701 bpc = min((unsigned int)8, display_bpc);
4702 break;
4703 }
4704
4705 display_bpc = min(display_bpc, bpc);
4706
4707 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4708 bpc, display_bpc);
4709
4710 *pipe_bpp = display_bpc * 3;
4711
4712 return display_bpc != bpc;
4713 }
4714
4715 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4716 struct drm_display_mode *mode,
4717 struct drm_display_mode *adjusted_mode,
4718 int x, int y,
4719 struct drm_framebuffer *old_fb)
4720 {
4721 struct drm_device *dev = crtc->dev;
4722 struct drm_i915_private *dev_priv = dev->dev_private;
4723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4724 int pipe = intel_crtc->pipe;
4725 int plane = intel_crtc->plane;
4726 int refclk, num_connectors = 0;
4727 intel_clock_t clock, reduced_clock;
4728 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4729 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4730 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4731 struct drm_mode_config *mode_config = &dev->mode_config;
4732 struct intel_encoder *encoder;
4733 const intel_limit_t *limit;
4734 int ret;
4735 u32 temp;
4736 u32 lvds_sync = 0;
4737
4738 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4739 if (encoder->base.crtc != crtc)
4740 continue;
4741
4742 switch (encoder->type) {
4743 case INTEL_OUTPUT_LVDS:
4744 is_lvds = true;
4745 break;
4746 case INTEL_OUTPUT_SDVO:
4747 case INTEL_OUTPUT_HDMI:
4748 is_sdvo = true;
4749 if (encoder->needs_tv_clock)
4750 is_tv = true;
4751 break;
4752 case INTEL_OUTPUT_DVO:
4753 is_dvo = true;
4754 break;
4755 case INTEL_OUTPUT_TVOUT:
4756 is_tv = true;
4757 break;
4758 case INTEL_OUTPUT_ANALOG:
4759 is_crt = true;
4760 break;
4761 case INTEL_OUTPUT_DISPLAYPORT:
4762 is_dp = true;
4763 break;
4764 }
4765
4766 num_connectors++;
4767 }
4768
4769 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4770 refclk = dev_priv->lvds_ssc_freq * 1000;
4771 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4772 refclk / 1000);
4773 } else if (!IS_GEN2(dev)) {
4774 refclk = 96000;
4775 } else {
4776 refclk = 48000;
4777 }
4778
4779 /*
4780 * Returns a set of divisors for the desired target clock with the given
4781 * refclk, or FALSE. The returned values represent the clock equation:
4782 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4783 */
4784 limit = intel_limit(crtc, refclk);
4785 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4786 if (!ok) {
4787 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4788 return -EINVAL;
4789 }
4790
4791 /* Ensure that the cursor is valid for the new mode before changing... */
4792 intel_crtc_update_cursor(crtc, true);
4793
4794 if (is_lvds && dev_priv->lvds_downclock_avail) {
4795 has_reduced_clock = limit->find_pll(limit, crtc,
4796 dev_priv->lvds_downclock,
4797 refclk,
4798 &reduced_clock);
4799 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4800 /*
4801 * If the different P is found, it means that we can't
4802 * switch the display clock by using the FP0/FP1.
4803 * In such case we will disable the LVDS downclock
4804 * feature.
4805 */
4806 DRM_DEBUG_KMS("Different P is found for "
4807 "LVDS clock/downclock\n");
4808 has_reduced_clock = 0;
4809 }
4810 }
4811 /* SDVO TV has fixed PLL values depend on its clock range,
4812 this mirrors vbios setting. */
4813 if (is_sdvo && is_tv) {
4814 if (adjusted_mode->clock >= 100000
4815 && adjusted_mode->clock < 140500) {
4816 clock.p1 = 2;
4817 clock.p2 = 10;
4818 clock.n = 3;
4819 clock.m1 = 16;
4820 clock.m2 = 8;
4821 } else if (adjusted_mode->clock >= 140500
4822 && adjusted_mode->clock <= 200000) {
4823 clock.p1 = 1;
4824 clock.p2 = 10;
4825 clock.n = 6;
4826 clock.m1 = 12;
4827 clock.m2 = 8;
4828 }
4829 }
4830
4831 if (IS_PINEVIEW(dev)) {
4832 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4833 if (has_reduced_clock)
4834 fp2 = (1 << reduced_clock.n) << 16 |
4835 reduced_clock.m1 << 8 | reduced_clock.m2;
4836 } else {
4837 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4838 if (has_reduced_clock)
4839 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4840 reduced_clock.m2;
4841 }
4842
4843 dpll = DPLL_VGA_MODE_DIS;
4844
4845 if (!IS_GEN2(dev)) {
4846 if (is_lvds)
4847 dpll |= DPLLB_MODE_LVDS;
4848 else
4849 dpll |= DPLLB_MODE_DAC_SERIAL;
4850 if (is_sdvo) {
4851 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4852 if (pixel_multiplier > 1) {
4853 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4854 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4855 }
4856 dpll |= DPLL_DVO_HIGH_SPEED;
4857 }
4858 if (is_dp)
4859 dpll |= DPLL_DVO_HIGH_SPEED;
4860
4861 /* compute bitmask from p1 value */
4862 if (IS_PINEVIEW(dev))
4863 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4864 else {
4865 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4866 if (IS_G4X(dev) && has_reduced_clock)
4867 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4868 }
4869 switch (clock.p2) {
4870 case 5:
4871 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4872 break;
4873 case 7:
4874 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4875 break;
4876 case 10:
4877 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4878 break;
4879 case 14:
4880 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4881 break;
4882 }
4883 if (INTEL_INFO(dev)->gen >= 4)
4884 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4885 } else {
4886 if (is_lvds) {
4887 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4888 } else {
4889 if (clock.p1 == 2)
4890 dpll |= PLL_P1_DIVIDE_BY_TWO;
4891 else
4892 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4893 if (clock.p2 == 4)
4894 dpll |= PLL_P2_DIVIDE_BY_4;
4895 }
4896 }
4897
4898 if (is_sdvo && is_tv)
4899 dpll |= PLL_REF_INPUT_TVCLKINBC;
4900 else if (is_tv)
4901 /* XXX: just matching BIOS for now */
4902 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4903 dpll |= 3;
4904 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4905 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4906 else
4907 dpll |= PLL_REF_INPUT_DREFCLK;
4908
4909 /* setup pipeconf */
4910 pipeconf = I915_READ(PIPECONF(pipe));
4911
4912 /* Set up the display plane register */
4913 dspcntr = DISPPLANE_GAMMA_ENABLE;
4914
4915 /* Ironlake's plane is forced to pipe, bit 24 is to
4916 enable color space conversion */
4917 if (pipe == 0)
4918 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4919 else
4920 dspcntr |= DISPPLANE_SEL_PIPE_B;
4921
4922 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4923 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4924 * core speed.
4925 *
4926 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4927 * pipe == 0 check?
4928 */
4929 if (mode->clock >
4930 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4931 pipeconf |= PIPECONF_DOUBLE_WIDE;
4932 else
4933 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4934 }
4935
4936 dpll |= DPLL_VCO_ENABLE;
4937
4938 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4939 drm_mode_debug_printmodeline(mode);
4940
4941 I915_WRITE(FP0(pipe), fp);
4942 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4943
4944 POSTING_READ(DPLL(pipe));
4945 udelay(150);
4946
4947 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4948 * This is an exception to the general rule that mode_set doesn't turn
4949 * things on.
4950 */
4951 if (is_lvds) {
4952 temp = I915_READ(LVDS);
4953 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4954 if (pipe == 1) {
4955 temp |= LVDS_PIPEB_SELECT;
4956 } else {
4957 temp &= ~LVDS_PIPEB_SELECT;
4958 }
4959 /* set the corresponsding LVDS_BORDER bit */
4960 temp |= dev_priv->lvds_border_bits;
4961 /* Set the B0-B3 data pairs corresponding to whether we're going to
4962 * set the DPLLs for dual-channel mode or not.
4963 */
4964 if (clock.p2 == 7)
4965 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4966 else
4967 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4968
4969 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4970 * appropriately here, but we need to look more thoroughly into how
4971 * panels behave in the two modes.
4972 */
4973 /* set the dithering flag on LVDS as needed */
4974 if (INTEL_INFO(dev)->gen >= 4) {
4975 if (dev_priv->lvds_dither)
4976 temp |= LVDS_ENABLE_DITHER;
4977 else
4978 temp &= ~LVDS_ENABLE_DITHER;
4979 }
4980 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4981 lvds_sync |= LVDS_HSYNC_POLARITY;
4982 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4983 lvds_sync |= LVDS_VSYNC_POLARITY;
4984 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4985 != lvds_sync) {
4986 char flags[2] = "-+";
4987 DRM_INFO("Changing LVDS panel from "
4988 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4989 flags[!(temp & LVDS_HSYNC_POLARITY)],
4990 flags[!(temp & LVDS_VSYNC_POLARITY)],
4991 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4992 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4993 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4994 temp |= lvds_sync;
4995 }
4996 I915_WRITE(LVDS, temp);
4997 }
4998
4999 if (is_dp) {
5000 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5001 }
5002
5003 I915_WRITE(DPLL(pipe), dpll);
5004
5005 /* Wait for the clocks to stabilize. */
5006 POSTING_READ(DPLL(pipe));
5007 udelay(150);
5008
5009 if (INTEL_INFO(dev)->gen >= 4) {
5010 temp = 0;
5011 if (is_sdvo) {
5012 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5013 if (temp > 1)
5014 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5015 else
5016 temp = 0;
5017 }
5018 I915_WRITE(DPLL_MD(pipe), temp);
5019 } else {
5020 /* The pixel multiplier can only be updated once the
5021 * DPLL is enabled and the clocks are stable.
5022 *
5023 * So write it again.
5024 */
5025 I915_WRITE(DPLL(pipe), dpll);
5026 }
5027
5028 intel_crtc->lowfreq_avail = false;
5029 if (is_lvds && has_reduced_clock && i915_powersave) {
5030 I915_WRITE(FP1(pipe), fp2);
5031 intel_crtc->lowfreq_avail = true;
5032 if (HAS_PIPE_CXSR(dev)) {
5033 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5034 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5035 }
5036 } else {
5037 I915_WRITE(FP1(pipe), fp);
5038 if (HAS_PIPE_CXSR(dev)) {
5039 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5040 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5041 }
5042 }
5043
5044 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5045 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5046 /* the chip adds 2 halflines automatically */
5047 adjusted_mode->crtc_vdisplay -= 1;
5048 adjusted_mode->crtc_vtotal -= 1;
5049 adjusted_mode->crtc_vblank_start -= 1;
5050 adjusted_mode->crtc_vblank_end -= 1;
5051 adjusted_mode->crtc_vsync_end -= 1;
5052 adjusted_mode->crtc_vsync_start -= 1;
5053 } else
5054 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5055
5056 I915_WRITE(HTOTAL(pipe),
5057 (adjusted_mode->crtc_hdisplay - 1) |
5058 ((adjusted_mode->crtc_htotal - 1) << 16));
5059 I915_WRITE(HBLANK(pipe),
5060 (adjusted_mode->crtc_hblank_start - 1) |
5061 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5062 I915_WRITE(HSYNC(pipe),
5063 (adjusted_mode->crtc_hsync_start - 1) |
5064 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5065
5066 I915_WRITE(VTOTAL(pipe),
5067 (adjusted_mode->crtc_vdisplay - 1) |
5068 ((adjusted_mode->crtc_vtotal - 1) << 16));
5069 I915_WRITE(VBLANK(pipe),
5070 (adjusted_mode->crtc_vblank_start - 1) |
5071 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5072 I915_WRITE(VSYNC(pipe),
5073 (adjusted_mode->crtc_vsync_start - 1) |
5074 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5075
5076 /* pipesrc and dspsize control the size that is scaled from,
5077 * which should always be the user's requested size.
5078 */
5079 I915_WRITE(DSPSIZE(plane),
5080 ((mode->vdisplay - 1) << 16) |
5081 (mode->hdisplay - 1));
5082 I915_WRITE(DSPPOS(plane), 0);
5083 I915_WRITE(PIPESRC(pipe),
5084 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5085
5086 I915_WRITE(PIPECONF(pipe), pipeconf);
5087 POSTING_READ(PIPECONF(pipe));
5088 intel_enable_pipe(dev_priv, pipe, false);
5089
5090 intel_wait_for_vblank(dev, pipe);
5091
5092 I915_WRITE(DSPCNTR(plane), dspcntr);
5093 POSTING_READ(DSPCNTR(plane));
5094 intel_enable_plane(dev_priv, plane, pipe);
5095
5096 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5097
5098 intel_update_watermarks(dev);
5099
5100 return ret;
5101 }
5102
5103 static void ironlake_update_pch_refclk(struct drm_device *dev)
5104 {
5105 struct drm_i915_private *dev_priv = dev->dev_private;
5106 struct drm_mode_config *mode_config = &dev->mode_config;
5107 struct drm_crtc *crtc;
5108 struct intel_encoder *encoder;
5109 struct intel_encoder *has_edp_encoder = NULL;
5110 u32 temp;
5111 bool has_lvds = false;
5112
5113 /* We need to take the global config into account */
5114 list_for_each_entry(crtc, &mode_config->crtc_list, head) {
5115 if (!crtc->enabled)
5116 continue;
5117
5118 list_for_each_entry(encoder, &mode_config->encoder_list,
5119 base.head) {
5120 if (encoder->base.crtc != crtc)
5121 continue;
5122
5123 switch (encoder->type) {
5124 case INTEL_OUTPUT_LVDS:
5125 has_lvds = true;
5126 case INTEL_OUTPUT_EDP:
5127 has_edp_encoder = encoder;
5128 break;
5129 }
5130 }
5131 }
5132
5133 /* Ironlake: try to setup display ref clock before DPLL
5134 * enabling. This is only under driver's control after
5135 * PCH B stepping, previous chipset stepping should be
5136 * ignoring this setting.
5137 */
5138 temp = I915_READ(PCH_DREF_CONTROL);
5139 /* Always enable nonspread source */
5140 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5141 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5142 temp &= ~DREF_SSC_SOURCE_MASK;
5143 temp |= DREF_SSC_SOURCE_ENABLE;
5144 I915_WRITE(PCH_DREF_CONTROL, temp);
5145
5146 POSTING_READ(PCH_DREF_CONTROL);
5147 udelay(200);
5148
5149 if (has_edp_encoder) {
5150 if (intel_panel_use_ssc(dev_priv)) {
5151 temp |= DREF_SSC1_ENABLE;
5152 I915_WRITE(PCH_DREF_CONTROL, temp);
5153
5154 POSTING_READ(PCH_DREF_CONTROL);
5155 udelay(200);
5156 }
5157 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5158
5159 /* Enable CPU source on CPU attached eDP */
5160 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5161 if (intel_panel_use_ssc(dev_priv))
5162 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5163 else
5164 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5165 } else {
5166 /* Enable SSC on PCH eDP if needed */
5167 if (intel_panel_use_ssc(dev_priv)) {
5168 DRM_ERROR("enabling SSC on PCH\n");
5169 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5170 }
5171 }
5172 I915_WRITE(PCH_DREF_CONTROL, temp);
5173 POSTING_READ(PCH_DREF_CONTROL);
5174 udelay(200);
5175 }
5176 }
5177
5178 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5179 struct drm_display_mode *mode,
5180 struct drm_display_mode *adjusted_mode,
5181 int x, int y,
5182 struct drm_framebuffer *old_fb)
5183 {
5184 struct drm_device *dev = crtc->dev;
5185 struct drm_i915_private *dev_priv = dev->dev_private;
5186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5187 int pipe = intel_crtc->pipe;
5188 int plane = intel_crtc->plane;
5189 int refclk, num_connectors = 0;
5190 intel_clock_t clock, reduced_clock;
5191 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5192 bool ok, has_reduced_clock = false, is_sdvo = false;
5193 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5194 struct intel_encoder *has_edp_encoder = NULL;
5195 struct drm_mode_config *mode_config = &dev->mode_config;
5196 struct intel_encoder *encoder;
5197 const intel_limit_t *limit;
5198 int ret;
5199 struct fdi_m_n m_n = {0};
5200 u32 temp;
5201 u32 lvds_sync = 0;
5202 int target_clock, pixel_multiplier, lane, link_bw, factor;
5203 unsigned int pipe_bpp;
5204 bool dither;
5205
5206 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5207 if (encoder->base.crtc != crtc)
5208 continue;
5209
5210 switch (encoder->type) {
5211 case INTEL_OUTPUT_LVDS:
5212 is_lvds = true;
5213 break;
5214 case INTEL_OUTPUT_SDVO:
5215 case INTEL_OUTPUT_HDMI:
5216 is_sdvo = true;
5217 if (encoder->needs_tv_clock)
5218 is_tv = true;
5219 break;
5220 case INTEL_OUTPUT_TVOUT:
5221 is_tv = true;
5222 break;
5223 case INTEL_OUTPUT_ANALOG:
5224 is_crt = true;
5225 break;
5226 case INTEL_OUTPUT_DISPLAYPORT:
5227 is_dp = true;
5228 break;
5229 case INTEL_OUTPUT_EDP:
5230 has_edp_encoder = encoder;
5231 break;
5232 }
5233
5234 num_connectors++;
5235 }
5236
5237 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5238 refclk = dev_priv->lvds_ssc_freq * 1000;
5239 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5240 refclk / 1000);
5241 } else {
5242 refclk = 96000;
5243 if (!has_edp_encoder ||
5244 intel_encoder_is_pch_edp(&has_edp_encoder->base))
5245 refclk = 120000; /* 120Mhz refclk */
5246 }
5247
5248 /*
5249 * Returns a set of divisors for the desired target clock with the given
5250 * refclk, or FALSE. The returned values represent the clock equation:
5251 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5252 */
5253 limit = intel_limit(crtc, refclk);
5254 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5255 if (!ok) {
5256 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5257 return -EINVAL;
5258 }
5259
5260 /* Ensure that the cursor is valid for the new mode before changing... */
5261 intel_crtc_update_cursor(crtc, true);
5262
5263 if (is_lvds && dev_priv->lvds_downclock_avail) {
5264 has_reduced_clock = limit->find_pll(limit, crtc,
5265 dev_priv->lvds_downclock,
5266 refclk,
5267 &reduced_clock);
5268 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5269 /*
5270 * If the different P is found, it means that we can't
5271 * switch the display clock by using the FP0/FP1.
5272 * In such case we will disable the LVDS downclock
5273 * feature.
5274 */
5275 DRM_DEBUG_KMS("Different P is found for "
5276 "LVDS clock/downclock\n");
5277 has_reduced_clock = 0;
5278 }
5279 }
5280 /* SDVO TV has fixed PLL values depend on its clock range,
5281 this mirrors vbios setting. */
5282 if (is_sdvo && is_tv) {
5283 if (adjusted_mode->clock >= 100000
5284 && adjusted_mode->clock < 140500) {
5285 clock.p1 = 2;
5286 clock.p2 = 10;
5287 clock.n = 3;
5288 clock.m1 = 16;
5289 clock.m2 = 8;
5290 } else if (adjusted_mode->clock >= 140500
5291 && adjusted_mode->clock <= 200000) {
5292 clock.p1 = 1;
5293 clock.p2 = 10;
5294 clock.n = 6;
5295 clock.m1 = 12;
5296 clock.m2 = 8;
5297 }
5298 }
5299
5300 /* FDI link */
5301 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5302 lane = 0;
5303 /* CPU eDP doesn't require FDI link, so just set DP M/N
5304 according to current link config */
5305 if (has_edp_encoder &&
5306 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5307 target_clock = mode->clock;
5308 intel_edp_link_config(has_edp_encoder,
5309 &lane, &link_bw);
5310 } else {
5311 /* [e]DP over FDI requires target mode clock
5312 instead of link clock */
5313 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5314 target_clock = mode->clock;
5315 else
5316 target_clock = adjusted_mode->clock;
5317
5318 /* FDI is a binary signal running at ~2.7GHz, encoding
5319 * each output octet as 10 bits. The actual frequency
5320 * is stored as a divider into a 100MHz clock, and the
5321 * mode pixel clock is stored in units of 1KHz.
5322 * Hence the bw of each lane in terms of the mode signal
5323 * is:
5324 */
5325 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5326 }
5327
5328 /* determine panel color depth */
5329 temp = I915_READ(PIPECONF(pipe));
5330 temp &= ~PIPE_BPC_MASK;
5331 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5332 switch (pipe_bpp) {
5333 case 18:
5334 temp |= PIPE_6BPC;
5335 break;
5336 case 24:
5337 temp |= PIPE_8BPC;
5338 break;
5339 case 30:
5340 temp |= PIPE_10BPC;
5341 break;
5342 case 36:
5343 temp |= PIPE_12BPC;
5344 break;
5345 default:
5346 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5347 pipe_bpp);
5348 temp |= PIPE_8BPC;
5349 pipe_bpp = 24;
5350 break;
5351 }
5352
5353 intel_crtc->bpp = pipe_bpp;
5354 I915_WRITE(PIPECONF(pipe), temp);
5355
5356 if (!lane) {
5357 /*
5358 * Account for spread spectrum to avoid
5359 * oversubscribing the link. Max center spread
5360 * is 2.5%; use 5% for safety's sake.
5361 */
5362 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5363 lane = bps / (link_bw * 8) + 1;
5364 }
5365
5366 intel_crtc->fdi_lanes = lane;
5367
5368 if (pixel_multiplier > 1)
5369 link_bw *= pixel_multiplier;
5370 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5371 &m_n);
5372
5373 ironlake_update_pch_refclk(dev);
5374
5375 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5376 if (has_reduced_clock)
5377 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5378 reduced_clock.m2;
5379
5380 /* Enable autotuning of the PLL clock (if permissible) */
5381 factor = 21;
5382 if (is_lvds) {
5383 if ((intel_panel_use_ssc(dev_priv) &&
5384 dev_priv->lvds_ssc_freq == 100) ||
5385 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5386 factor = 25;
5387 } else if (is_sdvo && is_tv)
5388 factor = 20;
5389
5390 if (clock.m < factor * clock.n)
5391 fp |= FP_CB_TUNE;
5392
5393 dpll = 0;
5394
5395 if (is_lvds)
5396 dpll |= DPLLB_MODE_LVDS;
5397 else
5398 dpll |= DPLLB_MODE_DAC_SERIAL;
5399 if (is_sdvo) {
5400 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5401 if (pixel_multiplier > 1) {
5402 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5403 }
5404 dpll |= DPLL_DVO_HIGH_SPEED;
5405 }
5406 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5407 dpll |= DPLL_DVO_HIGH_SPEED;
5408
5409 /* compute bitmask from p1 value */
5410 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5411 /* also FPA1 */
5412 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5413
5414 switch (clock.p2) {
5415 case 5:
5416 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5417 break;
5418 case 7:
5419 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5420 break;
5421 case 10:
5422 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5423 break;
5424 case 14:
5425 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5426 break;
5427 }
5428
5429 if (is_sdvo && is_tv)
5430 dpll |= PLL_REF_INPUT_TVCLKINBC;
5431 else if (is_tv)
5432 /* XXX: just matching BIOS for now */
5433 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5434 dpll |= 3;
5435 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5436 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5437 else
5438 dpll |= PLL_REF_INPUT_DREFCLK;
5439
5440 /* setup pipeconf */
5441 pipeconf = I915_READ(PIPECONF(pipe));
5442
5443 /* Set up the display plane register */
5444 dspcntr = DISPPLANE_GAMMA_ENABLE;
5445
5446 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5447 drm_mode_debug_printmodeline(mode);
5448
5449 /* PCH eDP needs FDI, but CPU eDP does not */
5450 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5451 I915_WRITE(PCH_FP0(pipe), fp);
5452 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5453
5454 POSTING_READ(PCH_DPLL(pipe));
5455 udelay(150);
5456 }
5457
5458 /* enable transcoder DPLL */
5459 if (HAS_PCH_CPT(dev)) {
5460 temp = I915_READ(PCH_DPLL_SEL);
5461 switch (pipe) {
5462 case 0:
5463 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5464 break;
5465 case 1:
5466 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5467 break;
5468 case 2:
5469 /* FIXME: manage transcoder PLLs? */
5470 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5471 break;
5472 default:
5473 BUG();
5474 }
5475 I915_WRITE(PCH_DPLL_SEL, temp);
5476
5477 POSTING_READ(PCH_DPLL_SEL);
5478 udelay(150);
5479 }
5480
5481 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5482 * This is an exception to the general rule that mode_set doesn't turn
5483 * things on.
5484 */
5485 if (is_lvds) {
5486 temp = I915_READ(PCH_LVDS);
5487 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5488 if (pipe == 1) {
5489 if (HAS_PCH_CPT(dev))
5490 temp |= PORT_TRANS_B_SEL_CPT;
5491 else
5492 temp |= LVDS_PIPEB_SELECT;
5493 } else {
5494 if (HAS_PCH_CPT(dev))
5495 temp &= ~PORT_TRANS_SEL_MASK;
5496 else
5497 temp &= ~LVDS_PIPEB_SELECT;
5498 }
5499 /* set the corresponsding LVDS_BORDER bit */
5500 temp |= dev_priv->lvds_border_bits;
5501 /* Set the B0-B3 data pairs corresponding to whether we're going to
5502 * set the DPLLs for dual-channel mode or not.
5503 */
5504 if (clock.p2 == 7)
5505 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5506 else
5507 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5508
5509 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5510 * appropriately here, but we need to look more thoroughly into how
5511 * panels behave in the two modes.
5512 */
5513 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5514 lvds_sync |= LVDS_HSYNC_POLARITY;
5515 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5516 lvds_sync |= LVDS_VSYNC_POLARITY;
5517 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5518 != lvds_sync) {
5519 char flags[2] = "-+";
5520 DRM_INFO("Changing LVDS panel from "
5521 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5522 flags[!(temp & LVDS_HSYNC_POLARITY)],
5523 flags[!(temp & LVDS_VSYNC_POLARITY)],
5524 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5525 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5526 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5527 temp |= lvds_sync;
5528 }
5529 I915_WRITE(PCH_LVDS, temp);
5530 }
5531
5532 pipeconf &= ~PIPECONF_DITHER_EN;
5533 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5534 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5535 pipeconf |= PIPECONF_DITHER_EN;
5536 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5537 }
5538 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5539 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5540 } else {
5541 /* For non-DP output, clear any trans DP clock recovery setting.*/
5542 I915_WRITE(TRANSDATA_M1(pipe), 0);
5543 I915_WRITE(TRANSDATA_N1(pipe), 0);
5544 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5545 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5546 }
5547
5548 if (!has_edp_encoder ||
5549 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5550 I915_WRITE(PCH_DPLL(pipe), dpll);
5551
5552 /* Wait for the clocks to stabilize. */
5553 POSTING_READ(PCH_DPLL(pipe));
5554 udelay(150);
5555
5556 /* The pixel multiplier can only be updated once the
5557 * DPLL is enabled and the clocks are stable.
5558 *
5559 * So write it again.
5560 */
5561 I915_WRITE(PCH_DPLL(pipe), dpll);
5562 }
5563
5564 intel_crtc->lowfreq_avail = false;
5565 if (is_lvds && has_reduced_clock && i915_powersave) {
5566 I915_WRITE(PCH_FP1(pipe), fp2);
5567 intel_crtc->lowfreq_avail = true;
5568 if (HAS_PIPE_CXSR(dev)) {
5569 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5570 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5571 }
5572 } else {
5573 I915_WRITE(PCH_FP1(pipe), fp);
5574 if (HAS_PIPE_CXSR(dev)) {
5575 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5576 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5577 }
5578 }
5579
5580 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5581 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5582 /* the chip adds 2 halflines automatically */
5583 adjusted_mode->crtc_vdisplay -= 1;
5584 adjusted_mode->crtc_vtotal -= 1;
5585 adjusted_mode->crtc_vblank_start -= 1;
5586 adjusted_mode->crtc_vblank_end -= 1;
5587 adjusted_mode->crtc_vsync_end -= 1;
5588 adjusted_mode->crtc_vsync_start -= 1;
5589 } else
5590 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5591
5592 I915_WRITE(HTOTAL(pipe),
5593 (adjusted_mode->crtc_hdisplay - 1) |
5594 ((adjusted_mode->crtc_htotal - 1) << 16));
5595 I915_WRITE(HBLANK(pipe),
5596 (adjusted_mode->crtc_hblank_start - 1) |
5597 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5598 I915_WRITE(HSYNC(pipe),
5599 (adjusted_mode->crtc_hsync_start - 1) |
5600 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5601
5602 I915_WRITE(VTOTAL(pipe),
5603 (adjusted_mode->crtc_vdisplay - 1) |
5604 ((adjusted_mode->crtc_vtotal - 1) << 16));
5605 I915_WRITE(VBLANK(pipe),
5606 (adjusted_mode->crtc_vblank_start - 1) |
5607 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5608 I915_WRITE(VSYNC(pipe),
5609 (adjusted_mode->crtc_vsync_start - 1) |
5610 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5611
5612 /* pipesrc controls the size that is scaled from, which should
5613 * always be the user's requested size.
5614 */
5615 I915_WRITE(PIPESRC(pipe),
5616 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5617
5618 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5619 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5620 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5621 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5622
5623 if (has_edp_encoder &&
5624 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5625 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5626 }
5627
5628 I915_WRITE(PIPECONF(pipe), pipeconf);
5629 POSTING_READ(PIPECONF(pipe));
5630
5631 intel_wait_for_vblank(dev, pipe);
5632
5633 if (IS_GEN5(dev)) {
5634 /* enable address swizzle for tiling buffer */
5635 temp = I915_READ(DISP_ARB_CTL);
5636 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5637 }
5638
5639 I915_WRITE(DSPCNTR(plane), dspcntr);
5640 POSTING_READ(DSPCNTR(plane));
5641
5642 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5643
5644 intel_update_watermarks(dev);
5645
5646 return ret;
5647 }
5648
5649 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5650 struct drm_display_mode *mode,
5651 struct drm_display_mode *adjusted_mode,
5652 int x, int y,
5653 struct drm_framebuffer *old_fb)
5654 {
5655 struct drm_device *dev = crtc->dev;
5656 struct drm_i915_private *dev_priv = dev->dev_private;
5657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5658 int pipe = intel_crtc->pipe;
5659 int ret;
5660
5661 drm_vblank_pre_modeset(dev, pipe);
5662
5663 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5664 x, y, old_fb);
5665
5666 drm_vblank_post_modeset(dev, pipe);
5667
5668 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5669
5670 return ret;
5671 }
5672
5673 static void g4x_write_eld(struct drm_connector *connector,
5674 struct drm_crtc *crtc)
5675 {
5676 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5677 uint8_t *eld = connector->eld;
5678 uint32_t eldv;
5679 uint32_t len;
5680 uint32_t i;
5681
5682 i = I915_READ(G4X_AUD_VID_DID);
5683
5684 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5685 eldv = G4X_ELDV_DEVCL_DEVBLC;
5686 else
5687 eldv = G4X_ELDV_DEVCTG;
5688
5689 i = I915_READ(G4X_AUD_CNTL_ST);
5690 i &= ~(eldv | G4X_ELD_ADDR);
5691 len = (i >> 9) & 0x1f; /* ELD buffer size */
5692 I915_WRITE(G4X_AUD_CNTL_ST, i);
5693
5694 if (!eld[0])
5695 return;
5696
5697 len = min_t(uint8_t, eld[2], len);
5698 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5699 for (i = 0; i < len; i++)
5700 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5701
5702 i = I915_READ(G4X_AUD_CNTL_ST);
5703 i |= eldv;
5704 I915_WRITE(G4X_AUD_CNTL_ST, i);
5705 }
5706
5707 static void ironlake_write_eld(struct drm_connector *connector,
5708 struct drm_crtc *crtc)
5709 {
5710 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5711 uint8_t *eld = connector->eld;
5712 uint32_t eldv;
5713 uint32_t i;
5714 int len;
5715 int hdmiw_hdmiedid;
5716 int aud_cntl_st;
5717 int aud_cntrl_st2;
5718
5719 if (IS_IVYBRIDGE(connector->dev)) {
5720 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5721 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5722 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5723 } else {
5724 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5725 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5726 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5727 }
5728
5729 i = to_intel_crtc(crtc)->pipe;
5730 hdmiw_hdmiedid += i * 0x100;
5731 aud_cntl_st += i * 0x100;
5732
5733 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5734
5735 i = I915_READ(aud_cntl_st);
5736 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5737 if (!i) {
5738 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5739 /* operate blindly on all ports */
5740 eldv = GEN5_ELD_VALIDB;
5741 eldv |= GEN5_ELD_VALIDB << 4;
5742 eldv |= GEN5_ELD_VALIDB << 8;
5743 } else {
5744 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5745 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5746 }
5747
5748 i = I915_READ(aud_cntrl_st2);
5749 i &= ~eldv;
5750 I915_WRITE(aud_cntrl_st2, i);
5751
5752 if (!eld[0])
5753 return;
5754
5755 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5756 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5757 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5758 }
5759
5760 i = I915_READ(aud_cntl_st);
5761 i &= ~GEN5_ELD_ADDRESS;
5762 I915_WRITE(aud_cntl_st, i);
5763
5764 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5765 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5766 for (i = 0; i < len; i++)
5767 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5768
5769 i = I915_READ(aud_cntrl_st2);
5770 i |= eldv;
5771 I915_WRITE(aud_cntrl_st2, i);
5772 }
5773
5774 void intel_write_eld(struct drm_encoder *encoder,
5775 struct drm_display_mode *mode)
5776 {
5777 struct drm_crtc *crtc = encoder->crtc;
5778 struct drm_connector *connector;
5779 struct drm_device *dev = encoder->dev;
5780 struct drm_i915_private *dev_priv = dev->dev_private;
5781
5782 connector = drm_select_eld(encoder, mode);
5783 if (!connector)
5784 return;
5785
5786 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5787 connector->base.id,
5788 drm_get_connector_name(connector),
5789 connector->encoder->base.id,
5790 drm_get_encoder_name(connector->encoder));
5791
5792 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5793
5794 if (dev_priv->display.write_eld)
5795 dev_priv->display.write_eld(connector, crtc);
5796 }
5797
5798 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5799 void intel_crtc_load_lut(struct drm_crtc *crtc)
5800 {
5801 struct drm_device *dev = crtc->dev;
5802 struct drm_i915_private *dev_priv = dev->dev_private;
5803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5804 int palreg = PALETTE(intel_crtc->pipe);
5805 int i;
5806
5807 /* The clocks have to be on to load the palette. */
5808 if (!crtc->enabled)
5809 return;
5810
5811 /* use legacy palette for Ironlake */
5812 if (HAS_PCH_SPLIT(dev))
5813 palreg = LGC_PALETTE(intel_crtc->pipe);
5814
5815 for (i = 0; i < 256; i++) {
5816 I915_WRITE(palreg + 4 * i,
5817 (intel_crtc->lut_r[i] << 16) |
5818 (intel_crtc->lut_g[i] << 8) |
5819 intel_crtc->lut_b[i]);
5820 }
5821 }
5822
5823 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5824 {
5825 struct drm_device *dev = crtc->dev;
5826 struct drm_i915_private *dev_priv = dev->dev_private;
5827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5828 bool visible = base != 0;
5829 u32 cntl;
5830
5831 if (intel_crtc->cursor_visible == visible)
5832 return;
5833
5834 cntl = I915_READ(_CURACNTR);
5835 if (visible) {
5836 /* On these chipsets we can only modify the base whilst
5837 * the cursor is disabled.
5838 */
5839 I915_WRITE(_CURABASE, base);
5840
5841 cntl &= ~(CURSOR_FORMAT_MASK);
5842 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5843 cntl |= CURSOR_ENABLE |
5844 CURSOR_GAMMA_ENABLE |
5845 CURSOR_FORMAT_ARGB;
5846 } else
5847 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5848 I915_WRITE(_CURACNTR, cntl);
5849
5850 intel_crtc->cursor_visible = visible;
5851 }
5852
5853 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5854 {
5855 struct drm_device *dev = crtc->dev;
5856 struct drm_i915_private *dev_priv = dev->dev_private;
5857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5858 int pipe = intel_crtc->pipe;
5859 bool visible = base != 0;
5860
5861 if (intel_crtc->cursor_visible != visible) {
5862 uint32_t cntl = I915_READ(CURCNTR(pipe));
5863 if (base) {
5864 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5865 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5866 cntl |= pipe << 28; /* Connect to correct pipe */
5867 } else {
5868 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5869 cntl |= CURSOR_MODE_DISABLE;
5870 }
5871 I915_WRITE(CURCNTR(pipe), cntl);
5872
5873 intel_crtc->cursor_visible = visible;
5874 }
5875 /* and commit changes on next vblank */
5876 I915_WRITE(CURBASE(pipe), base);
5877 }
5878
5879 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5880 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5881 bool on)
5882 {
5883 struct drm_device *dev = crtc->dev;
5884 struct drm_i915_private *dev_priv = dev->dev_private;
5885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5886 int pipe = intel_crtc->pipe;
5887 int x = intel_crtc->cursor_x;
5888 int y = intel_crtc->cursor_y;
5889 u32 base, pos;
5890 bool visible;
5891
5892 pos = 0;
5893
5894 if (on && crtc->enabled && crtc->fb) {
5895 base = intel_crtc->cursor_addr;
5896 if (x > (int) crtc->fb->width)
5897 base = 0;
5898
5899 if (y > (int) crtc->fb->height)
5900 base = 0;
5901 } else
5902 base = 0;
5903
5904 if (x < 0) {
5905 if (x + intel_crtc->cursor_width < 0)
5906 base = 0;
5907
5908 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5909 x = -x;
5910 }
5911 pos |= x << CURSOR_X_SHIFT;
5912
5913 if (y < 0) {
5914 if (y + intel_crtc->cursor_height < 0)
5915 base = 0;
5916
5917 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5918 y = -y;
5919 }
5920 pos |= y << CURSOR_Y_SHIFT;
5921
5922 visible = base != 0;
5923 if (!visible && !intel_crtc->cursor_visible)
5924 return;
5925
5926 I915_WRITE(CURPOS(pipe), pos);
5927 if (IS_845G(dev) || IS_I865G(dev))
5928 i845_update_cursor(crtc, base);
5929 else
5930 i9xx_update_cursor(crtc, base);
5931
5932 if (visible)
5933 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5934 }
5935
5936 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5937 struct drm_file *file,
5938 uint32_t handle,
5939 uint32_t width, uint32_t height)
5940 {
5941 struct drm_device *dev = crtc->dev;
5942 struct drm_i915_private *dev_priv = dev->dev_private;
5943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5944 struct drm_i915_gem_object *obj;
5945 uint32_t addr;
5946 int ret;
5947
5948 DRM_DEBUG_KMS("\n");
5949
5950 /* if we want to turn off the cursor ignore width and height */
5951 if (!handle) {
5952 DRM_DEBUG_KMS("cursor off\n");
5953 addr = 0;
5954 obj = NULL;
5955 mutex_lock(&dev->struct_mutex);
5956 goto finish;
5957 }
5958
5959 /* Currently we only support 64x64 cursors */
5960 if (width != 64 || height != 64) {
5961 DRM_ERROR("we currently only support 64x64 cursors\n");
5962 return -EINVAL;
5963 }
5964
5965 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5966 if (&obj->base == NULL)
5967 return -ENOENT;
5968
5969 if (obj->base.size < width * height * 4) {
5970 DRM_ERROR("buffer is to small\n");
5971 ret = -ENOMEM;
5972 goto fail;
5973 }
5974
5975 /* we only need to pin inside GTT if cursor is non-phy */
5976 mutex_lock(&dev->struct_mutex);
5977 if (!dev_priv->info->cursor_needs_physical) {
5978 if (obj->tiling_mode) {
5979 DRM_ERROR("cursor cannot be tiled\n");
5980 ret = -EINVAL;
5981 goto fail_locked;
5982 }
5983
5984 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5985 if (ret) {
5986 DRM_ERROR("failed to move cursor bo into the GTT\n");
5987 goto fail_locked;
5988 }
5989
5990 ret = i915_gem_object_put_fence(obj);
5991 if (ret) {
5992 DRM_ERROR("failed to release fence for cursor");
5993 goto fail_unpin;
5994 }
5995
5996 addr = obj->gtt_offset;
5997 } else {
5998 int align = IS_I830(dev) ? 16 * 1024 : 256;
5999 ret = i915_gem_attach_phys_object(dev, obj,
6000 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6001 align);
6002 if (ret) {
6003 DRM_ERROR("failed to attach phys object\n");
6004 goto fail_locked;
6005 }
6006 addr = obj->phys_obj->handle->busaddr;
6007 }
6008
6009 if (IS_GEN2(dev))
6010 I915_WRITE(CURSIZE, (height << 12) | width);
6011
6012 finish:
6013 if (intel_crtc->cursor_bo) {
6014 if (dev_priv->info->cursor_needs_physical) {
6015 if (intel_crtc->cursor_bo != obj)
6016 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6017 } else
6018 i915_gem_object_unpin(intel_crtc->cursor_bo);
6019 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6020 }
6021
6022 mutex_unlock(&dev->struct_mutex);
6023
6024 intel_crtc->cursor_addr = addr;
6025 intel_crtc->cursor_bo = obj;
6026 intel_crtc->cursor_width = width;
6027 intel_crtc->cursor_height = height;
6028
6029 intel_crtc_update_cursor(crtc, true);
6030
6031 return 0;
6032 fail_unpin:
6033 i915_gem_object_unpin(obj);
6034 fail_locked:
6035 mutex_unlock(&dev->struct_mutex);
6036 fail:
6037 drm_gem_object_unreference_unlocked(&obj->base);
6038 return ret;
6039 }
6040
6041 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6042 {
6043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6044
6045 intel_crtc->cursor_x = x;
6046 intel_crtc->cursor_y = y;
6047
6048 intel_crtc_update_cursor(crtc, true);
6049
6050 return 0;
6051 }
6052
6053 /** Sets the color ramps on behalf of RandR */
6054 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6055 u16 blue, int regno)
6056 {
6057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6058
6059 intel_crtc->lut_r[regno] = red >> 8;
6060 intel_crtc->lut_g[regno] = green >> 8;
6061 intel_crtc->lut_b[regno] = blue >> 8;
6062 }
6063
6064 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6065 u16 *blue, int regno)
6066 {
6067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6068
6069 *red = intel_crtc->lut_r[regno] << 8;
6070 *green = intel_crtc->lut_g[regno] << 8;
6071 *blue = intel_crtc->lut_b[regno] << 8;
6072 }
6073
6074 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6075 u16 *blue, uint32_t start, uint32_t size)
6076 {
6077 int end = (start + size > 256) ? 256 : start + size, i;
6078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6079
6080 for (i = start; i < end; i++) {
6081 intel_crtc->lut_r[i] = red[i] >> 8;
6082 intel_crtc->lut_g[i] = green[i] >> 8;
6083 intel_crtc->lut_b[i] = blue[i] >> 8;
6084 }
6085
6086 intel_crtc_load_lut(crtc);
6087 }
6088
6089 /**
6090 * Get a pipe with a simple mode set on it for doing load-based monitor
6091 * detection.
6092 *
6093 * It will be up to the load-detect code to adjust the pipe as appropriate for
6094 * its requirements. The pipe will be connected to no other encoders.
6095 *
6096 * Currently this code will only succeed if there is a pipe with no encoders
6097 * configured for it. In the future, it could choose to temporarily disable
6098 * some outputs to free up a pipe for its use.
6099 *
6100 * \return crtc, or NULL if no pipes are available.
6101 */
6102
6103 /* VESA 640x480x72Hz mode to set on the pipe */
6104 static struct drm_display_mode load_detect_mode = {
6105 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6106 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6107 };
6108
6109 static struct drm_framebuffer *
6110 intel_framebuffer_create(struct drm_device *dev,
6111 struct drm_mode_fb_cmd *mode_cmd,
6112 struct drm_i915_gem_object *obj)
6113 {
6114 struct intel_framebuffer *intel_fb;
6115 int ret;
6116
6117 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6118 if (!intel_fb) {
6119 drm_gem_object_unreference_unlocked(&obj->base);
6120 return ERR_PTR(-ENOMEM);
6121 }
6122
6123 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6124 if (ret) {
6125 drm_gem_object_unreference_unlocked(&obj->base);
6126 kfree(intel_fb);
6127 return ERR_PTR(ret);
6128 }
6129
6130 return &intel_fb->base;
6131 }
6132
6133 static u32
6134 intel_framebuffer_pitch_for_width(int width, int bpp)
6135 {
6136 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6137 return ALIGN(pitch, 64);
6138 }
6139
6140 static u32
6141 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6142 {
6143 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6144 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6145 }
6146
6147 static struct drm_framebuffer *
6148 intel_framebuffer_create_for_mode(struct drm_device *dev,
6149 struct drm_display_mode *mode,
6150 int depth, int bpp)
6151 {
6152 struct drm_i915_gem_object *obj;
6153 struct drm_mode_fb_cmd mode_cmd;
6154
6155 obj = i915_gem_alloc_object(dev,
6156 intel_framebuffer_size_for_mode(mode, bpp));
6157 if (obj == NULL)
6158 return ERR_PTR(-ENOMEM);
6159
6160 mode_cmd.width = mode->hdisplay;
6161 mode_cmd.height = mode->vdisplay;
6162 mode_cmd.depth = depth;
6163 mode_cmd.bpp = bpp;
6164 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6165
6166 return intel_framebuffer_create(dev, &mode_cmd, obj);
6167 }
6168
6169 static struct drm_framebuffer *
6170 mode_fits_in_fbdev(struct drm_device *dev,
6171 struct drm_display_mode *mode)
6172 {
6173 struct drm_i915_private *dev_priv = dev->dev_private;
6174 struct drm_i915_gem_object *obj;
6175 struct drm_framebuffer *fb;
6176
6177 if (dev_priv->fbdev == NULL)
6178 return NULL;
6179
6180 obj = dev_priv->fbdev->ifb.obj;
6181 if (obj == NULL)
6182 return NULL;
6183
6184 fb = &dev_priv->fbdev->ifb.base;
6185 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6186 fb->bits_per_pixel))
6187 return NULL;
6188
6189 if (obj->base.size < mode->vdisplay * fb->pitch)
6190 return NULL;
6191
6192 return fb;
6193 }
6194
6195 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6196 struct drm_connector *connector,
6197 struct drm_display_mode *mode,
6198 struct intel_load_detect_pipe *old)
6199 {
6200 struct intel_crtc *intel_crtc;
6201 struct drm_crtc *possible_crtc;
6202 struct drm_encoder *encoder = &intel_encoder->base;
6203 struct drm_crtc *crtc = NULL;
6204 struct drm_device *dev = encoder->dev;
6205 struct drm_framebuffer *old_fb;
6206 int i = -1;
6207
6208 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6209 connector->base.id, drm_get_connector_name(connector),
6210 encoder->base.id, drm_get_encoder_name(encoder));
6211
6212 /*
6213 * Algorithm gets a little messy:
6214 *
6215 * - if the connector already has an assigned crtc, use it (but make
6216 * sure it's on first)
6217 *
6218 * - try to find the first unused crtc that can drive this connector,
6219 * and use that if we find one
6220 */
6221
6222 /* See if we already have a CRTC for this connector */
6223 if (encoder->crtc) {
6224 crtc = encoder->crtc;
6225
6226 intel_crtc = to_intel_crtc(crtc);
6227 old->dpms_mode = intel_crtc->dpms_mode;
6228 old->load_detect_temp = false;
6229
6230 /* Make sure the crtc and connector are running */
6231 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6232 struct drm_encoder_helper_funcs *encoder_funcs;
6233 struct drm_crtc_helper_funcs *crtc_funcs;
6234
6235 crtc_funcs = crtc->helper_private;
6236 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6237
6238 encoder_funcs = encoder->helper_private;
6239 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6240 }
6241
6242 return true;
6243 }
6244
6245 /* Find an unused one (if possible) */
6246 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6247 i++;
6248 if (!(encoder->possible_crtcs & (1 << i)))
6249 continue;
6250 if (!possible_crtc->enabled) {
6251 crtc = possible_crtc;
6252 break;
6253 }
6254 }
6255
6256 /*
6257 * If we didn't find an unused CRTC, don't use any.
6258 */
6259 if (!crtc) {
6260 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6261 return false;
6262 }
6263
6264 encoder->crtc = crtc;
6265 connector->encoder = encoder;
6266
6267 intel_crtc = to_intel_crtc(crtc);
6268 old->dpms_mode = intel_crtc->dpms_mode;
6269 old->load_detect_temp = true;
6270 old->release_fb = NULL;
6271
6272 if (!mode)
6273 mode = &load_detect_mode;
6274
6275 old_fb = crtc->fb;
6276
6277 /* We need a framebuffer large enough to accommodate all accesses
6278 * that the plane may generate whilst we perform load detection.
6279 * We can not rely on the fbcon either being present (we get called
6280 * during its initialisation to detect all boot displays, or it may
6281 * not even exist) or that it is large enough to satisfy the
6282 * requested mode.
6283 */
6284 crtc->fb = mode_fits_in_fbdev(dev, mode);
6285 if (crtc->fb == NULL) {
6286 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6287 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6288 old->release_fb = crtc->fb;
6289 } else
6290 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6291 if (IS_ERR(crtc->fb)) {
6292 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6293 crtc->fb = old_fb;
6294 return false;
6295 }
6296
6297 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6298 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6299 if (old->release_fb)
6300 old->release_fb->funcs->destroy(old->release_fb);
6301 crtc->fb = old_fb;
6302 return false;
6303 }
6304
6305 /* let the connector get through one full cycle before testing */
6306 intel_wait_for_vblank(dev, intel_crtc->pipe);
6307
6308 return true;
6309 }
6310
6311 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6312 struct drm_connector *connector,
6313 struct intel_load_detect_pipe *old)
6314 {
6315 struct drm_encoder *encoder = &intel_encoder->base;
6316 struct drm_device *dev = encoder->dev;
6317 struct drm_crtc *crtc = encoder->crtc;
6318 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6319 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6320
6321 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6322 connector->base.id, drm_get_connector_name(connector),
6323 encoder->base.id, drm_get_encoder_name(encoder));
6324
6325 if (old->load_detect_temp) {
6326 connector->encoder = NULL;
6327 drm_helper_disable_unused_functions(dev);
6328
6329 if (old->release_fb)
6330 old->release_fb->funcs->destroy(old->release_fb);
6331
6332 return;
6333 }
6334
6335 /* Switch crtc and encoder back off if necessary */
6336 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6337 encoder_funcs->dpms(encoder, old->dpms_mode);
6338 crtc_funcs->dpms(crtc, old->dpms_mode);
6339 }
6340 }
6341
6342 /* Returns the clock of the currently programmed mode of the given pipe. */
6343 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6344 {
6345 struct drm_i915_private *dev_priv = dev->dev_private;
6346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6347 int pipe = intel_crtc->pipe;
6348 u32 dpll = I915_READ(DPLL(pipe));
6349 u32 fp;
6350 intel_clock_t clock;
6351
6352 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6353 fp = I915_READ(FP0(pipe));
6354 else
6355 fp = I915_READ(FP1(pipe));
6356
6357 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6358 if (IS_PINEVIEW(dev)) {
6359 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6360 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6361 } else {
6362 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6363 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6364 }
6365
6366 if (!IS_GEN2(dev)) {
6367 if (IS_PINEVIEW(dev))
6368 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6369 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6370 else
6371 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6372 DPLL_FPA01_P1_POST_DIV_SHIFT);
6373
6374 switch (dpll & DPLL_MODE_MASK) {
6375 case DPLLB_MODE_DAC_SERIAL:
6376 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6377 5 : 10;
6378 break;
6379 case DPLLB_MODE_LVDS:
6380 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6381 7 : 14;
6382 break;
6383 default:
6384 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6385 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6386 return 0;
6387 }
6388
6389 /* XXX: Handle the 100Mhz refclk */
6390 intel_clock(dev, 96000, &clock);
6391 } else {
6392 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6393
6394 if (is_lvds) {
6395 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6396 DPLL_FPA01_P1_POST_DIV_SHIFT);
6397 clock.p2 = 14;
6398
6399 if ((dpll & PLL_REF_INPUT_MASK) ==
6400 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6401 /* XXX: might not be 66MHz */
6402 intel_clock(dev, 66000, &clock);
6403 } else
6404 intel_clock(dev, 48000, &clock);
6405 } else {
6406 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6407 clock.p1 = 2;
6408 else {
6409 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6410 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6411 }
6412 if (dpll & PLL_P2_DIVIDE_BY_4)
6413 clock.p2 = 4;
6414 else
6415 clock.p2 = 2;
6416
6417 intel_clock(dev, 48000, &clock);
6418 }
6419 }
6420
6421 /* XXX: It would be nice to validate the clocks, but we can't reuse
6422 * i830PllIsValid() because it relies on the xf86_config connector
6423 * configuration being accurate, which it isn't necessarily.
6424 */
6425
6426 return clock.dot;
6427 }
6428
6429 /** Returns the currently programmed mode of the given pipe. */
6430 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6431 struct drm_crtc *crtc)
6432 {
6433 struct drm_i915_private *dev_priv = dev->dev_private;
6434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6435 int pipe = intel_crtc->pipe;
6436 struct drm_display_mode *mode;
6437 int htot = I915_READ(HTOTAL(pipe));
6438 int hsync = I915_READ(HSYNC(pipe));
6439 int vtot = I915_READ(VTOTAL(pipe));
6440 int vsync = I915_READ(VSYNC(pipe));
6441
6442 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6443 if (!mode)
6444 return NULL;
6445
6446 mode->clock = intel_crtc_clock_get(dev, crtc);
6447 mode->hdisplay = (htot & 0xffff) + 1;
6448 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6449 mode->hsync_start = (hsync & 0xffff) + 1;
6450 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6451 mode->vdisplay = (vtot & 0xffff) + 1;
6452 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6453 mode->vsync_start = (vsync & 0xffff) + 1;
6454 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6455
6456 drm_mode_set_name(mode);
6457 drm_mode_set_crtcinfo(mode, 0);
6458
6459 return mode;
6460 }
6461
6462 #define GPU_IDLE_TIMEOUT 500 /* ms */
6463
6464 /* When this timer fires, we've been idle for awhile */
6465 static void intel_gpu_idle_timer(unsigned long arg)
6466 {
6467 struct drm_device *dev = (struct drm_device *)arg;
6468 drm_i915_private_t *dev_priv = dev->dev_private;
6469
6470 if (!list_empty(&dev_priv->mm.active_list)) {
6471 /* Still processing requests, so just re-arm the timer. */
6472 mod_timer(&dev_priv->idle_timer, jiffies +
6473 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6474 return;
6475 }
6476
6477 dev_priv->busy = false;
6478 queue_work(dev_priv->wq, &dev_priv->idle_work);
6479 }
6480
6481 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6482
6483 static void intel_crtc_idle_timer(unsigned long arg)
6484 {
6485 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6486 struct drm_crtc *crtc = &intel_crtc->base;
6487 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6488 struct intel_framebuffer *intel_fb;
6489
6490 intel_fb = to_intel_framebuffer(crtc->fb);
6491 if (intel_fb && intel_fb->obj->active) {
6492 /* The framebuffer is still being accessed by the GPU. */
6493 mod_timer(&intel_crtc->idle_timer, jiffies +
6494 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6495 return;
6496 }
6497
6498 intel_crtc->busy = false;
6499 queue_work(dev_priv->wq, &dev_priv->idle_work);
6500 }
6501
6502 static void intel_increase_pllclock(struct drm_crtc *crtc)
6503 {
6504 struct drm_device *dev = crtc->dev;
6505 drm_i915_private_t *dev_priv = dev->dev_private;
6506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6507 int pipe = intel_crtc->pipe;
6508 int dpll_reg = DPLL(pipe);
6509 int dpll;
6510
6511 if (HAS_PCH_SPLIT(dev))
6512 return;
6513
6514 if (!dev_priv->lvds_downclock_avail)
6515 return;
6516
6517 dpll = I915_READ(dpll_reg);
6518 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6519 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6520
6521 /* Unlock panel regs */
6522 I915_WRITE(PP_CONTROL,
6523 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6524
6525 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6526 I915_WRITE(dpll_reg, dpll);
6527 intel_wait_for_vblank(dev, pipe);
6528
6529 dpll = I915_READ(dpll_reg);
6530 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6531 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6532
6533 /* ...and lock them again */
6534 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6535 }
6536
6537 /* Schedule downclock */
6538 mod_timer(&intel_crtc->idle_timer, jiffies +
6539 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6540 }
6541
6542 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6543 {
6544 struct drm_device *dev = crtc->dev;
6545 drm_i915_private_t *dev_priv = dev->dev_private;
6546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547 int pipe = intel_crtc->pipe;
6548 int dpll_reg = DPLL(pipe);
6549 int dpll = I915_READ(dpll_reg);
6550
6551 if (HAS_PCH_SPLIT(dev))
6552 return;
6553
6554 if (!dev_priv->lvds_downclock_avail)
6555 return;
6556
6557 /*
6558 * Since this is called by a timer, we should never get here in
6559 * the manual case.
6560 */
6561 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6562 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6563
6564 /* Unlock panel regs */
6565 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6566 PANEL_UNLOCK_REGS);
6567
6568 dpll |= DISPLAY_RATE_SELECT_FPA1;
6569 I915_WRITE(dpll_reg, dpll);
6570 intel_wait_for_vblank(dev, pipe);
6571 dpll = I915_READ(dpll_reg);
6572 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6573 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6574
6575 /* ...and lock them again */
6576 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6577 }
6578
6579 }
6580
6581 /**
6582 * intel_idle_update - adjust clocks for idleness
6583 * @work: work struct
6584 *
6585 * Either the GPU or display (or both) went idle. Check the busy status
6586 * here and adjust the CRTC and GPU clocks as necessary.
6587 */
6588 static void intel_idle_update(struct work_struct *work)
6589 {
6590 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6591 idle_work);
6592 struct drm_device *dev = dev_priv->dev;
6593 struct drm_crtc *crtc;
6594 struct intel_crtc *intel_crtc;
6595
6596 if (!i915_powersave)
6597 return;
6598
6599 mutex_lock(&dev->struct_mutex);
6600
6601 i915_update_gfx_val(dev_priv);
6602
6603 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6604 /* Skip inactive CRTCs */
6605 if (!crtc->fb)
6606 continue;
6607
6608 intel_crtc = to_intel_crtc(crtc);
6609 if (!intel_crtc->busy)
6610 intel_decrease_pllclock(crtc);
6611 }
6612
6613
6614 mutex_unlock(&dev->struct_mutex);
6615 }
6616
6617 /**
6618 * intel_mark_busy - mark the GPU and possibly the display busy
6619 * @dev: drm device
6620 * @obj: object we're operating on
6621 *
6622 * Callers can use this function to indicate that the GPU is busy processing
6623 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6624 * buffer), we'll also mark the display as busy, so we know to increase its
6625 * clock frequency.
6626 */
6627 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6628 {
6629 drm_i915_private_t *dev_priv = dev->dev_private;
6630 struct drm_crtc *crtc = NULL;
6631 struct intel_framebuffer *intel_fb;
6632 struct intel_crtc *intel_crtc;
6633
6634 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6635 return;
6636
6637 if (!dev_priv->busy)
6638 dev_priv->busy = true;
6639 else
6640 mod_timer(&dev_priv->idle_timer, jiffies +
6641 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6642
6643 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6644 if (!crtc->fb)
6645 continue;
6646
6647 intel_crtc = to_intel_crtc(crtc);
6648 intel_fb = to_intel_framebuffer(crtc->fb);
6649 if (intel_fb->obj == obj) {
6650 if (!intel_crtc->busy) {
6651 /* Non-busy -> busy, upclock */
6652 intel_increase_pllclock(crtc);
6653 intel_crtc->busy = true;
6654 } else {
6655 /* Busy -> busy, put off timer */
6656 mod_timer(&intel_crtc->idle_timer, jiffies +
6657 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6658 }
6659 }
6660 }
6661 }
6662
6663 static void intel_crtc_destroy(struct drm_crtc *crtc)
6664 {
6665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6666 struct drm_device *dev = crtc->dev;
6667 struct intel_unpin_work *work;
6668 unsigned long flags;
6669
6670 spin_lock_irqsave(&dev->event_lock, flags);
6671 work = intel_crtc->unpin_work;
6672 intel_crtc->unpin_work = NULL;
6673 spin_unlock_irqrestore(&dev->event_lock, flags);
6674
6675 if (work) {
6676 cancel_work_sync(&work->work);
6677 kfree(work);
6678 }
6679
6680 drm_crtc_cleanup(crtc);
6681
6682 kfree(intel_crtc);
6683 }
6684
6685 static void intel_unpin_work_fn(struct work_struct *__work)
6686 {
6687 struct intel_unpin_work *work =
6688 container_of(__work, struct intel_unpin_work, work);
6689
6690 mutex_lock(&work->dev->struct_mutex);
6691 i915_gem_object_unpin(work->old_fb_obj);
6692 drm_gem_object_unreference(&work->pending_flip_obj->base);
6693 drm_gem_object_unreference(&work->old_fb_obj->base);
6694
6695 intel_update_fbc(work->dev);
6696 mutex_unlock(&work->dev->struct_mutex);
6697 kfree(work);
6698 }
6699
6700 static void do_intel_finish_page_flip(struct drm_device *dev,
6701 struct drm_crtc *crtc)
6702 {
6703 drm_i915_private_t *dev_priv = dev->dev_private;
6704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6705 struct intel_unpin_work *work;
6706 struct drm_i915_gem_object *obj;
6707 struct drm_pending_vblank_event *e;
6708 struct timeval tnow, tvbl;
6709 unsigned long flags;
6710
6711 /* Ignore early vblank irqs */
6712 if (intel_crtc == NULL)
6713 return;
6714
6715 do_gettimeofday(&tnow);
6716
6717 spin_lock_irqsave(&dev->event_lock, flags);
6718 work = intel_crtc->unpin_work;
6719 if (work == NULL || !work->pending) {
6720 spin_unlock_irqrestore(&dev->event_lock, flags);
6721 return;
6722 }
6723
6724 intel_crtc->unpin_work = NULL;
6725
6726 if (work->event) {
6727 e = work->event;
6728 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6729
6730 /* Called before vblank count and timestamps have
6731 * been updated for the vblank interval of flip
6732 * completion? Need to increment vblank count and
6733 * add one videorefresh duration to returned timestamp
6734 * to account for this. We assume this happened if we
6735 * get called over 0.9 frame durations after the last
6736 * timestamped vblank.
6737 *
6738 * This calculation can not be used with vrefresh rates
6739 * below 5Hz (10Hz to be on the safe side) without
6740 * promoting to 64 integers.
6741 */
6742 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6743 9 * crtc->framedur_ns) {
6744 e->event.sequence++;
6745 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6746 crtc->framedur_ns);
6747 }
6748
6749 e->event.tv_sec = tvbl.tv_sec;
6750 e->event.tv_usec = tvbl.tv_usec;
6751
6752 list_add_tail(&e->base.link,
6753 &e->base.file_priv->event_list);
6754 wake_up_interruptible(&e->base.file_priv->event_wait);
6755 }
6756
6757 drm_vblank_put(dev, intel_crtc->pipe);
6758
6759 spin_unlock_irqrestore(&dev->event_lock, flags);
6760
6761 obj = work->old_fb_obj;
6762
6763 atomic_clear_mask(1 << intel_crtc->plane,
6764 &obj->pending_flip.counter);
6765 if (atomic_read(&obj->pending_flip) == 0)
6766 wake_up(&dev_priv->pending_flip_queue);
6767
6768 schedule_work(&work->work);
6769
6770 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6771 }
6772
6773 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6774 {
6775 drm_i915_private_t *dev_priv = dev->dev_private;
6776 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6777
6778 do_intel_finish_page_flip(dev, crtc);
6779 }
6780
6781 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6782 {
6783 drm_i915_private_t *dev_priv = dev->dev_private;
6784 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6785
6786 do_intel_finish_page_flip(dev, crtc);
6787 }
6788
6789 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6790 {
6791 drm_i915_private_t *dev_priv = dev->dev_private;
6792 struct intel_crtc *intel_crtc =
6793 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6794 unsigned long flags;
6795
6796 spin_lock_irqsave(&dev->event_lock, flags);
6797 if (intel_crtc->unpin_work) {
6798 if ((++intel_crtc->unpin_work->pending) > 1)
6799 DRM_ERROR("Prepared flip multiple times\n");
6800 } else {
6801 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6802 }
6803 spin_unlock_irqrestore(&dev->event_lock, flags);
6804 }
6805
6806 static int intel_gen2_queue_flip(struct drm_device *dev,
6807 struct drm_crtc *crtc,
6808 struct drm_framebuffer *fb,
6809 struct drm_i915_gem_object *obj)
6810 {
6811 struct drm_i915_private *dev_priv = dev->dev_private;
6812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6813 unsigned long offset;
6814 u32 flip_mask;
6815 int ret;
6816
6817 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6818 if (ret)
6819 goto out;
6820
6821 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6822 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6823
6824 ret = BEGIN_LP_RING(6);
6825 if (ret)
6826 goto out;
6827
6828 /* Can't queue multiple flips, so wait for the previous
6829 * one to finish before executing the next.
6830 */
6831 if (intel_crtc->plane)
6832 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6833 else
6834 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6835 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6836 OUT_RING(MI_NOOP);
6837 OUT_RING(MI_DISPLAY_FLIP |
6838 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6839 OUT_RING(fb->pitch);
6840 OUT_RING(obj->gtt_offset + offset);
6841 OUT_RING(MI_NOOP);
6842 ADVANCE_LP_RING();
6843 out:
6844 return ret;
6845 }
6846
6847 static int intel_gen3_queue_flip(struct drm_device *dev,
6848 struct drm_crtc *crtc,
6849 struct drm_framebuffer *fb,
6850 struct drm_i915_gem_object *obj)
6851 {
6852 struct drm_i915_private *dev_priv = dev->dev_private;
6853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6854 unsigned long offset;
6855 u32 flip_mask;
6856 int ret;
6857
6858 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6859 if (ret)
6860 goto out;
6861
6862 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6863 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6864
6865 ret = BEGIN_LP_RING(6);
6866 if (ret)
6867 goto out;
6868
6869 if (intel_crtc->plane)
6870 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6871 else
6872 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6873 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6874 OUT_RING(MI_NOOP);
6875 OUT_RING(MI_DISPLAY_FLIP_I915 |
6876 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6877 OUT_RING(fb->pitch);
6878 OUT_RING(obj->gtt_offset + offset);
6879 OUT_RING(MI_NOOP);
6880
6881 ADVANCE_LP_RING();
6882 out:
6883 return ret;
6884 }
6885
6886 static int intel_gen4_queue_flip(struct drm_device *dev,
6887 struct drm_crtc *crtc,
6888 struct drm_framebuffer *fb,
6889 struct drm_i915_gem_object *obj)
6890 {
6891 struct drm_i915_private *dev_priv = dev->dev_private;
6892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6893 uint32_t pf, pipesrc;
6894 int ret;
6895
6896 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6897 if (ret)
6898 goto out;
6899
6900 ret = BEGIN_LP_RING(4);
6901 if (ret)
6902 goto out;
6903
6904 /* i965+ uses the linear or tiled offsets from the
6905 * Display Registers (which do not change across a page-flip)
6906 * so we need only reprogram the base address.
6907 */
6908 OUT_RING(MI_DISPLAY_FLIP |
6909 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6910 OUT_RING(fb->pitch);
6911 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6912
6913 /* XXX Enabling the panel-fitter across page-flip is so far
6914 * untested on non-native modes, so ignore it for now.
6915 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6916 */
6917 pf = 0;
6918 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6919 OUT_RING(pf | pipesrc);
6920 ADVANCE_LP_RING();
6921 out:
6922 return ret;
6923 }
6924
6925 static int intel_gen6_queue_flip(struct drm_device *dev,
6926 struct drm_crtc *crtc,
6927 struct drm_framebuffer *fb,
6928 struct drm_i915_gem_object *obj)
6929 {
6930 struct drm_i915_private *dev_priv = dev->dev_private;
6931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6932 uint32_t pf, pipesrc;
6933 int ret;
6934
6935 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6936 if (ret)
6937 goto out;
6938
6939 ret = BEGIN_LP_RING(4);
6940 if (ret)
6941 goto out;
6942
6943 OUT_RING(MI_DISPLAY_FLIP |
6944 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6945 OUT_RING(fb->pitch | obj->tiling_mode);
6946 OUT_RING(obj->gtt_offset);
6947
6948 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6949 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6950 OUT_RING(pf | pipesrc);
6951 ADVANCE_LP_RING();
6952 out:
6953 return ret;
6954 }
6955
6956 /*
6957 * On gen7 we currently use the blit ring because (in early silicon at least)
6958 * the render ring doesn't give us interrpts for page flip completion, which
6959 * means clients will hang after the first flip is queued. Fortunately the
6960 * blit ring generates interrupts properly, so use it instead.
6961 */
6962 static int intel_gen7_queue_flip(struct drm_device *dev,
6963 struct drm_crtc *crtc,
6964 struct drm_framebuffer *fb,
6965 struct drm_i915_gem_object *obj)
6966 {
6967 struct drm_i915_private *dev_priv = dev->dev_private;
6968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6969 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6970 int ret;
6971
6972 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6973 if (ret)
6974 goto out;
6975
6976 ret = intel_ring_begin(ring, 4);
6977 if (ret)
6978 goto out;
6979
6980 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6981 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6982 intel_ring_emit(ring, (obj->gtt_offset));
6983 intel_ring_emit(ring, (MI_NOOP));
6984 intel_ring_advance(ring);
6985 out:
6986 return ret;
6987 }
6988
6989 static int intel_default_queue_flip(struct drm_device *dev,
6990 struct drm_crtc *crtc,
6991 struct drm_framebuffer *fb,
6992 struct drm_i915_gem_object *obj)
6993 {
6994 return -ENODEV;
6995 }
6996
6997 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6998 struct drm_framebuffer *fb,
6999 struct drm_pending_vblank_event *event)
7000 {
7001 struct drm_device *dev = crtc->dev;
7002 struct drm_i915_private *dev_priv = dev->dev_private;
7003 struct intel_framebuffer *intel_fb;
7004 struct drm_i915_gem_object *obj;
7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7006 struct intel_unpin_work *work;
7007 unsigned long flags;
7008 int ret;
7009
7010 work = kzalloc(sizeof *work, GFP_KERNEL);
7011 if (work == NULL)
7012 return -ENOMEM;
7013
7014 work->event = event;
7015 work->dev = crtc->dev;
7016 intel_fb = to_intel_framebuffer(crtc->fb);
7017 work->old_fb_obj = intel_fb->obj;
7018 INIT_WORK(&work->work, intel_unpin_work_fn);
7019
7020 /* We borrow the event spin lock for protecting unpin_work */
7021 spin_lock_irqsave(&dev->event_lock, flags);
7022 if (intel_crtc->unpin_work) {
7023 spin_unlock_irqrestore(&dev->event_lock, flags);
7024 kfree(work);
7025
7026 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7027 return -EBUSY;
7028 }
7029 intel_crtc->unpin_work = work;
7030 spin_unlock_irqrestore(&dev->event_lock, flags);
7031
7032 intel_fb = to_intel_framebuffer(fb);
7033 obj = intel_fb->obj;
7034
7035 mutex_lock(&dev->struct_mutex);
7036
7037 /* Reference the objects for the scheduled work. */
7038 drm_gem_object_reference(&work->old_fb_obj->base);
7039 drm_gem_object_reference(&obj->base);
7040
7041 crtc->fb = fb;
7042
7043 ret = drm_vblank_get(dev, intel_crtc->pipe);
7044 if (ret)
7045 goto cleanup_objs;
7046
7047 work->pending_flip_obj = obj;
7048
7049 work->enable_stall_check = true;
7050
7051 /* Block clients from rendering to the new back buffer until
7052 * the flip occurs and the object is no longer visible.
7053 */
7054 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7055
7056 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7057 if (ret)
7058 goto cleanup_pending;
7059
7060 intel_disable_fbc(dev);
7061 mutex_unlock(&dev->struct_mutex);
7062
7063 trace_i915_flip_request(intel_crtc->plane, obj);
7064
7065 return 0;
7066
7067 cleanup_pending:
7068 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7069 cleanup_objs:
7070 drm_gem_object_unreference(&work->old_fb_obj->base);
7071 drm_gem_object_unreference(&obj->base);
7072 mutex_unlock(&dev->struct_mutex);
7073
7074 spin_lock_irqsave(&dev->event_lock, flags);
7075 intel_crtc->unpin_work = NULL;
7076 spin_unlock_irqrestore(&dev->event_lock, flags);
7077
7078 kfree(work);
7079
7080 return ret;
7081 }
7082
7083 static void intel_sanitize_modesetting(struct drm_device *dev,
7084 int pipe, int plane)
7085 {
7086 struct drm_i915_private *dev_priv = dev->dev_private;
7087 u32 reg, val;
7088
7089 if (HAS_PCH_SPLIT(dev))
7090 return;
7091
7092 /* Who knows what state these registers were left in by the BIOS or
7093 * grub?
7094 *
7095 * If we leave the registers in a conflicting state (e.g. with the
7096 * display plane reading from the other pipe than the one we intend
7097 * to use) then when we attempt to teardown the active mode, we will
7098 * not disable the pipes and planes in the correct order -- leaving
7099 * a plane reading from a disabled pipe and possibly leading to
7100 * undefined behaviour.
7101 */
7102
7103 reg = DSPCNTR(plane);
7104 val = I915_READ(reg);
7105
7106 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7107 return;
7108 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7109 return;
7110
7111 /* This display plane is active and attached to the other CPU pipe. */
7112 pipe = !pipe;
7113
7114 /* Disable the plane and wait for it to stop reading from the pipe. */
7115 intel_disable_plane(dev_priv, plane, pipe);
7116 intel_disable_pipe(dev_priv, pipe);
7117 }
7118
7119 static void intel_crtc_reset(struct drm_crtc *crtc)
7120 {
7121 struct drm_device *dev = crtc->dev;
7122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7123
7124 /* Reset flags back to the 'unknown' status so that they
7125 * will be correctly set on the initial modeset.
7126 */
7127 intel_crtc->dpms_mode = -1;
7128
7129 /* We need to fix up any BIOS configuration that conflicts with
7130 * our expectations.
7131 */
7132 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7133 }
7134
7135 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7136 .dpms = intel_crtc_dpms,
7137 .mode_fixup = intel_crtc_mode_fixup,
7138 .mode_set = intel_crtc_mode_set,
7139 .mode_set_base = intel_pipe_set_base,
7140 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7141 .load_lut = intel_crtc_load_lut,
7142 .disable = intel_crtc_disable,
7143 };
7144
7145 static const struct drm_crtc_funcs intel_crtc_funcs = {
7146 .reset = intel_crtc_reset,
7147 .cursor_set = intel_crtc_cursor_set,
7148 .cursor_move = intel_crtc_cursor_move,
7149 .gamma_set = intel_crtc_gamma_set,
7150 .set_config = drm_crtc_helper_set_config,
7151 .destroy = intel_crtc_destroy,
7152 .page_flip = intel_crtc_page_flip,
7153 };
7154
7155 static void intel_crtc_init(struct drm_device *dev, int pipe)
7156 {
7157 drm_i915_private_t *dev_priv = dev->dev_private;
7158 struct intel_crtc *intel_crtc;
7159 int i;
7160
7161 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7162 if (intel_crtc == NULL)
7163 return;
7164
7165 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7166
7167 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7168 for (i = 0; i < 256; i++) {
7169 intel_crtc->lut_r[i] = i;
7170 intel_crtc->lut_g[i] = i;
7171 intel_crtc->lut_b[i] = i;
7172 }
7173
7174 /* Swap pipes & planes for FBC on pre-965 */
7175 intel_crtc->pipe = pipe;
7176 intel_crtc->plane = pipe;
7177 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7178 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7179 intel_crtc->plane = !pipe;
7180 }
7181
7182 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7183 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7184 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7185 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7186
7187 intel_crtc_reset(&intel_crtc->base);
7188 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7189 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7190
7191 if (HAS_PCH_SPLIT(dev)) {
7192 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7193 intel_helper_funcs.commit = ironlake_crtc_commit;
7194 } else {
7195 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7196 intel_helper_funcs.commit = i9xx_crtc_commit;
7197 }
7198
7199 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7200
7201 intel_crtc->busy = false;
7202
7203 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7204 (unsigned long)intel_crtc);
7205 }
7206
7207 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7208 struct drm_file *file)
7209 {
7210 drm_i915_private_t *dev_priv = dev->dev_private;
7211 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7212 struct drm_mode_object *drmmode_obj;
7213 struct intel_crtc *crtc;
7214
7215 if (!dev_priv) {
7216 DRM_ERROR("called with no initialization\n");
7217 return -EINVAL;
7218 }
7219
7220 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7221 DRM_MODE_OBJECT_CRTC);
7222
7223 if (!drmmode_obj) {
7224 DRM_ERROR("no such CRTC id\n");
7225 return -EINVAL;
7226 }
7227
7228 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7229 pipe_from_crtc_id->pipe = crtc->pipe;
7230
7231 return 0;
7232 }
7233
7234 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7235 {
7236 struct intel_encoder *encoder;
7237 int index_mask = 0;
7238 int entry = 0;
7239
7240 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7241 if (type_mask & encoder->clone_mask)
7242 index_mask |= (1 << entry);
7243 entry++;
7244 }
7245
7246 return index_mask;
7247 }
7248
7249 static bool has_edp_a(struct drm_device *dev)
7250 {
7251 struct drm_i915_private *dev_priv = dev->dev_private;
7252
7253 if (!IS_MOBILE(dev))
7254 return false;
7255
7256 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7257 return false;
7258
7259 if (IS_GEN5(dev) &&
7260 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7261 return false;
7262
7263 return true;
7264 }
7265
7266 static void intel_setup_outputs(struct drm_device *dev)
7267 {
7268 struct drm_i915_private *dev_priv = dev->dev_private;
7269 struct intel_encoder *encoder;
7270 bool dpd_is_edp = false;
7271 bool has_lvds = false;
7272
7273 if (IS_MOBILE(dev) && !IS_I830(dev))
7274 has_lvds = intel_lvds_init(dev);
7275 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7276 /* disable the panel fitter on everything but LVDS */
7277 I915_WRITE(PFIT_CONTROL, 0);
7278 }
7279
7280 if (HAS_PCH_SPLIT(dev)) {
7281 dpd_is_edp = intel_dpd_is_edp(dev);
7282
7283 if (has_edp_a(dev))
7284 intel_dp_init(dev, DP_A);
7285
7286 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7287 intel_dp_init(dev, PCH_DP_D);
7288 }
7289
7290 intel_crt_init(dev);
7291
7292 if (HAS_PCH_SPLIT(dev)) {
7293 int found;
7294
7295 if (I915_READ(HDMIB) & PORT_DETECTED) {
7296 /* PCH SDVOB multiplex with HDMIB */
7297 found = intel_sdvo_init(dev, PCH_SDVOB);
7298 if (!found)
7299 intel_hdmi_init(dev, HDMIB);
7300 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7301 intel_dp_init(dev, PCH_DP_B);
7302 }
7303
7304 if (I915_READ(HDMIC) & PORT_DETECTED)
7305 intel_hdmi_init(dev, HDMIC);
7306
7307 if (I915_READ(HDMID) & PORT_DETECTED)
7308 intel_hdmi_init(dev, HDMID);
7309
7310 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7311 intel_dp_init(dev, PCH_DP_C);
7312
7313 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7314 intel_dp_init(dev, PCH_DP_D);
7315
7316 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7317 bool found = false;
7318
7319 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7320 DRM_DEBUG_KMS("probing SDVOB\n");
7321 found = intel_sdvo_init(dev, SDVOB);
7322 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7323 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7324 intel_hdmi_init(dev, SDVOB);
7325 }
7326
7327 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7328 DRM_DEBUG_KMS("probing DP_B\n");
7329 intel_dp_init(dev, DP_B);
7330 }
7331 }
7332
7333 /* Before G4X SDVOC doesn't have its own detect register */
7334
7335 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7336 DRM_DEBUG_KMS("probing SDVOC\n");
7337 found = intel_sdvo_init(dev, SDVOC);
7338 }
7339
7340 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7341
7342 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7343 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7344 intel_hdmi_init(dev, SDVOC);
7345 }
7346 if (SUPPORTS_INTEGRATED_DP(dev)) {
7347 DRM_DEBUG_KMS("probing DP_C\n");
7348 intel_dp_init(dev, DP_C);
7349 }
7350 }
7351
7352 if (SUPPORTS_INTEGRATED_DP(dev) &&
7353 (I915_READ(DP_D) & DP_DETECTED)) {
7354 DRM_DEBUG_KMS("probing DP_D\n");
7355 intel_dp_init(dev, DP_D);
7356 }
7357 } else if (IS_GEN2(dev))
7358 intel_dvo_init(dev);
7359
7360 if (SUPPORTS_TV(dev))
7361 intel_tv_init(dev);
7362
7363 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7364 encoder->base.possible_crtcs = encoder->crtc_mask;
7365 encoder->base.possible_clones =
7366 intel_encoder_clones(dev, encoder->clone_mask);
7367 }
7368
7369 /* disable all the possible outputs/crtcs before entering KMS mode */
7370 drm_helper_disable_unused_functions(dev);
7371 }
7372
7373 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7374 {
7375 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7376
7377 drm_framebuffer_cleanup(fb);
7378 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7379
7380 kfree(intel_fb);
7381 }
7382
7383 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7384 struct drm_file *file,
7385 unsigned int *handle)
7386 {
7387 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7388 struct drm_i915_gem_object *obj = intel_fb->obj;
7389
7390 return drm_gem_handle_create(file, &obj->base, handle);
7391 }
7392
7393 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7394 .destroy = intel_user_framebuffer_destroy,
7395 .create_handle = intel_user_framebuffer_create_handle,
7396 };
7397
7398 int intel_framebuffer_init(struct drm_device *dev,
7399 struct intel_framebuffer *intel_fb,
7400 struct drm_mode_fb_cmd *mode_cmd,
7401 struct drm_i915_gem_object *obj)
7402 {
7403 int ret;
7404
7405 if (obj->tiling_mode == I915_TILING_Y)
7406 return -EINVAL;
7407
7408 if (mode_cmd->pitch & 63)
7409 return -EINVAL;
7410
7411 switch (mode_cmd->bpp) {
7412 case 8:
7413 case 16:
7414 /* Only pre-ILK can handle 5:5:5 */
7415 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7416 return -EINVAL;
7417 break;
7418
7419 case 24:
7420 case 32:
7421 break;
7422 default:
7423 return -EINVAL;
7424 }
7425
7426 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7427 if (ret) {
7428 DRM_ERROR("framebuffer init failed %d\n", ret);
7429 return ret;
7430 }
7431
7432 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7433 intel_fb->obj = obj;
7434 return 0;
7435 }
7436
7437 static struct drm_framebuffer *
7438 intel_user_framebuffer_create(struct drm_device *dev,
7439 struct drm_file *filp,
7440 struct drm_mode_fb_cmd *mode_cmd)
7441 {
7442 struct drm_i915_gem_object *obj;
7443
7444 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7445 if (&obj->base == NULL)
7446 return ERR_PTR(-ENOENT);
7447
7448 return intel_framebuffer_create(dev, mode_cmd, obj);
7449 }
7450
7451 static const struct drm_mode_config_funcs intel_mode_funcs = {
7452 .fb_create = intel_user_framebuffer_create,
7453 .output_poll_changed = intel_fb_output_poll_changed,
7454 };
7455
7456 static struct drm_i915_gem_object *
7457 intel_alloc_context_page(struct drm_device *dev)
7458 {
7459 struct drm_i915_gem_object *ctx;
7460 int ret;
7461
7462 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7463
7464 ctx = i915_gem_alloc_object(dev, 4096);
7465 if (!ctx) {
7466 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7467 return NULL;
7468 }
7469
7470 ret = i915_gem_object_pin(ctx, 4096, true);
7471 if (ret) {
7472 DRM_ERROR("failed to pin power context: %d\n", ret);
7473 goto err_unref;
7474 }
7475
7476 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7477 if (ret) {
7478 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7479 goto err_unpin;
7480 }
7481
7482 return ctx;
7483
7484 err_unpin:
7485 i915_gem_object_unpin(ctx);
7486 err_unref:
7487 drm_gem_object_unreference(&ctx->base);
7488 mutex_unlock(&dev->struct_mutex);
7489 return NULL;
7490 }
7491
7492 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7493 {
7494 struct drm_i915_private *dev_priv = dev->dev_private;
7495 u16 rgvswctl;
7496
7497 rgvswctl = I915_READ16(MEMSWCTL);
7498 if (rgvswctl & MEMCTL_CMD_STS) {
7499 DRM_DEBUG("gpu busy, RCS change rejected\n");
7500 return false; /* still busy with another command */
7501 }
7502
7503 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7504 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7505 I915_WRITE16(MEMSWCTL, rgvswctl);
7506 POSTING_READ16(MEMSWCTL);
7507
7508 rgvswctl |= MEMCTL_CMD_STS;
7509 I915_WRITE16(MEMSWCTL, rgvswctl);
7510
7511 return true;
7512 }
7513
7514 void ironlake_enable_drps(struct drm_device *dev)
7515 {
7516 struct drm_i915_private *dev_priv = dev->dev_private;
7517 u32 rgvmodectl = I915_READ(MEMMODECTL);
7518 u8 fmax, fmin, fstart, vstart;
7519
7520 /* Enable temp reporting */
7521 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7522 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7523
7524 /* 100ms RC evaluation intervals */
7525 I915_WRITE(RCUPEI, 100000);
7526 I915_WRITE(RCDNEI, 100000);
7527
7528 /* Set max/min thresholds to 90ms and 80ms respectively */
7529 I915_WRITE(RCBMAXAVG, 90000);
7530 I915_WRITE(RCBMINAVG, 80000);
7531
7532 I915_WRITE(MEMIHYST, 1);
7533
7534 /* Set up min, max, and cur for interrupt handling */
7535 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7536 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7537 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7538 MEMMODE_FSTART_SHIFT;
7539
7540 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7541 PXVFREQ_PX_SHIFT;
7542
7543 dev_priv->fmax = fmax; /* IPS callback will increase this */
7544 dev_priv->fstart = fstart;
7545
7546 dev_priv->max_delay = fstart;
7547 dev_priv->min_delay = fmin;
7548 dev_priv->cur_delay = fstart;
7549
7550 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7551 fmax, fmin, fstart);
7552
7553 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7554
7555 /*
7556 * Interrupts will be enabled in ironlake_irq_postinstall
7557 */
7558
7559 I915_WRITE(VIDSTART, vstart);
7560 POSTING_READ(VIDSTART);
7561
7562 rgvmodectl |= MEMMODE_SWMODE_EN;
7563 I915_WRITE(MEMMODECTL, rgvmodectl);
7564
7565 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7566 DRM_ERROR("stuck trying to change perf mode\n");
7567 msleep(1);
7568
7569 ironlake_set_drps(dev, fstart);
7570
7571 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7572 I915_READ(0x112e0);
7573 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7574 dev_priv->last_count2 = I915_READ(0x112f4);
7575 getrawmonotonic(&dev_priv->last_time2);
7576 }
7577
7578 void ironlake_disable_drps(struct drm_device *dev)
7579 {
7580 struct drm_i915_private *dev_priv = dev->dev_private;
7581 u16 rgvswctl = I915_READ16(MEMSWCTL);
7582
7583 /* Ack interrupts, disable EFC interrupt */
7584 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7585 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7586 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7587 I915_WRITE(DEIIR, DE_PCU_EVENT);
7588 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7589
7590 /* Go back to the starting frequency */
7591 ironlake_set_drps(dev, dev_priv->fstart);
7592 msleep(1);
7593 rgvswctl |= MEMCTL_CMD_STS;
7594 I915_WRITE(MEMSWCTL, rgvswctl);
7595 msleep(1);
7596
7597 }
7598
7599 void gen6_set_rps(struct drm_device *dev, u8 val)
7600 {
7601 struct drm_i915_private *dev_priv = dev->dev_private;
7602 u32 swreq;
7603
7604 swreq = (val & 0x3ff) << 25;
7605 I915_WRITE(GEN6_RPNSWREQ, swreq);
7606 }
7607
7608 void gen6_disable_rps(struct drm_device *dev)
7609 {
7610 struct drm_i915_private *dev_priv = dev->dev_private;
7611
7612 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7613 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7614 I915_WRITE(GEN6_PMIER, 0);
7615
7616 spin_lock_irq(&dev_priv->rps_lock);
7617 dev_priv->pm_iir = 0;
7618 spin_unlock_irq(&dev_priv->rps_lock);
7619
7620 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7621 }
7622
7623 static unsigned long intel_pxfreq(u32 vidfreq)
7624 {
7625 unsigned long freq;
7626 int div = (vidfreq & 0x3f0000) >> 16;
7627 int post = (vidfreq & 0x3000) >> 12;
7628 int pre = (vidfreq & 0x7);
7629
7630 if (!pre)
7631 return 0;
7632
7633 freq = ((div * 133333) / ((1<<post) * pre));
7634
7635 return freq;
7636 }
7637
7638 void intel_init_emon(struct drm_device *dev)
7639 {
7640 struct drm_i915_private *dev_priv = dev->dev_private;
7641 u32 lcfuse;
7642 u8 pxw[16];
7643 int i;
7644
7645 /* Disable to program */
7646 I915_WRITE(ECR, 0);
7647 POSTING_READ(ECR);
7648
7649 /* Program energy weights for various events */
7650 I915_WRITE(SDEW, 0x15040d00);
7651 I915_WRITE(CSIEW0, 0x007f0000);
7652 I915_WRITE(CSIEW1, 0x1e220004);
7653 I915_WRITE(CSIEW2, 0x04000004);
7654
7655 for (i = 0; i < 5; i++)
7656 I915_WRITE(PEW + (i * 4), 0);
7657 for (i = 0; i < 3; i++)
7658 I915_WRITE(DEW + (i * 4), 0);
7659
7660 /* Program P-state weights to account for frequency power adjustment */
7661 for (i = 0; i < 16; i++) {
7662 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7663 unsigned long freq = intel_pxfreq(pxvidfreq);
7664 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7665 PXVFREQ_PX_SHIFT;
7666 unsigned long val;
7667
7668 val = vid * vid;
7669 val *= (freq / 1000);
7670 val *= 255;
7671 val /= (127*127*900);
7672 if (val > 0xff)
7673 DRM_ERROR("bad pxval: %ld\n", val);
7674 pxw[i] = val;
7675 }
7676 /* Render standby states get 0 weight */
7677 pxw[14] = 0;
7678 pxw[15] = 0;
7679
7680 for (i = 0; i < 4; i++) {
7681 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7682 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7683 I915_WRITE(PXW + (i * 4), val);
7684 }
7685
7686 /* Adjust magic regs to magic values (more experimental results) */
7687 I915_WRITE(OGW0, 0);
7688 I915_WRITE(OGW1, 0);
7689 I915_WRITE(EG0, 0x00007f00);
7690 I915_WRITE(EG1, 0x0000000e);
7691 I915_WRITE(EG2, 0x000e0000);
7692 I915_WRITE(EG3, 0x68000300);
7693 I915_WRITE(EG4, 0x42000000);
7694 I915_WRITE(EG5, 0x00140031);
7695 I915_WRITE(EG6, 0);
7696 I915_WRITE(EG7, 0);
7697
7698 for (i = 0; i < 8; i++)
7699 I915_WRITE(PXWL + (i * 4), 0);
7700
7701 /* Enable PMON + select events */
7702 I915_WRITE(ECR, 0x80000019);
7703
7704 lcfuse = I915_READ(LCFUSE02);
7705
7706 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7707 }
7708
7709 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7710 {
7711 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7712 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7713 u32 pcu_mbox, rc6_mask = 0;
7714 int cur_freq, min_freq, max_freq;
7715 int i;
7716
7717 /* Here begins a magic sequence of register writes to enable
7718 * auto-downclocking.
7719 *
7720 * Perhaps there might be some value in exposing these to
7721 * userspace...
7722 */
7723 I915_WRITE(GEN6_RC_STATE, 0);
7724 mutex_lock(&dev_priv->dev->struct_mutex);
7725 gen6_gt_force_wake_get(dev_priv);
7726
7727 /* disable the counters and set deterministic thresholds */
7728 I915_WRITE(GEN6_RC_CONTROL, 0);
7729
7730 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7731 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7732 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7733 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7734 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7735
7736 for (i = 0; i < I915_NUM_RINGS; i++)
7737 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7738
7739 I915_WRITE(GEN6_RC_SLEEP, 0);
7740 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7741 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7742 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7743 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7744
7745 if (i915_enable_rc6)
7746 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7747 GEN6_RC_CTL_RC6_ENABLE;
7748
7749 I915_WRITE(GEN6_RC_CONTROL,
7750 rc6_mask |
7751 GEN6_RC_CTL_EI_MODE(1) |
7752 GEN6_RC_CTL_HW_ENABLE);
7753
7754 I915_WRITE(GEN6_RPNSWREQ,
7755 GEN6_FREQUENCY(10) |
7756 GEN6_OFFSET(0) |
7757 GEN6_AGGRESSIVE_TURBO);
7758 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7759 GEN6_FREQUENCY(12));
7760
7761 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7762 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7763 18 << 24 |
7764 6 << 16);
7765 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7766 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7767 I915_WRITE(GEN6_RP_UP_EI, 100000);
7768 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7769 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7770 I915_WRITE(GEN6_RP_CONTROL,
7771 GEN6_RP_MEDIA_TURBO |
7772 GEN6_RP_USE_NORMAL_FREQ |
7773 GEN6_RP_MEDIA_IS_GFX |
7774 GEN6_RP_ENABLE |
7775 GEN6_RP_UP_BUSY_AVG |
7776 GEN6_RP_DOWN_IDLE_CONT);
7777
7778 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7779 500))
7780 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7781
7782 I915_WRITE(GEN6_PCODE_DATA, 0);
7783 I915_WRITE(GEN6_PCODE_MAILBOX,
7784 GEN6_PCODE_READY |
7785 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7786 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7787 500))
7788 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7789
7790 min_freq = (rp_state_cap & 0xff0000) >> 16;
7791 max_freq = rp_state_cap & 0xff;
7792 cur_freq = (gt_perf_status & 0xff00) >> 8;
7793
7794 /* Check for overclock support */
7795 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7796 500))
7797 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7798 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7799 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7800 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7801 500))
7802 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7803 if (pcu_mbox & (1<<31)) { /* OC supported */
7804 max_freq = pcu_mbox & 0xff;
7805 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7806 }
7807
7808 /* In units of 100MHz */
7809 dev_priv->max_delay = max_freq;
7810 dev_priv->min_delay = min_freq;
7811 dev_priv->cur_delay = cur_freq;
7812
7813 /* requires MSI enabled */
7814 I915_WRITE(GEN6_PMIER,
7815 GEN6_PM_MBOX_EVENT |
7816 GEN6_PM_THERMAL_EVENT |
7817 GEN6_PM_RP_DOWN_TIMEOUT |
7818 GEN6_PM_RP_UP_THRESHOLD |
7819 GEN6_PM_RP_DOWN_THRESHOLD |
7820 GEN6_PM_RP_UP_EI_EXPIRED |
7821 GEN6_PM_RP_DOWN_EI_EXPIRED);
7822 spin_lock_irq(&dev_priv->rps_lock);
7823 WARN_ON(dev_priv->pm_iir != 0);
7824 I915_WRITE(GEN6_PMIMR, 0);
7825 spin_unlock_irq(&dev_priv->rps_lock);
7826 /* enable all PM interrupts */
7827 I915_WRITE(GEN6_PMINTRMSK, 0);
7828
7829 gen6_gt_force_wake_put(dev_priv);
7830 mutex_unlock(&dev_priv->dev->struct_mutex);
7831 }
7832
7833 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7834 {
7835 int min_freq = 15;
7836 int gpu_freq, ia_freq, max_ia_freq;
7837 int scaling_factor = 180;
7838
7839 max_ia_freq = cpufreq_quick_get_max(0);
7840 /*
7841 * Default to measured freq if none found, PCU will ensure we don't go
7842 * over
7843 */
7844 if (!max_ia_freq)
7845 max_ia_freq = tsc_khz;
7846
7847 /* Convert from kHz to MHz */
7848 max_ia_freq /= 1000;
7849
7850 mutex_lock(&dev_priv->dev->struct_mutex);
7851
7852 /*
7853 * For each potential GPU frequency, load a ring frequency we'd like
7854 * to use for memory access. We do this by specifying the IA frequency
7855 * the PCU should use as a reference to determine the ring frequency.
7856 */
7857 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7858 gpu_freq--) {
7859 int diff = dev_priv->max_delay - gpu_freq;
7860
7861 /*
7862 * For GPU frequencies less than 750MHz, just use the lowest
7863 * ring freq.
7864 */
7865 if (gpu_freq < min_freq)
7866 ia_freq = 800;
7867 else
7868 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7869 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7870
7871 I915_WRITE(GEN6_PCODE_DATA,
7872 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7873 gpu_freq);
7874 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7875 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7876 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7877 GEN6_PCODE_READY) == 0, 10)) {
7878 DRM_ERROR("pcode write of freq table timed out\n");
7879 continue;
7880 }
7881 }
7882
7883 mutex_unlock(&dev_priv->dev->struct_mutex);
7884 }
7885
7886 static void ironlake_init_clock_gating(struct drm_device *dev)
7887 {
7888 struct drm_i915_private *dev_priv = dev->dev_private;
7889 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7890
7891 /* Required for FBC */
7892 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7893 DPFCRUNIT_CLOCK_GATE_DISABLE |
7894 DPFDUNIT_CLOCK_GATE_DISABLE;
7895 /* Required for CxSR */
7896 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7897
7898 I915_WRITE(PCH_3DCGDIS0,
7899 MARIUNIT_CLOCK_GATE_DISABLE |
7900 SVSMUNIT_CLOCK_GATE_DISABLE);
7901 I915_WRITE(PCH_3DCGDIS1,
7902 VFMUNIT_CLOCK_GATE_DISABLE);
7903
7904 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7905
7906 /*
7907 * According to the spec the following bits should be set in
7908 * order to enable memory self-refresh
7909 * The bit 22/21 of 0x42004
7910 * The bit 5 of 0x42020
7911 * The bit 15 of 0x45000
7912 */
7913 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7914 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7915 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7916 I915_WRITE(ILK_DSPCLK_GATE,
7917 (I915_READ(ILK_DSPCLK_GATE) |
7918 ILK_DPARB_CLK_GATE));
7919 I915_WRITE(DISP_ARB_CTL,
7920 (I915_READ(DISP_ARB_CTL) |
7921 DISP_FBC_WM_DIS));
7922 I915_WRITE(WM3_LP_ILK, 0);
7923 I915_WRITE(WM2_LP_ILK, 0);
7924 I915_WRITE(WM1_LP_ILK, 0);
7925
7926 /*
7927 * Based on the document from hardware guys the following bits
7928 * should be set unconditionally in order to enable FBC.
7929 * The bit 22 of 0x42000
7930 * The bit 22 of 0x42004
7931 * The bit 7,8,9 of 0x42020.
7932 */
7933 if (IS_IRONLAKE_M(dev)) {
7934 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7935 I915_READ(ILK_DISPLAY_CHICKEN1) |
7936 ILK_FBCQ_DIS);
7937 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7938 I915_READ(ILK_DISPLAY_CHICKEN2) |
7939 ILK_DPARB_GATE);
7940 I915_WRITE(ILK_DSPCLK_GATE,
7941 I915_READ(ILK_DSPCLK_GATE) |
7942 ILK_DPFC_DIS1 |
7943 ILK_DPFC_DIS2 |
7944 ILK_CLK_FBC);
7945 }
7946
7947 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7948 I915_READ(ILK_DISPLAY_CHICKEN2) |
7949 ILK_ELPIN_409_SELECT);
7950 I915_WRITE(_3D_CHICKEN2,
7951 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7952 _3D_CHICKEN2_WM_READ_PIPELINED);
7953 }
7954
7955 static void gen6_init_clock_gating(struct drm_device *dev)
7956 {
7957 struct drm_i915_private *dev_priv = dev->dev_private;
7958 int pipe;
7959 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7960
7961 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7962
7963 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7964 I915_READ(ILK_DISPLAY_CHICKEN2) |
7965 ILK_ELPIN_409_SELECT);
7966
7967 I915_WRITE(WM3_LP_ILK, 0);
7968 I915_WRITE(WM2_LP_ILK, 0);
7969 I915_WRITE(WM1_LP_ILK, 0);
7970
7971 /*
7972 * According to the spec the following bits should be
7973 * set in order to enable memory self-refresh and fbc:
7974 * The bit21 and bit22 of 0x42000
7975 * The bit21 and bit22 of 0x42004
7976 * The bit5 and bit7 of 0x42020
7977 * The bit14 of 0x70180
7978 * The bit14 of 0x71180
7979 */
7980 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7981 I915_READ(ILK_DISPLAY_CHICKEN1) |
7982 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7983 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7984 I915_READ(ILK_DISPLAY_CHICKEN2) |
7985 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7986 I915_WRITE(ILK_DSPCLK_GATE,
7987 I915_READ(ILK_DSPCLK_GATE) |
7988 ILK_DPARB_CLK_GATE |
7989 ILK_DPFD_CLK_GATE);
7990
7991 for_each_pipe(pipe) {
7992 I915_WRITE(DSPCNTR(pipe),
7993 I915_READ(DSPCNTR(pipe)) |
7994 DISPPLANE_TRICKLE_FEED_DISABLE);
7995 intel_flush_display_plane(dev_priv, pipe);
7996 }
7997 }
7998
7999 static void ivybridge_init_clock_gating(struct drm_device *dev)
8000 {
8001 struct drm_i915_private *dev_priv = dev->dev_private;
8002 int pipe;
8003 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8004
8005 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8006
8007 I915_WRITE(WM3_LP_ILK, 0);
8008 I915_WRITE(WM2_LP_ILK, 0);
8009 I915_WRITE(WM1_LP_ILK, 0);
8010
8011 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8012
8013 for_each_pipe(pipe) {
8014 I915_WRITE(DSPCNTR(pipe),
8015 I915_READ(DSPCNTR(pipe)) |
8016 DISPPLANE_TRICKLE_FEED_DISABLE);
8017 intel_flush_display_plane(dev_priv, pipe);
8018 }
8019 }
8020
8021 static void g4x_init_clock_gating(struct drm_device *dev)
8022 {
8023 struct drm_i915_private *dev_priv = dev->dev_private;
8024 uint32_t dspclk_gate;
8025
8026 I915_WRITE(RENCLK_GATE_D1, 0);
8027 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8028 GS_UNIT_CLOCK_GATE_DISABLE |
8029 CL_UNIT_CLOCK_GATE_DISABLE);
8030 I915_WRITE(RAMCLK_GATE_D, 0);
8031 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8032 OVRUNIT_CLOCK_GATE_DISABLE |
8033 OVCUNIT_CLOCK_GATE_DISABLE;
8034 if (IS_GM45(dev))
8035 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8036 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8037 }
8038
8039 static void crestline_init_clock_gating(struct drm_device *dev)
8040 {
8041 struct drm_i915_private *dev_priv = dev->dev_private;
8042
8043 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8044 I915_WRITE(RENCLK_GATE_D2, 0);
8045 I915_WRITE(DSPCLK_GATE_D, 0);
8046 I915_WRITE(RAMCLK_GATE_D, 0);
8047 I915_WRITE16(DEUC, 0);
8048 }
8049
8050 static void broadwater_init_clock_gating(struct drm_device *dev)
8051 {
8052 struct drm_i915_private *dev_priv = dev->dev_private;
8053
8054 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8055 I965_RCC_CLOCK_GATE_DISABLE |
8056 I965_RCPB_CLOCK_GATE_DISABLE |
8057 I965_ISC_CLOCK_GATE_DISABLE |
8058 I965_FBC_CLOCK_GATE_DISABLE);
8059 I915_WRITE(RENCLK_GATE_D2, 0);
8060 }
8061
8062 static void gen3_init_clock_gating(struct drm_device *dev)
8063 {
8064 struct drm_i915_private *dev_priv = dev->dev_private;
8065 u32 dstate = I915_READ(D_STATE);
8066
8067 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8068 DSTATE_DOT_CLOCK_GATING;
8069 I915_WRITE(D_STATE, dstate);
8070 }
8071
8072 static void i85x_init_clock_gating(struct drm_device *dev)
8073 {
8074 struct drm_i915_private *dev_priv = dev->dev_private;
8075
8076 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8077 }
8078
8079 static void i830_init_clock_gating(struct drm_device *dev)
8080 {
8081 struct drm_i915_private *dev_priv = dev->dev_private;
8082
8083 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8084 }
8085
8086 static void ibx_init_clock_gating(struct drm_device *dev)
8087 {
8088 struct drm_i915_private *dev_priv = dev->dev_private;
8089
8090 /*
8091 * On Ibex Peak and Cougar Point, we need to disable clock
8092 * gating for the panel power sequencer or it will fail to
8093 * start up when no ports are active.
8094 */
8095 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8096 }
8097
8098 static void cpt_init_clock_gating(struct drm_device *dev)
8099 {
8100 struct drm_i915_private *dev_priv = dev->dev_private;
8101 int pipe;
8102
8103 /*
8104 * On Ibex Peak and Cougar Point, we need to disable clock
8105 * gating for the panel power sequencer or it will fail to
8106 * start up when no ports are active.
8107 */
8108 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8109 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8110 DPLS_EDP_PPS_FIX_DIS);
8111 /* Without this, mode sets may fail silently on FDI */
8112 for_each_pipe(pipe)
8113 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8114 }
8115
8116 static void ironlake_teardown_rc6(struct drm_device *dev)
8117 {
8118 struct drm_i915_private *dev_priv = dev->dev_private;
8119
8120 if (dev_priv->renderctx) {
8121 i915_gem_object_unpin(dev_priv->renderctx);
8122 drm_gem_object_unreference(&dev_priv->renderctx->base);
8123 dev_priv->renderctx = NULL;
8124 }
8125
8126 if (dev_priv->pwrctx) {
8127 i915_gem_object_unpin(dev_priv->pwrctx);
8128 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8129 dev_priv->pwrctx = NULL;
8130 }
8131 }
8132
8133 static void ironlake_disable_rc6(struct drm_device *dev)
8134 {
8135 struct drm_i915_private *dev_priv = dev->dev_private;
8136
8137 if (I915_READ(PWRCTXA)) {
8138 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8139 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8140 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8141 50);
8142
8143 I915_WRITE(PWRCTXA, 0);
8144 POSTING_READ(PWRCTXA);
8145
8146 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8147 POSTING_READ(RSTDBYCTL);
8148 }
8149
8150 ironlake_teardown_rc6(dev);
8151 }
8152
8153 static int ironlake_setup_rc6(struct drm_device *dev)
8154 {
8155 struct drm_i915_private *dev_priv = dev->dev_private;
8156
8157 if (dev_priv->renderctx == NULL)
8158 dev_priv->renderctx = intel_alloc_context_page(dev);
8159 if (!dev_priv->renderctx)
8160 return -ENOMEM;
8161
8162 if (dev_priv->pwrctx == NULL)
8163 dev_priv->pwrctx = intel_alloc_context_page(dev);
8164 if (!dev_priv->pwrctx) {
8165 ironlake_teardown_rc6(dev);
8166 return -ENOMEM;
8167 }
8168
8169 return 0;
8170 }
8171
8172 void ironlake_enable_rc6(struct drm_device *dev)
8173 {
8174 struct drm_i915_private *dev_priv = dev->dev_private;
8175 int ret;
8176
8177 /* rc6 disabled by default due to repeated reports of hanging during
8178 * boot and resume.
8179 */
8180 if (!i915_enable_rc6)
8181 return;
8182
8183 mutex_lock(&dev->struct_mutex);
8184 ret = ironlake_setup_rc6(dev);
8185 if (ret) {
8186 mutex_unlock(&dev->struct_mutex);
8187 return;
8188 }
8189
8190 /*
8191 * GPU can automatically power down the render unit if given a page
8192 * to save state.
8193 */
8194 ret = BEGIN_LP_RING(6);
8195 if (ret) {
8196 ironlake_teardown_rc6(dev);
8197 mutex_unlock(&dev->struct_mutex);
8198 return;
8199 }
8200
8201 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8202 OUT_RING(MI_SET_CONTEXT);
8203 OUT_RING(dev_priv->renderctx->gtt_offset |
8204 MI_MM_SPACE_GTT |
8205 MI_SAVE_EXT_STATE_EN |
8206 MI_RESTORE_EXT_STATE_EN |
8207 MI_RESTORE_INHIBIT);
8208 OUT_RING(MI_SUSPEND_FLUSH);
8209 OUT_RING(MI_NOOP);
8210 OUT_RING(MI_FLUSH);
8211 ADVANCE_LP_RING();
8212
8213 /*
8214 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8215 * does an implicit flush, combined with MI_FLUSH above, it should be
8216 * safe to assume that renderctx is valid
8217 */
8218 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8219 if (ret) {
8220 DRM_ERROR("failed to enable ironlake power power savings\n");
8221 ironlake_teardown_rc6(dev);
8222 mutex_unlock(&dev->struct_mutex);
8223 return;
8224 }
8225
8226 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8227 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8228 mutex_unlock(&dev->struct_mutex);
8229 }
8230
8231 void intel_init_clock_gating(struct drm_device *dev)
8232 {
8233 struct drm_i915_private *dev_priv = dev->dev_private;
8234
8235 dev_priv->display.init_clock_gating(dev);
8236
8237 if (dev_priv->display.init_pch_clock_gating)
8238 dev_priv->display.init_pch_clock_gating(dev);
8239 }
8240
8241 /* Set up chip specific display functions */
8242 static void intel_init_display(struct drm_device *dev)
8243 {
8244 struct drm_i915_private *dev_priv = dev->dev_private;
8245
8246 /* We always want a DPMS function */
8247 if (HAS_PCH_SPLIT(dev)) {
8248 dev_priv->display.dpms = ironlake_crtc_dpms;
8249 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8250 dev_priv->display.update_plane = ironlake_update_plane;
8251 } else {
8252 dev_priv->display.dpms = i9xx_crtc_dpms;
8253 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8254 dev_priv->display.update_plane = i9xx_update_plane;
8255 }
8256
8257 if (I915_HAS_FBC(dev)) {
8258 if (HAS_PCH_SPLIT(dev)) {
8259 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8260 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8261 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8262 } else if (IS_GM45(dev)) {
8263 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8264 dev_priv->display.enable_fbc = g4x_enable_fbc;
8265 dev_priv->display.disable_fbc = g4x_disable_fbc;
8266 } else if (IS_CRESTLINE(dev)) {
8267 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8268 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8269 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8270 }
8271 /* 855GM needs testing */
8272 }
8273
8274 /* Returns the core display clock speed */
8275 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8276 dev_priv->display.get_display_clock_speed =
8277 i945_get_display_clock_speed;
8278 else if (IS_I915G(dev))
8279 dev_priv->display.get_display_clock_speed =
8280 i915_get_display_clock_speed;
8281 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8282 dev_priv->display.get_display_clock_speed =
8283 i9xx_misc_get_display_clock_speed;
8284 else if (IS_I915GM(dev))
8285 dev_priv->display.get_display_clock_speed =
8286 i915gm_get_display_clock_speed;
8287 else if (IS_I865G(dev))
8288 dev_priv->display.get_display_clock_speed =
8289 i865_get_display_clock_speed;
8290 else if (IS_I85X(dev))
8291 dev_priv->display.get_display_clock_speed =
8292 i855_get_display_clock_speed;
8293 else /* 852, 830 */
8294 dev_priv->display.get_display_clock_speed =
8295 i830_get_display_clock_speed;
8296
8297 /* For FIFO watermark updates */
8298 if (HAS_PCH_SPLIT(dev)) {
8299 if (HAS_PCH_IBX(dev))
8300 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8301 else if (HAS_PCH_CPT(dev))
8302 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8303
8304 if (IS_GEN5(dev)) {
8305 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8306 dev_priv->display.update_wm = ironlake_update_wm;
8307 else {
8308 DRM_DEBUG_KMS("Failed to get proper latency. "
8309 "Disable CxSR\n");
8310 dev_priv->display.update_wm = NULL;
8311 }
8312 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8313 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8314 dev_priv->display.write_eld = ironlake_write_eld;
8315 } else if (IS_GEN6(dev)) {
8316 if (SNB_READ_WM0_LATENCY()) {
8317 dev_priv->display.update_wm = sandybridge_update_wm;
8318 } else {
8319 DRM_DEBUG_KMS("Failed to read display plane latency. "
8320 "Disable CxSR\n");
8321 dev_priv->display.update_wm = NULL;
8322 }
8323 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8324 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8325 dev_priv->display.write_eld = ironlake_write_eld;
8326 } else if (IS_IVYBRIDGE(dev)) {
8327 /* FIXME: detect B0+ stepping and use auto training */
8328 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8329 if (SNB_READ_WM0_LATENCY()) {
8330 dev_priv->display.update_wm = sandybridge_update_wm;
8331 } else {
8332 DRM_DEBUG_KMS("Failed to read display plane latency. "
8333 "Disable CxSR\n");
8334 dev_priv->display.update_wm = NULL;
8335 }
8336 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8337 dev_priv->display.write_eld = ironlake_write_eld;
8338 } else
8339 dev_priv->display.update_wm = NULL;
8340 } else if (IS_PINEVIEW(dev)) {
8341 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8342 dev_priv->is_ddr3,
8343 dev_priv->fsb_freq,
8344 dev_priv->mem_freq)) {
8345 DRM_INFO("failed to find known CxSR latency "
8346 "(found ddr%s fsb freq %d, mem freq %d), "
8347 "disabling CxSR\n",
8348 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8349 dev_priv->fsb_freq, dev_priv->mem_freq);
8350 /* Disable CxSR and never update its watermark again */
8351 pineview_disable_cxsr(dev);
8352 dev_priv->display.update_wm = NULL;
8353 } else
8354 dev_priv->display.update_wm = pineview_update_wm;
8355 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8356 } else if (IS_G4X(dev)) {
8357 dev_priv->display.write_eld = g4x_write_eld;
8358 dev_priv->display.update_wm = g4x_update_wm;
8359 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8360 } else if (IS_GEN4(dev)) {
8361 dev_priv->display.update_wm = i965_update_wm;
8362 if (IS_CRESTLINE(dev))
8363 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8364 else if (IS_BROADWATER(dev))
8365 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8366 } else if (IS_GEN3(dev)) {
8367 dev_priv->display.update_wm = i9xx_update_wm;
8368 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8369 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8370 } else if (IS_I865G(dev)) {
8371 dev_priv->display.update_wm = i830_update_wm;
8372 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8373 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8374 } else if (IS_I85X(dev)) {
8375 dev_priv->display.update_wm = i9xx_update_wm;
8376 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8377 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8378 } else {
8379 dev_priv->display.update_wm = i830_update_wm;
8380 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8381 if (IS_845G(dev))
8382 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8383 else
8384 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8385 }
8386
8387 /* Default just returns -ENODEV to indicate unsupported */
8388 dev_priv->display.queue_flip = intel_default_queue_flip;
8389
8390 switch (INTEL_INFO(dev)->gen) {
8391 case 2:
8392 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8393 break;
8394
8395 case 3:
8396 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8397 break;
8398
8399 case 4:
8400 case 5:
8401 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8402 break;
8403
8404 case 6:
8405 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8406 break;
8407 case 7:
8408 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8409 break;
8410 }
8411 }
8412
8413 /*
8414 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8415 * resume, or other times. This quirk makes sure that's the case for
8416 * affected systems.
8417 */
8418 static void quirk_pipea_force(struct drm_device *dev)
8419 {
8420 struct drm_i915_private *dev_priv = dev->dev_private;
8421
8422 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8423 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8424 }
8425
8426 /*
8427 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8428 */
8429 static void quirk_ssc_force_disable(struct drm_device *dev)
8430 {
8431 struct drm_i915_private *dev_priv = dev->dev_private;
8432 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8433 }
8434
8435 struct intel_quirk {
8436 int device;
8437 int subsystem_vendor;
8438 int subsystem_device;
8439 void (*hook)(struct drm_device *dev);
8440 };
8441
8442 struct intel_quirk intel_quirks[] = {
8443 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8444 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8445 /* HP Mini needs pipe A force quirk (LP: #322104) */
8446 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8447
8448 /* Thinkpad R31 needs pipe A force quirk */
8449 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8450 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8451 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8452
8453 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8454 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8455 /* ThinkPad X40 needs pipe A force quirk */
8456
8457 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8458 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8459
8460 /* 855 & before need to leave pipe A & dpll A up */
8461 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8462 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8463
8464 /* Lenovo U160 cannot use SSC on LVDS */
8465 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8466
8467 /* Sony Vaio Y cannot use SSC on LVDS */
8468 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8469 };
8470
8471 static void intel_init_quirks(struct drm_device *dev)
8472 {
8473 struct pci_dev *d = dev->pdev;
8474 int i;
8475
8476 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8477 struct intel_quirk *q = &intel_quirks[i];
8478
8479 if (d->device == q->device &&
8480 (d->subsystem_vendor == q->subsystem_vendor ||
8481 q->subsystem_vendor == PCI_ANY_ID) &&
8482 (d->subsystem_device == q->subsystem_device ||
8483 q->subsystem_device == PCI_ANY_ID))
8484 q->hook(dev);
8485 }
8486 }
8487
8488 /* Disable the VGA plane that we never use */
8489 static void i915_disable_vga(struct drm_device *dev)
8490 {
8491 struct drm_i915_private *dev_priv = dev->dev_private;
8492 u8 sr1;
8493 u32 vga_reg;
8494
8495 if (HAS_PCH_SPLIT(dev))
8496 vga_reg = CPU_VGACNTRL;
8497 else
8498 vga_reg = VGACNTRL;
8499
8500 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8501 outb(1, VGA_SR_INDEX);
8502 sr1 = inb(VGA_SR_DATA);
8503 outb(sr1 | 1<<5, VGA_SR_DATA);
8504 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8505 udelay(300);
8506
8507 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8508 POSTING_READ(vga_reg);
8509 }
8510
8511 void intel_modeset_init(struct drm_device *dev)
8512 {
8513 struct drm_i915_private *dev_priv = dev->dev_private;
8514 int i;
8515
8516 drm_mode_config_init(dev);
8517
8518 dev->mode_config.min_width = 0;
8519 dev->mode_config.min_height = 0;
8520
8521 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8522
8523 intel_init_quirks(dev);
8524
8525 intel_init_display(dev);
8526
8527 if (IS_GEN2(dev)) {
8528 dev->mode_config.max_width = 2048;
8529 dev->mode_config.max_height = 2048;
8530 } else if (IS_GEN3(dev)) {
8531 dev->mode_config.max_width = 4096;
8532 dev->mode_config.max_height = 4096;
8533 } else {
8534 dev->mode_config.max_width = 8192;
8535 dev->mode_config.max_height = 8192;
8536 }
8537 dev->mode_config.fb_base = dev->agp->base;
8538
8539 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8540 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8541
8542 for (i = 0; i < dev_priv->num_pipe; i++) {
8543 intel_crtc_init(dev, i);
8544 }
8545
8546 /* Just disable it once at startup */
8547 i915_disable_vga(dev);
8548 intel_setup_outputs(dev);
8549
8550 intel_init_clock_gating(dev);
8551
8552 if (IS_IRONLAKE_M(dev)) {
8553 ironlake_enable_drps(dev);
8554 intel_init_emon(dev);
8555 }
8556
8557 if (IS_GEN6(dev) || IS_GEN7(dev)) {
8558 gen6_enable_rps(dev_priv);
8559 gen6_update_ring_freq(dev_priv);
8560 }
8561
8562 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8563 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8564 (unsigned long)dev);
8565 }
8566
8567 void intel_modeset_gem_init(struct drm_device *dev)
8568 {
8569 if (IS_IRONLAKE_M(dev))
8570 ironlake_enable_rc6(dev);
8571
8572 intel_setup_overlay(dev);
8573 }
8574
8575 void intel_modeset_cleanup(struct drm_device *dev)
8576 {
8577 struct drm_i915_private *dev_priv = dev->dev_private;
8578 struct drm_crtc *crtc;
8579 struct intel_crtc *intel_crtc;
8580
8581 drm_kms_helper_poll_fini(dev);
8582 mutex_lock(&dev->struct_mutex);
8583
8584 intel_unregister_dsm_handler();
8585
8586
8587 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8588 /* Skip inactive CRTCs */
8589 if (!crtc->fb)
8590 continue;
8591
8592 intel_crtc = to_intel_crtc(crtc);
8593 intel_increase_pllclock(crtc);
8594 }
8595
8596 intel_disable_fbc(dev);
8597
8598 if (IS_IRONLAKE_M(dev))
8599 ironlake_disable_drps(dev);
8600 if (IS_GEN6(dev) || IS_GEN7(dev))
8601 gen6_disable_rps(dev);
8602
8603 if (IS_IRONLAKE_M(dev))
8604 ironlake_disable_rc6(dev);
8605
8606 mutex_unlock(&dev->struct_mutex);
8607
8608 /* Disable the irq before mode object teardown, for the irq might
8609 * enqueue unpin/hotplug work. */
8610 drm_irq_uninstall(dev);
8611 cancel_work_sync(&dev_priv->hotplug_work);
8612
8613 /* flush any delayed tasks or pending work */
8614 flush_scheduled_work();
8615
8616 /* Shut off idle work before the crtcs get freed. */
8617 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8618 intel_crtc = to_intel_crtc(crtc);
8619 del_timer_sync(&intel_crtc->idle_timer);
8620 }
8621 del_timer_sync(&dev_priv->idle_timer);
8622 cancel_work_sync(&dev_priv->idle_work);
8623
8624 drm_mode_config_cleanup(dev);
8625 }
8626
8627 /*
8628 * Return which encoder is currently attached for connector.
8629 */
8630 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8631 {
8632 return &intel_attached_encoder(connector)->base;
8633 }
8634
8635 void intel_connector_attach_encoder(struct intel_connector *connector,
8636 struct intel_encoder *encoder)
8637 {
8638 connector->encoder = encoder;
8639 drm_mode_connector_attach_encoder(&connector->base,
8640 &encoder->base);
8641 }
8642
8643 /*
8644 * set vga decode state - true == enable VGA decode
8645 */
8646 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8647 {
8648 struct drm_i915_private *dev_priv = dev->dev_private;
8649 u16 gmch_ctrl;
8650
8651 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8652 if (state)
8653 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8654 else
8655 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8656 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8657 return 0;
8658 }
8659
8660 #ifdef CONFIG_DEBUG_FS
8661 #include <linux/seq_file.h>
8662
8663 struct intel_display_error_state {
8664 struct intel_cursor_error_state {
8665 u32 control;
8666 u32 position;
8667 u32 base;
8668 u32 size;
8669 } cursor[2];
8670
8671 struct intel_pipe_error_state {
8672 u32 conf;
8673 u32 source;
8674
8675 u32 htotal;
8676 u32 hblank;
8677 u32 hsync;
8678 u32 vtotal;
8679 u32 vblank;
8680 u32 vsync;
8681 } pipe[2];
8682
8683 struct intel_plane_error_state {
8684 u32 control;
8685 u32 stride;
8686 u32 size;
8687 u32 pos;
8688 u32 addr;
8689 u32 surface;
8690 u32 tile_offset;
8691 } plane[2];
8692 };
8693
8694 struct intel_display_error_state *
8695 intel_display_capture_error_state(struct drm_device *dev)
8696 {
8697 drm_i915_private_t *dev_priv = dev->dev_private;
8698 struct intel_display_error_state *error;
8699 int i;
8700
8701 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8702 if (error == NULL)
8703 return NULL;
8704
8705 for (i = 0; i < 2; i++) {
8706 error->cursor[i].control = I915_READ(CURCNTR(i));
8707 error->cursor[i].position = I915_READ(CURPOS(i));
8708 error->cursor[i].base = I915_READ(CURBASE(i));
8709
8710 error->plane[i].control = I915_READ(DSPCNTR(i));
8711 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8712 error->plane[i].size = I915_READ(DSPSIZE(i));
8713 error->plane[i].pos = I915_READ(DSPPOS(i));
8714 error->plane[i].addr = I915_READ(DSPADDR(i));
8715 if (INTEL_INFO(dev)->gen >= 4) {
8716 error->plane[i].surface = I915_READ(DSPSURF(i));
8717 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8718 }
8719
8720 error->pipe[i].conf = I915_READ(PIPECONF(i));
8721 error->pipe[i].source = I915_READ(PIPESRC(i));
8722 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8723 error->pipe[i].hblank = I915_READ(HBLANK(i));
8724 error->pipe[i].hsync = I915_READ(HSYNC(i));
8725 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8726 error->pipe[i].vblank = I915_READ(VBLANK(i));
8727 error->pipe[i].vsync = I915_READ(VSYNC(i));
8728 }
8729
8730 return error;
8731 }
8732
8733 void
8734 intel_display_print_error_state(struct seq_file *m,
8735 struct drm_device *dev,
8736 struct intel_display_error_state *error)
8737 {
8738 int i;
8739
8740 for (i = 0; i < 2; i++) {
8741 seq_printf(m, "Pipe [%d]:\n", i);
8742 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8743 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8744 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8745 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8746 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8747 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8748 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8749 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8750
8751 seq_printf(m, "Plane [%d]:\n", i);
8752 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8753 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8754 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8755 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8756 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8757 if (INTEL_INFO(dev)->gen >= 4) {
8758 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8759 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8760 }
8761
8762 seq_printf(m, "Cursor [%d]:\n", i);
8763 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8764 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8765 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8766 }
8767 }
8768 #endif
Linus' kernel tree