?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / serial / pmac_zilog.c
blob72586594be4c1ea6de7e35250a41145711208045
1 /*
2 * linux/drivers/serial/pmac_zilog.c
3 *
4 * Driver for PowerMac Z85c30 based ESCC cell found in the
5 * "macio" ASICs of various PowerMac models
6 *
7 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
8 *
9 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
10 * and drivers/serial/sunzilog.c by David S. Miller
11 *
12 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
13 * adapted special tweaks needed for us. I don't think it's worth
14 * merging back those though. The DMA code still has to get in
15 * and once done, I expect that driver to remain fairly stable in
16 * the long term, unless we change the driver model again...
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * TODO: - Add DMA support
33 * - Defer port shutdown to a few seconds after close
34 * - maybe put something right into uap->clk_divisor
35 */
36
37 #undef DEBUG
38 #undef DEBUG_HARD
39
40 #include <linux/config.h>
41 #include <linux/module.h>
42 #include <linux/tty.h>
43
44 #include <linux/tty_flip.h>
45 #include <linux/major.h>
46 #include <linux/string.h>
47 #include <linux/fcntl.h>
48 #include <linux/mm.h>
49 #include <linux/kernel.h>
50 #include <linux/delay.h>
51 #include <linux/init.h>
52 #include <linux/console.h>
53 #include <linux/slab.h>
54 #include <linux/adb.h>
55 #include <linux/pmu.h>
56 #include <asm/sections.h>
57 #include <asm/io.h>
58 #include <asm/irq.h>
59 #include <asm/prom.h>
60 #include <asm/bitops.h>
61 #include <asm/machdep.h>
62 #include <asm/pmac_feature.h>
63 #include <asm/dbdma.h>
64 #include <asm/macio.h>
65 #include <asm/semaphore.h>
66
67 #include <linux/serial.h>
68 #include <linux/serial_core.h>
69
70 #include "pmac_zilog.h"
71
72 /* Not yet implemented */
73 #undef HAS_DBDMA
74
75 static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
76 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
77 MODULE_DESCRIPTION("Driver for the PowerMac serial ports.");
78 MODULE_LICENSE("GPL");
79
80 #define PWRDBG(fmt, arg...) printk(KERN_DEBUG fmt , ## arg)
81
82
83 /*
84 * For the sake of early serial console, we can do a pre-probe
85 * (optional) of the ports at rather early boot time.
86 */
87 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
88 static int pmz_ports_count;
89 static DECLARE_MUTEX(pmz_irq_sem);
90
91 static struct uart_driver pmz_uart_reg = {
92 .owner = THIS_MODULE,
93 .driver_name = "ttyS",
94 .devfs_name = "tts/",
95 .dev_name = "ttyS",
96 .major = TTY_MAJOR,
97 };
98
99
100 /*
101 * Load all registers to reprogram the port
102 * This function must only be called when the TX is not busy. The UART
103 * port lock must be held and local interrupts disabled.
104 */
105 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
106 {
107 int i;
108
109 if (ZS_IS_ASLEEP(uap))
110 return;
111
112 /* Let pending transmits finish. */
113 for (i = 0; i < 1000; i++) {
114 unsigned char stat = read_zsreg(uap, R1);
115 if (stat & ALL_SNT)
116 break;
117 udelay(100);
118 }
119
120 ZS_CLEARERR(uap);
121 zssync(uap);
122 ZS_CLEARFIFO(uap);
123 zssync(uap);
124 ZS_CLEARERR(uap);
125
126 /* Disable all interrupts. */
127 write_zsreg(uap, R1,
128 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
129
130 /* Set parity, sync config, stop bits, and clock divisor. */
131 write_zsreg(uap, R4, regs[R4]);
132
133 /* Set misc. TX/RX control bits. */
134 write_zsreg(uap, R10, regs[R10]);
135
136 /* Set TX/RX controls sans the enable bits. */
137 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
138 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
139
140 /* now set R7 "prime" on ESCC */
141 write_zsreg(uap, R15, regs[R15] | EN85C30);
142 write_zsreg(uap, R7, regs[R7P]);
143
144 /* make sure we use R7 "non-prime" on ESCC */
145 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
146
147 /* Synchronous mode config. */
148 write_zsreg(uap, R6, regs[R6]);
149 write_zsreg(uap, R7, regs[R7]);
150
151 /* Disable baud generator. */
152 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
153
154 /* Clock mode control. */
155 write_zsreg(uap, R11, regs[R11]);
156
157 /* Lower and upper byte of baud rate generator divisor. */
158 write_zsreg(uap, R12, regs[R12]);
159 write_zsreg(uap, R13, regs[R13]);
160
161 /* Now rewrite R14, with BRENAB (if set). */
162 write_zsreg(uap, R14, regs[R14]);
163
164 /* Reset external status interrupts. */
165 write_zsreg(uap, R0, RES_EXT_INT);
166 write_zsreg(uap, R0, RES_EXT_INT);
167
168 /* Rewrite R3/R5, this time without enables masked. */
169 write_zsreg(uap, R3, regs[R3]);
170 write_zsreg(uap, R5, regs[R5]);
171
172 /* Rewrite R1, this time without IRQ enabled masked. */
173 write_zsreg(uap, R1, regs[R1]);
174
175 /* Enable interrupts */
176 write_zsreg(uap, R9, regs[R9]);
177 }
178
179 /*
180 * We do like sunzilog to avoid disrupting pending Tx
181 * Reprogram the Zilog channel HW registers with the copies found in the
182 * software state struct. If the transmitter is busy, we defer this update
183 * until the next TX complete interrupt. Else, we do it right now.
184 *
185 * The UART port lock must be held and local interrupts disabled.
186 */
187 static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
188 {
189 if (!ZS_REGS_HELD(uap)) {
190 if (ZS_TX_ACTIVE(uap)) {
191 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
192 } else {
193 pmz_debug("pmz: maybe_update_regs: updating\n");
194 pmz_load_zsregs(uap, uap->curregs);
195 }
196 }
197 }
198
199 static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap,
200 struct pt_regs *regs)
201 {
202 struct tty_struct *tty = NULL;
203 unsigned char ch, r1, drop, error;
204 int loops = 0;
205
206 retry:
207 /* The interrupt can be enabled when the port isn't open, typically
208 * that happens when using one port is open and the other closed (stale
209 * interrupt) or when one port is used as a console.
210 */
211 if (!ZS_IS_OPEN(uap)) {
212 pmz_debug("pmz: draining input\n");
213 /* Port is closed, drain input data */
214 for (;;) {
215 if ((++loops) > 1000)
216 goto flood;
217 (void)read_zsreg(uap, R1);
218 write_zsreg(uap, R0, ERR_RES);
219 (void)read_zsdata(uap);
220 ch = read_zsreg(uap, R0);
221 if (!(ch & Rx_CH_AV))
222 break;
223 }
224 return NULL;
225 }
226
227 /* Sanity check, make sure the old bug is no longer happening */
228 if (uap->port.info == NULL || uap->port.info->tty == NULL) {
229 WARN_ON(1);
230 (void)read_zsdata(uap);
231 return NULL;
232 }
233 tty = uap->port.info->tty;
234
235 while (1) {
236 error = 0;
237 drop = 0;
238
239 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
240 /* Have to drop the lock here */
241 pmz_debug("pmz: flip overflow\n");
242 spin_unlock(&uap->port.lock);
243 tty->flip.work.func((void *)tty);
244 spin_lock(&uap->port.lock);
245 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
246 drop = 1;
247 if (ZS_IS_ASLEEP(uap))
248 return NULL;
249 if (!ZS_IS_OPEN(uap))
250 goto retry;
251 }
252
253 r1 = read_zsreg(uap, R1);
254 ch = read_zsdata(uap);
255
256 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
257 write_zsreg(uap, R0, ERR_RES);
258 zssync(uap);
259 }
260
261 ch &= uap->parity_mask;
262 if (ch == 0 && uap->prev_status & BRK_ABRT)
263 r1 |= BRK_ABRT;
264
265 /* A real serial line, record the character and status. */
266 if (drop)
267 goto next_char;
268
269 *tty->flip.char_buf_ptr = ch;
270 *tty->flip.flag_buf_ptr = TTY_NORMAL;
271 uap->port.icount.rx++;
272
273 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
274 error = 1;
275 if (r1 & BRK_ABRT) {
276 pmz_debug("pmz: got break !\n");
277 r1 &= ~(PAR_ERR | CRC_ERR);
278 uap->port.icount.brk++;
279 if (uart_handle_break(&uap->port)) {
280 pmz_debug("pmz: do handle break !\n");
281 goto next_char;
282 }
283 }
284 else if (r1 & PAR_ERR)
285 uap->port.icount.parity++;
286 else if (r1 & CRC_ERR)
287 uap->port.icount.frame++;
288 if (r1 & Rx_OVR)
289 uap->port.icount.overrun++;
290 r1 &= uap->port.read_status_mask;
291 if (r1 & BRK_ABRT)
292 *tty->flip.flag_buf_ptr = TTY_BREAK;
293 else if (r1 & PAR_ERR)
294 *tty->flip.flag_buf_ptr = TTY_PARITY;
295 else if (r1 & CRC_ERR)
296 *tty->flip.flag_buf_ptr = TTY_FRAME;
297 }
298 if (uart_handle_sysrq_char(&uap->port, ch, regs)) {
299 pmz_debug("pmz: sysrq swallowed the char\n");
300 goto next_char;
301 }
302
303 if (uap->port.ignore_status_mask == 0xff ||
304 (r1 & uap->port.ignore_status_mask) == 0) {
305 tty->flip.flag_buf_ptr++;
306 tty->flip.char_buf_ptr++;
307 tty->flip.count++;
308 }
309 if ((r1 & Rx_OVR) &&
310 tty->flip.count < TTY_FLIPBUF_SIZE) {
311 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
312 tty->flip.flag_buf_ptr++;
313 tty->flip.char_buf_ptr++;
314 tty->flip.count++;
315 }
316 next_char:
317 /* We can get stuck in an infinite loop getting char 0 when the
318 * line is in a wrong HW state, we break that here.
319 * When that happens, I disable the receive side of the driver.
320 * Note that what I've been experiencing is a real irq loop where
321 * I'm getting flooded regardless of the actual port speed.
322 * Something stange is going on with the HW
323 */
324 if ((++loops) > 1000)
325 goto flood;
326 ch = read_zsreg(uap, R0);
327 if (!(ch & Rx_CH_AV))
328 break;
329 }
330
331 return tty;
332 flood:
333 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
334 write_zsreg(uap, R1, uap->curregs[R1]);
335 zssync(uap);
336 dev_err(&uap->dev->ofdev.dev, "pmz: rx irq flood !\n");
337 return tty;
338 }
339
340 static void pmz_status_handle(struct uart_pmac_port *uap, struct pt_regs *regs)
341 {
342 unsigned char status;
343
344 status = read_zsreg(uap, R0);
345 write_zsreg(uap, R0, RES_EXT_INT);
346 zssync(uap);
347
348 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
349 if (status & SYNC_HUNT)
350 uap->port.icount.dsr++;
351
352 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
353 * But it does not tell us which bit has changed, we have to keep
354 * track of this ourselves.
355 * The CTS input is inverted for some reason. -- paulus
356 */
357 if ((status ^ uap->prev_status) & DCD)
358 uart_handle_dcd_change(&uap->port,
359 (status & DCD));
360 if ((status ^ uap->prev_status) & CTS)
361 uart_handle_cts_change(&uap->port,
362 !(status & CTS));
363
364 wake_up_interruptible(&uap->port.info->delta_msr_wait);
365 }
366
367 uap->prev_status = status;
368 }
369
370 static void pmz_transmit_chars(struct uart_pmac_port *uap)
371 {
372 struct circ_buf *xmit;
373
374 if (ZS_IS_ASLEEP(uap))
375 return;
376 if (ZS_IS_CONS(uap)) {
377 unsigned char status = read_zsreg(uap, R0);
378
379 /* TX still busy? Just wait for the next TX done interrupt.
380 *
381 * It can occur because of how we do serial console writes. It would
382 * be nice to transmit console writes just like we normally would for
383 * a TTY line. (ie. buffered and TX interrupt driven). That is not
384 * easy because console writes cannot sleep. One solution might be
385 * to poll on enough port->xmit space becomming free. -DaveM
386 */
387 if (!(status & Tx_BUF_EMP))
388 return;
389 }
390
391 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
392
393 if (ZS_REGS_HELD(uap)) {
394 pmz_load_zsregs(uap, uap->curregs);
395 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
396 }
397
398 if (ZS_TX_STOPPED(uap)) {
399 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
400 goto ack_tx_int;
401 }
402
403 if (uap->port.x_char) {
404 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
405 write_zsdata(uap, uap->port.x_char);
406 zssync(uap);
407 uap->port.icount.tx++;
408 uap->port.x_char = 0;
409 return;
410 }
411
412 if (uap->port.info == NULL)
413 goto ack_tx_int;
414 xmit = &uap->port.info->xmit;
415 if (uart_circ_empty(xmit)) {
416 uart_write_wakeup(&uap->port);
417 goto ack_tx_int;
418 }
419 if (uart_tx_stopped(&uap->port))
420 goto ack_tx_int;
421
422 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
423 write_zsdata(uap, xmit->buf[xmit->tail]);
424 zssync(uap);
425
426 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
427 uap->port.icount.tx++;
428
429 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
430 uart_write_wakeup(&uap->port);
431
432 return;
433
434 ack_tx_int:
435 write_zsreg(uap, R0, RES_Tx_P);
436 zssync(uap);
437 }
438
439 /* Hrm... we register that twice, fixme later.... */
440 static irqreturn_t pmz_interrupt(int irq, void *dev_id, struct pt_regs *regs)
441 {
442 struct uart_pmac_port *uap = dev_id;
443 struct uart_pmac_port *uap_a;
444 struct uart_pmac_port *uap_b;
445 int rc = IRQ_NONE;
446 struct tty_struct *tty;
447 u8 r3;
448
449 uap_a = pmz_get_port_A(uap);
450 uap_b = uap_a->mate;
451
452 spin_lock(&uap_a->port.lock);
453 r3 = read_zsreg(uap_a, R3);
454
455 #ifdef DEBUG_HARD
456 pmz_debug("irq, r3: %x\n", r3);
457 #endif
458 /* Channel A */
459 tty = NULL;
460 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
461 write_zsreg(uap_a, R0, RES_H_IUS);
462 zssync(uap_a);
463 if (r3 & CHAEXT)
464 pmz_status_handle(uap_a, regs);
465 if (r3 & CHARxIP)
466 tty = pmz_receive_chars(uap_a, regs);
467 if (r3 & CHATxIP)
468 pmz_transmit_chars(uap_a);
469 rc = IRQ_HANDLED;
470 }
471 spin_unlock(&uap_a->port.lock);
472 if (tty != NULL)
473 tty_flip_buffer_push(tty);
474
475 if (uap_b->node == NULL)
476 goto out;
477
478 spin_lock(&uap_b->port.lock);
479 tty = NULL;
480 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
481 write_zsreg(uap_b, R0, RES_H_IUS);
482 zssync(uap_b);
483 if (r3 & CHBEXT)
484 pmz_status_handle(uap_b, regs);
485 if (r3 & CHBRxIP)
486 tty = pmz_receive_chars(uap_b, regs);
487 if (r3 & CHBTxIP)
488 pmz_transmit_chars(uap_b);
489 rc = IRQ_HANDLED;
490 }
491 spin_unlock(&uap_b->port.lock);
492 if (tty != NULL)
493 tty_flip_buffer_push(tty);
494
495 out:
496 #ifdef DEBUG_HARD
497 pmz_debug("irq done.\n");
498 #endif
499 return rc;
500 }
501
502 /*
503 * Peek the status register, lock not held by caller
504 */
505 static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
506 {
507 unsigned long flags;
508 u8 status;
509
510 spin_lock_irqsave(&uap->port.lock, flags);
511 status = read_zsreg(uap, R0);
512 spin_unlock_irqrestore(&uap->port.lock, flags);
513
514 return status;
515 }
516
517 /*
518 * Check if transmitter is empty
519 * The port lock is not held.
520 */
521 static unsigned int pmz_tx_empty(struct uart_port *port)
522 {
523 struct uart_pmac_port *uap = to_pmz(port);
524 unsigned char status;
525
526 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
527 return TIOCSER_TEMT;
528
529 status = pmz_peek_status(to_pmz(port));
530 if (status & Tx_BUF_EMP)
531 return TIOCSER_TEMT;
532 return 0;
533 }
534
535 /*
536 * Set Modem Control (RTS & DTR) bits
537 * The port lock is held and interrupts are disabled.
538 * Note: Shall we really filter out RTS on external ports or
539 * should that be dealt at higher level only ?
540 */
541 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
542 {
543 struct uart_pmac_port *uap = to_pmz(port);
544 unsigned char set_bits, clear_bits;
545
546 /* Do nothing for irda for now... */
547 if (ZS_IS_IRDA(uap))
548 return;
549 /* We get called during boot with a port not up yet */
550 if (ZS_IS_ASLEEP(uap) ||
551 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
552 return;
553
554 set_bits = clear_bits = 0;
555
556 if (ZS_IS_INTMODEM(uap)) {
557 if (mctrl & TIOCM_RTS)
558 set_bits |= RTS;
559 else
560 clear_bits |= RTS;
561 }
562 if (mctrl & TIOCM_DTR)
563 set_bits |= DTR;
564 else
565 clear_bits |= DTR;
566
567 /* NOTE: Not subject to 'transmitter active' rule. */
568 uap->curregs[R5] |= set_bits;
569 uap->curregs[R5] &= ~clear_bits;
570 if (ZS_IS_ASLEEP(uap))
571 return;
572 write_zsreg(uap, R5, uap->curregs[R5]);
573 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
574 set_bits, clear_bits, uap->curregs[R5]);
575 zssync(uap);
576 }
577
578 /*
579 * Get Modem Control bits (only the input ones, the core will
580 * or that with a cached value of the control ones)
581 * The port lock is not held.
582 */
583 static unsigned int pmz_get_mctrl(struct uart_port *port)
584 {
585 struct uart_pmac_port *uap = to_pmz(port);
586 unsigned char status;
587 unsigned int ret;
588
589 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
590 return 0;
591
592 status = pmz_peek_status(to_pmz(port));
593
594 ret = 0;
595 if (status & DCD)
596 ret |= TIOCM_CAR;
597 if (status & SYNC_HUNT)
598 ret |= TIOCM_DSR;
599 if (!(status & CTS))
600 ret |= TIOCM_CTS;
601
602 return ret;
603 }
604
605 /*
606 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
607 * though for DMA, we will have to do a bit more. What is
608 * the meaning of the tty_stop bit ? XXX
609 * The port lock is held and interrupts are disabled.
610 */
611 static void pmz_stop_tx(struct uart_port *port, unsigned int tty_stop)
612 {
613 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
614 }
615
616 /*
617 * Kick the Tx side.
618 * The port lock is held and interrupts are disabled.
619 */
620 static void pmz_start_tx(struct uart_port *port, unsigned int tty_start)
621 {
622 struct uart_pmac_port *uap = to_pmz(port);
623 unsigned char status;
624
625 pmz_debug("pmz: start_tx()\n");
626
627 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
628 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
629
630 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
631 return;
632
633 status = read_zsreg(uap, R0);
634
635 /* TX busy? Just wait for the TX done interrupt. */
636 if (!(status & Tx_BUF_EMP))
637 return;
638
639 /* Send the first character to jump-start the TX done
640 * IRQ sending engine.
641 */
642 if (port->x_char) {
643 write_zsdata(uap, port->x_char);
644 zssync(uap);
645 port->icount.tx++;
646 port->x_char = 0;
647 } else {
648 struct circ_buf *xmit = &port->info->xmit;
649
650 write_zsdata(uap, xmit->buf[xmit->tail]);
651 zssync(uap);
652 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
653 port->icount.tx++;
654
655 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
656 uart_write_wakeup(&uap->port);
657 }
658 pmz_debug("pmz: start_tx() done.\n");
659 }
660
661 /*
662 * Stop Rx side, basically disable emitting of
663 * Rx interrupts on the port. We don't disable the rx
664 * side of the chip proper though
665 * The port lock is held.
666 */
667 static void pmz_stop_rx(struct uart_port *port)
668 {
669 struct uart_pmac_port *uap = to_pmz(port);
670
671 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
672 return;
673
674 pmz_debug("pmz: stop_rx()()\n");
675
676 /* Disable all RX interrupts. */
677 uap->curregs[R1] &= ~RxINT_MASK;
678 pmz_maybe_update_regs(uap);
679
680 pmz_debug("pmz: stop_rx() done.\n");
681 }
682
683 /*
684 * Enable modem status change interrupts
685 * The port lock is held.
686 */
687 static void pmz_enable_ms(struct uart_port *port)
688 {
689 struct uart_pmac_port *uap = to_pmz(port);
690 unsigned char new_reg;
691
692 if (ZS_IS_IRDA(uap) || uap->node == NULL)
693 return;
694 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
695 if (new_reg != uap->curregs[R15]) {
696 uap->curregs[R15] = new_reg;
697
698 if (ZS_IS_ASLEEP(uap))
699 return;
700 /* NOTE: Not subject to 'transmitter active' rule. */
701 write_zsreg(uap, R15, uap->curregs[R15]);
702 }
703 }
704
705 /*
706 * Control break state emission
707 * The port lock is not held.
708 */
709 static void pmz_break_ctl(struct uart_port *port, int break_state)
710 {
711 struct uart_pmac_port *uap = to_pmz(port);
712 unsigned char set_bits, clear_bits, new_reg;
713 unsigned long flags;
714
715 if (uap->node == NULL)
716 return;
717 set_bits = clear_bits = 0;
718
719 if (break_state)
720 set_bits |= SND_BRK;
721 else
722 clear_bits |= SND_BRK;
723
724 spin_lock_irqsave(&port->lock, flags);
725
726 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
727 if (new_reg != uap->curregs[R5]) {
728 uap->curregs[R5] = new_reg;
729
730 /* NOTE: Not subject to 'transmitter active' rule. */
731 if (ZS_IS_ASLEEP(uap))
732 return;
733 write_zsreg(uap, R5, uap->curregs[R5]);
734 }
735
736 spin_unlock_irqrestore(&port->lock, flags);
737 }
738
739 /*
740 * Turn power on or off to the SCC and associated stuff
741 * (port drivers, modem, IR port, etc.)
742 * Returns the number of milliseconds we should wait before
743 * trying to use the port.
744 */
745 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
746 {
747 int delay = 0;
748 int rc;
749
750 if (state) {
751 rc = pmac_call_feature(
752 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
753 pmz_debug("port power on result: %d\n", rc);
754 if (ZS_IS_INTMODEM(uap)) {
755 rc = pmac_call_feature(
756 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
757 delay = 2500; /* wait for 2.5s before using */
758 pmz_debug("modem power result: %d\n", rc);
759 }
760 } else {
761 /* TODO: Make that depend on a timer, don't power down
762 * immediately
763 */
764 if (ZS_IS_INTMODEM(uap)) {
765 rc = pmac_call_feature(
766 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
767 pmz_debug("port power off result: %d\n", rc);
768 }
769 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
770 }
771 return delay;
772 }
773
774 /*
775 * FixZeroBug....Works around a bug in the SCC receving channel.
776 * Inspired from Darwin code, 15 Sept. 2000 -DanM
777 *
778 * The following sequence prevents a problem that is seen with O'Hare ASICs
779 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
780 * at the input to the receiver becomes 'stuck' and locks up the receiver.
781 * This problem can occur as a result of a zero bit at the receiver input
782 * coincident with any of the following events:
783 *
784 * The SCC is initialized (hardware or software).
785 * A framing error is detected.
786 * The clocking option changes from synchronous or X1 asynchronous
787 * clocking to X16, X32, or X64 asynchronous clocking.
788 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
789 *
790 * This workaround attempts to recover from the lockup condition by placing
791 * the SCC in synchronous loopback mode with a fast clock before programming
792 * any of the asynchronous modes.
793 */
794 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
795 {
796 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
797 zssync(uap);
798 udelay(10);
799 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
800 zssync(uap);
801
802 write_zsreg(uap, 4, X1CLK | MONSYNC);
803 write_zsreg(uap, 3, Rx8);
804 write_zsreg(uap, 5, Tx8 | RTS);
805 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
806 write_zsreg(uap, 11, RCBR | TCBR);
807 write_zsreg(uap, 12, 0);
808 write_zsreg(uap, 13, 0);
809 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
810 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
811 write_zsreg(uap, 3, Rx8 | RxENABLE);
812 write_zsreg(uap, 0, RES_EXT_INT);
813 write_zsreg(uap, 0, RES_EXT_INT);
814 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
815
816 /* The channel should be OK now, but it is probably receiving
817 * loopback garbage.
818 * Switch to asynchronous mode, disable the receiver,
819 * and discard everything in the receive buffer.
820 */
821 write_zsreg(uap, 9, NV);
822 write_zsreg(uap, 4, X16CLK | SB_MASK);
823 write_zsreg(uap, 3, Rx8);
824
825 while (read_zsreg(uap, 0) & Rx_CH_AV) {
826 (void)read_zsreg(uap, 8);
827 write_zsreg(uap, 0, RES_EXT_INT);
828 write_zsreg(uap, 0, ERR_RES);
829 }
830 }
831
832 /*
833 * Real startup routine, powers up the hardware and sets up
834 * the SCC. Returns a delay in ms where you need to wait before
835 * actually using the port, this is typically the internal modem
836 * powerup delay. This routine expect the lock to be taken.
837 */
838 static int __pmz_startup(struct uart_pmac_port *uap)
839 {
840 int pwr_delay = 0;
841
842 memset(&uap->curregs, 0, sizeof(uap->curregs));
843
844 /* Power up the SCC & underlying hardware (modem/irda) */
845 pwr_delay = pmz_set_scc_power(uap, 1);
846
847 /* Nice buggy HW ... */
848 pmz_fix_zero_bug_scc(uap);
849
850 /* Reset the channel */
851 uap->curregs[R9] = 0;
852 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
853 zssync(uap);
854 udelay(10);
855 write_zsreg(uap, 9, 0);
856 zssync(uap);
857
858 /* Clear the interrupt registers */
859 write_zsreg(uap, R1, 0);
860 write_zsreg(uap, R0, ERR_RES);
861 write_zsreg(uap, R0, ERR_RES);
862 write_zsreg(uap, R0, RES_H_IUS);
863 write_zsreg(uap, R0, RES_H_IUS);
864
865 /* Setup some valid baud rate */
866 uap->curregs[R4] = X16CLK | SB1;
867 uap->curregs[R3] = Rx8;
868 uap->curregs[R5] = Tx8 | RTS;
869 if (!ZS_IS_IRDA(uap))
870 uap->curregs[R5] |= DTR;
871 uap->curregs[R12] = 0;
872 uap->curregs[R13] = 0;
873 uap->curregs[R14] = BRENAB;
874
875 /* Clear handshaking */
876 uap->curregs[R15] = 0;
877
878 /* Master interrupt enable */
879 uap->curregs[R9] |= NV | MIE;
880
881 pmz_load_zsregs(uap, uap->curregs);
882
883 /* Enable receiver and transmitter. */
884 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
885 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
886
887 /* Remember status for DCD/CTS changes */
888 uap->prev_status = read_zsreg(uap, R0);
889
890
891 return pwr_delay;
892 }
893
894 static void pmz_irda_reset(struct uart_pmac_port *uap)
895 {
896 uap->curregs[R5] |= DTR;
897 write_zsreg(uap, R5, uap->curregs[R5]);
898 zssync(uap);
899 mdelay(110);
900 uap->curregs[R5] &= ~DTR;
901 write_zsreg(uap, R5, uap->curregs[R5]);
902 zssync(uap);
903 mdelay(10);
904 }
905
906 /*
907 * This is the "normal" startup routine, using the above one
908 * wrapped with the lock and doing a schedule delay
909 */
910 static int pmz_startup(struct uart_port *port)
911 {
912 struct uart_pmac_port *uap = to_pmz(port);
913 unsigned long flags;
914 int pwr_delay = 0;
915
916 pmz_debug("pmz: startup()\n");
917
918 if (ZS_IS_ASLEEP(uap))
919 return -EAGAIN;
920 if (uap->node == NULL)
921 return -ENODEV;
922
923 down(&pmz_irq_sem);
924
925 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
926
927 /* A console is never powered down. Else, power up and
928 * initialize the chip
929 */
930 if (!ZS_IS_CONS(uap)) {
931 spin_lock_irqsave(&port->lock, flags);
932 pwr_delay = __pmz_startup(uap);
933 spin_unlock_irqrestore(&port->lock, flags);
934 }
935
936 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
937 if (request_irq(uap->port.irq, pmz_interrupt, SA_SHIRQ, "PowerMac Zilog", uap)) {
938 dev_err(&uap->dev->ofdev.dev,
939 "Unable to register zs interrupt handler.\n");
940 pmz_set_scc_power(uap, 0);
941 up(&pmz_irq_sem);
942 return -ENXIO;
943 }
944
945 up(&pmz_irq_sem);
946
947 /* Right now, we deal with delay by blocking here, I'll be
948 * smarter later on
949 */
950 if (pwr_delay != 0) {
951 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
952 set_current_state(TASK_UNINTERRUPTIBLE);
953 schedule_timeout((pwr_delay * HZ)/1000);
954 }
955
956 /* IrDA reset is done now */
957 if (ZS_IS_IRDA(uap))
958 pmz_irda_reset(uap);
959
960 /* Enable interrupts emission from the chip */
961 spin_lock_irqsave(&port->lock, flags);
962 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
963 if (!ZS_IS_EXTCLK(uap))
964 uap->curregs[R1] |= EXT_INT_ENAB;
965 write_zsreg(uap, R1, uap->curregs[R1]);
966 spin_unlock_irqrestore(&port->lock, flags);
967
968 pmz_debug("pmz: startup() done.\n");
969
970 return 0;
971 }
972
973 static void pmz_shutdown(struct uart_port *port)
974 {
975 struct uart_pmac_port *uap = to_pmz(port);
976 unsigned long flags;
977
978 pmz_debug("pmz: shutdown()\n");
979
980 if (uap->node == NULL)
981 return;
982
983 down(&pmz_irq_sem);
984
985 /* Release interrupt handler */
986 free_irq(uap->port.irq, uap);
987
988 spin_lock_irqsave(&port->lock, flags);
989
990 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
991
992 if (!ZS_IS_OPEN(uap->mate))
993 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
994
995 /* Disable interrupts */
996 if (!ZS_IS_ASLEEP(uap)) {
997 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
998 write_zsreg(uap, R1, uap->curregs[R1]);
999 zssync(uap);
1000 }
1001
1002 if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) {
1003 spin_unlock_irqrestore(&port->lock, flags);
1004 up(&pmz_irq_sem);
1005 return;
1006 }
1007
1008 /* Disable receiver and transmitter. */
1009 uap->curregs[R3] &= ~RxENABLE;
1010 uap->curregs[R5] &= ~TxENABLE;
1011
1012 /* Disable all interrupts and BRK assertion. */
1013 uap->curregs[R5] &= ~SND_BRK;
1014 pmz_maybe_update_regs(uap);
1015
1016 /* Shut the chip down */
1017 pmz_set_scc_power(uap, 0);
1018
1019 spin_unlock_irqrestore(&port->lock, flags);
1020
1021 up(&pmz_irq_sem);
1022
1023 pmz_debug("pmz: shutdown() done.\n");
1024 }
1025
1026 /* Shared by TTY driver and serial console setup. The port lock is held
1027 * and local interrupts are disabled.
1028 */
1029 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
1030 unsigned int iflag, unsigned long baud)
1031 {
1032 int brg;
1033
1034
1035 /* Switch to external clocking for IrDA high clock rates. That
1036 * code could be re-used for Midi interfaces with different
1037 * multipliers
1038 */
1039 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1040 uap->curregs[R4] = X1CLK;
1041 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1042 uap->curregs[R14] = 0; /* BRG off */
1043 uap->curregs[R12] = 0;
1044 uap->curregs[R13] = 0;
1045 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1046 } else {
1047 switch (baud) {
1048 case ZS_CLOCK/16: /* 230400 */
1049 uap->curregs[R4] = X16CLK;
1050 uap->curregs[R11] = 0;
1051 uap->curregs[R14] = 0;
1052 break;
1053 case ZS_CLOCK/32: /* 115200 */
1054 uap->curregs[R4] = X32CLK;
1055 uap->curregs[R11] = 0;
1056 uap->curregs[R14] = 0;
1057 break;
1058 default:
1059 uap->curregs[R4] = X16CLK;
1060 uap->curregs[R11] = TCBR | RCBR;
1061 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1062 uap->curregs[R12] = (brg & 255);
1063 uap->curregs[R13] = ((brg >> 8) & 255);
1064 uap->curregs[R14] = BRENAB;
1065 }
1066 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1067 }
1068
1069 /* Character size, stop bits, and parity. */
1070 uap->curregs[3] &= ~RxN_MASK;
1071 uap->curregs[5] &= ~TxN_MASK;
1072
1073 switch (cflag & CSIZE) {
1074 case CS5:
1075 uap->curregs[3] |= Rx5;
1076 uap->curregs[5] |= Tx5;
1077 uap->parity_mask = 0x1f;
1078 break;
1079 case CS6:
1080 uap->curregs[3] |= Rx6;
1081 uap->curregs[5] |= Tx6;
1082 uap->parity_mask = 0x3f;
1083 break;
1084 case CS7:
1085 uap->curregs[3] |= Rx7;
1086 uap->curregs[5] |= Tx7;
1087 uap->parity_mask = 0x7f;
1088 break;
1089 case CS8:
1090 default:
1091 uap->curregs[3] |= Rx8;
1092 uap->curregs[5] |= Tx8;
1093 uap->parity_mask = 0xff;
1094 break;
1095 };
1096 uap->curregs[4] &= ~(SB_MASK);
1097 if (cflag & CSTOPB)
1098 uap->curregs[4] |= SB2;
1099 else
1100 uap->curregs[4] |= SB1;
1101 if (cflag & PARENB)
1102 uap->curregs[4] |= PAR_ENAB;
1103 else
1104 uap->curregs[4] &= ~PAR_ENAB;
1105 if (!(cflag & PARODD))
1106 uap->curregs[4] |= PAR_EVEN;
1107 else
1108 uap->curregs[4] &= ~PAR_EVEN;
1109
1110 uap->port.read_status_mask = Rx_OVR;
1111 if (iflag & INPCK)
1112 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1113 if (iflag & (BRKINT | PARMRK))
1114 uap->port.read_status_mask |= BRK_ABRT;
1115
1116 uap->port.ignore_status_mask = 0;
1117 if (iflag & IGNPAR)
1118 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1119 if (iflag & IGNBRK) {
1120 uap->port.ignore_status_mask |= BRK_ABRT;
1121 if (iflag & IGNPAR)
1122 uap->port.ignore_status_mask |= Rx_OVR;
1123 }
1124
1125 if ((cflag & CREAD) == 0)
1126 uap->port.ignore_status_mask = 0xff;
1127 }
1128
1129
1130 /*
1131 * Set the irda codec on the imac to the specified baud rate.
1132 */
1133 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1134 {
1135 u8 cmdbyte;
1136 int t, version;
1137
1138 switch (*baud) {
1139 /* SIR modes */
1140 case 2400:
1141 cmdbyte = 0x53;
1142 break;
1143 case 4800:
1144 cmdbyte = 0x52;
1145 break;
1146 case 9600:
1147 cmdbyte = 0x51;
1148 break;
1149 case 19200:
1150 cmdbyte = 0x50;
1151 break;
1152 case 38400:
1153 cmdbyte = 0x4f;
1154 break;
1155 case 57600:
1156 cmdbyte = 0x4e;
1157 break;
1158 case 115200:
1159 cmdbyte = 0x4d;
1160 break;
1161 /* The FIR modes aren't really supported at this point, how
1162 * do we select the speed ? via the FCR on KeyLargo ?
1163 */
1164 case 1152000:
1165 cmdbyte = 0;
1166 break;
1167 case 4000000:
1168 cmdbyte = 0;
1169 break;
1170 default: /* 9600 */
1171 cmdbyte = 0x51;
1172 *baud = 9600;
1173 break;
1174 }
1175
1176 /* Wait for transmitter to drain */
1177 t = 10000;
1178 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1179 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1180 if (--t <= 0) {
1181 dev_err(&uap->dev->ofdev.dev, "transmitter didn't drain\n");
1182 return;
1183 }
1184 udelay(10);
1185 }
1186
1187 /* Drain the receiver too */
1188 t = 100;
1189 (void)read_zsdata(uap);
1190 (void)read_zsdata(uap);
1191 (void)read_zsdata(uap);
1192 mdelay(10);
1193 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1194 read_zsdata(uap);
1195 mdelay(10);
1196 if (--t <= 0) {
1197 dev_err(&uap->dev->ofdev.dev, "receiver didn't drain\n");
1198 return;
1199 }
1200 }
1201
1202 /* Switch to command mode */
1203 uap->curregs[R5] |= DTR;
1204 write_zsreg(uap, R5, uap->curregs[R5]);
1205 zssync(uap);
1206 mdelay(1);
1207
1208 /* Switch SCC to 19200 */
1209 pmz_convert_to_zs(uap, CS8, 0, 19200);
1210 pmz_load_zsregs(uap, uap->curregs);
1211 mdelay(1);
1212
1213 /* Write get_version command byte */
1214 write_zsdata(uap, 1);
1215 t = 5000;
1216 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1217 if (--t <= 0) {
1218 dev_err(&uap->dev->ofdev.dev,
1219 "irda_setup timed out on get_version byte\n");
1220 goto out;
1221 }
1222 udelay(10);
1223 }
1224 version = read_zsdata(uap);
1225
1226 if (version < 4) {
1227 dev_info(&uap->dev->ofdev.dev, "IrDA: dongle version %d not supported\n",
1228 version);
1229 goto out;
1230 }
1231
1232 /* Send speed mode */
1233 write_zsdata(uap, cmdbyte);
1234 t = 5000;
1235 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1236 if (--t <= 0) {
1237 dev_err(&uap->dev->ofdev.dev,
1238 "irda_setup timed out on speed mode byte\n");
1239 goto out;
1240 }
1241 udelay(10);
1242 }
1243 t = read_zsdata(uap);
1244 if (t != cmdbyte)
1245 dev_err(&uap->dev->ofdev.dev,
1246 "irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1247
1248 dev_info(&uap->dev->ofdev.dev, "IrDA setup for %ld bps, dongle version: %d\n",
1249 *baud, version);
1250
1251 (void)read_zsdata(uap);
1252 (void)read_zsdata(uap);
1253 (void)read_zsdata(uap);
1254
1255 out:
1256 /* Switch back to data mode */
1257 uap->curregs[R5] &= ~DTR;
1258 write_zsreg(uap, R5, uap->curregs[R5]);
1259 zssync(uap);
1260
1261 (void)read_zsdata(uap);
1262 (void)read_zsdata(uap);
1263 (void)read_zsdata(uap);
1264 }
1265
1266
1267 static void __pmz_set_termios(struct uart_port *port, struct termios *termios,
1268 struct termios *old)
1269 {
1270 struct uart_pmac_port *uap = to_pmz(port);
1271 unsigned long baud;
1272
1273 pmz_debug("pmz: set_termios()\n");
1274
1275 if (ZS_IS_ASLEEP(uap))
1276 return;
1277
1278 memcpy(&uap->termios_cache, termios, sizeof(struct termios));
1279
1280 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1281 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1282 * about the FIR mode and high speed modes. So these are unused. For
1283 * implementing proper support for these, we should probably add some
1284 * DMA as well, at least on the Rx side, which isn't a simple thing
1285 * at this point.
1286 */
1287 if (ZS_IS_IRDA(uap)) {
1288 /* Calc baud rate */
1289 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1290 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1291 /* Cet the irda codec to the right rate */
1292 pmz_irda_setup(uap, &baud);
1293 /* Set final baud rate */
1294 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1295 pmz_load_zsregs(uap, uap->curregs);
1296 zssync(uap);
1297 } else {
1298 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1299 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1300 /* Make sure modem status interrupts are correctly configured */
1301 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1302 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1303 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1304 } else {
1305 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1306 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1307 }
1308
1309 /* Load registers to the chip */
1310 pmz_maybe_update_regs(uap);
1311 }
1312 pmz_debug("pmz: set_termios() done.\n");
1313 }
1314
1315 /* The port lock is not held. */
1316 static void pmz_set_termios(struct uart_port *port, struct termios *termios,
1317 struct termios *old)
1318 {
1319 struct uart_pmac_port *uap = to_pmz(port);
1320 unsigned long flags;
1321
1322 spin_lock_irqsave(&port->lock, flags);
1323
1324 /* Disable IRQs on the port */
1325 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1326 write_zsreg(uap, R1, uap->curregs[R1]);
1327
1328 /* Setup new port configuration */
1329 __pmz_set_termios(port, termios, old);
1330
1331 /* Re-enable IRQs on the port */
1332 if (ZS_IS_OPEN(uap)) {
1333 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1334 if (!ZS_IS_EXTCLK(uap))
1335 uap->curregs[R1] |= EXT_INT_ENAB;
1336 write_zsreg(uap, R1, uap->curregs[R1]);
1337 }
1338 spin_unlock_irqrestore(&port->lock, flags);
1339 }
1340
1341 static const char *pmz_type(struct uart_port *port)
1342 {
1343 struct uart_pmac_port *uap = to_pmz(port);
1344
1345 if (ZS_IS_IRDA(uap))
1346 return "Z85c30 ESCC - Infrared port";
1347 else if (ZS_IS_INTMODEM(uap))
1348 return "Z85c30 ESCC - Internal modem";
1349 return "Z85c30 ESCC - Serial port";
1350 }
1351
1352 /* We do not request/release mappings of the registers here, this
1353 * happens at early serial probe time.
1354 */
1355 static void pmz_release_port(struct uart_port *port)
1356 {
1357 }
1358
1359 static int pmz_request_port(struct uart_port *port)
1360 {
1361 return 0;
1362 }
1363
1364 /* These do not need to do anything interesting either. */
1365 static void pmz_config_port(struct uart_port *port, int flags)
1366 {
1367 }
1368
1369 /* We do not support letting the user mess with the divisor, IRQ, etc. */
1370 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1371 {
1372 return -EINVAL;
1373 }
1374
1375 static struct uart_ops pmz_pops = {
1376 .tx_empty = pmz_tx_empty,
1377 .set_mctrl = pmz_set_mctrl,
1378 .get_mctrl = pmz_get_mctrl,
1379 .stop_tx = pmz_stop_tx,
1380 .start_tx = pmz_start_tx,
1381 .stop_rx = pmz_stop_rx,
1382 .enable_ms = pmz_enable_ms,
1383 .break_ctl = pmz_break_ctl,
1384 .startup = pmz_startup,
1385 .shutdown = pmz_shutdown,
1386 .set_termios = pmz_set_termios,
1387 .type = pmz_type,
1388 .release_port = pmz_release_port,
1389 .request_port = pmz_request_port,
1390 .config_port = pmz_config_port,
1391 .verify_port = pmz_verify_port,
1392 };
1393
1394 /*
1395 * Setup one port structure after probing, HW is down at this point,
1396 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1397 * register our console before uart_add_one_port() is called
1398 */
1399 static int __init pmz_init_port(struct uart_pmac_port *uap)
1400 {
1401 struct device_node *np = uap->node;
1402 char *conn;
1403 struct slot_names_prop {
1404 int count;
1405 char name[1];
1406 } *slots;
1407 int len;
1408
1409 /*
1410 * Request & map chip registers
1411 */
1412 uap->port.mapbase = np->addrs[0].address;
1413 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1414
1415 uap->control_reg = (volatile u8 *)uap->port.membase;
1416 uap->data_reg = uap->control_reg + 0x10;
1417
1418 /*
1419 * Request & map DBDMA registers
1420 */
1421 #ifdef HAS_DBDMA
1422 if (np->n_addrs >= 3 && np->n_intrs >= 3)
1423 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1424 #endif
1425 if (ZS_HAS_DMA(uap)) {
1426 uap->tx_dma_regs = (volatile struct dbdma_regs *)
1427 ioremap(np->addrs[np->n_addrs - 2].address, 0x1000);
1428 if (uap->tx_dma_regs == NULL) {
1429 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1430 goto no_dma;
1431 }
1432 uap->rx_dma_regs = (volatile struct dbdma_regs *)
1433 ioremap(np->addrs[np->n_addrs - 1].address, 0x1000);
1434 if (uap->rx_dma_regs == NULL) {
1435 iounmap((void *)uap->tx_dma_regs);
1436 uap->tx_dma_regs = NULL;
1437 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1438 goto no_dma;
1439 }
1440 uap->tx_dma_irq = np->intrs[1].line;
1441 uap->rx_dma_irq = np->intrs[2].line;
1442 }
1443 no_dma:
1444
1445 /*
1446 * Detect port type
1447 */
1448 if (device_is_compatible(np, "cobalt"))
1449 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1450 conn = get_property(np, "AAPL,connector", &len);
1451 if (conn && (strcmp(conn, "infrared") == 0))
1452 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1453 uap->port_type = PMAC_SCC_ASYNC;
1454 /* 1999 Powerbook G3 has slot-names property instead */
1455 slots = (struct slot_names_prop *)get_property(np, "slot-names", &len);
1456 if (slots && slots->count > 0) {
1457 if (strcmp(slots->name, "IrDA") == 0)
1458 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1459 else if (strcmp(slots->name, "Modem") == 0)
1460 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1461 }
1462 if (ZS_IS_IRDA(uap))
1463 uap->port_type = PMAC_SCC_IRDA;
1464 if (ZS_IS_INTMODEM(uap)) {
1465 struct device_node* i2c_modem = find_devices("i2c-modem");
1466 if (i2c_modem) {
1467 char* mid = get_property(i2c_modem, "modem-id", NULL);
1468 if (mid) switch(*mid) {
1469 case 0x04 :
1470 case 0x05 :
1471 case 0x07 :
1472 case 0x08 :
1473 case 0x0b :
1474 case 0x0c :
1475 uap->port_type = PMAC_SCC_I2S1;
1476 }
1477 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1478 mid ? (*mid) : 0);
1479 } else {
1480 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1481 }
1482 }
1483
1484 /*
1485 * Init remaining bits of "port" structure
1486 */
1487 uap->port.iotype = SERIAL_IO_MEM;
1488 uap->port.irq = np->intrs[0].line;
1489 uap->port.uartclk = ZS_CLOCK;
1490 uap->port.fifosize = 1;
1491 uap->port.ops = &pmz_pops;
1492 uap->port.type = PORT_PMAC_ZILOG;
1493 uap->port.flags = 0;
1494
1495 /* Setup some valid baud rate information in the register
1496 * shadows so we don't write crap there before baud rate is
1497 * first initialized.
1498 */
1499 pmz_convert_to_zs(uap, CS8, 0, 9600);
1500
1501 return 0;
1502 }
1503
1504 /*
1505 * Get rid of a port on module removal
1506 */
1507 static void pmz_dispose_port(struct uart_pmac_port *uap)
1508 {
1509 struct device_node *np;
1510
1511 np = uap->node;
1512 iounmap((void *)uap->rx_dma_regs);
1513 iounmap((void *)uap->tx_dma_regs);
1514 iounmap((void *)uap->control_reg);
1515 uap->node = NULL;
1516 of_node_put(np);
1517 memset(uap, 0, sizeof(struct uart_pmac_port));
1518 }
1519
1520 /*
1521 * Called upon match with an escc node in the devive-tree.
1522 */
1523 static int pmz_attach(struct macio_dev *mdev, const struct of_match *match)
1524 {
1525 int i;
1526
1527 /* Iterate the pmz_ports array to find a matching entry
1528 */
1529 for (i = 0; i < MAX_ZS_PORTS; i++)
1530 if (pmz_ports[i].node == mdev->ofdev.node) {
1531 struct uart_pmac_port *uap = &pmz_ports[i];
1532
1533 uap->dev = mdev;
1534 dev_set_drvdata(&mdev->ofdev.dev, uap);
1535 if (macio_request_resources(uap->dev, "pmac_zilog"))
1536 printk(KERN_WARNING "%s: Failed to request resource"
1537 ", port still active\n",
1538 uap->node->name);
1539 else
1540 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1541 return 0;
1542 }
1543 return -ENODEV;
1544 }
1545
1546 /*
1547 * That one should not be called, macio isn't really a hotswap device,
1548 * we don't expect one of those serial ports to go away...
1549 */
1550 static int pmz_detach(struct macio_dev *mdev)
1551 {
1552 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1553
1554 if (!uap)
1555 return -ENODEV;
1556
1557 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1558 macio_release_resources(uap->dev);
1559 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1560 }
1561 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1562 uap->dev = NULL;
1563
1564 return 0;
1565 }
1566
1567
1568 static int pmz_suspend(struct macio_dev *mdev, u32 pm_state)
1569 {
1570 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1571 struct uart_state *state;
1572 unsigned long flags;
1573
1574 if (uap == NULL) {
1575 printk("HRM... pmz_suspend with NULL uap\n");
1576 return 0;
1577 }
1578
1579 if (pm_state == mdev->ofdev.dev.power_state || pm_state < 2)
1580 return 0;
1581
1582 pmz_debug("suspend, switching to state %d\n", pm_state);
1583
1584 state = pmz_uart_reg.state + uap->port.line;
1585
1586 down(&pmz_irq_sem);
1587 down(&state->sem);
1588
1589 spin_lock_irqsave(&uap->port.lock, flags);
1590
1591 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
1592 /* Disable receiver and transmitter. */
1593 uap->curregs[R3] &= ~RxENABLE;
1594 uap->curregs[R5] &= ~TxENABLE;
1595
1596 /* Disable all interrupts and BRK assertion. */
1597 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1598 uap->curregs[R5] &= ~SND_BRK;
1599 pmz_load_zsregs(uap, uap->curregs);
1600 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
1601 mb();
1602 }
1603
1604 spin_unlock_irqrestore(&uap->port.lock, flags);
1605
1606 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate))
1607 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1608 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1609 disable_irq(uap->port.irq);
1610 }
1611
1612 if (ZS_IS_CONS(uap))
1613 uap->port.cons->flags &= ~CON_ENABLED;
1614
1615 /* Shut the chip down */
1616 pmz_set_scc_power(uap, 0);
1617
1618 up(&state->sem);
1619 up(&pmz_irq_sem);
1620
1621 pmz_debug("suspend, switching complete\n");
1622
1623 mdev->ofdev.dev.power_state = pm_state;
1624
1625 return 0;
1626 }
1627
1628
1629 static int pmz_resume(struct macio_dev *mdev)
1630 {
1631 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1632 struct uart_state *state;
1633 unsigned long flags;
1634 int pwr_delay = 0;
1635
1636 if (uap == NULL)
1637 return 0;
1638
1639 if (mdev->ofdev.dev.power_state == 0)
1640 return 0;
1641
1642 pmz_debug("resume, switching to state 0\n");
1643
1644 state = pmz_uart_reg.state + uap->port.line;
1645
1646 down(&pmz_irq_sem);
1647 down(&state->sem);
1648
1649 spin_lock_irqsave(&uap->port.lock, flags);
1650 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) {
1651 spin_unlock_irqrestore(&uap->port.lock, flags);
1652 goto bail;
1653 }
1654 pwr_delay = __pmz_startup(uap);
1655
1656 /* Take care of config that may have changed while asleep */
1657 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
1658
1659 if (ZS_IS_OPEN(uap)) {
1660 /* Enable interrupts */
1661 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1662 if (!ZS_IS_EXTCLK(uap))
1663 uap->curregs[R1] |= EXT_INT_ENAB;
1664 write_zsreg(uap, R1, uap->curregs[R1]);
1665 }
1666
1667 spin_unlock_irqrestore(&uap->port.lock, flags);
1668
1669 if (ZS_IS_CONS(uap))
1670 uap->port.cons->flags |= CON_ENABLED;
1671
1672 /* Re-enable IRQ on the controller */
1673 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1674 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
1675 enable_irq(uap->port.irq);
1676 }
1677
1678 bail:
1679 up(&state->sem);
1680 up(&pmz_irq_sem);
1681
1682 /* Right now, we deal with delay by blocking here, I'll be
1683 * smarter later on
1684 */
1685 if (pwr_delay != 0) {
1686 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
1687 set_current_state(TASK_UNINTERRUPTIBLE);
1688 schedule_timeout((pwr_delay * HZ)/1000);
1689 }
1690
1691 pmz_debug("resume, switching complete\n");
1692
1693 mdev->ofdev.dev.power_state = 0;
1694
1695 return 0;
1696 }
1697
1698 /*
1699 * Probe all ports in the system and build the ports array, we register
1700 * with the serial layer at this point, the macio-type probing is only
1701 * used later to "attach" to the sysfs tree so we get power management
1702 * events
1703 */
1704 static int __init pmz_probe(void)
1705 {
1706 struct device_node *node_p, *node_a, *node_b, *np;
1707 int count = 0;
1708 int rc;
1709
1710 /*
1711 * Find all escc chips in the system
1712 */
1713 node_p = of_find_node_by_name(NULL, "escc");
1714 while (node_p) {
1715 /*
1716 * First get channel A/B node pointers
1717 *
1718 * TODO: Add routines with proper locking to do that...
1719 */
1720 node_a = node_b = NULL;
1721 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
1722 if (strncmp(np->name, "ch-a", 4) == 0)
1723 node_a = of_node_get(np);
1724 else if (strncmp(np->name, "ch-b", 4) == 0)
1725 node_b = of_node_get(np);
1726 }
1727 if (!node_a && !node_b) {
1728 of_node_put(node_a);
1729 of_node_put(node_b);
1730 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n",
1731 (!node_a) ? 'a' : 'b', node_p->full_name);
1732 goto next;
1733 }
1734
1735 /*
1736 * Fill basic fields in the port structures
1737 */
1738 pmz_ports[count].mate = &pmz_ports[count+1];
1739 pmz_ports[count+1].mate = &pmz_ports[count];
1740 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1741 pmz_ports[count].node = node_a;
1742 pmz_ports[count+1].node = node_b;
1743 pmz_ports[count].port.line = count;
1744 pmz_ports[count+1].port.line = count+1;
1745
1746 /*
1747 * Setup the ports for real
1748 */
1749 rc = pmz_init_port(&pmz_ports[count]);
1750 if (rc == 0 && node_b != NULL)
1751 rc = pmz_init_port(&pmz_ports[count+1]);
1752 if (rc != 0) {
1753 of_node_put(node_a);
1754 of_node_put(node_b);
1755 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1756 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1757 goto next;
1758 }
1759 count += 2;
1760 next:
1761 node_p = of_find_node_by_name(node_p, "escc");
1762 }
1763 pmz_ports_count = count;
1764
1765 return 0;
1766 }
1767
1768 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1769
1770 static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1771 static int __init pmz_console_setup(struct console *co, char *options);
1772
1773 static struct console pmz_console = {
1774 .name = "ttyS",
1775 .write = pmz_console_write,
1776 .device = uart_console_device,
1777 .setup = pmz_console_setup,
1778 .flags = CON_PRINTBUFFER,
1779 .index = -1,
1780 .data = &pmz_uart_reg,
1781 };
1782
1783 #define PMACZILOG_CONSOLE &pmz_console
1784 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1785 #define PMACZILOG_CONSOLE (NULL)
1786 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1787
1788 /*
1789 * Register the driver, console driver and ports with the serial
1790 * core
1791 */
1792 static int __init pmz_register(void)
1793 {
1794 int i, rc;
1795
1796 pmz_uart_reg.nr = pmz_ports_count;
1797 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1798 pmz_uart_reg.minor = 64;
1799
1800 /*
1801 * Register this driver with the serial core
1802 */
1803 rc = uart_register_driver(&pmz_uart_reg);
1804 if (rc)
1805 return rc;
1806
1807 /*
1808 * Register each port with the serial core
1809 */
1810 for (i = 0; i < pmz_ports_count; i++) {
1811 struct uart_pmac_port *uport = &pmz_ports[i];
1812 /* NULL node may happen on wallstreet */
1813 if (uport->node != NULL)
1814 rc = uart_add_one_port(&pmz_uart_reg, &uport->port);
1815 if (rc)
1816 goto err_out;
1817 }
1818
1819 return 0;
1820 err_out:
1821 while (i-- > 0) {
1822 struct uart_pmac_port *uport = &pmz_ports[i];
1823 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1824 }
1825 uart_unregister_driver(&pmz_uart_reg);
1826 return rc;
1827 }
1828
1829 static struct of_match pmz_match[] =
1830 {
1831 {
1832 .name = "ch-a",
1833 .type = OF_ANY_MATCH,
1834 .compatible = OF_ANY_MATCH
1835 },
1836 {
1837 .name = "ch-b",
1838 .type = OF_ANY_MATCH,
1839 .compatible = OF_ANY_MATCH
1840 },
1841 {},
1842 };
1843
1844 static struct macio_driver pmz_driver =
1845 {
1846 .name = "pmac_zilog",
1847 .match_table = pmz_match,
1848 .probe = pmz_attach,
1849 .remove = pmz_detach,
1850 .suspend = pmz_suspend,
1851 .resume = pmz_resume,
1852 };
1853
1854 static int __init init_pmz(void)
1855 {
1856 int rc, i;
1857 printk(KERN_INFO "%s\n", version);
1858
1859 /*
1860 * First, we need to do a direct OF-based probe pass. We
1861 * do that because we want serial console up before the
1862 * macio stuffs calls us back, and since that makes it
1863 * easier to pass the proper number of channels to
1864 * uart_register_driver()
1865 */
1866 if (pmz_ports_count == 0)
1867 pmz_probe();
1868
1869 /*
1870 * Bail early if no port found
1871 */
1872 if (pmz_ports_count == 0)
1873 return -ENODEV;
1874
1875 /*
1876 * Now we register with the serial layer
1877 */
1878 rc = pmz_register();
1879 if (rc) {
1880 printk(KERN_ERR
1881 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1882 "pmac_zilog: Did another serial driver already claim the minors?\n");
1883 /* effectively "pmz_unprobe()" */
1884 for (i=0; i < pmz_ports_count; i++)
1885 pmz_dispose_port(&pmz_ports[i]);
1886 return rc;
1887 }
1888
1889 /*
1890 * Then we register the macio driver itself
1891 */
1892 return macio_register_driver(&pmz_driver);
1893 }
1894
1895 static void __exit exit_pmz(void)
1896 {
1897 int i;
1898
1899 /* Get rid of macio-driver (detach from macio) */
1900 macio_unregister_driver(&pmz_driver);
1901
1902 for (i = 0; i < pmz_ports_count; i++) {
1903 struct uart_pmac_port *uport = &pmz_ports[i];
1904 if (uport->node != NULL) {
1905 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1906 pmz_dispose_port(uport);
1907 }
1908 }
1909 /* Unregister UART driver */
1910 uart_unregister_driver(&pmz_uart_reg);
1911 }
1912
1913 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1914
1915 /*
1916 * Print a string to the serial port trying not to disturb
1917 * any possible real use of the port...
1918 */
1919 static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1920 {
1921 struct uart_pmac_port *uap = &pmz_ports[con->index];
1922 unsigned long flags;
1923 int i;
1924
1925 spin_lock_irqsave(&uap->port.lock, flags);
1926
1927 /* Turn of interrupts and enable the transmitter. */
1928 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1929 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1930
1931 for (i = 0; i < count; i++) {
1932 /* Wait for the transmit buffer to empty. */
1933 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1934 udelay(5);
1935 write_zsdata(uap, s[i]);
1936 if (s[i] == 10) {
1937 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1938 udelay(5);
1939 write_zsdata(uap, R13);
1940 }
1941 }
1942
1943 /* Restore the values in the registers. */
1944 write_zsreg(uap, R1, uap->curregs[1]);
1945 /* Don't disable the transmitter. */
1946
1947 spin_unlock_irqrestore(&uap->port.lock, flags);
1948 }
1949
1950 /*
1951 * Setup the serial console
1952 */
1953 static int __init pmz_console_setup(struct console *co, char *options)
1954 {
1955 struct uart_pmac_port *uap;
1956 struct uart_port *port;
1957 int baud = 38400;
1958 int bits = 8;
1959 int parity = 'n';
1960 int flow = 'n';
1961 unsigned long pwr_delay;
1962
1963 /*
1964 * XServe's default to 57600 bps
1965 */
1966 if (machine_is_compatible("RackMac1,1")
1967 || machine_is_compatible("RackMac1,2")
1968 || machine_is_compatible("MacRISC4"))
1969 baud = 57600;
1970
1971 /*
1972 * Check whether an invalid uart number has been specified, and
1973 * if so, search for the first available port that does have
1974 * console support.
1975 */
1976 if (co->index >= pmz_ports_count)
1977 co->index = 0;
1978 uap = &pmz_ports[co->index];
1979 if (uap->node == NULL)
1980 return -ENODEV;
1981 port = &uap->port;
1982
1983 /*
1984 * Mark port as beeing a console
1985 */
1986 uap->flags |= PMACZILOG_FLAG_IS_CONS;
1987
1988 /*
1989 * Temporary fix for uart layer who didn't setup the spinlock yet
1990 */
1991 spin_lock_init(&port->lock);
1992
1993 /*
1994 * Enable the hardware
1995 */
1996 pwr_delay = __pmz_startup(uap);
1997 if (pwr_delay)
1998 mdelay(pwr_delay);
1999
2000 if (options)
2001 uart_parse_options(options, &baud, &parity, &bits, &flow);
2002
2003 return uart_set_options(port, co, baud, parity, bits, flow);
2004 }
2005
2006 static int __init pmz_console_init(void)
2007 {
2008 /* Probe ports */
2009 pmz_probe();
2010
2011 /* TODO: Autoprobe console based on OF */
2012 /* pmz_console.index = i; */
2013 register_console(&pmz_console);
2014
2015 return 0;
2016
2017 }
2018 console_initcall(pmz_console_init);
2019 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2020
2021 module_init(init_pmz);
2022 module_exit(exit_pmz);
MOXA 2.6.9 from sdlinux-moxaart.tgz