drivers/net/s2io.h

   1 /************************************************************************
   2  * s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
   3  * Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com)
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  ************************************************************************/
  13 #ifndef _S2IO_H
  14 #define _S2IO_H
  15
  16 #define TBD 0
  17 #define BIT(loc)                (0x8000000000000000ULL >> (loc))
  18 #define vBIT(val, loc, sz)      (((u64)val) << (64-loc-sz))
  19
  20 #ifndef BOOL
  21 #define BOOL    int
  22 #endif
  23
  24 #ifndef TRUE
  25 #define TRUE    1
  26 #define FALSE   0
  27 #endif
  28
  29 #undef SUCCESS
  30 #define SUCCESS 0
  31 #define FAILURE -1
  32
  33 /* Maximum outstanding splits to be configured into xena. */
  34 typedef enum xena_max_outstanding_splits {
  35         XENA_ONE_SPLIT_TRANSACTION = 0,
  36         XENA_TWO_SPLIT_TRANSACTION = 1,
  37         XENA_THREE_SPLIT_TRANSACTION = 2,
  38         XENA_FOUR_SPLIT_TRANSACTION = 3,
  39         XENA_EIGHT_SPLIT_TRANSACTION = 4,
  40         XENA_TWELVE_SPLIT_TRANSACTION = 5,
  41         XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
  42         XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
  43 } xena_max_outstanding_splits;
  44 #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
  45
  46 /*  OS concerned variables and constants */
  47 #define WATCH_DOG_TIMEOUT       5*HZ
  48 #define EFILL                           0x1234
  49 #define ALIGN_SIZE                      127
  50 #define PCIX_COMMAND_REGISTER   0x62
  51
  52 /*
  53  * Debug related variables.
  54  */
  55 #define DEBUG_ON TRUE
  56
  57 /* different debug levels. */
  58 #define ERR_DBG         0
  59 #define INIT_DBG        1
  60 #define INFO_DBG        2
  61 #define TX_DBG          3
  62 #define INTR_DBG        4
  63
  64 /* Global variable that defines the present debug level of the driver. */
  65 int debug_level = ERR_DBG;      /* Default level. */
  66
  67 /* DEBUG message print. */
  68 #define DBG_PRINT(dbg_level, args...)  if(!(debug_level<dbg_level)) printk(args)
  69
  70 /* Protocol assist features of the NIC */
  71 #define L3_CKSUM_OK 0xFFFF
  72 #define L4_CKSUM_OK 0xFFFF
  73 #define S2IO_JUMBO_SIZE 9600
  74
  75 /* The statistics block of Xena */
  76 typedef struct stat_block {
  77 #ifdef  __BIG_ENDIAN
  78 /* Tx MAC statistics counters. */
  79         u32 tmac_frms;
  80         u32 tmac_data_octets;
  81         u64 tmac_drop_frms;
  82         u32 tmac_mcst_frms;
  83         u32 tmac_bcst_frms;
  84         u64 tmac_pause_ctrl_frms;
  85         u32 tmac_ttl_octets;
  86         u32 tmac_ucst_frms;
  87         u32 tmac_nucst_frms;
  88         u32 tmac_any_err_frms;
  89         u64 tmac_ttl_less_fb_octets;
  90         u64 tmac_vld_ip_octets;
  91         u32 tmac_vld_ip;
  92         u32 tmac_drop_ip;
  93         u32 tmac_icmp;
  94         u32 tmac_rst_tcp;
  95         u64 tmac_tcp;
  96         u32 tmac_udp;
  97         u32 reserved_0;
  98
  99 /* Rx MAC Statistics counters. */
 100         u32 rmac_vld_frms;
 101         u32 rmac_data_octets;
 102         u64 rmac_fcs_err_frms;
 103         u64 rmac_drop_frms;
 104         u32 rmac_vld_mcst_frms;
 105         u32 rmac_vld_bcst_frms;
 106         u32 rmac_in_rng_len_err_frms;
 107         u32 rmac_out_rng_len_err_frms;
 108         u64 rmac_long_frms;
 109         u64 rmac_pause_ctrl_frms;
 110         u64 rmac_unsup_ctrl_frms;
 111         u32 rmac_ttl_octets;
 112         u32 rmac_accepted_ucst_frms;
 113         u32 rmac_accepted_nucst_frms;
 114         u32 rmac_discarded_frms;
 115         u32 rmac_drop_events;
 116         u32 reserved_1;
 117         u64 rmac_ttl_less_fb_octets;
 118         u64 rmac_ttl_frms;
 119         u64 reserved_2;
 120         u32 reserved_3;
 121         u32 rmac_usized_frms;
 122         u32 rmac_osized_frms;
 123         u32 rmac_frag_frms;
 124         u32 rmac_jabber_frms;
 125         u32 reserved_4;
 126         u64 rmac_ttl_64_frms;
 127         u64 rmac_ttl_65_127_frms;
 128         u64 reserved_5;
 129         u64 rmac_ttl_128_255_frms;
 130         u64 rmac_ttl_256_511_frms;
 131         u64 reserved_6;
 132         u64 rmac_ttl_512_1023_frms;
 133         u64 rmac_ttl_1024_1518_frms;
 134         u32 reserved_7;
 135         u32 rmac_ip;
 136         u64 rmac_ip_octets;
 137         u32 rmac_hdr_err_ip;
 138         u32 rmac_drop_ip;
 139         u32 rmac_icmp;
 140         u32 reserved_8;
 141         u64 rmac_tcp;
 142         u32 rmac_udp;
 143         u32 rmac_err_drp_udp;
 144         u64 rmac_xgmii_err_sym;
 145         u64 rmac_frms_q0;
 146         u64 rmac_frms_q1;
 147         u64 rmac_frms_q2;
 148         u64 rmac_frms_q3;
 149         u64 rmac_frms_q4;
 150         u64 rmac_frms_q5;
 151         u64 rmac_frms_q6;
 152         u64 rmac_frms_q7;
 153         u16 rmac_full_q0;
 154         u16 rmac_full_q1;
 155         u16 rmac_full_q2;
 156         u16 rmac_full_q3;
 157         u16 rmac_full_q4;
 158         u16 rmac_full_q5;
 159         u16 rmac_full_q6;
 160         u16 rmac_full_q7;
 161         u32 rmac_pause_cnt;
 162         u32 reserved_9;
 163         u64 rmac_xgmii_data_err_cnt;
 164         u64 rmac_xgmii_ctrl_err_cnt;
 165         u32 rmac_accepted_ip;
 166         u32 rmac_err_tcp;
 167
 168 /* PCI/PCI-X Read transaction statistics. */
 169         u32 rd_req_cnt;
 170         u32 new_rd_req_cnt;
 171         u32 new_rd_req_rtry_cnt;
 172         u32 rd_rtry_cnt;
 173         u32 wr_rtry_rd_ack_cnt;
 174
 175 /* PCI/PCI-X write transaction statistics. */
 176         u32 wr_req_cnt;
 177         u32 new_wr_req_cnt;
 178         u32 new_wr_req_rtry_cnt;
 179         u32 wr_rtry_cnt;
 180         u32 wr_disc_cnt;
 181         u32 rd_rtry_wr_ack_cnt;
 182
 183 /*      DMA Transaction statistics. */
 184         u32 txp_wr_cnt;
 185         u32 txd_rd_cnt;
 186         u32 txd_wr_cnt;
 187         u32 rxd_rd_cnt;
 188         u32 rxd_wr_cnt;
 189         u32 txf_rd_cnt;
 190         u32 rxf_wr_cnt;
 191 #else
 192 /* Tx MAC statistics counters. */
 193         u32 tmac_data_octets;
 194         u32 tmac_frms;
 195         u64 tmac_drop_frms;
 196         u32 tmac_bcst_frms;
 197         u32 tmac_mcst_frms;
 198         u64 tmac_pause_ctrl_frms;
 199         u32 tmac_ucst_frms;
 200         u32 tmac_ttl_octets;
 201         u32 tmac_any_err_frms;
 202         u32 tmac_nucst_frms;
 203         u64 tmac_ttl_less_fb_octets;
 204         u64 tmac_vld_ip_octets;
 205         u32 tmac_drop_ip;
 206         u32 tmac_vld_ip;
 207         u32 tmac_rst_tcp;
 208         u32 tmac_icmp;
 209         u64 tmac_tcp;
 210         u32 reserved_0;
 211         u32 tmac_udp;
 212
 213 /* Rx MAC Statistics counters. */
 214         u32 rmac_data_octets;
 215         u32 rmac_vld_frms;
 216         u64 rmac_fcs_err_frms;
 217         u64 rmac_drop_frms;
 218         u32 rmac_vld_bcst_frms;
 219         u32 rmac_vld_mcst_frms;
 220         u32 rmac_out_rng_len_err_frms;
 221         u32 rmac_in_rng_len_err_frms;
 222         u64 rmac_long_frms;
 223         u64 rmac_pause_ctrl_frms;
 224         u64 rmac_unsup_ctrl_frms;
 225         u32 rmac_accepted_ucst_frms;
 226         u32 rmac_ttl_octets;
 227         u32 rmac_discarded_frms;
 228         u32 rmac_accepted_nucst_frms;
 229         u32 reserved_1;
 230         u32 rmac_drop_events;
 231         u64 rmac_ttl_less_fb_octets;
 232         u64 rmac_ttl_frms;
 233         u64 reserved_2;
 234         u32 rmac_usized_frms;
 235         u32 reserved_3;
 236         u32 rmac_frag_frms;
 237         u32 rmac_osized_frms;
 238         u32 reserved_4;
 239         u32 rmac_jabber_frms;
 240         u64 rmac_ttl_64_frms;
 241         u64 rmac_ttl_65_127_frms;
 242         u64 reserved_5;
 243         u64 rmac_ttl_128_255_frms;
 244         u64 rmac_ttl_256_511_frms;
 245         u64 reserved_6;
 246         u64 rmac_ttl_512_1023_frms;
 247         u64 rmac_ttl_1024_1518_frms;
 248         u32 rmac_ip;
 249         u32 reserved_7;
 250         u64 rmac_ip_octets;
 251         u32 rmac_drop_ip;
 252         u32 rmac_hdr_err_ip;
 253         u32 reserved_8;
 254         u32 rmac_icmp;
 255         u64 rmac_tcp;
 256         u32 rmac_err_drp_udp;
 257         u32 rmac_udp;
 258         u64 rmac_xgmii_err_sym;
 259         u64 rmac_frms_q0;
 260         u64 rmac_frms_q1;
 261         u64 rmac_frms_q2;
 262         u64 rmac_frms_q3;
 263         u64 rmac_frms_q4;
 264         u64 rmac_frms_q5;
 265         u64 rmac_frms_q6;
 266         u64 rmac_frms_q7;
 267         u16 rmac_full_q3;
 268         u16 rmac_full_q2;
 269         u16 rmac_full_q1;
 270         u16 rmac_full_q0;
 271         u16 rmac_full_q7;
 272         u16 rmac_full_q6;
 273         u16 rmac_full_q5;
 274         u16 rmac_full_q4;
 275         u32 reserved_9;
 276         u32 rmac_pause_cnt;
 277         u64 rmac_xgmii_data_err_cnt;
 278         u64 rmac_xgmii_ctrl_err_cnt;
 279         u32 rmac_err_tcp;
 280         u32 rmac_accepted_ip;
 281
 282 /* PCI/PCI-X Read transaction statistics. */
 283         u32 new_rd_req_cnt;
 284         u32 rd_req_cnt;
 285         u32 rd_rtry_cnt;
 286         u32 new_rd_req_rtry_cnt;
 287
 288 /* PCI/PCI-X Write/Read transaction statistics. */
 289         u32 wr_req_cnt;
 290         u32 wr_rtry_rd_ack_cnt;
 291         u32 new_wr_req_rtry_cnt;
 292         u32 new_wr_req_cnt;
 293         u32 wr_disc_cnt;
 294         u32 wr_rtry_cnt;
 295
 296 /*      PCI/PCI-X Write / DMA Transaction statistics. */
 297         u32 txp_wr_cnt;
 298         u32 rd_rtry_wr_ack_cnt;
 299         u32 txd_wr_cnt;
 300         u32 txd_rd_cnt;
 301         u32 rxd_wr_cnt;
 302         u32 rxd_rd_cnt;
 303         u32 rxf_wr_cnt;
 304         u32 txf_rd_cnt;
 305 #endif
 306 } StatInfo_t;
 307
 308 /* Structures representing different init time configuration
 309  * parameters of the NIC.
 310  */
 311
 312 /* Maintains Per FIFO related information. */
 313 typedef struct tx_fifo_config {
 314 #define MAX_AVAILABLE_TXDS      8192
 315         u32 FifoLen;            /* specifies len of FIFO upto 8192, ie no of TxDLs */
 316 /* Priority definition */
 317 #define TX_FIFO_PRI_0               0   /*Highest */
 318 #define TX_FIFO_PRI_1               1
 319 #define TX_FIFO_PRI_2               2
 320 #define TX_FIFO_PRI_3               3
 321 #define TX_FIFO_PRI_4               4
 322 #define TX_FIFO_PRI_5               5
 323 #define TX_FIFO_PRI_6               6
 324 #define TX_FIFO_PRI_7               7   /*lowest */
 325         u8 FifoPriority;        /* specifies pointer level for FIFO */
 326         /* user should not set twos fifos with same pri */
 327         u8 fNoSnoop;
 328 #define NO_SNOOP_TXD                0x01
 329 #define NO_SNOOP_TXD_BUFFER          0x02
 330 } tx_fifo_config_t;
 331
 332
 333 /* Maintains per Ring related information */
 334 typedef struct rx_ring_config {
 335         u32 NumRxd;             /*No of RxDs per Rx Ring */
 336 #define RX_RING_PRI_0               0   /* highest */
 337 #define RX_RING_PRI_1               1
 338 #define RX_RING_PRI_2               2
 339 #define RX_RING_PRI_3               3
 340 #define RX_RING_PRI_4               4
 341 #define RX_RING_PRI_5               5
 342 #define RX_RING_PRI_6               6
 343 #define RX_RING_PRI_7               7   /* lowest */
 344
 345         u8 RingPriority;        /*Specifies service priority of ring */
 346         /* OSM should not set any two rings with same priority */
 347         u8 RingOrg;             /*Organization of ring */
 348 #define RING_ORG_BUFF1           0x01
 349 #define RX_RING_ORG_BUFF3           0x03
 350 #define RX_RING_ORG_BUFF5           0x05
 351
 352 /* In case of 3 buffer recv. mode, size of three buffers is expected as.. */
 353 #define BUFF_SZ_1                   22  /* ethernet header */
 354 #define BUFF_SZ_2                   (64+64)     /* max. IP+TCP header size */
 355 #define BUFF_SZ_3                   (1500-20-20)        /* TCP payload */
 356 #define BUFF_SZ_3_JUMBO             (9600-20-20)        /* Jumbo TCP payload */
 357
 358         u32 RxdThresh;          /*No of used Rxds NIC can store before transfer to host */
 359 #define DEFAULT_RXD_THRESHOLD       0x1 /* TODO */
 360         u8 fNoSnoop;
 361 #define NO_SNOOP_RXD                0x01
 362 #define NO_SNOOP_RXD_BUFFER         0x02
 363         u32 RxD_BackOff_Interval;
 364 #define RXD_BACKOFF_INTERVAL_DEF        0x0
 365 #define RXD_BACKOFF_INTERVAL_MIN        0x0
 366 #define RXD_BACKOFF_INTERVAL_MAX        0x0
 367 } rx_ring_config_t;
 368
 369 /* This structure provides contains values of the tunable parameters
 370  * of the H/W
 371  */
 372 struct config_param {
 373
 374 /* Tx Side */
 375         u32 TxFIFONum;          /*Number of Tx FIFOs */
 376 #define MAX_TX_FIFOS 8
 377
 378         tx_fifo_config_t TxCfg[MAX_TX_FIFOS];   /*Per-Tx FIFO config */
 379         u32 MaxTxDs;            /*Max no. of Tx buffer descriptor per TxDL */
 380         BOOL TxVLANEnable;      /*TRUE: Insert VLAN ID, FALSE: Don't insert */
 381 #define TX_REQ_TIMEOUT_DEFAULT          0x0
 382 #define TX_REQ_TIMEOUT_MIN              0x0
 383 #define TX_REQ_TIMEOUT_MAX              0x0
 384         u32 TxReqTimeOut;
 385         BOOL TxFlow;            /*Tx flow control enable */
 386         BOOL RxFlow;
 387         BOOL OverrideTxServiceState;    /* TRUE: Overide, FALSE: Do not override
 388                                            Use the new priority information
 389                                            of service state. It is not recommended
 390                                            to change but OSM can opt to do so */
 391 #define MAX_SERVICE_STATES  36
 392         u8 TxServiceState[MAX_SERVICE_STATES];
 393         /* Array element represent 'priority'
 394          * and array index represents
 395          *  'Service state' e.g.
 396          *  TxServiceState[3]=7; it means
 397          *  Service state 3 is associated
 398          *  with priority 7 of a Tx FIFO */
 399         u64 TxIntrType;         /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
 400
 401 /* Rx Side */
 402         u32 RxRingNum;          /*Number of receive rings */
 403 #define MAX_RX_RINGS 8
 404 #define MAX_RX_BLOCKS_PER_RING  150
 405
 406         rx_ring_config_t RxCfg[MAX_RX_RINGS];   /*Per-Rx Ring config */
 407         BOOL RxVLANEnable;      /*TRUE: Strip off VLAN tag from the frame,
 408                                    FALSE: Don't strip off VLAN tag */
 409
 410 #define HEADER_ETHERNET_II_802_3_SIZE 14
 411 #define HEADER_802_2_SIZE              3
 412 #define HEADER_SNAP_SIZE               5
 413 #define HEADER_VLAN_SIZE               4
 414
 415 #define MIN_MTU                       46
 416 #define MAX_PYLD                    1500
 417 #define MAX_MTU                     (MAX_PYLD+18)
 418 #define MAX_MTU_VLAN                (MAX_PYLD+22)
 419 #define MAX_PYLD_JUMBO              9600
 420 #define MAX_MTU_JUMBO               (MAX_PYLD_JUMBO+18)
 421 #define MAX_MTU_JUMBO_VLAN          (MAX_PYLD_JUMBO+22)
 422         u32 MTU;                /*Maximum Payload */
 423         BOOL JumboEnable;       /*Enable Jumbo frames recv/send */
 424         BOOL OverrideRxServiceState;    /* TRUE: Overide, FALSE: Do not override
 425                                            Use the new priority information
 426                                            of service state. It is not recommended
 427                                            to change but OSM can opt to do so */
 428 #define MAX_SERVICE_STATES  36
 429         u8 RxServiceState[MAX_SERVICE_STATES];
 430         /* Array element represent 'priority'
 431          * and array index represents
 432          * 'Service state'e.g.
 433          * RxServiceState[3]=7; it means
 434          * Service state 3 is associated
 435          * with priority 7 of a Rx FIFO */
 436         BOOL StatAutoRefresh;   /* When true, StatRefreshTime have valid value */
 437         u32 StatRefreshTime;    /*Time for refreshing statistics */
 438 #define     STAT_TRSF_PER_1_SECOND      0x208D5
 439 };
 440
 441 /* Structure representing MAC Addrs */
 442 typedef struct mac_addr {
 443         u8 mac_addr[ETH_ALEN];
 444 } macaddr_t;
 445
 446 /* Structure that represent every FIFO element in the BAR1
 447  * Address location.
 448  */
 449 typedef struct _TxFIFO_element {
 450         u64 TxDL_Pointer;
 451
 452         u64 List_Control;
 453 #define TX_FIFO_LAST_TXD_NUM( val)     vBIT(val,0,8)
 454 #define TX_FIFO_FIRST_LIST             BIT(14)
 455 #define TX_FIFO_LAST_LIST              BIT(15)
 456 #define TX_FIFO_FIRSTNLAST_LIST        vBIT(3,14,2)
 457 #define TX_FIFO_SPECIAL_FUNC           BIT(23)
 458 #define TX_FIFO_DS_NO_SNOOP            BIT(31)
 459 #define TX_FIFO_BUFF_NO_SNOOP          BIT(30)
 460 } TxFIFO_element_t;
 461
 462 /* Tx descriptor structure */
 463 typedef struct _TxD {
 464         u64 Control_1;
 465 /* bit mask */
 466 #define TXD_LIST_OWN_XENA       BIT(7)
 467 #define TXD_T_CODE              (BIT(12)|BIT(13)|BIT(14)|BIT(15))
 468 #define TXD_T_CODE_OK(val)      (|(val & TXD_T_CODE))
 469 #define GET_TXD_T_CODE(val)     ((val & TXD_T_CODE)<<12)
 470 #define TXD_GATHER_CODE         (BIT(22) | BIT(23))
 471 #define TXD_GATHER_CODE_FIRST   BIT(22)
 472 #define TXD_GATHER_CODE_LAST    BIT(23)
 473 #define TXD_TCP_LSO_EN          BIT(30)
 474 #define TXD_UDP_COF_EN          BIT(31)
 475 #define TXD_TCP_LSO_MSS(val)    vBIT(val,34,14)
 476 #define TXD_BUFFER0_SIZE(val)   vBIT(val,48,16)
 477
 478         u64 Control_2;
 479 #define TXD_TX_CKO_CONTROL      (BIT(5)|BIT(6)|BIT(7))
 480 #define TXD_TX_CKO_IPV4_EN      BIT(5)
 481 #define TXD_TX_CKO_TCP_EN       BIT(6)
 482 #define TXD_TX_CKO_UDP_EN       BIT(7)
 483 #define TXD_VLAN_ENABLE         BIT(15)
 484 #define TXD_VLAN_TAG(val)       vBIT(val,16,16)
 485 #define TXD_INT_NUMBER(val)     vBIT(val,34,6)
 486 #define TXD_INT_TYPE_PER_LIST   BIT(47)
 487 #define TXD_INT_TYPE_UTILZ      BIT(46)
 488 #define TXD_SET_MARKER         vBIT(0x6,0,4)
 489
 490         u64 Buffer_Pointer;
 491         u64 Host_Control;       /* reserved for host */
 492 } TxD_t;
 493
 494 /* Rx descriptor structure */
 495 typedef struct _RxD_t {
 496         u64 Host_Control;       /* reserved for host */
 497         u64 Control_1;
 498 #define RXD_OWN_XENA            BIT(7)
 499 #define RXD_T_CODE              (BIT(12)|BIT(13)|BIT(14)|BIT(15))
 500 #define RXD_FRAME_PROTO         vBIT(0xFFFF,24,8)
 501 #define RXD_FRAME_PROTO_IPV4    BIT(27)
 502 #define RXD_FRAME_PROTO_IPV6    BIT(28)
 503 #define RXD_FRAME_PROTO_TCP     BIT(30)
 504 #define RXD_FRAME_PROTO_UDP     BIT(31)
 505 #define TCP_OR_UDP_FRAME        (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
 506 #define RXD_GET_L3_CKSUM(val)   ((u16)(val>> 16) & 0xFFFF)
 507 #define RXD_GET_L4_CKSUM(val)   ((u16)(val) & 0xFFFF)
 508
 509         u64 Control_2;
 510 #define MASK_BUFFER0_SIZE       vBIT(0xFFFF,0,16)
 511 #define SET_BUFFER0_SIZE(val)   vBIT(val,0,16)
 512 #define MASK_VLAN_TAG           vBIT(0xFFFF,48,16)
 513 #define SET_VLAN_TAG(val)       vBIT(val,48,16)
 514 #define SET_NUM_TAG(val)       vBIT(val,16,32)
 515
 516 #define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16)))
 517 /*
 518 #define TXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) >> (63-31))
 519 #define TXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) >> (63-47))
 520 */
 521         u64 Buffer0_ptr;
 522 } RxD_t;
 523
 524
 525 /* Structure that represents the Rx descriptor block which contains
 526  * 128 Rx descriptors.
 527  */
 528 typedef struct _RxD_block {
 529 #define MAX_RXDS_PER_BLOCK             127
 530         RxD_t rxd[MAX_RXDS_PER_BLOCK];
 531
 532         u64 reserved_0;
 533 #define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL
 534         u64 reserved_1;         /* 0xFEFFFFFFFFFFFFFF to mark last Rxd in this blk */
 535         u64 reserved_2_pNext_RxD_block; /*@ Logical ptr to next */
 536         u64 pNext_RxD_Blk_physical;     /* Buff0_ptr.
 537                                            In a 32 bit arch the upper 32 bits
 538                                            should be 0 */
 539 } RxD_block_t;
 540
 541 /* Structure which stores all the MAC control parameters */
 542
 543 /* This structure stores the offset of the RxD in the ring
 544  * from which the Rx Interrupt processor can start picking
 545  * up the RxDs for processing.
 546  */
 547 typedef struct _rx_curr_get_info_t {
 548         u32 block_index;
 549         u32 offset;
 550         u32 ring_len;
 551 } rx_curr_get_info_t;
 552
 553 typedef rx_curr_get_info_t rx_curr_put_info_t;
 554
 555 /* This structure stores the offset of the TxDl in the FIFO
 556  * from which the Tx Interrupt processor can start picking
 557  * up the TxDLs for send complete interrupt processing.
 558  */
 559 typedef struct {
 560         u32 offset;
 561         u32 fifo_len;
 562 } tx_curr_get_info_t;
 563
 564 typedef tx_curr_get_info_t tx_curr_put_info_t;
 565
 566 /* Infomation related to the Tx and Rx FIFOs and Rings of Xena
 567  * is maintained in this structure.
 568  */
 569 typedef struct mac_info {
 570 /* rx side stuff */
 571         u32 rxd_ring_mem_sz;
 572         RxD_t *RxRing[MAX_RX_RINGS];    /* Logical Rx ring pointers */
 573         dma_addr_t RxRing_Phy[MAX_RX_RINGS];
 574
 575         /* Put pointer info which indictes which RxD has to be replenished
 576          * with a new buffer.
 577          */
 578         rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS];
 579
 580         /* Get pointer info which indictes which is the last RxD that was
 581          * processed by the driver.
 582          */
 583         rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS];
 584
 585         u16 rmac_pause_time;
 586
 587         /* this will be used in receive function, this decides which ring would
 588            be processed first. eg: ring with priority value 0 (highest) should
 589            be processed first.
 590            first 3 LSB bits represent ring number which should be processed
 591            first, similarly next 3 bits represent next ring to be processed.
 592            eg: value of _rx_ring_pri_map = 0x0000 003A means
 593            ring #2 would be processed first and #7 would be processed next
 594          */
 595         u32 _rx_ring_pri_map;
 596
 597 /* tx side stuff */
 598         void *txd_list_mem;     /* orignal pointer to allocated mem */
 599         dma_addr_t txd_list_mem_phy;
 600         u32 txd_list_mem_sz;
 601
 602         /* logical pointer of start of each Tx FIFO */
 603         TxFIFO_element_t *tx_FIFO_start[MAX_TX_FIFOS];
 604
 605         /* logical pointer of start of TxDL which corresponds to each Tx FIFO */
 606         TxD_t *txdl_start[MAX_TX_FIFOS];
 607
 608         /* Same as txdl_start but phy addr */
 609         dma_addr_t txdl_start_phy[MAX_TX_FIFOS];
 610
 611 /* Current offset within tx_FIFO_start, where driver would write new Tx frame*/
 612         tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS];
 613         tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS];
 614
 615         u16 txdl_len;           /* length of a TxDL, same for all */
 616
 617         void *stats_mem;        /* orignal pointer to allocated mem */
 618         dma_addr_t stats_mem_phy;       /* Physical address of the stat block */
 619         u32 stats_mem_sz;
 620         StatInfo_t *StatsInfo;  /* Logical address of the stat block */
 621 } mac_info_t;
 622
 623 /* structure representing the user defined MAC addresses */
 624 typedef struct {
 625         char addr[ETH_ALEN];
 626         int usage_cnt;
 627 } usr_addr_t;
 628
 629 /* Structure that holds the Phy and virt addresses of the Blocks */
 630 typedef struct rx_block_info {
 631         RxD_t *block_virt_addr;
 632         dma_addr_t block_dma_addr;
 633 } rx_block_info_t;
 634
 635 /* Structure representing one instance of the NIC */
 636 typedef struct s2io_nic {
 637 #define MAX_MAC_SUPPORTED   16
 638 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
 639
 640         macaddr_t defMacAddr[MAX_MAC_SUPPORTED];
 641         macaddr_t preMacAddr[MAX_MAC_SUPPORTED];
 642
 643         struct net_device_stats stats;
 644         caddr_t bar0;
 645         caddr_t bar1;
 646         struct config_param config;
 647         mac_info_t mac_control;
 648         int high_dma_flag;
 649         int device_close_flag;
 650         int device_enabled_once;
 651
 652         char name[32];
 653         struct tasklet_struct task;
 654         atomic_t tasklet_status;
 655         struct timer_list timer;
 656         struct net_device *dev;
 657         struct pci_dev *pdev;
 658
 659         u16 vendor_id;
 660         u16 device_id;
 661         u16 ccmd;
 662         u32 cbar0_1;
 663         u32 cbar0_2;
 664         u32 cbar1_1;
 665         u32 cbar1_2;
 666         u32 cirq;
 667         u8 cache_line;
 668         u32 rom_expansion;
 669         u16 pcix_cmd;
 670         u32 config_space[256 / sizeof(u32)];
 671         u32 irq;
 672         atomic_t rx_bufs_left[MAX_RX_RINGS];
 673
 674         spinlock_t isr_lock;
 675         spinlock_t tx_lock;
 676
 677 #define PROMISC     1
 678 #define ALL_MULTI   2
 679
 680 #define MAX_ADDRS_SUPPORTED 64
 681         u16 usr_addr_count;
 682         u16 mc_addr_count;
 683         usr_addr_t usr_addrs[MAX_ADDRS_SUPPORTED];
 684
 685         u16 m_cast_flg;
 686         u16 all_multi_pos;
 687         u16 promisc_flg;
 688
 689         u16 tx_pkt_count;
 690         u16 rx_pkt_count;
 691         u16 tx_err_count;
 692         u16 rx_err_count;
 693
 694 #if DEBUG_ON
 695         u64 rxpkt_bytes;
 696         u64 txpkt_bytes;
 697         int int_cnt;
 698         int rxint_cnt;
 699         int txint_cnt;
 700         u64 rxpkt_cnt;
 701 #endif
 702
 703         /*  Place holders for the virtual and physical addresses of
 704          *  all the Rx Blocks
 705          */
 706         struct rx_block_info
 707          rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
 708         int block_count[MAX_RX_RINGS];
 709         int pkt_cnt[MAX_RX_RINGS];
 710
 711         /*  Id timer, used to blink NIC to physically identify NIC. */
 712         struct timer_list id_timer;
 713
 714         /*  Restart timer, used to restart NIC if the device is stuck and
 715          *  a schedule task that will set the correct Link state once the
 716          *  NIC's PHY has stabilized after a state change.
 717          */
 718 #ifdef INIT_TQUEUE
 719         struct tq_struct rst_timer_task;
 720         struct tq_struct set_link_task;
 721 #else
 722         struct work_struct rst_timer_task;
 723         struct work_struct set_link_task;
 724 #endif
 725
 726         /* Flag that can be used to turn on or turn off the Rx checksum
 727          * offload feature.
 728          */
 729         int rx_csum;
 730
 731         /*  after blink, the adapter must be restored with original
 732          *  values.
 733          */
 734         u64 adapt_ctrl_org;
 735
 736         /* Last known link state. */
 737         u16 last_link_state;
 738 #define LINK_DOWN       1
 739 #define LINK_UP         2
 740 } nic_t;
 741
 742 #define RESET_ERROR 1;
 743 #define CMD_ERROR   2;
 744
 745 /* Default Tunable parameters of the NIC. */
 746 #define DEFAULT_FIFO_LEN 4096
 747 #define SMALL_RXD_CNT   40 * (MAX_RXDS_PER_BLOCK+1)
 748 #define LARGE_RXD_CNT   100 * (MAX_RXDS_PER_BLOCK+1)
 749
 750 /*  OS related system calls */
 751 #ifndef readq
 752 static inline u64 readq(void *addr)
 753 {
 754         u64 ret = 0;
 755         ret = readl(addr + 4);
 756         ret <<= 32;
 757         ret |= readl(addr);
 758
 759         return ret;
 760 }
 761 #endif
 762
 763 #ifndef writeq
 764 static inline void writeq(u64 val, void *addr)
 765 {
 766         writel((u32) (val), addr);
 767         writel((u32) (val >> 32), (addr + 4));
 768 }
 769 #endif
 770
 771 /*  Interrupt related values of Xena */
 772
 773 #define ENABLE_INTRS    1
 774 #define DISABLE_INTRS   2
 775
 776 /*  Highest level interrupt blocks */
 777 #define TX_PIC_INTR     (0x0001<<0)
 778 #define TX_DMA_INTR     (0x0001<<1)
 779 #define TX_MAC_INTR     (0x0001<<2)
 780 #define TX_XGXS_INTR    (0x0001<<3)
 781 #define TX_TRAFFIC_INTR (0x0001<<4)
 782 #define RX_PIC_INTR     (0x0001<<5)
 783 #define RX_DMA_INTR     (0x0001<<6)
 784 #define RX_MAC_INTR     (0x0001<<7)
 785 #define RX_XGXS_INTR    (0x0001<<8)
 786 #define RX_TRAFFIC_INTR (0x0001<<9)
 787 #define MC_INTR         (0x0001<<10)
 788 #define ENA_ALL_INTRS    (   TX_PIC_INTR     | \
 789                             TX_DMA_INTR     | \
 790                             TX_MAC_INTR     | \
 791                             TX_XGXS_INTR    | \
 792                             TX_TRAFFIC_INTR | \
 793                             RX_PIC_INTR     | \
 794                             RX_DMA_INTR     | \
 795                             RX_MAC_INTR     | \
 796                             RX_XGXS_INTR    | \
 797                             RX_TRAFFIC_INTR | \
 798                             MC_INTR )
 799
 800 /*  Interrupt masks for the general interrupt mask register */
 801 #define DISABLE_ALL_INTRS   0xFFFFFFFFFFFFFFFFULL
 802
 803 #define TXPIC_INT_M         BIT(0)
 804 #define TXDMA_INT_M         BIT(1)
 805 #define TXMAC_INT_M         BIT(2)
 806 #define TXXGXS_INT_M        BIT(3)
 807 #define TXTRAFFIC_INT_M     BIT(8)
 808 #define PIC_RX_INT_M        BIT(32)
 809 #define RXDMA_INT_M         BIT(33)
 810 #define RXMAC_INT_M         BIT(34)
 811 #define MC_INT_M            BIT(35)
 812 #define RXXGXS_INT_M        BIT(36)
 813 #define RXTRAFFIC_INT_M     BIT(40)
 814
 815 /*  PIC level Interrupts TODO*/
 816
 817 /*  DMA level Inressupts */
 818 #define TXDMA_PFC_INT_M     BIT(0)
 819     /*  PFC block interrupts */
 820 #define PFC_MISC_ERR_1      BIT(0)      /* Interrupt to indicate FIFO full */
 821
 822 /*
 823  * Prototype declaration.
 824  */
 825 static int __devinit s2io_init_nic(struct pci_dev *pdev,
 826                                    const struct pci_device_id *pre);
 827 static void __devexit s2io_rem_nic(struct pci_dev *pdev);
 828 static int initSharedMem(struct s2io_nic *sp);
 829 static void freeSharedMem(struct s2io_nic *sp);
 830 static int initNic(struct s2io_nic *nic);
 831 #ifndef CONFIG_S2IO_NAPI
 832 static void rxIntrHandler(struct s2io_nic *sp);
 833 #endif
 834 static void txIntrHandler(struct s2io_nic *sp);
 835 static void alarmIntrHandler(struct s2io_nic *sp);
 836
 837 static int s2io_starter(void);
 838 void s2io_closer(void);
 839 static void s2io_tx_watchdog(struct net_device *dev);
 840 static void s2io_tasklet(unsigned long dev_addr);
 841 static void s2io_set_multicast(struct net_device *dev);
 842 static int rxOsmHandler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);
 843 void s2io_link(nic_t * sp, int link);
 844 void s2io_reset(nic_t * sp);
 845 #ifdef CONFIG_S2IO_NAPI
 846 static int s2io_poll(struct net_device *dev, int *budget);
 847 #endif
 848 static void s2io_init_pci(nic_t * sp);
 849 int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
 850 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
 851 static int verify_xena_quiescence(u64 val64, int flag);
 852 static struct ethtool_ops netdev_ethtool_ops;
 853
 854 #endif                          /* _S2IO_H */