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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / char / synclink.c
blob0a1cc1d3630f392a40c9a4a1435a924190baf32e
1 /*
2 * linux/drivers/char/synclink.c
3 *
4 * $Id: synclink.c,v 4.28 2004/08/11 19:30:01 paulkf Exp $
5 *
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
15 *
16 * Original release 01/11/99
17 *
18 * This code is released under the GNU General Public License (GPL)
19 *
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
22 *
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
27 *
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
32 *
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
35 *
36 * 2000/02/16
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
42 *
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
57 #if defined(__i386__)
58 # define BREAKPOINT() asm(" int $3");
59 #else
60 # define BREAKPOINT() { }
61 #endif
62
63 #define MAX_ISA_DEVICES 10
64 #define MAX_PCI_DEVICES 10
65 #define MAX_TOTAL_DEVICES 20
66
67 #include <linux/config.h>
68 #include <linux/module.h>
69 #include <linux/errno.h>
70 #include <linux/signal.h>
71 #include <linux/sched.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
74 #include <linux/pci.h>
75 #include <linux/tty.h>
76 #include <linux/tty_flip.h>
77 #include <linux/serial.h>
78 #include <linux/major.h>
79 #include <linux/string.h>
80 #include <linux/fcntl.h>
81 #include <linux/ptrace.h>
82 #include <linux/ioport.h>
83 #include <linux/mm.h>
84 #include <linux/slab.h>
85
86 #include <linux/netdevice.h>
87
88 #include <linux/vmalloc.h>
89 #include <linux/init.h>
90 #include <asm/serial.h>
91
92 #include <linux/delay.h>
93 #include <linux/ioctl.h>
94
95 #include <asm/system.h>
96 #include <asm/io.h>
97 #include <asm/irq.h>
98 #include <asm/dma.h>
99 #include <asm/bitops.h>
100 #include <asm/types.h>
101 #include <linux/termios.h>
102 #include <linux/workqueue.h>
103 #include <linux/hdlc.h>
104
105 #ifdef CONFIG_HDLC_MODULE
106 #define CONFIG_HDLC 1
107 #endif
108
109 #define GET_USER(error,value,addr) error = get_user(value,addr)
110 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
111 #define PUT_USER(error,value,addr) error = put_user(value,addr)
112 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
113
114 #include <asm/uaccess.h>
115
116 #include "linux/synclink.h"
117
118 #define RCLRVALUE 0xffff
119
120 MGSL_PARAMS default_params = {
121 MGSL_MODE_HDLC, /* unsigned long mode */
122 0, /* unsigned char loopback; */
123 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
124 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
125 0, /* unsigned long clock_speed; */
126 0xff, /* unsigned char addr_filter; */
127 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
128 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
129 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
130 9600, /* unsigned long data_rate; */
131 8, /* unsigned char data_bits; */
132 1, /* unsigned char stop_bits; */
133 ASYNC_PARITY_NONE /* unsigned char parity; */
134 };
135
136 #define SHARED_MEM_ADDRESS_SIZE 0x40000
137 #define BUFFERLISTSIZE (PAGE_SIZE)
138 #define DMABUFFERSIZE (PAGE_SIZE)
139 #define MAXRXFRAMES 7
140
141 typedef struct _DMABUFFERENTRY
142 {
143 u32 phys_addr; /* 32-bit flat physical address of data buffer */
144 u16 count; /* buffer size/data count */
145 u16 status; /* Control/status field */
146 u16 rcc; /* character count field */
147 u16 reserved; /* padding required by 16C32 */
148 u32 link; /* 32-bit flat link to next buffer entry */
149 char *virt_addr; /* virtual address of data buffer */
150 u32 phys_entry; /* physical address of this buffer entry */
151 } DMABUFFERENTRY, *DMAPBUFFERENTRY;
152
153 /* The queue of BH actions to be performed */
154
155 #define BH_RECEIVE 1
156 #define BH_TRANSMIT 2
157 #define BH_STATUS 4
158
159 #define IO_PIN_SHUTDOWN_LIMIT 100
160
161 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
162
163 struct _input_signal_events {
164 int ri_up;
165 int ri_down;
166 int dsr_up;
167 int dsr_down;
168 int dcd_up;
169 int dcd_down;
170 int cts_up;
171 int cts_down;
172 };
173
174 /* transmit holding buffer definitions*/
175 #define MAX_TX_HOLDING_BUFFERS 5
176 struct tx_holding_buffer {
177 int buffer_size;
178 unsigned char * buffer;
179 };
180
181
182 /*
183 * Device instance data structure
184 */
185
186 struct mgsl_struct {
187 int magic;
188 int flags;
189 int count; /* count of opens */
190 int line;
191 int hw_version;
192 unsigned short close_delay;
193 unsigned short closing_wait; /* time to wait before closing */
194
195 struct mgsl_icount icount;
196
197 struct tty_struct *tty;
198 int timeout;
199 int x_char; /* xon/xoff character */
200 int blocked_open; /* # of blocked opens */
201 u16 read_status_mask;
202 u16 ignore_status_mask;
203 unsigned char *xmit_buf;
204 int xmit_head;
205 int xmit_tail;
206 int xmit_cnt;
207
208 wait_queue_head_t open_wait;
209 wait_queue_head_t close_wait;
210
211 wait_queue_head_t status_event_wait_q;
212 wait_queue_head_t event_wait_q;
213 struct timer_list tx_timer; /* HDLC transmit timeout timer */
214 struct mgsl_struct *next_device; /* device list link */
215
216 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
217 struct work_struct task; /* task structure for scheduling bh */
218
219 u32 EventMask; /* event trigger mask */
220 u32 RecordedEvents; /* pending events */
221
222 u32 max_frame_size; /* as set by device config */
223
224 u32 pending_bh;
225
226 int bh_running; /* Protection from multiple */
227 int isr_overflow;
228 int bh_requested;
229
230 int dcd_chkcount; /* check counts to prevent */
231 int cts_chkcount; /* too many IRQs if a signal */
232 int dsr_chkcount; /* is floating */
233 int ri_chkcount;
234
235 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
236 unsigned long buffer_list_phys;
237
238 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
239 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
240 unsigned int current_rx_buffer;
241
242 int num_tx_dma_buffers; /* number of tx dma frames required */
243 int tx_dma_buffers_used;
244 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
245 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
246 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
247 int current_tx_buffer; /* next tx dma buffer to be loaded */
248
249 unsigned char *intermediate_rxbuffer;
250
251 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
252 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
253 int put_tx_holding_index; /* next tx holding buffer to store user request */
254 int tx_holding_count; /* number of tx holding buffers waiting */
255 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
256
257 int rx_enabled;
258 int rx_overflow;
259 int rx_rcc_underrun;
260
261 int tx_enabled;
262 int tx_active;
263 u32 idle_mode;
264
265 u16 cmr_value;
266 u16 tcsr_value;
267
268 char device_name[25]; /* device instance name */
269
270 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
271 unsigned char bus; /* expansion bus number (zero based) */
272 unsigned char function; /* PCI device number */
273
274 unsigned int io_base; /* base I/O address of adapter */
275 unsigned int io_addr_size; /* size of the I/O address range */
276 int io_addr_requested; /* nonzero if I/O address requested */
277
278 unsigned int irq_level; /* interrupt level */
279 unsigned long irq_flags;
280 int irq_requested; /* nonzero if IRQ requested */
281
282 unsigned int dma_level; /* DMA channel */
283 int dma_requested; /* nonzero if dma channel requested */
284
285 u16 mbre_bit;
286 u16 loopback_bits;
287 u16 usc_idle_mode;
288
289 MGSL_PARAMS params; /* communications parameters */
290
291 unsigned char serial_signals; /* current serial signal states */
292
293 int irq_occurred; /* for diagnostics use */
294 unsigned int init_error; /* Initialization startup error (DIAGS) */
295 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
296
297 u32 last_mem_alloc;
298 unsigned char* memory_base; /* shared memory address (PCI only) */
299 u32 phys_memory_base;
300 int shared_mem_requested;
301
302 unsigned char* lcr_base; /* local config registers (PCI only) */
303 u32 phys_lcr_base;
304 u32 lcr_offset;
305 int lcr_mem_requested;
306
307 u32 misc_ctrl_value;
308 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
309 char char_buf[MAX_ASYNC_BUFFER_SIZE];
310 BOOLEAN drop_rts_on_tx_done;
311
312 BOOLEAN loopmode_insert_requested;
313 BOOLEAN loopmode_send_done_requested;
314
315 struct _input_signal_events input_signal_events;
316
317 /* generic HDLC device parts */
318 int netcount;
319 int dosyncppp;
320 spinlock_t netlock;
321
322 #ifdef CONFIG_HDLC
323 struct net_device *netdev;
324 #endif
325 };
326
327 #define MGSL_MAGIC 0x5401
328
329 /*
330 * The size of the serial xmit buffer is 1 page, or 4096 bytes
331 */
332 #ifndef SERIAL_XMIT_SIZE
333 #define SERIAL_XMIT_SIZE 4096
334 #endif
335
336 /*
337 * These macros define the offsets used in calculating the
338 * I/O address of the specified USC registers.
339 */
340
341
342 #define DCPIN 2 /* Bit 1 of I/O address */
343 #define SDPIN 4 /* Bit 2 of I/O address */
344
345 #define DCAR 0 /* DMA command/address register */
346 #define CCAR SDPIN /* channel command/address register */
347 #define DATAREG DCPIN + SDPIN /* serial data register */
348 #define MSBONLY 0x41
349 #define LSBONLY 0x40
350
351 /*
352 * These macros define the register address (ordinal number)
353 * used for writing address/value pairs to the USC.
354 */
355
356 #define CMR 0x02 /* Channel mode Register */
357 #define CCSR 0x04 /* Channel Command/status Register */
358 #define CCR 0x06 /* Channel Control Register */
359 #define PSR 0x08 /* Port status Register */
360 #define PCR 0x0a /* Port Control Register */
361 #define TMDR 0x0c /* Test mode Data Register */
362 #define TMCR 0x0e /* Test mode Control Register */
363 #define CMCR 0x10 /* Clock mode Control Register */
364 #define HCR 0x12 /* Hardware Configuration Register */
365 #define IVR 0x14 /* Interrupt Vector Register */
366 #define IOCR 0x16 /* Input/Output Control Register */
367 #define ICR 0x18 /* Interrupt Control Register */
368 #define DCCR 0x1a /* Daisy Chain Control Register */
369 #define MISR 0x1c /* Misc Interrupt status Register */
370 #define SICR 0x1e /* status Interrupt Control Register */
371 #define RDR 0x20 /* Receive Data Register */
372 #define RMR 0x22 /* Receive mode Register */
373 #define RCSR 0x24 /* Receive Command/status Register */
374 #define RICR 0x26 /* Receive Interrupt Control Register */
375 #define RSR 0x28 /* Receive Sync Register */
376 #define RCLR 0x2a /* Receive count Limit Register */
377 #define RCCR 0x2c /* Receive Character count Register */
378 #define TC0R 0x2e /* Time Constant 0 Register */
379 #define TDR 0x30 /* Transmit Data Register */
380 #define TMR 0x32 /* Transmit mode Register */
381 #define TCSR 0x34 /* Transmit Command/status Register */
382 #define TICR 0x36 /* Transmit Interrupt Control Register */
383 #define TSR 0x38 /* Transmit Sync Register */
384 #define TCLR 0x3a /* Transmit count Limit Register */
385 #define TCCR 0x3c /* Transmit Character count Register */
386 #define TC1R 0x3e /* Time Constant 1 Register */
387
388
389 /*
390 * MACRO DEFINITIONS FOR DMA REGISTERS
391 */
392
393 #define DCR 0x06 /* DMA Control Register (shared) */
394 #define DACR 0x08 /* DMA Array count Register (shared) */
395 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
396 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
397 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
398 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
399 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
400
401 #define TDMR 0x02 /* Transmit DMA mode Register */
402 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
403 #define TBCR 0x2a /* Transmit Byte count Register */
404 #define TARL 0x2c /* Transmit Address Register (low) */
405 #define TARU 0x2e /* Transmit Address Register (high) */
406 #define NTBCR 0x3a /* Next Transmit Byte count Register */
407 #define NTARL 0x3c /* Next Transmit Address Register (low) */
408 #define NTARU 0x3e /* Next Transmit Address Register (high) */
409
410 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
411 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
412 #define RBCR 0xaa /* Receive Byte count Register */
413 #define RARL 0xac /* Receive Address Register (low) */
414 #define RARU 0xae /* Receive Address Register (high) */
415 #define NRBCR 0xba /* Next Receive Byte count Register */
416 #define NRARL 0xbc /* Next Receive Address Register (low) */
417 #define NRARU 0xbe /* Next Receive Address Register (high) */
418
419
420 /*
421 * MACRO DEFINITIONS FOR MODEM STATUS BITS
422 */
423
424 #define MODEMSTATUS_DTR 0x80
425 #define MODEMSTATUS_DSR 0x40
426 #define MODEMSTATUS_RTS 0x20
427 #define MODEMSTATUS_CTS 0x10
428 #define MODEMSTATUS_RI 0x04
429 #define MODEMSTATUS_DCD 0x01
430
431
432 /*
433 * Channel Command/Address Register (CCAR) Command Codes
434 */
435
436 #define RTCmd_Null 0x0000
437 #define RTCmd_ResetHighestIus 0x1000
438 #define RTCmd_TriggerChannelLoadDma 0x2000
439 #define RTCmd_TriggerRxDma 0x2800
440 #define RTCmd_TriggerTxDma 0x3000
441 #define RTCmd_TriggerRxAndTxDma 0x3800
442 #define RTCmd_PurgeRxFifo 0x4800
443 #define RTCmd_PurgeTxFifo 0x5000
444 #define RTCmd_PurgeRxAndTxFifo 0x5800
445 #define RTCmd_LoadRcc 0x6800
446 #define RTCmd_LoadTcc 0x7000
447 #define RTCmd_LoadRccAndTcc 0x7800
448 #define RTCmd_LoadTC0 0x8800
449 #define RTCmd_LoadTC1 0x9000
450 #define RTCmd_LoadTC0AndTC1 0x9800
451 #define RTCmd_SerialDataLSBFirst 0xa000
452 #define RTCmd_SerialDataMSBFirst 0xa800
453 #define RTCmd_SelectBigEndian 0xb000
454 #define RTCmd_SelectLittleEndian 0xb800
455
456
457 /*
458 * DMA Command/Address Register (DCAR) Command Codes
459 */
460
461 #define DmaCmd_Null 0x0000
462 #define DmaCmd_ResetTxChannel 0x1000
463 #define DmaCmd_ResetRxChannel 0x1200
464 #define DmaCmd_StartTxChannel 0x2000
465 #define DmaCmd_StartRxChannel 0x2200
466 #define DmaCmd_ContinueTxChannel 0x3000
467 #define DmaCmd_ContinueRxChannel 0x3200
468 #define DmaCmd_PauseTxChannel 0x4000
469 #define DmaCmd_PauseRxChannel 0x4200
470 #define DmaCmd_AbortTxChannel 0x5000
471 #define DmaCmd_AbortRxChannel 0x5200
472 #define DmaCmd_InitTxChannel 0x7000
473 #define DmaCmd_InitRxChannel 0x7200
474 #define DmaCmd_ResetHighestDmaIus 0x8000
475 #define DmaCmd_ResetAllChannels 0x9000
476 #define DmaCmd_StartAllChannels 0xa000
477 #define DmaCmd_ContinueAllChannels 0xb000
478 #define DmaCmd_PauseAllChannels 0xc000
479 #define DmaCmd_AbortAllChannels 0xd000
480 #define DmaCmd_InitAllChannels 0xf000
481
482 #define TCmd_Null 0x0000
483 #define TCmd_ClearTxCRC 0x2000
484 #define TCmd_SelectTicrTtsaData 0x4000
485 #define TCmd_SelectTicrTxFifostatus 0x5000
486 #define TCmd_SelectTicrIntLevel 0x6000
487 #define TCmd_SelectTicrdma_level 0x7000
488 #define TCmd_SendFrame 0x8000
489 #define TCmd_SendAbort 0x9000
490 #define TCmd_EnableDleInsertion 0xc000
491 #define TCmd_DisableDleInsertion 0xd000
492 #define TCmd_ClearEofEom 0xe000
493 #define TCmd_SetEofEom 0xf000
494
495 #define RCmd_Null 0x0000
496 #define RCmd_ClearRxCRC 0x2000
497 #define RCmd_EnterHuntmode 0x3000
498 #define RCmd_SelectRicrRtsaData 0x4000
499 #define RCmd_SelectRicrRxFifostatus 0x5000
500 #define RCmd_SelectRicrIntLevel 0x6000
501 #define RCmd_SelectRicrdma_level 0x7000
502
503 /*
504 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
505 */
506
507 #define RECEIVE_STATUS BIT5
508 #define RECEIVE_DATA BIT4
509 #define TRANSMIT_STATUS BIT3
510 #define TRANSMIT_DATA BIT2
511 #define IO_PIN BIT1
512 #define MISC BIT0
513
514
515 /*
516 * Receive status Bits in Receive Command/status Register RCSR
517 */
518
519 #define RXSTATUS_SHORT_FRAME BIT8
520 #define RXSTATUS_CODE_VIOLATION BIT8
521 #define RXSTATUS_EXITED_HUNT BIT7
522 #define RXSTATUS_IDLE_RECEIVED BIT6
523 #define RXSTATUS_BREAK_RECEIVED BIT5
524 #define RXSTATUS_ABORT_RECEIVED BIT5
525 #define RXSTATUS_RXBOUND BIT4
526 #define RXSTATUS_CRC_ERROR BIT3
527 #define RXSTATUS_FRAMING_ERROR BIT3
528 #define RXSTATUS_ABORT BIT2
529 #define RXSTATUS_PARITY_ERROR BIT2
530 #define RXSTATUS_OVERRUN BIT1
531 #define RXSTATUS_DATA_AVAILABLE BIT0
532 #define RXSTATUS_ALL 0x01f6
533 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
534
535 /*
536 * Values for setting transmit idle mode in
537 * Transmit Control/status Register (TCSR)
538 */
539 #define IDLEMODE_FLAGS 0x0000
540 #define IDLEMODE_ALT_ONE_ZERO 0x0100
541 #define IDLEMODE_ZERO 0x0200
542 #define IDLEMODE_ONE 0x0300
543 #define IDLEMODE_ALT_MARK_SPACE 0x0500
544 #define IDLEMODE_SPACE 0x0600
545 #define IDLEMODE_MARK 0x0700
546 #define IDLEMODE_MASK 0x0700
547
548 /*
549 * IUSC revision identifiers
550 */
551 #define IUSC_SL1660 0x4d44
552 #define IUSC_PRE_SL1660 0x4553
553
554 /*
555 * Transmit status Bits in Transmit Command/status Register (TCSR)
556 */
557
558 #define TCSR_PRESERVE 0x0F00
559
560 #define TCSR_UNDERWAIT BIT11
561 #define TXSTATUS_PREAMBLE_SENT BIT7
562 #define TXSTATUS_IDLE_SENT BIT6
563 #define TXSTATUS_ABORT_SENT BIT5
564 #define TXSTATUS_EOF_SENT BIT4
565 #define TXSTATUS_EOM_SENT BIT4
566 #define TXSTATUS_CRC_SENT BIT3
567 #define TXSTATUS_ALL_SENT BIT2
568 #define TXSTATUS_UNDERRUN BIT1
569 #define TXSTATUS_FIFO_EMPTY BIT0
570 #define TXSTATUS_ALL 0x00fa
571 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
572
573
574 #define MISCSTATUS_RXC_LATCHED BIT15
575 #define MISCSTATUS_RXC BIT14
576 #define MISCSTATUS_TXC_LATCHED BIT13
577 #define MISCSTATUS_TXC BIT12
578 #define MISCSTATUS_RI_LATCHED BIT11
579 #define MISCSTATUS_RI BIT10
580 #define MISCSTATUS_DSR_LATCHED BIT9
581 #define MISCSTATUS_DSR BIT8
582 #define MISCSTATUS_DCD_LATCHED BIT7
583 #define MISCSTATUS_DCD BIT6
584 #define MISCSTATUS_CTS_LATCHED BIT5
585 #define MISCSTATUS_CTS BIT4
586 #define MISCSTATUS_RCC_UNDERRUN BIT3
587 #define MISCSTATUS_DPLL_NO_SYNC BIT2
588 #define MISCSTATUS_BRG1_ZERO BIT1
589 #define MISCSTATUS_BRG0_ZERO BIT0
590
591 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
592 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
593
594 #define SICR_RXC_ACTIVE BIT15
595 #define SICR_RXC_INACTIVE BIT14
596 #define SICR_RXC (BIT15+BIT14)
597 #define SICR_TXC_ACTIVE BIT13
598 #define SICR_TXC_INACTIVE BIT12
599 #define SICR_TXC (BIT13+BIT12)
600 #define SICR_RI_ACTIVE BIT11
601 #define SICR_RI_INACTIVE BIT10
602 #define SICR_RI (BIT11+BIT10)
603 #define SICR_DSR_ACTIVE BIT9
604 #define SICR_DSR_INACTIVE BIT8
605 #define SICR_DSR (BIT9+BIT8)
606 #define SICR_DCD_ACTIVE BIT7
607 #define SICR_DCD_INACTIVE BIT6
608 #define SICR_DCD (BIT7+BIT6)
609 #define SICR_CTS_ACTIVE BIT5
610 #define SICR_CTS_INACTIVE BIT4
611 #define SICR_CTS (BIT5+BIT4)
612 #define SICR_RCC_UNDERFLOW BIT3
613 #define SICR_DPLL_NO_SYNC BIT2
614 #define SICR_BRG1_ZERO BIT1
615 #define SICR_BRG0_ZERO BIT0
616
617 void usc_DisableMasterIrqBit( struct mgsl_struct *info );
618 void usc_EnableMasterIrqBit( struct mgsl_struct *info );
619 void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
620 void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
621 void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
622
623 #define usc_EnableInterrupts( a, b ) \
624 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
625
626 #define usc_DisableInterrupts( a, b ) \
627 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
628
629 #define usc_EnableMasterIrqBit(a) \
630 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
631
632 #define usc_DisableMasterIrqBit(a) \
633 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
634
635 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
636
637 /*
638 * Transmit status Bits in Transmit Control status Register (TCSR)
639 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
640 */
641
642 #define TXSTATUS_PREAMBLE_SENT BIT7
643 #define TXSTATUS_IDLE_SENT BIT6
644 #define TXSTATUS_ABORT_SENT BIT5
645 #define TXSTATUS_EOF BIT4
646 #define TXSTATUS_CRC_SENT BIT3
647 #define TXSTATUS_ALL_SENT BIT2
648 #define TXSTATUS_UNDERRUN BIT1
649 #define TXSTATUS_FIFO_EMPTY BIT0
650
651 #define DICR_MASTER BIT15
652 #define DICR_TRANSMIT BIT0
653 #define DICR_RECEIVE BIT1
654
655 #define usc_EnableDmaInterrupts(a,b) \
656 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
657
658 #define usc_DisableDmaInterrupts(a,b) \
659 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
660
661 #define usc_EnableStatusIrqs(a,b) \
662 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
663
664 #define usc_DisablestatusIrqs(a,b) \
665 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
666
667 /* Transmit status Bits in Transmit Control status Register (TCSR) */
668 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
669
670
671 #define DISABLE_UNCONDITIONAL 0
672 #define DISABLE_END_OF_FRAME 1
673 #define ENABLE_UNCONDITIONAL 2
674 #define ENABLE_AUTO_CTS 3
675 #define ENABLE_AUTO_DCD 3
676 #define usc_EnableTransmitter(a,b) \
677 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
678 #define usc_EnableReceiver(a,b) \
679 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
680
681 u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
682 void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
683 void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
684
685 u16 usc_InReg( struct mgsl_struct *info, u16 Port );
686 void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
687 void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
688 void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
689 void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
690
691 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
692 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
693
694 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
695
696 void usc_process_rxoverrun_sync( struct mgsl_struct *info );
697 void usc_start_receiver( struct mgsl_struct *info );
698 void usc_stop_receiver( struct mgsl_struct *info );
699
700 void usc_start_transmitter( struct mgsl_struct *info );
701 void usc_stop_transmitter( struct mgsl_struct *info );
702 void usc_set_txidle( struct mgsl_struct *info );
703 void usc_load_txfifo( struct mgsl_struct *info );
704
705 void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
706 void usc_enable_loopback( struct mgsl_struct *info, int enable );
707
708 void usc_get_serial_signals( struct mgsl_struct *info );
709 void usc_set_serial_signals( struct mgsl_struct *info );
710
711 void usc_reset( struct mgsl_struct *info );
712
713 void usc_set_sync_mode( struct mgsl_struct *info );
714 void usc_set_sdlc_mode( struct mgsl_struct *info );
715 void usc_set_async_mode( struct mgsl_struct *info );
716 void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
717
718 void usc_loopback_frame( struct mgsl_struct *info );
719
720 void mgsl_tx_timeout(unsigned long context);
721
722
723 void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
724 void usc_loopmode_insert_request( struct mgsl_struct * info );
725 int usc_loopmode_active( struct mgsl_struct * info);
726 void usc_loopmode_send_done( struct mgsl_struct * info );
727 int usc_loopmode_send_active( struct mgsl_struct * info );
728
729 int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
730
731 #ifdef CONFIG_HDLC
732 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
733 static void hdlcdev_tx_done(struct mgsl_struct *info);
734 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
735 static int hdlcdev_init(struct mgsl_struct *info);
736 static void hdlcdev_exit(struct mgsl_struct *info);
737 #endif
738
739 /*
740 * Defines a BUS descriptor value for the PCI adapter
741 * local bus address ranges.
742 */
743
744 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
745 (0x00400020 + \
746 ((WrHold) << 30) + \
747 ((WrDly) << 28) + \
748 ((RdDly) << 26) + \
749 ((Nwdd) << 20) + \
750 ((Nwad) << 15) + \
751 ((Nxda) << 13) + \
752 ((Nrdd) << 11) + \
753 ((Nrad) << 6) )
754
755 void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
756
757 /*
758 * Adapter diagnostic routines
759 */
760 BOOLEAN mgsl_register_test( struct mgsl_struct *info );
761 BOOLEAN mgsl_irq_test( struct mgsl_struct *info );
762 BOOLEAN mgsl_dma_test( struct mgsl_struct *info );
763 BOOLEAN mgsl_memory_test( struct mgsl_struct *info );
764 int mgsl_adapter_test( struct mgsl_struct *info );
765
766 /*
767 * device and resource management routines
768 */
769 int mgsl_claim_resources(struct mgsl_struct *info);
770 void mgsl_release_resources(struct mgsl_struct *info);
771 void mgsl_add_device(struct mgsl_struct *info);
772 struct mgsl_struct* mgsl_allocate_device(void);
773
774 /*
775 * DMA buffer manupulation functions.
776 */
777 void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
778 int mgsl_get_rx_frame( struct mgsl_struct *info );
779 int mgsl_get_raw_rx_frame( struct mgsl_struct *info );
780 void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
781 void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
782 int num_free_tx_dma_buffers(struct mgsl_struct *info);
783 void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
784 void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
785
786 /*
787 * DMA and Shared Memory buffer allocation and formatting
788 */
789 int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
790 void mgsl_free_dma_buffers(struct mgsl_struct *info);
791 int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
792 void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
793 int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
794 void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
795 int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
796 void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
797 int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
798 void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
799 int load_next_tx_holding_buffer(struct mgsl_struct *info);
800 int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
801
802 /*
803 * Bottom half interrupt handlers
804 */
805 void mgsl_bh_handler(void* Context);
806 void mgsl_bh_receive(struct mgsl_struct *info);
807 void mgsl_bh_transmit(struct mgsl_struct *info);
808 void mgsl_bh_status(struct mgsl_struct *info);
809
810 /*
811 * Interrupt handler routines and dispatch table.
812 */
813 void mgsl_isr_null( struct mgsl_struct *info );
814 void mgsl_isr_transmit_data( struct mgsl_struct *info );
815 void mgsl_isr_receive_data( struct mgsl_struct *info );
816 void mgsl_isr_receive_status( struct mgsl_struct *info );
817 void mgsl_isr_transmit_status( struct mgsl_struct *info );
818 void mgsl_isr_io_pin( struct mgsl_struct *info );
819 void mgsl_isr_misc( struct mgsl_struct *info );
820 void mgsl_isr_receive_dma( struct mgsl_struct *info );
821 void mgsl_isr_transmit_dma( struct mgsl_struct *info );
822
823 typedef void (*isr_dispatch_func)(struct mgsl_struct *);
824
825 isr_dispatch_func UscIsrTable[7] =
826 {
827 mgsl_isr_null,
828 mgsl_isr_misc,
829 mgsl_isr_io_pin,
830 mgsl_isr_transmit_data,
831 mgsl_isr_transmit_status,
832 mgsl_isr_receive_data,
833 mgsl_isr_receive_status
834 };
835
836 /*
837 * ioctl call handlers
838 */
839 static int tiocmget(struct tty_struct *tty, struct file *file);
840 static int tiocmset(struct tty_struct *tty, struct file *file,
841 unsigned int set, unsigned int clear);
842 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
843 __user *user_icount);
844 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
845 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
846 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
847 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
848 static int mgsl_txenable(struct mgsl_struct * info, int enable);
849 static int mgsl_txabort(struct mgsl_struct * info);
850 static int mgsl_rxenable(struct mgsl_struct * info, int enable);
851 static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
852 static int mgsl_loopmode_send_done( struct mgsl_struct * info );
853
854 /* set non-zero on successful registration with PCI subsystem */
855 static int pci_registered;
856
857 /*
858 * Global linked list of SyncLink devices
859 */
860 struct mgsl_struct *mgsl_device_list;
861 static int mgsl_device_count;
862
863 /*
864 * Set this param to non-zero to load eax with the
865 * .text section address and breakpoint on module load.
866 * This is useful for use with gdb and add-symbol-file command.
867 */
868 static int break_on_load;
869
870 /*
871 * Driver major number, defaults to zero to get auto
872 * assigned major number. May be forced as module parameter.
873 */
874 static int ttymajor;
875
876 /*
877 * Array of user specified options for ISA adapters.
878 */
879 static int io[MAX_ISA_DEVICES];
880 static int irq[MAX_ISA_DEVICES];
881 static int dma[MAX_ISA_DEVICES];
882 static int debug_level;
883 static int maxframe[MAX_TOTAL_DEVICES];
884 static int dosyncppp[MAX_TOTAL_DEVICES];
885 static int txdmabufs[MAX_TOTAL_DEVICES];
886 static int txholdbufs[MAX_TOTAL_DEVICES];
887
888 MODULE_PARM(break_on_load,"i");
889 MODULE_PARM(ttymajor,"i");
890 MODULE_PARM(io,"1-" __MODULE_STRING(MAX_ISA_DEVICES) "i");
891 MODULE_PARM(irq,"1-" __MODULE_STRING(MAX_ISA_DEVICES) "i");
892 MODULE_PARM(dma,"1-" __MODULE_STRING(MAX_ISA_DEVICES) "i");
893 MODULE_PARM(debug_level,"i");
894 MODULE_PARM(maxframe,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES) "i");
895 MODULE_PARM(dosyncppp,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES) "i");
896 MODULE_PARM(txdmabufs,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES) "i");
897 MODULE_PARM(txholdbufs,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES) "i");
898
899 static char *driver_name = "SyncLink serial driver";
900 static char *driver_version = "$Revision: 4.28 $";
901
902 static int synclink_init_one (struct pci_dev *dev,
903 const struct pci_device_id *ent);
904 static void synclink_remove_one (struct pci_dev *dev);
905
906 static struct pci_device_id synclink_pci_tbl[] = {
907 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
908 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
909 { 0, }, /* terminate list */
910 };
911 MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
912
913 MODULE_LICENSE("GPL");
914
915 static struct pci_driver synclink_pci_driver = {
916 .name = "synclink",
917 .id_table = synclink_pci_tbl,
918 .probe = synclink_init_one,
919 .remove = __devexit_p(synclink_remove_one),
920 };
921
922 static struct tty_driver *serial_driver;
923
924 /* number of characters left in xmit buffer before we ask for more */
925 #define WAKEUP_CHARS 256
926
927
928 static void mgsl_change_params(struct mgsl_struct *info);
929 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
930
931 /*
932 * 1st function defined in .text section. Calling this function in
933 * init_module() followed by a breakpoint allows a remote debugger
934 * (gdb) to get the .text address for the add-symbol-file command.
935 * This allows remote debugging of dynamically loadable modules.
936 */
937 void* mgsl_get_text_ptr(void)
938 {
939 return mgsl_get_text_ptr;
940 }
941
942 /*
943 * tmp_buf is used as a temporary buffer by mgsl_write. We need to
944 * lock it in case the COPY_FROM_USER blocks while swapping in a page,
945 * and some other program tries to do a serial write at the same time.
946 * Since the lock will only come under contention when the system is
947 * swapping and available memory is low, it makes sense to share one
948 * buffer across all the serial ioports, since it significantly saves
949 * memory if large numbers of serial ports are open.
950 */
951 static unsigned char *tmp_buf;
952 static DECLARE_MUTEX(tmp_buf_sem);
953
954 static inline int mgsl_paranoia_check(struct mgsl_struct *info,
955 char *name, const char *routine)
956 {
957 #ifdef MGSL_PARANOIA_CHECK
958 static const char *badmagic =
959 "Warning: bad magic number for mgsl struct (%s) in %s\n";
960 static const char *badinfo =
961 "Warning: null mgsl_struct for (%s) in %s\n";
962
963 if (!info) {
964 printk(badinfo, name, routine);
965 return 1;
966 }
967 if (info->magic != MGSL_MAGIC) {
968 printk(badmagic, name, routine);
969 return 1;
970 }
971 #else
972 if (!info)
973 return 1;
974 #endif
975 return 0;
976 }
977
978 /**
979 * line discipline callback wrappers
980 *
981 * The wrappers maintain line discipline references
982 * while calling into the line discipline.
983 *
984 * ldisc_receive_buf - pass receive data to line discipline
985 */
986
987 static void ldisc_receive_buf(struct tty_struct *tty,
988 const __u8 *data, char *flags, int count)
989 {
990 struct tty_ldisc *ld;
991 if (!tty)
992 return;
993 ld = tty_ldisc_ref(tty);
994 if (ld) {
995 if (ld->receive_buf)
996 ld->receive_buf(tty, data, flags, count);
997 tty_ldisc_deref(ld);
998 }
999 }
1000
1001 /* mgsl_stop() throttle (stop) transmitter
1002 *
1003 * Arguments: tty pointer to tty info structure
1004 * Return Value: None
1005 */
1006 static void mgsl_stop(struct tty_struct *tty)
1007 {
1008 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1009 unsigned long flags;
1010
1011 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
1012 return;
1013
1014 if ( debug_level >= DEBUG_LEVEL_INFO )
1015 printk("mgsl_stop(%s)\n",info->device_name);
1016
1017 spin_lock_irqsave(&info->irq_spinlock,flags);
1018 if (info->tx_enabled)
1019 usc_stop_transmitter(info);
1020 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1021
1022 } /* end of mgsl_stop() */
1023
1024 /* mgsl_start() release (start) transmitter
1025 *
1026 * Arguments: tty pointer to tty info structure
1027 * Return Value: None
1028 */
1029 static void mgsl_start(struct tty_struct *tty)
1030 {
1031 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1032 unsigned long flags;
1033
1034 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1035 return;
1036
1037 if ( debug_level >= DEBUG_LEVEL_INFO )
1038 printk("mgsl_start(%s)\n",info->device_name);
1039
1040 spin_lock_irqsave(&info->irq_spinlock,flags);
1041 if (!info->tx_enabled)
1042 usc_start_transmitter(info);
1043 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1044
1045 } /* end of mgsl_start() */
1046
1047 /*
1048 * Bottom half work queue access functions
1049 */
1050
1051 /* mgsl_bh_action() Return next bottom half action to perform.
1052 * Return Value: BH action code or 0 if nothing to do.
1053 */
1054 int mgsl_bh_action(struct mgsl_struct *info)
1055 {
1056 unsigned long flags;
1057 int rc = 0;
1058
1059 spin_lock_irqsave(&info->irq_spinlock,flags);
1060
1061 if (info->pending_bh & BH_RECEIVE) {
1062 info->pending_bh &= ~BH_RECEIVE;
1063 rc = BH_RECEIVE;
1064 } else if (info->pending_bh & BH_TRANSMIT) {
1065 info->pending_bh &= ~BH_TRANSMIT;
1066 rc = BH_TRANSMIT;
1067 } else if (info->pending_bh & BH_STATUS) {
1068 info->pending_bh &= ~BH_STATUS;
1069 rc = BH_STATUS;
1070 }
1071
1072 if (!rc) {
1073 /* Mark BH routine as complete */
1074 info->bh_running = 0;
1075 info->bh_requested = 0;
1076 }
1077
1078 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1079
1080 return rc;
1081 }
1082
1083 /*
1084 * Perform bottom half processing of work items queued by ISR.
1085 */
1086 void mgsl_bh_handler(void* Context)
1087 {
1088 struct mgsl_struct *info = (struct mgsl_struct*)Context;
1089 int action;
1090
1091 if (!info)
1092 return;
1093
1094 if ( debug_level >= DEBUG_LEVEL_BH )
1095 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1096 __FILE__,__LINE__,info->device_name);
1097
1098 info->bh_running = 1;
1099
1100 while((action = mgsl_bh_action(info)) != 0) {
1101
1102 /* Process work item */
1103 if ( debug_level >= DEBUG_LEVEL_BH )
1104 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1105 __FILE__,__LINE__,action);
1106
1107 switch (action) {
1108
1109 case BH_RECEIVE:
1110 mgsl_bh_receive(info);
1111 break;
1112 case BH_TRANSMIT:
1113 mgsl_bh_transmit(info);
1114 break;
1115 case BH_STATUS:
1116 mgsl_bh_status(info);
1117 break;
1118 default:
1119 /* unknown work item ID */
1120 printk("Unknown work item ID=%08X!\n", action);
1121 break;
1122 }
1123 }
1124
1125 if ( debug_level >= DEBUG_LEVEL_BH )
1126 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1127 __FILE__,__LINE__,info->device_name);
1128 }
1129
1130 void mgsl_bh_receive(struct mgsl_struct *info)
1131 {
1132 int (*get_rx_frame)(struct mgsl_struct *info) =
1133 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1134
1135 if ( debug_level >= DEBUG_LEVEL_BH )
1136 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1137 __FILE__,__LINE__,info->device_name);
1138
1139 do
1140 {
1141 if (info->rx_rcc_underrun) {
1142 unsigned long flags;
1143 spin_lock_irqsave(&info->irq_spinlock,flags);
1144 usc_start_receiver(info);
1145 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1146 return;
1147 }
1148 } while(get_rx_frame(info));
1149 }
1150
1151 void mgsl_bh_transmit(struct mgsl_struct *info)
1152 {
1153 struct tty_struct *tty = info->tty;
1154 unsigned long flags;
1155
1156 if ( debug_level >= DEBUG_LEVEL_BH )
1157 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1158 __FILE__,__LINE__,info->device_name);
1159
1160 if (tty) {
1161 tty_wakeup(tty);
1162 wake_up_interruptible(&tty->write_wait);
1163 }
1164
1165 /* if transmitter idle and loopmode_send_done_requested
1166 * then start echoing RxD to TxD
1167 */
1168 spin_lock_irqsave(&info->irq_spinlock,flags);
1169 if ( !info->tx_active && info->loopmode_send_done_requested )
1170 usc_loopmode_send_done( info );
1171 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1172 }
1173
1174 void mgsl_bh_status(struct mgsl_struct *info)
1175 {
1176 if ( debug_level >= DEBUG_LEVEL_BH )
1177 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1178 __FILE__,__LINE__,info->device_name);
1179
1180 info->ri_chkcount = 0;
1181 info->dsr_chkcount = 0;
1182 info->dcd_chkcount = 0;
1183 info->cts_chkcount = 0;
1184 }
1185
1186 /* mgsl_isr_receive_status()
1187 *
1188 * Service a receive status interrupt. The type of status
1189 * interrupt is indicated by the state of the RCSR.
1190 * This is only used for HDLC mode.
1191 *
1192 * Arguments: info pointer to device instance data
1193 * Return Value: None
1194 */
1195 void mgsl_isr_receive_status( struct mgsl_struct *info )
1196 {
1197 u16 status = usc_InReg( info, RCSR );
1198
1199 if ( debug_level >= DEBUG_LEVEL_ISR )
1200 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1201 __FILE__,__LINE__,status);
1202
1203 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1204 info->loopmode_insert_requested &&
1205 usc_loopmode_active(info) )
1206 {
1207 ++info->icount.rxabort;
1208 info->loopmode_insert_requested = FALSE;
1209
1210 /* clear CMR:13 to start echoing RxD to TxD */
1211 info->cmr_value &= ~BIT13;
1212 usc_OutReg(info, CMR, info->cmr_value);
1213
1214 /* disable received abort irq (no longer required) */
1215 usc_OutReg(info, RICR,
1216 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1217 }
1218
1219 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1220 if (status & RXSTATUS_EXITED_HUNT)
1221 info->icount.exithunt++;
1222 if (status & RXSTATUS_IDLE_RECEIVED)
1223 info->icount.rxidle++;
1224 wake_up_interruptible(&info->event_wait_q);
1225 }
1226
1227 if (status & RXSTATUS_OVERRUN){
1228 info->icount.rxover++;
1229 usc_process_rxoverrun_sync( info );
1230 }
1231
1232 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1233 usc_UnlatchRxstatusBits( info, status );
1234
1235 } /* end of mgsl_isr_receive_status() */
1236
1237 /* mgsl_isr_transmit_status()
1238 *
1239 * Service a transmit status interrupt
1240 * HDLC mode :end of transmit frame
1241 * Async mode:all data is sent
1242 * transmit status is indicated by bits in the TCSR.
1243 *
1244 * Arguments: info pointer to device instance data
1245 * Return Value: None
1246 */
1247 void mgsl_isr_transmit_status( struct mgsl_struct *info )
1248 {
1249 u16 status = usc_InReg( info, TCSR );
1250
1251 if ( debug_level >= DEBUG_LEVEL_ISR )
1252 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1253 __FILE__,__LINE__,status);
1254
1255 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1256 usc_UnlatchTxstatusBits( info, status );
1257
1258 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1259 {
1260 /* finished sending HDLC abort. This may leave */
1261 /* the TxFifo with data from the aborted frame */
1262 /* so purge the TxFifo. Also shutdown the DMA */
1263 /* channel in case there is data remaining in */
1264 /* the DMA buffer */
1265 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1266 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1267 }
1268
1269 if ( status & TXSTATUS_EOF_SENT )
1270 info->icount.txok++;
1271 else if ( status & TXSTATUS_UNDERRUN )
1272 info->icount.txunder++;
1273 else if ( status & TXSTATUS_ABORT_SENT )
1274 info->icount.txabort++;
1275 else
1276 info->icount.txunder++;
1277
1278 info->tx_active = 0;
1279 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1280 del_timer(&info->tx_timer);
1281
1282 if ( info->drop_rts_on_tx_done ) {
1283 usc_get_serial_signals( info );
1284 if ( info->serial_signals & SerialSignal_RTS ) {
1285 info->serial_signals &= ~SerialSignal_RTS;
1286 usc_set_serial_signals( info );
1287 }
1288 info->drop_rts_on_tx_done = 0;
1289 }
1290
1291 #ifdef CONFIG_HDLC
1292 if (info->netcount)
1293 hdlcdev_tx_done(info);
1294 else
1295 #endif
1296 {
1297 if (info->tty->stopped || info->tty->hw_stopped) {
1298 usc_stop_transmitter(info);
1299 return;
1300 }
1301 info->pending_bh |= BH_TRANSMIT;
1302 }
1303
1304 } /* end of mgsl_isr_transmit_status() */
1305
1306 /* mgsl_isr_io_pin()
1307 *
1308 * Service an Input/Output pin interrupt. The type of
1309 * interrupt is indicated by bits in the MISR
1310 *
1311 * Arguments: info pointer to device instance data
1312 * Return Value: None
1313 */
1314 void mgsl_isr_io_pin( struct mgsl_struct *info )
1315 {
1316 struct mgsl_icount *icount;
1317 u16 status = usc_InReg( info, MISR );
1318
1319 if ( debug_level >= DEBUG_LEVEL_ISR )
1320 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1321 __FILE__,__LINE__,status);
1322
1323 usc_ClearIrqPendingBits( info, IO_PIN );
1324 usc_UnlatchIostatusBits( info, status );
1325
1326 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1327 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1328 icount = &info->icount;
1329 /* update input line counters */
1330 if (status & MISCSTATUS_RI_LATCHED) {
1331 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1332 usc_DisablestatusIrqs(info,SICR_RI);
1333 icount->rng++;
1334 if ( status & MISCSTATUS_RI )
1335 info->input_signal_events.ri_up++;
1336 else
1337 info->input_signal_events.ri_down++;
1338 }
1339 if (status & MISCSTATUS_DSR_LATCHED) {
1340 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1341 usc_DisablestatusIrqs(info,SICR_DSR);
1342 icount->dsr++;
1343 if ( status & MISCSTATUS_DSR )
1344 info->input_signal_events.dsr_up++;
1345 else
1346 info->input_signal_events.dsr_down++;
1347 }
1348 if (status & MISCSTATUS_DCD_LATCHED) {
1349 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1350 usc_DisablestatusIrqs(info,SICR_DCD);
1351 icount->dcd++;
1352 if (status & MISCSTATUS_DCD) {
1353 info->input_signal_events.dcd_up++;
1354 } else
1355 info->input_signal_events.dcd_down++;
1356 #ifdef CONFIG_HDLC
1357 if (info->netcount)
1358 hdlc_set_carrier(status & MISCSTATUS_DCD, info->netdev);
1359 #endif
1360 }
1361 if (status & MISCSTATUS_CTS_LATCHED)
1362 {
1363 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1364 usc_DisablestatusIrqs(info,SICR_CTS);
1365 icount->cts++;
1366 if ( status & MISCSTATUS_CTS )
1367 info->input_signal_events.cts_up++;
1368 else
1369 info->input_signal_events.cts_down++;
1370 }
1371 wake_up_interruptible(&info->status_event_wait_q);
1372 wake_up_interruptible(&info->event_wait_q);
1373
1374 if ( (info->flags & ASYNC_CHECK_CD) &&
1375 (status & MISCSTATUS_DCD_LATCHED) ) {
1376 if ( debug_level >= DEBUG_LEVEL_ISR )
1377 printk("%s CD now %s...", info->device_name,
1378 (status & MISCSTATUS_DCD) ? "on" : "off");
1379 if (status & MISCSTATUS_DCD)
1380 wake_up_interruptible(&info->open_wait);
1381 else {
1382 if ( debug_level >= DEBUG_LEVEL_ISR )
1383 printk("doing serial hangup...");
1384 if (info->tty)
1385 tty_hangup(info->tty);
1386 }
1387 }
1388
1389 if ( (info->flags & ASYNC_CTS_FLOW) &&
1390 (status & MISCSTATUS_CTS_LATCHED) ) {
1391 if (info->tty->hw_stopped) {
1392 if (status & MISCSTATUS_CTS) {
1393 if ( debug_level >= DEBUG_LEVEL_ISR )
1394 printk("CTS tx start...");
1395 if (info->tty)
1396 info->tty->hw_stopped = 0;
1397 usc_start_transmitter(info);
1398 info->pending_bh |= BH_TRANSMIT;
1399 return;
1400 }
1401 } else {
1402 if (!(status & MISCSTATUS_CTS)) {
1403 if ( debug_level >= DEBUG_LEVEL_ISR )
1404 printk("CTS tx stop...");
1405 if (info->tty)
1406 info->tty->hw_stopped = 1;
1407 usc_stop_transmitter(info);
1408 }
1409 }
1410 }
1411 }
1412
1413 info->pending_bh |= BH_STATUS;
1414
1415 /* for diagnostics set IRQ flag */
1416 if ( status & MISCSTATUS_TXC_LATCHED ){
1417 usc_OutReg( info, SICR,
1418 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1419 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1420 info->irq_occurred = 1;
1421 }
1422
1423 } /* end of mgsl_isr_io_pin() */
1424
1425 /* mgsl_isr_transmit_data()
1426 *
1427 * Service a transmit data interrupt (async mode only).
1428 *
1429 * Arguments: info pointer to device instance data
1430 * Return Value: None
1431 */
1432 void mgsl_isr_transmit_data( struct mgsl_struct *info )
1433 {
1434 if ( debug_level >= DEBUG_LEVEL_ISR )
1435 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1436 __FILE__,__LINE__,info->xmit_cnt);
1437
1438 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1439
1440 if (info->tty->stopped || info->tty->hw_stopped) {
1441 usc_stop_transmitter(info);
1442 return;
1443 }
1444
1445 if ( info->xmit_cnt )
1446 usc_load_txfifo( info );
1447 else
1448 info->tx_active = 0;
1449
1450 if (info->xmit_cnt < WAKEUP_CHARS)
1451 info->pending_bh |= BH_TRANSMIT;
1452
1453 } /* end of mgsl_isr_transmit_data() */
1454
1455 /* mgsl_isr_receive_data()
1456 *
1457 * Service a receive data interrupt. This occurs
1458 * when operating in asynchronous interrupt transfer mode.
1459 * The receive data FIFO is flushed to the receive data buffers.
1460 *
1461 * Arguments: info pointer to device instance data
1462 * Return Value: None
1463 */
1464 void mgsl_isr_receive_data( struct mgsl_struct *info )
1465 {
1466 int Fifocount;
1467 u16 status;
1468 unsigned char DataByte;
1469 struct tty_struct *tty = info->tty;
1470 struct mgsl_icount *icount = &info->icount;
1471
1472 if ( debug_level >= DEBUG_LEVEL_ISR )
1473 printk("%s(%d):mgsl_isr_receive_data\n",
1474 __FILE__,__LINE__);
1475
1476 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1477
1478 /* select FIFO status for RICR readback */
1479 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1480
1481 /* clear the Wordstatus bit so that status readback */
1482 /* only reflects the status of this byte */
1483 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1484
1485 /* flush the receive FIFO */
1486
1487 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1488 /* read one byte from RxFIFO */
1489 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1490 info->io_base + CCAR );
1491 DataByte = inb( info->io_base + CCAR );
1492
1493 /* get the status of the received byte */
1494 status = usc_InReg(info, RCSR);
1495 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1496 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1497 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1498
1499 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
1500 continue;
1501
1502 *tty->flip.char_buf_ptr = DataByte;
1503 icount->rx++;
1504
1505 *tty->flip.flag_buf_ptr = 0;
1506 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1507 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1508 printk("rxerr=%04X\n",status);
1509 /* update error statistics */
1510 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1511 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1512 icount->brk++;
1513 } else if (status & RXSTATUS_PARITY_ERROR)
1514 icount->parity++;
1515 else if (status & RXSTATUS_FRAMING_ERROR)
1516 icount->frame++;
1517 else if (status & RXSTATUS_OVERRUN) {
1518 /* must issue purge fifo cmd before */
1519 /* 16C32 accepts more receive chars */
1520 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1521 icount->overrun++;
1522 }
1523
1524 /* discard char if tty control flags say so */
1525 if (status & info->ignore_status_mask)
1526 continue;
1527
1528 status &= info->read_status_mask;
1529
1530 if (status & RXSTATUS_BREAK_RECEIVED) {
1531 *tty->flip.flag_buf_ptr = TTY_BREAK;
1532 if (info->flags & ASYNC_SAK)
1533 do_SAK(tty);
1534 } else if (status & RXSTATUS_PARITY_ERROR)
1535 *tty->flip.flag_buf_ptr = TTY_PARITY;
1536 else if (status & RXSTATUS_FRAMING_ERROR)
1537 *tty->flip.flag_buf_ptr = TTY_FRAME;
1538 if (status & RXSTATUS_OVERRUN) {
1539 /* Overrun is special, since it's
1540 * reported immediately, and doesn't
1541 * affect the current character
1542 */
1543 if (tty->flip.count < TTY_FLIPBUF_SIZE) {
1544 tty->flip.count++;
1545 tty->flip.flag_buf_ptr++;
1546 tty->flip.char_buf_ptr++;
1547 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
1548 }
1549 }
1550 } /* end of if (error) */
1551
1552 tty->flip.flag_buf_ptr++;
1553 tty->flip.char_buf_ptr++;
1554 tty->flip.count++;
1555 }
1556
1557 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1558 printk("%s(%d):mgsl_isr_receive_data flip count=%d\n",
1559 __FILE__,__LINE__,tty->flip.count);
1560 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1561 __FILE__,__LINE__,icount->rx,icount->brk,
1562 icount->parity,icount->frame,icount->overrun);
1563 }
1564
1565 if ( tty->flip.count )
1566 tty_flip_buffer_push(tty);
1567 }
1568
1569 /* mgsl_isr_misc()
1570 *
1571 * Service a miscellaneos interrupt source.
1572 *
1573 * Arguments: info pointer to device extension (instance data)
1574 * Return Value: None
1575 */
1576 void mgsl_isr_misc( struct mgsl_struct *info )
1577 {
1578 u16 status = usc_InReg( info, MISR );
1579
1580 if ( debug_level >= DEBUG_LEVEL_ISR )
1581 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1582 __FILE__,__LINE__,status);
1583
1584 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1585 (info->params.mode == MGSL_MODE_HDLC)) {
1586
1587 /* turn off receiver and rx DMA */
1588 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1589 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1590 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1591 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1592 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1593
1594 /* schedule BH handler to restart receiver */
1595 info->pending_bh |= BH_RECEIVE;
1596 info->rx_rcc_underrun = 1;
1597 }
1598
1599 usc_ClearIrqPendingBits( info, MISC );
1600 usc_UnlatchMiscstatusBits( info, status );
1601
1602 } /* end of mgsl_isr_misc() */
1603
1604 /* mgsl_isr_null()
1605 *
1606 * Services undefined interrupt vectors from the
1607 * USC. (hence this function SHOULD never be called)
1608 *
1609 * Arguments: info pointer to device extension (instance data)
1610 * Return Value: None
1611 */
1612 void mgsl_isr_null( struct mgsl_struct *info )
1613 {
1614
1615 } /* end of mgsl_isr_null() */
1616
1617 /* mgsl_isr_receive_dma()
1618 *
1619 * Service a receive DMA channel interrupt.
1620 * For this driver there are two sources of receive DMA interrupts
1621 * as identified in the Receive DMA mode Register (RDMR):
1622 *
1623 * BIT3 EOA/EOL End of List, all receive buffers in receive
1624 * buffer list have been filled (no more free buffers
1625 * available). The DMA controller has shut down.
1626 *
1627 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1628 * DMA buffer is terminated in response to completion
1629 * of a good frame or a frame with errors. The status
1630 * of the frame is stored in the buffer entry in the
1631 * list of receive buffer entries.
1632 *
1633 * Arguments: info pointer to device instance data
1634 * Return Value: None
1635 */
1636 void mgsl_isr_receive_dma( struct mgsl_struct *info )
1637 {
1638 u16 status;
1639
1640 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1641 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1642
1643 /* Read the receive DMA status to identify interrupt type. */
1644 /* This also clears the status bits. */
1645 status = usc_InDmaReg( info, RDMR );
1646
1647 if ( debug_level >= DEBUG_LEVEL_ISR )
1648 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1649 __FILE__,__LINE__,info->device_name,status);
1650
1651 info->pending_bh |= BH_RECEIVE;
1652
1653 if ( status & BIT3 ) {
1654 info->rx_overflow = 1;
1655 info->icount.buf_overrun++;
1656 }
1657
1658 } /* end of mgsl_isr_receive_dma() */
1659
1660 /* mgsl_isr_transmit_dma()
1661 *
1662 * This function services a transmit DMA channel interrupt.
1663 *
1664 * For this driver there is one source of transmit DMA interrupts
1665 * as identified in the Transmit DMA Mode Register (TDMR):
1666 *
1667 * BIT2 EOB End of Buffer. This interrupt occurs when a
1668 * transmit DMA buffer has been emptied.
1669 *
1670 * The driver maintains enough transmit DMA buffers to hold at least
1671 * one max frame size transmit frame. When operating in a buffered
1672 * transmit mode, there may be enough transmit DMA buffers to hold at
1673 * least two or more max frame size frames. On an EOB condition,
1674 * determine if there are any queued transmit buffers and copy into
1675 * transmit DMA buffers if we have room.
1676 *
1677 * Arguments: info pointer to device instance data
1678 * Return Value: None
1679 */
1680 void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1681 {
1682 u16 status;
1683
1684 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1685 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1686
1687 /* Read the transmit DMA status to identify interrupt type. */
1688 /* This also clears the status bits. */
1689
1690 status = usc_InDmaReg( info, TDMR );
1691
1692 if ( debug_level >= DEBUG_LEVEL_ISR )
1693 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1694 __FILE__,__LINE__,info->device_name,status);
1695
1696 if ( status & BIT2 ) {
1697 --info->tx_dma_buffers_used;
1698
1699 /* if there are transmit frames queued,
1700 * try to load the next one
1701 */
1702 if ( load_next_tx_holding_buffer(info) ) {
1703 /* if call returns non-zero value, we have
1704 * at least one free tx holding buffer
1705 */
1706 info->pending_bh |= BH_TRANSMIT;
1707 }
1708 }
1709
1710 } /* end of mgsl_isr_transmit_dma() */
1711
1712 /* mgsl_interrupt()
1713 *
1714 * Interrupt service routine entry point.
1715 *
1716 * Arguments:
1717 *
1718 * irq interrupt number that caused interrupt
1719 * dev_id device ID supplied during interrupt registration
1720 * regs interrupted processor context
1721 *
1722 * Return Value: None
1723 */
1724 static irqreturn_t mgsl_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1725 {
1726 struct mgsl_struct * info;
1727 u16 UscVector;
1728 u16 DmaVector;
1729
1730 if ( debug_level >= DEBUG_LEVEL_ISR )
1731 printk("%s(%d):mgsl_interrupt(%d)entry.\n",
1732 __FILE__,__LINE__,irq);
1733
1734 info = (struct mgsl_struct *)dev_id;
1735 if (!info)
1736 return IRQ_NONE;
1737
1738 spin_lock(&info->irq_spinlock);
1739
1740 for(;;) {
1741 /* Read the interrupt vectors from hardware. */
1742 UscVector = usc_InReg(info, IVR) >> 9;
1743 DmaVector = usc_InDmaReg(info, DIVR);
1744
1745 if ( debug_level >= DEBUG_LEVEL_ISR )
1746 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1747 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1748
1749 if ( !UscVector && !DmaVector )
1750 break;
1751
1752 /* Dispatch interrupt vector */
1753 if ( UscVector )
1754 (*UscIsrTable[UscVector])(info);
1755 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1756 mgsl_isr_transmit_dma(info);
1757 else
1758 mgsl_isr_receive_dma(info);
1759
1760 if ( info->isr_overflow ) {
1761 printk(KERN_ERR"%s(%d):%s isr overflow irq=%d\n",
1762 __FILE__,__LINE__,info->device_name, irq);
1763 usc_DisableMasterIrqBit(info);
1764 usc_DisableDmaInterrupts(info,DICR_MASTER);
1765 break;
1766 }
1767 }
1768
1769 /* Request bottom half processing if there's something
1770 * for it to do and the bh is not already running
1771 */
1772
1773 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1774 if ( debug_level >= DEBUG_LEVEL_ISR )
1775 printk("%s(%d):%s queueing bh task.\n",
1776 __FILE__,__LINE__,info->device_name);
1777 schedule_work(&info->task);
1778 info->bh_requested = 1;
1779 }
1780
1781 spin_unlock(&info->irq_spinlock);
1782
1783 if ( debug_level >= DEBUG_LEVEL_ISR )
1784 printk("%s(%d):mgsl_interrupt(%d)exit.\n",
1785 __FILE__,__LINE__,irq);
1786 return IRQ_HANDLED;
1787 } /* end of mgsl_interrupt() */
1788
1789 /* startup()
1790 *
1791 * Initialize and start device.
1792 *
1793 * Arguments: info pointer to device instance data
1794 * Return Value: 0 if success, otherwise error code
1795 */
1796 static int startup(struct mgsl_struct * info)
1797 {
1798 int retval = 0;
1799
1800 if ( debug_level >= DEBUG_LEVEL_INFO )
1801 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1802
1803 if (info->flags & ASYNC_INITIALIZED)
1804 return 0;
1805
1806 if (!info->xmit_buf) {
1807 /* allocate a page of memory for a transmit buffer */
1808 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1809 if (!info->xmit_buf) {
1810 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1811 __FILE__,__LINE__,info->device_name);
1812 return -ENOMEM;
1813 }
1814 }
1815
1816 info->pending_bh = 0;
1817
1818 init_timer(&info->tx_timer);
1819 info->tx_timer.data = (unsigned long)info;
1820 info->tx_timer.function = mgsl_tx_timeout;
1821
1822 /* Allocate and claim adapter resources */
1823 retval = mgsl_claim_resources(info);
1824
1825 /* perform existence check and diagnostics */
1826 if ( !retval )
1827 retval = mgsl_adapter_test(info);
1828
1829 if ( retval ) {
1830 if (capable(CAP_SYS_ADMIN) && info->tty)
1831 set_bit(TTY_IO_ERROR, &info->tty->flags);
1832 mgsl_release_resources(info);
1833 return retval;
1834 }
1835
1836 /* program hardware for current parameters */
1837 mgsl_change_params(info);
1838
1839 if (info->tty)
1840 clear_bit(TTY_IO_ERROR, &info->tty->flags);
1841
1842 info->flags |= ASYNC_INITIALIZED;
1843
1844 return 0;
1845
1846 } /* end of startup() */
1847
1848 /* shutdown()
1849 *
1850 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1851 *
1852 * Arguments: info pointer to device instance data
1853 * Return Value: None
1854 */
1855 static void shutdown(struct mgsl_struct * info)
1856 {
1857 unsigned long flags;
1858
1859 if (!(info->flags & ASYNC_INITIALIZED))
1860 return;
1861
1862 if (debug_level >= DEBUG_LEVEL_INFO)
1863 printk("%s(%d):mgsl_shutdown(%s)\n",
1864 __FILE__,__LINE__, info->device_name );
1865
1866 /* clear status wait queue because status changes */
1867 /* can't happen after shutting down the hardware */
1868 wake_up_interruptible(&info->status_event_wait_q);
1869 wake_up_interruptible(&info->event_wait_q);
1870
1871 del_timer(&info->tx_timer);
1872
1873 if (info->xmit_buf) {
1874 free_page((unsigned long) info->xmit_buf);
1875 info->xmit_buf = NULL;
1876 }
1877
1878 spin_lock_irqsave(&info->irq_spinlock,flags);
1879 usc_DisableMasterIrqBit(info);
1880 usc_stop_receiver(info);
1881 usc_stop_transmitter(info);
1882 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1883 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1884 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1885
1886 /* Disable DMAEN (Port 7, Bit 14) */
1887 /* This disconnects the DMA request signal from the ISA bus */
1888 /* on the ISA adapter. This has no effect for the PCI adapter */
1889 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1890
1891 /* Disable INTEN (Port 6, Bit12) */
1892 /* This disconnects the IRQ request signal to the ISA bus */
1893 /* on the ISA adapter. This has no effect for the PCI adapter */
1894 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1895
1896 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
1897 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1898 usc_set_serial_signals(info);
1899 }
1900
1901 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1902
1903 mgsl_release_resources(info);
1904
1905 if (info->tty)
1906 set_bit(TTY_IO_ERROR, &info->tty->flags);
1907
1908 info->flags &= ~ASYNC_INITIALIZED;
1909
1910 } /* end of shutdown() */
1911
1912 static void mgsl_program_hw(struct mgsl_struct *info)
1913 {
1914 unsigned long flags;
1915
1916 spin_lock_irqsave(&info->irq_spinlock,flags);
1917
1918 usc_stop_receiver(info);
1919 usc_stop_transmitter(info);
1920 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1921
1922 if (info->params.mode == MGSL_MODE_HDLC ||
1923 info->params.mode == MGSL_MODE_RAW ||
1924 info->netcount)
1925 usc_set_sync_mode(info);
1926 else
1927 usc_set_async_mode(info);
1928
1929 usc_set_serial_signals(info);
1930
1931 info->dcd_chkcount = 0;
1932 info->cts_chkcount = 0;
1933 info->ri_chkcount = 0;
1934 info->dsr_chkcount = 0;
1935
1936 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1937 usc_EnableInterrupts(info, IO_PIN);
1938 usc_get_serial_signals(info);
1939
1940 if (info->netcount || info->tty->termios->c_cflag & CREAD)
1941 usc_start_receiver(info);
1942
1943 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1944 }
1945
1946 /* Reconfigure adapter based on new parameters
1947 */
1948 static void mgsl_change_params(struct mgsl_struct *info)
1949 {
1950 unsigned cflag;
1951 int bits_per_char;
1952
1953 if (!info->tty || !info->tty->termios)
1954 return;
1955
1956 if (debug_level >= DEBUG_LEVEL_INFO)
1957 printk("%s(%d):mgsl_change_params(%s)\n",
1958 __FILE__,__LINE__, info->device_name );
1959
1960 cflag = info->tty->termios->c_cflag;
1961
1962 /* if B0 rate (hangup) specified then negate DTR and RTS */
1963 /* otherwise assert DTR and RTS */
1964 if (cflag & CBAUD)
1965 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1966 else
1967 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1968
1969 /* byte size and parity */
1970
1971 switch (cflag & CSIZE) {
1972 case CS5: info->params.data_bits = 5; break;
1973 case CS6: info->params.data_bits = 6; break;
1974 case CS7: info->params.data_bits = 7; break;
1975 case CS8: info->params.data_bits = 8; break;
1976 /* Never happens, but GCC is too dumb to figure it out */
1977 default: info->params.data_bits = 7; break;
1978 }
1979
1980 if (cflag & CSTOPB)
1981 info->params.stop_bits = 2;
1982 else
1983 info->params.stop_bits = 1;
1984
1985 info->params.parity = ASYNC_PARITY_NONE;
1986 if (cflag & PARENB) {
1987 if (cflag & PARODD)
1988 info->params.parity = ASYNC_PARITY_ODD;
1989 else
1990 info->params.parity = ASYNC_PARITY_EVEN;
1991 #ifdef CMSPAR
1992 if (cflag & CMSPAR)
1993 info->params.parity = ASYNC_PARITY_SPACE;
1994 #endif
1995 }
1996
1997 /* calculate number of jiffies to transmit a full
1998 * FIFO (32 bytes) at specified data rate
1999 */
2000 bits_per_char = info->params.data_bits +
2001 info->params.stop_bits + 1;
2002
2003 /* if port data rate is set to 460800 or less then
2004 * allow tty settings to override, otherwise keep the
2005 * current data rate.
2006 */
2007 if (info->params.data_rate <= 460800)
2008 info->params.data_rate = tty_get_baud_rate(info->tty);
2009
2010 if ( info->params.data_rate ) {
2011 info->timeout = (32*HZ*bits_per_char) /
2012 info->params.data_rate;
2013 }
2014 info->timeout += HZ/50; /* Add .02 seconds of slop */
2015
2016 if (cflag & CRTSCTS)
2017 info->flags |= ASYNC_CTS_FLOW;
2018 else
2019 info->flags &= ~ASYNC_CTS_FLOW;
2020
2021 if (cflag & CLOCAL)
2022 info->flags &= ~ASYNC_CHECK_CD;
2023 else
2024 info->flags |= ASYNC_CHECK_CD;
2025
2026 /* process tty input control flags */
2027
2028 info->read_status_mask = RXSTATUS_OVERRUN;
2029 if (I_INPCK(info->tty))
2030 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
2031 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2032 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
2033
2034 if (I_IGNPAR(info->tty))
2035 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
2036 if (I_IGNBRK(info->tty)) {
2037 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
2038 /* If ignoring parity and break indicators, ignore
2039 * overruns too. (For real raw support).
2040 */
2041 if (I_IGNPAR(info->tty))
2042 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2043 }
2044
2045 mgsl_program_hw(info);
2046
2047 } /* end of mgsl_change_params() */
2048
2049 /* mgsl_put_char()
2050 *
2051 * Add a character to the transmit buffer.
2052 *
2053 * Arguments: tty pointer to tty information structure
2054 * ch character to add to transmit buffer
2055 *
2056 * Return Value: None
2057 */
2058 static void mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2059 {
2060 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2061 unsigned long flags;
2062
2063 if ( debug_level >= DEBUG_LEVEL_INFO ) {
2064 printk( "%s(%d):mgsl_put_char(%d) on %s\n",
2065 __FILE__,__LINE__,ch,info->device_name);
2066 }
2067
2068 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2069 return;
2070
2071 if (!tty || !info->xmit_buf)
2072 return;
2073
2074 spin_lock_irqsave(&info->irq_spinlock,flags);
2075
2076 if ( (info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active ) {
2077
2078 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2079 info->xmit_buf[info->xmit_head++] = ch;
2080 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2081 info->xmit_cnt++;
2082 }
2083 }
2084
2085 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2086
2087 } /* end of mgsl_put_char() */
2088
2089 /* mgsl_flush_chars()
2090 *
2091 * Enable transmitter so remaining characters in the
2092 * transmit buffer are sent.
2093 *
2094 * Arguments: tty pointer to tty information structure
2095 * Return Value: None
2096 */
2097 static void mgsl_flush_chars(struct tty_struct *tty)
2098 {
2099 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2100 unsigned long flags;
2101
2102 if ( debug_level >= DEBUG_LEVEL_INFO )
2103 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2104 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2105
2106 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2107 return;
2108
2109 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2110 !info->xmit_buf)
2111 return;
2112
2113 if ( debug_level >= DEBUG_LEVEL_INFO )
2114 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2115 __FILE__,__LINE__,info->device_name );
2116
2117 spin_lock_irqsave(&info->irq_spinlock,flags);
2118
2119 if (!info->tx_active) {
2120 if ( (info->params.mode == MGSL_MODE_HDLC ||
2121 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2122 /* operating in synchronous (frame oriented) mode */
2123 /* copy data from circular xmit_buf to */
2124 /* transmit DMA buffer. */
2125 mgsl_load_tx_dma_buffer(info,
2126 info->xmit_buf,info->xmit_cnt);
2127 }
2128 usc_start_transmitter(info);
2129 }
2130
2131 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2132
2133 } /* end of mgsl_flush_chars() */
2134
2135 /* mgsl_write()
2136 *
2137 * Send a block of data
2138 *
2139 * Arguments:
2140 *
2141 * tty pointer to tty information structure
2142 * from_user flag: 1 = from user process
2143 * buf pointer to buffer containing send data
2144 * count size of send data in bytes
2145 *
2146 * Return Value: number of characters written
2147 */
2148 static int mgsl_write(struct tty_struct * tty, int from_user,
2149 const unsigned char *buf, int count)
2150 {
2151 int c, ret = 0, err;
2152 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2153 unsigned long flags;
2154
2155 if ( debug_level >= DEBUG_LEVEL_INFO )
2156 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2157 __FILE__,__LINE__,info->device_name,count);
2158
2159 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2160 goto cleanup;
2161
2162 if (!tty || !info->xmit_buf || !tmp_buf)
2163 goto cleanup;
2164
2165 if ( info->params.mode == MGSL_MODE_HDLC ||
2166 info->params.mode == MGSL_MODE_RAW ) {
2167 /* operating in synchronous (frame oriented) mode */
2168 /* operating in synchronous (frame oriented) mode */
2169 if (info->tx_active) {
2170
2171 if ( info->params.mode == MGSL_MODE_HDLC ) {
2172 ret = 0;
2173 goto cleanup;
2174 }
2175 /* transmitter is actively sending data -
2176 * if we have multiple transmit dma and
2177 * holding buffers, attempt to queue this
2178 * frame for transmission at a later time.
2179 */
2180 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2181 /* no tx holding buffers available */
2182 ret = 0;
2183 goto cleanup;
2184 }
2185
2186 /* queue transmit frame request */
2187 ret = count;
2188 if (from_user) {
2189 down(&tmp_buf_sem);
2190 COPY_FROM_USER(err,tmp_buf, buf, count);
2191 if (err) {
2192 if ( debug_level >= DEBUG_LEVEL_INFO )
2193 printk( "%s(%d):mgsl_write(%s) sync user buf copy failed\n",
2194 __FILE__,__LINE__,info->device_name);
2195 ret = -EFAULT;
2196 } else
2197 save_tx_buffer_request(info,tmp_buf,count);
2198 up(&tmp_buf_sem);
2199 }
2200 else
2201 save_tx_buffer_request(info,buf,count);
2202
2203 /* if we have sufficient tx dma buffers,
2204 * load the next buffered tx request
2205 */
2206 spin_lock_irqsave(&info->irq_spinlock,flags);
2207 load_next_tx_holding_buffer(info);
2208 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2209 goto cleanup;
2210 }
2211
2212 /* if operating in HDLC LoopMode and the adapter */
2213 /* has yet to be inserted into the loop, we can't */
2214 /* transmit */
2215
2216 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2217 !usc_loopmode_active(info) )
2218 {
2219 ret = 0;
2220 goto cleanup;
2221 }
2222
2223 if ( info->xmit_cnt ) {
2224 /* Send accumulated from send_char() calls */
2225 /* as frame and wait before accepting more data. */
2226 ret = 0;
2227
2228 /* copy data from circular xmit_buf to */
2229 /* transmit DMA buffer. */
2230 mgsl_load_tx_dma_buffer(info,
2231 info->xmit_buf,info->xmit_cnt);
2232 if ( debug_level >= DEBUG_LEVEL_INFO )
2233 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2234 __FILE__,__LINE__,info->device_name);
2235 } else {
2236 if ( debug_level >= DEBUG_LEVEL_INFO )
2237 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2238 __FILE__,__LINE__,info->device_name);
2239 ret = count;
2240 info->xmit_cnt = count;
2241 if (from_user) {
2242 down(&tmp_buf_sem);
2243 COPY_FROM_USER(err,tmp_buf, buf, count);
2244 if (err) {
2245 if ( debug_level >= DEBUG_LEVEL_INFO )
2246 printk( "%s(%d):mgsl_write(%s) sync user buf copy failed\n",
2247 __FILE__,__LINE__,info->device_name);
2248 ret = -EFAULT;
2249 } else
2250 mgsl_load_tx_dma_buffer(info,tmp_buf,count);
2251 up(&tmp_buf_sem);
2252 }
2253 else
2254 mgsl_load_tx_dma_buffer(info,buf,count);
2255 }
2256 } else {
2257 if (from_user) {
2258 down(&tmp_buf_sem);
2259 while (1) {
2260 c = min_t(int, count,
2261 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2262 SERIAL_XMIT_SIZE - info->xmit_head));
2263 if (c <= 0)
2264 break;
2265
2266 COPY_FROM_USER(err,tmp_buf, buf, c);
2267 c -= err;
2268 if (!c) {
2269 if (!ret)
2270 ret = -EFAULT;
2271 break;
2272 }
2273 spin_lock_irqsave(&info->irq_spinlock,flags);
2274 c = min_t(int, c, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2275 SERIAL_XMIT_SIZE - info->xmit_head));
2276 memcpy(info->xmit_buf + info->xmit_head, tmp_buf, c);
2277 info->xmit_head = ((info->xmit_head + c) &
2278 (SERIAL_XMIT_SIZE-1));
2279 info->xmit_cnt += c;
2280 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2281 buf += c;
2282 count -= c;
2283 ret += c;
2284 }
2285 up(&tmp_buf_sem);
2286 } else {
2287 while (1) {
2288 spin_lock_irqsave(&info->irq_spinlock,flags);
2289 c = min_t(int, count,
2290 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2291 SERIAL_XMIT_SIZE - info->xmit_head));
2292 if (c <= 0) {
2293 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2294 break;
2295 }
2296 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2297 info->xmit_head = ((info->xmit_head + c) &
2298 (SERIAL_XMIT_SIZE-1));
2299 info->xmit_cnt += c;
2300 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2301 buf += c;
2302 count -= c;
2303 ret += c;
2304 }
2305 }
2306 }
2307
2308 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2309 spin_lock_irqsave(&info->irq_spinlock,flags);
2310 if (!info->tx_active)
2311 usc_start_transmitter(info);
2312 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2313 }
2314 cleanup:
2315 if ( debug_level >= DEBUG_LEVEL_INFO )
2316 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2317 __FILE__,__LINE__,info->device_name,ret);
2318
2319 return ret;
2320
2321 } /* end of mgsl_write() */
2322
2323 /* mgsl_write_room()
2324 *
2325 * Return the count of free bytes in transmit buffer
2326 *
2327 * Arguments: tty pointer to tty info structure
2328 * Return Value: None
2329 */
2330 static int mgsl_write_room(struct tty_struct *tty)
2331 {
2332 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2333 int ret;
2334
2335 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2336 return 0;
2337 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2338 if (ret < 0)
2339 ret = 0;
2340
2341 if (debug_level >= DEBUG_LEVEL_INFO)
2342 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2343 __FILE__,__LINE__, info->device_name,ret );
2344
2345 if ( info->params.mode == MGSL_MODE_HDLC ||
2346 info->params.mode == MGSL_MODE_RAW ) {
2347 /* operating in synchronous (frame oriented) mode */
2348 if ( info->tx_active )
2349 return 0;
2350 else
2351 return HDLC_MAX_FRAME_SIZE;
2352 }
2353
2354 return ret;
2355
2356 } /* end of mgsl_write_room() */
2357
2358 /* mgsl_chars_in_buffer()
2359 *
2360 * Return the count of bytes in transmit buffer
2361 *
2362 * Arguments: tty pointer to tty info structure
2363 * Return Value: None
2364 */
2365 static int mgsl_chars_in_buffer(struct tty_struct *tty)
2366 {
2367 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2368
2369 if (debug_level >= DEBUG_LEVEL_INFO)
2370 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2371 __FILE__,__LINE__, info->device_name );
2372
2373 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2374 return 0;
2375
2376 if (debug_level >= DEBUG_LEVEL_INFO)
2377 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2378 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2379
2380 if ( info->params.mode == MGSL_MODE_HDLC ||
2381 info->params.mode == MGSL_MODE_RAW ) {
2382 /* operating in synchronous (frame oriented) mode */
2383 if ( info->tx_active )
2384 return info->max_frame_size;
2385 else
2386 return 0;
2387 }
2388
2389 return info->xmit_cnt;
2390 } /* end of mgsl_chars_in_buffer() */
2391
2392 /* mgsl_flush_buffer()
2393 *
2394 * Discard all data in the send buffer
2395 *
2396 * Arguments: tty pointer to tty info structure
2397 * Return Value: None
2398 */
2399 static void mgsl_flush_buffer(struct tty_struct *tty)
2400 {
2401 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2402 unsigned long flags;
2403
2404 if (debug_level >= DEBUG_LEVEL_INFO)
2405 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2406 __FILE__,__LINE__, info->device_name );
2407
2408 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2409 return;
2410
2411 spin_lock_irqsave(&info->irq_spinlock,flags);
2412 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2413 del_timer(&info->tx_timer);
2414 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2415
2416 wake_up_interruptible(&tty->write_wait);
2417 tty_wakeup(tty);
2418 }
2419
2420 /* mgsl_send_xchar()
2421 *
2422 * Send a high-priority XON/XOFF character
2423 *
2424 * Arguments: tty pointer to tty info structure
2425 * ch character to send
2426 * Return Value: None
2427 */
2428 static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2429 {
2430 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2431 unsigned long flags;
2432
2433 if (debug_level >= DEBUG_LEVEL_INFO)
2434 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2435 __FILE__,__LINE__, info->device_name, ch );
2436
2437 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2438 return;
2439
2440 info->x_char = ch;
2441 if (ch) {
2442 /* Make sure transmit interrupts are on */
2443 spin_lock_irqsave(&info->irq_spinlock,flags);
2444 if (!info->tx_enabled)
2445 usc_start_transmitter(info);
2446 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2447 }
2448 } /* end of mgsl_send_xchar() */
2449
2450 /* mgsl_throttle()
2451 *
2452 * Signal remote device to throttle send data (our receive data)
2453 *
2454 * Arguments: tty pointer to tty info structure
2455 * Return Value: None
2456 */
2457 static void mgsl_throttle(struct tty_struct * tty)
2458 {
2459 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2460 unsigned long flags;
2461
2462 if (debug_level >= DEBUG_LEVEL_INFO)
2463 printk("%s(%d):mgsl_throttle(%s) entry\n",
2464 __FILE__,__LINE__, info->device_name );
2465
2466 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2467 return;
2468
2469 if (I_IXOFF(tty))
2470 mgsl_send_xchar(tty, STOP_CHAR(tty));
2471
2472 if (tty->termios->c_cflag & CRTSCTS) {
2473 spin_lock_irqsave(&info->irq_spinlock,flags);
2474 info->serial_signals &= ~SerialSignal_RTS;
2475 usc_set_serial_signals(info);
2476 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2477 }
2478 } /* end of mgsl_throttle() */
2479
2480 /* mgsl_unthrottle()
2481 *
2482 * Signal remote device to stop throttling send data (our receive data)
2483 *
2484 * Arguments: tty pointer to tty info structure
2485 * Return Value: None
2486 */
2487 static void mgsl_unthrottle(struct tty_struct * tty)
2488 {
2489 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2490 unsigned long flags;
2491
2492 if (debug_level >= DEBUG_LEVEL_INFO)
2493 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2494 __FILE__,__LINE__, info->device_name );
2495
2496 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2497 return;
2498
2499 if (I_IXOFF(tty)) {
2500 if (info->x_char)
2501 info->x_char = 0;
2502 else
2503 mgsl_send_xchar(tty, START_CHAR(tty));
2504 }
2505
2506 if (tty->termios->c_cflag & CRTSCTS) {
2507 spin_lock_irqsave(&info->irq_spinlock,flags);
2508 info->serial_signals |= SerialSignal_RTS;
2509 usc_set_serial_signals(info);
2510 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2511 }
2512
2513 } /* end of mgsl_unthrottle() */
2514
2515 /* mgsl_get_stats()
2516 *
2517 * get the current serial parameters information
2518 *
2519 * Arguments: info pointer to device instance data
2520 * user_icount pointer to buffer to hold returned stats
2521 *
2522 * Return Value: 0 if success, otherwise error code
2523 */
2524 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2525 {
2526 int err;
2527
2528 if (debug_level >= DEBUG_LEVEL_INFO)
2529 printk("%s(%d):mgsl_get_params(%s)\n",
2530 __FILE__,__LINE__, info->device_name);
2531
2532 COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2533 if (err) {
2534 if ( debug_level >= DEBUG_LEVEL_INFO )
2535 printk( "%s(%d):mgsl_get_stats(%s) user buffer copy failed\n",
2536 __FILE__,__LINE__,info->device_name);
2537 return -EFAULT;
2538 }
2539
2540 return 0;
2541
2542 } /* end of mgsl_get_stats() */
2543
2544 /* mgsl_get_params()
2545 *
2546 * get the current serial parameters information
2547 *
2548 * Arguments: info pointer to device instance data
2549 * user_params pointer to buffer to hold returned params
2550 *
2551 * Return Value: 0 if success, otherwise error code
2552 */
2553 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2554 {
2555 int err;
2556 if (debug_level >= DEBUG_LEVEL_INFO)
2557 printk("%s(%d):mgsl_get_params(%s)\n",
2558 __FILE__,__LINE__, info->device_name);
2559
2560 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2561 if (err) {
2562 if ( debug_level >= DEBUG_LEVEL_INFO )
2563 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2564 __FILE__,__LINE__,info->device_name);
2565 return -EFAULT;
2566 }
2567
2568 return 0;
2569
2570 } /* end of mgsl_get_params() */
2571
2572 /* mgsl_set_params()
2573 *
2574 * set the serial parameters
2575 *
2576 * Arguments:
2577 *
2578 * info pointer to device instance data
2579 * new_params user buffer containing new serial params
2580 *
2581 * Return Value: 0 if success, otherwise error code
2582 */
2583 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2584 {
2585 unsigned long flags;
2586 MGSL_PARAMS tmp_params;
2587 int err;
2588
2589 if (debug_level >= DEBUG_LEVEL_INFO)
2590 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2591 info->device_name );
2592 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2593 if (err) {
2594 if ( debug_level >= DEBUG_LEVEL_INFO )
2595 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2596 __FILE__,__LINE__,info->device_name);
2597 return -EFAULT;
2598 }
2599
2600 spin_lock_irqsave(&info->irq_spinlock,flags);
2601 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2602 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2603
2604 mgsl_change_params(info);
2605
2606 return 0;
2607
2608 } /* end of mgsl_set_params() */
2609
2610 /* mgsl_get_txidle()
2611 *
2612 * get the current transmit idle mode
2613 *
2614 * Arguments: info pointer to device instance data
2615 * idle_mode pointer to buffer to hold returned idle mode
2616 *
2617 * Return Value: 0 if success, otherwise error code
2618 */
2619 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2620 {
2621 int err;
2622
2623 if (debug_level >= DEBUG_LEVEL_INFO)
2624 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2625 __FILE__,__LINE__, info->device_name, info->idle_mode);
2626
2627 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2628 if (err) {
2629 if ( debug_level >= DEBUG_LEVEL_INFO )
2630 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2631 __FILE__,__LINE__,info->device_name);
2632 return -EFAULT;
2633 }
2634
2635 return 0;
2636
2637 } /* end of mgsl_get_txidle() */
2638
2639 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2640 *
2641 * Arguments: info pointer to device instance data
2642 * idle_mode new idle mode
2643 *
2644 * Return Value: 0 if success, otherwise error code
2645 */
2646 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2647 {
2648 unsigned long flags;
2649
2650 if (debug_level >= DEBUG_LEVEL_INFO)
2651 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2652 info->device_name, idle_mode );
2653
2654 spin_lock_irqsave(&info->irq_spinlock,flags);
2655 info->idle_mode = idle_mode;
2656 usc_set_txidle( info );
2657 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2658 return 0;
2659
2660 } /* end of mgsl_set_txidle() */
2661
2662 /* mgsl_txenable()
2663 *
2664 * enable or disable the transmitter
2665 *
2666 * Arguments:
2667 *
2668 * info pointer to device instance data
2669 * enable 1 = enable, 0 = disable
2670 *
2671 * Return Value: 0 if success, otherwise error code
2672 */
2673 static int mgsl_txenable(struct mgsl_struct * info, int enable)
2674 {
2675 unsigned long flags;
2676
2677 if (debug_level >= DEBUG_LEVEL_INFO)
2678 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2679 info->device_name, enable);
2680
2681 spin_lock_irqsave(&info->irq_spinlock,flags);
2682 if ( enable ) {
2683 if ( !info->tx_enabled ) {
2684
2685 usc_start_transmitter(info);
2686 /*--------------------------------------------------
2687 * if HDLC/SDLC Loop mode, attempt to insert the
2688 * station in the 'loop' by setting CMR:13. Upon
2689 * receipt of the next GoAhead (RxAbort) sequence,
2690 * the OnLoop indicator (CCSR:7) should go active
2691 * to indicate that we are on the loop
2692 *--------------------------------------------------*/
2693 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2694 usc_loopmode_insert_request( info );
2695 }
2696 } else {
2697 if ( info->tx_enabled )
2698 usc_stop_transmitter(info);
2699 }
2700 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2701 return 0;
2702
2703 } /* end of mgsl_txenable() */
2704
2705 /* mgsl_txabort() abort send HDLC frame
2706 *
2707 * Arguments: info pointer to device instance data
2708 * Return Value: 0 if success, otherwise error code
2709 */
2710 static int mgsl_txabort(struct mgsl_struct * info)
2711 {
2712 unsigned long flags;
2713
2714 if (debug_level >= DEBUG_LEVEL_INFO)
2715 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2716 info->device_name);
2717
2718 spin_lock_irqsave(&info->irq_spinlock,flags);
2719 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2720 {
2721 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2722 usc_loopmode_cancel_transmit( info );
2723 else
2724 usc_TCmd(info,TCmd_SendAbort);
2725 }
2726 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2727 return 0;
2728
2729 } /* end of mgsl_txabort() */
2730
2731 /* mgsl_rxenable() enable or disable the receiver
2732 *
2733 * Arguments: info pointer to device instance data
2734 * enable 1 = enable, 0 = disable
2735 * Return Value: 0 if success, otherwise error code
2736 */
2737 static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2738 {
2739 unsigned long flags;
2740
2741 if (debug_level >= DEBUG_LEVEL_INFO)
2742 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2743 info->device_name, enable);
2744
2745 spin_lock_irqsave(&info->irq_spinlock,flags);
2746 if ( enable ) {
2747 if ( !info->rx_enabled )
2748 usc_start_receiver(info);
2749 } else {
2750 if ( info->rx_enabled )
2751 usc_stop_receiver(info);
2752 }
2753 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2754 return 0;
2755
2756 } /* end of mgsl_rxenable() */
2757
2758 /* mgsl_wait_event() wait for specified event to occur
2759 *
2760 * Arguments: info pointer to device instance data
2761 * mask pointer to bitmask of events to wait for
2762 * Return Value: 0 if successful and bit mask updated with
2763 * of events triggerred,
2764 * otherwise error code
2765 */
2766 static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2767 {
2768 unsigned long flags;
2769 int s;
2770 int rc=0;
2771 struct mgsl_icount cprev, cnow;
2772 int events;
2773 int mask;
2774 struct _input_signal_events oldsigs, newsigs;
2775 DECLARE_WAITQUEUE(wait, current);
2776
2777 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2778 if (rc) {
2779 return -EFAULT;
2780 }
2781
2782 if (debug_level >= DEBUG_LEVEL_INFO)
2783 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2784 info->device_name, mask);
2785
2786 spin_lock_irqsave(&info->irq_spinlock,flags);
2787
2788 /* return immediately if state matches requested events */
2789 usc_get_serial_signals(info);
2790 s = info->serial_signals;
2791 events = mask &
2792 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2793 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2794 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2795 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2796 if (events) {
2797 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2798 goto exit;
2799 }
2800
2801 /* save current irq counts */
2802 cprev = info->icount;
2803 oldsigs = info->input_signal_events;
2804
2805 /* enable hunt and idle irqs if needed */
2806 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2807 u16 oldreg = usc_InReg(info,RICR);
2808 u16 newreg = oldreg +
2809 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2810 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2811 if (oldreg != newreg)
2812 usc_OutReg(info, RICR, newreg);
2813 }
2814
2815 set_current_state(TASK_INTERRUPTIBLE);
2816 add_wait_queue(&info->event_wait_q, &wait);
2817
2818 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2819
2820
2821 for(;;) {
2822 schedule();
2823 if (signal_pending(current)) {
2824 rc = -ERESTARTSYS;
2825 break;
2826 }
2827
2828 /* get current irq counts */
2829 spin_lock_irqsave(&info->irq_spinlock,flags);
2830 cnow = info->icount;
2831 newsigs = info->input_signal_events;
2832 set_current_state(TASK_INTERRUPTIBLE);
2833 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2834
2835 /* if no change, wait aborted for some reason */
2836 if (newsigs.dsr_up == oldsigs.dsr_up &&
2837 newsigs.dsr_down == oldsigs.dsr_down &&
2838 newsigs.dcd_up == oldsigs.dcd_up &&
2839 newsigs.dcd_down == oldsigs.dcd_down &&
2840 newsigs.cts_up == oldsigs.cts_up &&
2841 newsigs.cts_down == oldsigs.cts_down &&
2842 newsigs.ri_up == oldsigs.ri_up &&
2843 newsigs.ri_down == oldsigs.ri_down &&
2844 cnow.exithunt == cprev.exithunt &&
2845 cnow.rxidle == cprev.rxidle) {
2846 rc = -EIO;
2847 break;
2848 }
2849
2850 events = mask &
2851 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2852 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2853 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2854 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2855 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2856 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2857 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2858 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2859 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2860 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2861 if (events)
2862 break;
2863
2864 cprev = cnow;
2865 oldsigs = newsigs;
2866 }
2867
2868 remove_wait_queue(&info->event_wait_q, &wait);
2869 set_current_state(TASK_RUNNING);
2870
2871 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2872 spin_lock_irqsave(&info->irq_spinlock,flags);
2873 if (!waitqueue_active(&info->event_wait_q)) {
2874 /* disable enable exit hunt mode/idle rcvd IRQs */
2875 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2876 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2877 }
2878 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2879 }
2880 exit:
2881 if ( rc == 0 )
2882 PUT_USER(rc, events, mask_ptr);
2883
2884 return rc;
2885
2886 } /* end of mgsl_wait_event() */
2887
2888 static int modem_input_wait(struct mgsl_struct *info,int arg)
2889 {
2890 unsigned long flags;
2891 int rc;
2892 struct mgsl_icount cprev, cnow;
2893 DECLARE_WAITQUEUE(wait, current);
2894
2895 /* save current irq counts */
2896 spin_lock_irqsave(&info->irq_spinlock,flags);
2897 cprev = info->icount;
2898 add_wait_queue(&info->status_event_wait_q, &wait);
2899 set_current_state(TASK_INTERRUPTIBLE);
2900 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2901
2902 for(;;) {
2903 schedule();
2904 if (signal_pending(current)) {
2905 rc = -ERESTARTSYS;
2906 break;
2907 }
2908
2909 /* get new irq counts */
2910 spin_lock_irqsave(&info->irq_spinlock,flags);
2911 cnow = info->icount;
2912 set_current_state(TASK_INTERRUPTIBLE);
2913 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2914
2915 /* if no change, wait aborted for some reason */
2916 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2917 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2918 rc = -EIO;
2919 break;
2920 }
2921
2922 /* check for change in caller specified modem input */
2923 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2924 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2925 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2926 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2927 rc = 0;
2928 break;
2929 }
2930
2931 cprev = cnow;
2932 }
2933 remove_wait_queue(&info->status_event_wait_q, &wait);
2934 set_current_state(TASK_RUNNING);
2935 return rc;
2936 }
2937
2938 /* return the state of the serial control and status signals
2939 */
2940 static int tiocmget(struct tty_struct *tty, struct file *file)
2941 {
2942 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2943 unsigned int result;
2944 unsigned long flags;
2945
2946 spin_lock_irqsave(&info->irq_spinlock,flags);
2947 usc_get_serial_signals(info);
2948 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2949
2950 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2951 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2952 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2953 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2954 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2955 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2956
2957 if (debug_level >= DEBUG_LEVEL_INFO)
2958 printk("%s(%d):%s tiocmget() value=%08X\n",
2959 __FILE__,__LINE__, info->device_name, result );
2960 return result;
2961 }
2962
2963 /* set modem control signals (DTR/RTS)
2964 */
2965 static int tiocmset(struct tty_struct *tty, struct file *file,
2966 unsigned int set, unsigned int clear)
2967 {
2968 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2969 unsigned long flags;
2970
2971 if (debug_level >= DEBUG_LEVEL_INFO)
2972 printk("%s(%d):%s tiocmset(%x,%x)\n",
2973 __FILE__,__LINE__,info->device_name, set, clear);
2974
2975 if (set & TIOCM_RTS)
2976 info->serial_signals |= SerialSignal_RTS;
2977 if (set & TIOCM_DTR)
2978 info->serial_signals |= SerialSignal_DTR;
2979 if (clear & TIOCM_RTS)
2980 info->serial_signals &= ~SerialSignal_RTS;
2981 if (clear & TIOCM_DTR)
2982 info->serial_signals &= ~SerialSignal_DTR;
2983
2984 spin_lock_irqsave(&info->irq_spinlock,flags);
2985 usc_set_serial_signals(info);
2986 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2987
2988 return 0;
2989 }
2990
2991 /* mgsl_break() Set or clear transmit break condition
2992 *
2993 * Arguments: tty pointer to tty instance data
2994 * break_state -1=set break condition, 0=clear
2995 * Return Value: None
2996 */
2997 static void mgsl_break(struct tty_struct *tty, int break_state)
2998 {
2999 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3000 unsigned long flags;
3001
3002 if (debug_level >= DEBUG_LEVEL_INFO)
3003 printk("%s(%d):mgsl_break(%s,%d)\n",
3004 __FILE__,__LINE__, info->device_name, break_state);
3005
3006 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
3007 return;
3008
3009 spin_lock_irqsave(&info->irq_spinlock,flags);
3010 if (break_state == -1)
3011 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
3012 else
3013 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
3014 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3015
3016 } /* end of mgsl_break() */
3017
3018 /* mgsl_ioctl() Service an IOCTL request
3019 *
3020 * Arguments:
3021 *
3022 * tty pointer to tty instance data
3023 * file pointer to associated file object for device
3024 * cmd IOCTL command code
3025 * arg command argument/context
3026 *
3027 * Return Value: 0 if success, otherwise error code
3028 */
3029 static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
3030 unsigned int cmd, unsigned long arg)
3031 {
3032 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3033
3034 if (debug_level >= DEBUG_LEVEL_INFO)
3035 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
3036 info->device_name, cmd );
3037
3038 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
3039 return -ENODEV;
3040
3041 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3042 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
3043 if (tty->flags & (1 << TTY_IO_ERROR))
3044 return -EIO;
3045 }
3046
3047 return mgsl_ioctl_common(info, cmd, arg);
3048 }
3049
3050 int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
3051 {
3052 int error;
3053 struct mgsl_icount cnow; /* kernel counter temps */
3054 void __user *argp = (void __user *)arg;
3055 struct serial_icounter_struct __user *p_cuser; /* user space */
3056 unsigned long flags;
3057
3058 switch (cmd) {
3059 case MGSL_IOCGPARAMS:
3060 return mgsl_get_params(info, argp);
3061 case MGSL_IOCSPARAMS:
3062 return mgsl_set_params(info, argp);
3063 case MGSL_IOCGTXIDLE:
3064 return mgsl_get_txidle(info, argp);
3065 case MGSL_IOCSTXIDLE:
3066 return mgsl_set_txidle(info,(int)arg);
3067 case MGSL_IOCTXENABLE:
3068 return mgsl_txenable(info,(int)arg);
3069 case MGSL_IOCRXENABLE:
3070 return mgsl_rxenable(info,(int)arg);
3071 case MGSL_IOCTXABORT:
3072 return mgsl_txabort(info);
3073 case MGSL_IOCGSTATS:
3074 return mgsl_get_stats(info, argp);
3075 case MGSL_IOCWAITEVENT:
3076 return mgsl_wait_event(info, argp);
3077 case MGSL_IOCLOOPTXDONE:
3078 return mgsl_loopmode_send_done(info);
3079 /* Wait for modem input (DCD,RI,DSR,CTS) change
3080 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3081 */
3082 case TIOCMIWAIT:
3083 return modem_input_wait(info,(int)arg);
3084
3085 /*
3086 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
3087 * Return: write counters to the user passed counter struct
3088 * NB: both 1->0 and 0->1 transitions are counted except for
3089 * RI where only 0->1 is counted.
3090 */
3091 case TIOCGICOUNT:
3092 spin_lock_irqsave(&info->irq_spinlock,flags);
3093 cnow = info->icount;
3094 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3095 p_cuser = argp;
3096 PUT_USER(error,cnow.cts, &p_cuser->cts);
3097 if (error) return error;
3098 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3099 if (error) return error;
3100 PUT_USER(error,cnow.rng, &p_cuser->rng);
3101 if (error) return error;
3102 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3103 if (error) return error;
3104 PUT_USER(error,cnow.rx, &p_cuser->rx);
3105 if (error) return error;
3106 PUT_USER(error,cnow.tx, &p_cuser->tx);
3107 if (error) return error;
3108 PUT_USER(error,cnow.frame, &p_cuser->frame);
3109 if (error) return error;
3110 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3111 if (error) return error;
3112 PUT_USER(error,cnow.parity, &p_cuser->parity);
3113 if (error) return error;
3114 PUT_USER(error,cnow.brk, &p_cuser->brk);
3115 if (error) return error;
3116 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3117 if (error) return error;
3118 return 0;
3119 default:
3120 return -ENOIOCTLCMD;
3121 }
3122 return 0;
3123 }
3124
3125 /* mgsl_set_termios()
3126 *
3127 * Set new termios settings
3128 *
3129 * Arguments:
3130 *
3131 * tty pointer to tty structure
3132 * termios pointer to buffer to hold returned old termios
3133 *
3134 * Return Value: None
3135 */
3136 static void mgsl_set_termios(struct tty_struct *tty, struct termios *old_termios)
3137 {
3138 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
3139 unsigned long flags;
3140
3141 if (debug_level >= DEBUG_LEVEL_INFO)
3142 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3143 tty->driver->name );
3144
3145 /* just return if nothing has changed */
3146 if ((tty->termios->c_cflag == old_termios->c_cflag)
3147 && (RELEVANT_IFLAG(tty->termios->c_iflag)
3148 == RELEVANT_IFLAG(old_termios->c_iflag)))
3149 return;
3150
3151 mgsl_change_params(info);
3152
3153 /* Handle transition to B0 status */
3154 if (old_termios->c_cflag & CBAUD &&
3155 !(tty->termios->c_cflag & CBAUD)) {
3156 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3157 spin_lock_irqsave(&info->irq_spinlock,flags);
3158 usc_set_serial_signals(info);
3159 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3160 }
3161
3162 /* Handle transition away from B0 status */
3163 if (!(old_termios->c_cflag & CBAUD) &&
3164 tty->termios->c_cflag & CBAUD) {
3165 info->serial_signals |= SerialSignal_DTR;
3166 if (!(tty->termios->c_cflag & CRTSCTS) ||
3167 !test_bit(TTY_THROTTLED, &tty->flags)) {
3168 info->serial_signals |= SerialSignal_RTS;
3169 }
3170 spin_lock_irqsave(&info->irq_spinlock,flags);
3171 usc_set_serial_signals(info);
3172 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3173 }
3174
3175 /* Handle turning off CRTSCTS */
3176 if (old_termios->c_cflag & CRTSCTS &&
3177 !(tty->termios->c_cflag & CRTSCTS)) {
3178 tty->hw_stopped = 0;
3179 mgsl_start(tty);
3180 }
3181
3182 } /* end of mgsl_set_termios() */
3183
3184 /* mgsl_close()
3185 *
3186 * Called when port is closed. Wait for remaining data to be
3187 * sent. Disable port and free resources.
3188 *
3189 * Arguments:
3190 *
3191 * tty pointer to open tty structure
3192 * filp pointer to open file object
3193 *
3194 * Return Value: None
3195 */
3196 static void mgsl_close(struct tty_struct *tty, struct file * filp)
3197 {
3198 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3199
3200 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3201 return;
3202
3203 if (debug_level >= DEBUG_LEVEL_INFO)
3204 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3205 __FILE__,__LINE__, info->device_name, info->count);
3206
3207 if (!info->count)
3208 return;
3209
3210 if (tty_hung_up_p(filp))
3211 goto cleanup;
3212
3213 if ((tty->count == 1) && (info->count != 1)) {
3214 /*
3215 * tty->count is 1 and the tty structure will be freed.
3216 * info->count should be one in this case.
3217 * if it's not, correct it so that the port is shutdown.
3218 */
3219 printk("mgsl_close: bad refcount; tty->count is 1, "
3220 "info->count is %d\n", info->count);
3221 info->count = 1;
3222 }
3223
3224 info->count--;
3225
3226 /* if at least one open remaining, leave hardware active */
3227 if (info->count)
3228 goto cleanup;
3229
3230 info->flags |= ASYNC_CLOSING;
3231
3232 /* set tty->closing to notify line discipline to
3233 * only process XON/XOFF characters. Only the N_TTY
3234 * discipline appears to use this (ppp does not).
3235 */
3236 tty->closing = 1;
3237
3238 /* wait for transmit data to clear all layers */
3239
3240 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
3241 if (debug_level >= DEBUG_LEVEL_INFO)
3242 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3243 __FILE__,__LINE__, info->device_name );
3244 tty_wait_until_sent(tty, info->closing_wait);
3245 }
3246
3247 if (info->flags & ASYNC_INITIALIZED)
3248 mgsl_wait_until_sent(tty, info->timeout);
3249
3250 if (tty->driver->flush_buffer)
3251 tty->driver->flush_buffer(tty);
3252
3253 tty_ldisc_flush(tty);
3254
3255 shutdown(info);
3256
3257 tty->closing = 0;
3258 info->tty = NULL;
3259
3260 if (info->blocked_open) {
3261 if (info->close_delay) {
3262 set_current_state(TASK_INTERRUPTIBLE);
3263 schedule_timeout(info->close_delay);
3264 }
3265 wake_up_interruptible(&info->open_wait);
3266 }
3267
3268 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3269
3270 wake_up_interruptible(&info->close_wait);
3271
3272 cleanup:
3273 if (debug_level >= DEBUG_LEVEL_INFO)
3274 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3275 tty->driver->name, info->count);
3276
3277 } /* end of mgsl_close() */
3278
3279 /* mgsl_wait_until_sent()
3280 *
3281 * Wait until the transmitter is empty.
3282 *
3283 * Arguments:
3284 *
3285 * tty pointer to tty info structure
3286 * timeout time to wait for send completion
3287 *
3288 * Return Value: None
3289 */
3290 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3291 {
3292 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3293 unsigned long orig_jiffies, char_time;
3294
3295 if (!info )
3296 return;
3297
3298 if (debug_level >= DEBUG_LEVEL_INFO)
3299 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3300 __FILE__,__LINE__, info->device_name );
3301
3302 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3303 return;
3304
3305 if (!(info->flags & ASYNC_INITIALIZED))
3306 goto exit;
3307
3308 orig_jiffies = jiffies;
3309
3310 /* Set check interval to 1/5 of estimated time to
3311 * send a character, and make it at least 1. The check
3312 * interval should also be less than the timeout.
3313 * Note: use tight timings here to satisfy the NIST-PCTS.
3314 */
3315
3316 if ( info->params.data_rate ) {
3317 char_time = info->timeout/(32 * 5);
3318 if (!char_time)
3319 char_time++;
3320 } else
3321 char_time = 1;
3322
3323 if (timeout)
3324 char_time = min_t(unsigned long, char_time, timeout);
3325
3326 if ( info->params.mode == MGSL_MODE_HDLC ||
3327 info->params.mode == MGSL_MODE_RAW ) {
3328 while (info->tx_active) {
3329 set_current_state(TASK_INTERRUPTIBLE);
3330 schedule_timeout(char_time);
3331 if (signal_pending(current))
3332 break;
3333 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3334 break;
3335 }
3336 } else {
3337 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3338 info->tx_enabled) {
3339 set_current_state(TASK_INTERRUPTIBLE);
3340 schedule_timeout(char_time);
3341 if (signal_pending(current))
3342 break;
3343 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3344 break;
3345 }
3346 }
3347
3348 exit:
3349 if (debug_level >= DEBUG_LEVEL_INFO)
3350 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3351 __FILE__,__LINE__, info->device_name );
3352
3353 } /* end of mgsl_wait_until_sent() */
3354
3355 /* mgsl_hangup()
3356 *
3357 * Called by tty_hangup() when a hangup is signaled.
3358 * This is the same as to closing all open files for the port.
3359 *
3360 * Arguments: tty pointer to associated tty object
3361 * Return Value: None
3362 */
3363 static void mgsl_hangup(struct tty_struct *tty)
3364 {
3365 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3366
3367 if (debug_level >= DEBUG_LEVEL_INFO)
3368 printk("%s(%d):mgsl_hangup(%s)\n",
3369 __FILE__,__LINE__, info->device_name );
3370
3371 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3372 return;
3373
3374 mgsl_flush_buffer(tty);
3375 shutdown(info);
3376
3377 info->count = 0;
3378 info->flags &= ~ASYNC_NORMAL_ACTIVE;
3379 info->tty = NULL;
3380
3381 wake_up_interruptible(&info->open_wait);
3382
3383 } /* end of mgsl_hangup() */
3384
3385 /* block_til_ready()
3386 *
3387 * Block the current process until the specified port
3388 * is ready to be opened.
3389 *
3390 * Arguments:
3391 *
3392 * tty pointer to tty info structure
3393 * filp pointer to open file object
3394 * info pointer to device instance data
3395 *
3396 * Return Value: 0 if success, otherwise error code
3397 */
3398 static int block_til_ready(struct tty_struct *tty, struct file * filp,
3399 struct mgsl_struct *info)
3400 {
3401 DECLARE_WAITQUEUE(wait, current);
3402 int retval;
3403 int do_clocal = 0, extra_count = 0;
3404 unsigned long flags;
3405
3406 if (debug_level >= DEBUG_LEVEL_INFO)
3407 printk("%s(%d):block_til_ready on %s\n",
3408 __FILE__,__LINE__, tty->driver->name );
3409
3410 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3411 /* nonblock mode is set or port is not enabled */
3412 info->flags |= ASYNC_NORMAL_ACTIVE;
3413 return 0;
3414 }
3415
3416 if (tty->termios->c_cflag & CLOCAL)
3417 do_clocal = 1;
3418
3419 /* Wait for carrier detect and the line to become
3420 * free (i.e., not in use by the callout). While we are in
3421 * this loop, info->count is dropped by one, so that
3422 * mgsl_close() knows when to free things. We restore it upon
3423 * exit, either normal or abnormal.
3424 */
3425
3426 retval = 0;
3427 add_wait_queue(&info->open_wait, &wait);
3428
3429 if (debug_level >= DEBUG_LEVEL_INFO)
3430 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3431 __FILE__,__LINE__, tty->driver->name, info->count );
3432
3433 spin_lock_irqsave(&info->irq_spinlock, flags);
3434 if (!tty_hung_up_p(filp)) {
3435 extra_count = 1;
3436 info->count--;
3437 }
3438 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3439 info->blocked_open++;
3440
3441 while (1) {
3442 if (tty->termios->c_cflag & CBAUD) {
3443 spin_lock_irqsave(&info->irq_spinlock,flags);
3444 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3445 usc_set_serial_signals(info);
3446 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3447 }
3448
3449 set_current_state(TASK_INTERRUPTIBLE);
3450
3451 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3452 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3453 -EAGAIN : -ERESTARTSYS;
3454 break;
3455 }
3456
3457 spin_lock_irqsave(&info->irq_spinlock,flags);
3458 usc_get_serial_signals(info);
3459 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3460
3461 if (!(info->flags & ASYNC_CLOSING) &&
3462 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3463 break;
3464 }
3465
3466 if (signal_pending(current)) {
3467 retval = -ERESTARTSYS;
3468 break;
3469 }
3470
3471 if (debug_level >= DEBUG_LEVEL_INFO)
3472 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3473 __FILE__,__LINE__, tty->driver->name, info->count );
3474
3475 schedule();
3476 }
3477
3478 set_current_state(TASK_RUNNING);
3479 remove_wait_queue(&info->open_wait, &wait);
3480
3481 if (extra_count)
3482 info->count++;
3483 info->blocked_open--;
3484
3485 if (debug_level >= DEBUG_LEVEL_INFO)
3486 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3487 __FILE__,__LINE__, tty->driver->name, info->count );
3488
3489 if (!retval)
3490 info->flags |= ASYNC_NORMAL_ACTIVE;
3491
3492 return retval;
3493
3494 } /* end of block_til_ready() */
3495
3496 /* mgsl_open()
3497 *
3498 * Called when a port is opened. Init and enable port.
3499 * Perform serial-specific initialization for the tty structure.
3500 *
3501 * Arguments: tty pointer to tty info structure
3502 * filp associated file pointer
3503 *
3504 * Return Value: 0 if success, otherwise error code
3505 */
3506 static int mgsl_open(struct tty_struct *tty, struct file * filp)
3507 {
3508 struct mgsl_struct *info;
3509 int retval, line;
3510 unsigned long page;
3511 unsigned long flags;
3512
3513 /* verify range of specified line number */
3514 line = tty->index;
3515 if ((line < 0) || (line >= mgsl_device_count)) {
3516 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3517 __FILE__,__LINE__,line);
3518 return -ENODEV;
3519 }
3520
3521 /* find the info structure for the specified line */
3522 info = mgsl_device_list;
3523 while(info && info->line != line)
3524 info = info->next_device;
3525 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3526 return -ENODEV;
3527
3528 tty->driver_data = info;
3529 info->tty = tty;
3530
3531 if (debug_level >= DEBUG_LEVEL_INFO)
3532 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3533 __FILE__,__LINE__,tty->driver->name, info->count);
3534
3535 /* If port is closing, signal caller to try again */
3536 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
3537 if (info->flags & ASYNC_CLOSING)
3538 interruptible_sleep_on(&info->close_wait);
3539 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
3540 -EAGAIN : -ERESTARTSYS);
3541 goto cleanup;
3542 }
3543
3544 if (!tmp_buf) {
3545 page = get_zeroed_page(GFP_KERNEL);
3546 if (!page) {
3547 retval = -ENOMEM;
3548 goto cleanup;
3549 }
3550 if (tmp_buf)
3551 free_page(page);
3552 else
3553 tmp_buf = (unsigned char *) page;
3554 }
3555
3556 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3557
3558 spin_lock_irqsave(&info->netlock, flags);
3559 if (info->netcount) {
3560 retval = -EBUSY;
3561 spin_unlock_irqrestore(&info->netlock, flags);
3562 goto cleanup;
3563 }
3564 info->count++;
3565 spin_unlock_irqrestore(&info->netlock, flags);
3566
3567 if (info->count == 1) {
3568 /* 1st open on this device, init hardware */
3569 retval = startup(info);
3570 if (retval < 0)
3571 goto cleanup;
3572 }
3573
3574 retval = block_til_ready(tty, filp, info);
3575 if (retval) {
3576 if (debug_level >= DEBUG_LEVEL_INFO)
3577 printk("%s(%d):block_til_ready(%s) returned %d\n",
3578 __FILE__,__LINE__, info->device_name, retval);
3579 goto cleanup;
3580 }
3581
3582 if (debug_level >= DEBUG_LEVEL_INFO)
3583 printk("%s(%d):mgsl_open(%s) success\n",
3584 __FILE__,__LINE__, info->device_name);
3585 retval = 0;
3586
3587 cleanup:
3588 if (retval) {
3589 if (tty->count == 1)
3590 info->tty = NULL; /* tty layer will release tty struct */
3591 if(info->count)
3592 info->count--;
3593 }
3594
3595 return retval;
3596
3597 } /* end of mgsl_open() */
3598
3599 /*
3600 * /proc fs routines....
3601 */
3602
3603 static inline int line_info(char *buf, struct mgsl_struct *info)
3604 {
3605 char stat_buf[30];
3606 int ret;
3607 unsigned long flags;
3608
3609 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3610 ret = sprintf(buf, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3611 info->device_name, info->io_base, info->irq_level,
3612 info->phys_memory_base, info->phys_lcr_base);
3613 } else {
3614 ret = sprintf(buf, "%s:(E)ISA io:%04X irq:%d dma:%d",
3615 info->device_name, info->io_base,
3616 info->irq_level, info->dma_level);
3617 }
3618
3619 /* output current serial signal states */
3620 spin_lock_irqsave(&info->irq_spinlock,flags);
3621 usc_get_serial_signals(info);
3622 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3623
3624 stat_buf[0] = 0;
3625 stat_buf[1] = 0;
3626 if (info->serial_signals & SerialSignal_RTS)
3627 strcat(stat_buf, "|RTS");
3628 if (info->serial_signals & SerialSignal_CTS)
3629 strcat(stat_buf, "|CTS");
3630 if (info->serial_signals & SerialSignal_DTR)
3631 strcat(stat_buf, "|DTR");
3632 if (info->serial_signals & SerialSignal_DSR)
3633 strcat(stat_buf, "|DSR");
3634 if (info->serial_signals & SerialSignal_DCD)
3635 strcat(stat_buf, "|CD");
3636 if (info->serial_signals & SerialSignal_RI)
3637 strcat(stat_buf, "|RI");
3638
3639 if (info->params.mode == MGSL_MODE_HDLC ||
3640 info->params.mode == MGSL_MODE_RAW ) {
3641 ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
3642 info->icount.txok, info->icount.rxok);
3643 if (info->icount.txunder)
3644 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
3645 if (info->icount.txabort)
3646 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
3647 if (info->icount.rxshort)
3648 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
3649 if (info->icount.rxlong)
3650 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
3651 if (info->icount.rxover)
3652 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
3653 if (info->icount.rxcrc)
3654 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
3655 } else {
3656 ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
3657 info->icount.tx, info->icount.rx);
3658 if (info->icount.frame)
3659 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
3660 if (info->icount.parity)
3661 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
3662 if (info->icount.brk)
3663 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
3664 if (info->icount.overrun)
3665 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
3666 }
3667
3668 /* Append serial signal status to end */
3669 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
3670
3671 ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3672 info->tx_active,info->bh_requested,info->bh_running,
3673 info->pending_bh);
3674
3675 spin_lock_irqsave(&info->irq_spinlock,flags);
3676 {
3677 u16 Tcsr = usc_InReg( info, TCSR );
3678 u16 Tdmr = usc_InDmaReg( info, TDMR );
3679 u16 Ticr = usc_InReg( info, TICR );
3680 u16 Rscr = usc_InReg( info, RCSR );
3681 u16 Rdmr = usc_InDmaReg( info, RDMR );
3682 u16 Ricr = usc_InReg( info, RICR );
3683 u16 Icr = usc_InReg( info, ICR );
3684 u16 Dccr = usc_InReg( info, DCCR );
3685 u16 Tmr = usc_InReg( info, TMR );
3686 u16 Tccr = usc_InReg( info, TCCR );
3687 u16 Ccar = inw( info->io_base + CCAR );
3688 ret += sprintf(buf+ret, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3689 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3690 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3691 }
3692 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3693
3694 return ret;
3695
3696 } /* end of line_info() */
3697
3698 /* mgsl_read_proc()
3699 *
3700 * Called to print information about devices
3701 *
3702 * Arguments:
3703 * page page of memory to hold returned info
3704 * start
3705 * off
3706 * count
3707 * eof
3708 * data
3709 *
3710 * Return Value:
3711 */
3712 int mgsl_read_proc(char *page, char **start, off_t off, int count,
3713 int *eof, void *data)
3714 {
3715 int len = 0, l;
3716 off_t begin = 0;
3717 struct mgsl_struct *info;
3718
3719 len += sprintf(page, "synclink driver:%s\n", driver_version);
3720
3721 info = mgsl_device_list;
3722 while( info ) {
3723 l = line_info(page + len, info);
3724 len += l;
3725 if (len+begin > off+count)
3726 goto done;
3727 if (len+begin < off) {
3728 begin += len;
3729 len = 0;
3730 }
3731 info = info->next_device;
3732 }
3733
3734 *eof = 1;
3735 done:
3736 if (off >= len+begin)
3737 return 0;
3738 *start = page + (off-begin);
3739 return ((count < begin+len-off) ? count : begin+len-off);
3740
3741 } /* end of mgsl_read_proc() */
3742
3743 /* mgsl_allocate_dma_buffers()
3744 *
3745 * Allocate and format DMA buffers (ISA adapter)
3746 * or format shared memory buffers (PCI adapter).
3747 *
3748 * Arguments: info pointer to device instance data
3749 * Return Value: 0 if success, otherwise error
3750 */
3751 int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3752 {
3753 unsigned short BuffersPerFrame;
3754
3755 info->last_mem_alloc = 0;
3756
3757 /* Calculate the number of DMA buffers necessary to hold the */
3758 /* largest allowable frame size. Note: If the max frame size is */
3759 /* not an even multiple of the DMA buffer size then we need to */
3760 /* round the buffer count per frame up one. */
3761
3762 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3763 if ( info->max_frame_size % DMABUFFERSIZE )
3764 BuffersPerFrame++;
3765
3766 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3767 /*
3768 * The PCI adapter has 256KBytes of shared memory to use.
3769 * This is 64 PAGE_SIZE buffers.
3770 *
3771 * The first page is used for padding at this time so the
3772 * buffer list does not begin at offset 0 of the PCI
3773 * adapter's shared memory.
3774 *
3775 * The 2nd page is used for the buffer list. A 4K buffer
3776 * list can hold 128 DMA_BUFFER structures at 32 bytes
3777 * each.
3778 *
3779 * This leaves 62 4K pages.
3780 *
3781 * The next N pages are used for transmit frame(s). We
3782 * reserve enough 4K page blocks to hold the required
3783 * number of transmit dma buffers (num_tx_dma_buffers),
3784 * each of MaxFrameSize size.
3785 *
3786 * Of the remaining pages (62-N), determine how many can
3787 * be used to receive full MaxFrameSize inbound frames
3788 */
3789 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3790 info->rx_buffer_count = 62 - info->tx_buffer_count;
3791 } else {
3792 /* Calculate the number of PAGE_SIZE buffers needed for */
3793 /* receive and transmit DMA buffers. */
3794
3795
3796 /* Calculate the number of DMA buffers necessary to */
3797 /* hold 7 max size receive frames and one max size transmit frame. */
3798 /* The receive buffer count is bumped by one so we avoid an */
3799 /* End of List condition if all receive buffers are used when */
3800 /* using linked list DMA buffers. */
3801
3802 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3803 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3804
3805 /*
3806 * limit total TxBuffers & RxBuffers to 62 4K total
3807 * (ala PCI Allocation)
3808 */
3809
3810 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3811 info->rx_buffer_count = 62 - info->tx_buffer_count;
3812
3813 }
3814
3815 if ( debug_level >= DEBUG_LEVEL_INFO )
3816 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3817 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3818
3819 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3820 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3821 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3822 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3823 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3824 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3825 return -ENOMEM;
3826 }
3827
3828 mgsl_reset_rx_dma_buffers( info );
3829 mgsl_reset_tx_dma_buffers( info );
3830
3831 return 0;
3832
3833 } /* end of mgsl_allocate_dma_buffers() */
3834
3835 /*
3836 * mgsl_alloc_buffer_list_memory()
3837 *
3838 * Allocate a common DMA buffer for use as the
3839 * receive and transmit buffer lists.
3840 *
3841 * A buffer list is a set of buffer entries where each entry contains
3842 * a pointer to an actual buffer and a pointer to the next buffer entry
3843 * (plus some other info about the buffer).
3844 *
3845 * The buffer entries for a list are built to form a circular list so
3846 * that when the entire list has been traversed you start back at the
3847 * beginning.
3848 *
3849 * This function allocates memory for just the buffer entries.
3850 * The links (pointer to next entry) are filled in with the physical
3851 * address of the next entry so the adapter can navigate the list
3852 * using bus master DMA. The pointers to the actual buffers are filled
3853 * out later when the actual buffers are allocated.
3854 *
3855 * Arguments: info pointer to device instance data
3856 * Return Value: 0 if success, otherwise error
3857 */
3858 int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3859 {
3860 unsigned int i;
3861
3862 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3863 /* PCI adapter uses shared memory. */
3864 info->buffer_list = info->memory_base + info->last_mem_alloc;
3865 info->buffer_list_phys = info->last_mem_alloc;
3866 info->last_mem_alloc += BUFFERLISTSIZE;
3867 } else {
3868 /* ISA adapter uses system memory. */
3869 /* The buffer lists are allocated as a common buffer that both */
3870 /* the processor and adapter can access. This allows the driver to */
3871 /* inspect portions of the buffer while other portions are being */
3872 /* updated by the adapter using Bus Master DMA. */
3873
3874 info->buffer_list = kmalloc(BUFFERLISTSIZE, GFP_KERNEL | GFP_DMA);
3875 if ( info->buffer_list == NULL )
3876 return -ENOMEM;
3877
3878 info->buffer_list_phys = isa_virt_to_bus(info->buffer_list);
3879 }
3880
3881 /* We got the memory for the buffer entry lists. */
3882 /* Initialize the memory block to all zeros. */
3883 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3884
3885 /* Save virtual address pointers to the receive and */
3886 /* transmit buffer lists. (Receive 1st). These pointers will */
3887 /* be used by the processor to access the lists. */
3888 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3889 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3890 info->tx_buffer_list += info->rx_buffer_count;
3891
3892 /*
3893 * Build the links for the buffer entry lists such that
3894 * two circular lists are built. (Transmit and Receive).
3895 *
3896 * Note: the links are physical addresses
3897 * which are read by the adapter to determine the next
3898 * buffer entry to use.
3899 */
3900
3901 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3902 /* calculate and store physical address of this buffer entry */
3903 info->rx_buffer_list[i].phys_entry =
3904 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3905
3906 /* calculate and store physical address of */
3907 /* next entry in cirular list of entries */
3908
3909 info->rx_buffer_list[i].link = info->buffer_list_phys;
3910
3911 if ( i < info->rx_buffer_count - 1 )
3912 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3913 }
3914
3915 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3916 /* calculate and store physical address of this buffer entry */
3917 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3918 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3919
3920 /* calculate and store physical address of */
3921 /* next entry in cirular list of entries */
3922
3923 info->tx_buffer_list[i].link = info->buffer_list_phys +
3924 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3925
3926 if ( i < info->tx_buffer_count - 1 )
3927 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3928 }
3929
3930 return 0;
3931
3932 } /* end of mgsl_alloc_buffer_list_memory() */
3933
3934 /* Free DMA buffers allocated for use as the
3935 * receive and transmit buffer lists.
3936 * Warning:
3937 *
3938 * The data transfer buffers associated with the buffer list
3939 * MUST be freed before freeing the buffer list itself because
3940 * the buffer list contains the information necessary to free
3941 * the individual buffers!
3942 */
3943 void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3944 {
3945 if ( info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI )
3946 kfree(info->buffer_list);
3947
3948 info->buffer_list = NULL;
3949 info->rx_buffer_list = NULL;
3950 info->tx_buffer_list = NULL;
3951
3952 } /* end of mgsl_free_buffer_list_memory() */
3953
3954 /*
3955 * mgsl_alloc_frame_memory()
3956 *
3957 * Allocate the frame DMA buffers used by the specified buffer list.
3958 * Each DMA buffer will be one memory page in size. This is necessary
3959 * because memory can fragment enough that it may be impossible
3960 * contiguous pages.
3961 *
3962 * Arguments:
3963 *
3964 * info pointer to device instance data
3965 * BufferList pointer to list of buffer entries
3966 * Buffercount count of buffer entries in buffer list
3967 *
3968 * Return Value: 0 if success, otherwise -ENOMEM
3969 */
3970 int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3971 {
3972 int i;
3973 unsigned long phys_addr;
3974
3975 /* Allocate page sized buffers for the receive buffer list */
3976
3977 for ( i = 0; i < Buffercount; i++ ) {
3978 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3979 /* PCI adapter uses shared memory buffers. */
3980 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3981 phys_addr = info->last_mem_alloc;
3982 info->last_mem_alloc += DMABUFFERSIZE;
3983 } else {
3984 /* ISA adapter uses system memory. */
3985 BufferList[i].virt_addr =
3986 kmalloc(DMABUFFERSIZE, GFP_KERNEL | GFP_DMA);
3987 if ( BufferList[i].virt_addr == NULL )
3988 return -ENOMEM;
3989 phys_addr = isa_virt_to_bus(BufferList[i].virt_addr);
3990 }
3991 BufferList[i].phys_addr = phys_addr;
3992 }
3993
3994 return 0;
3995
3996 } /* end of mgsl_alloc_frame_memory() */
3997
3998 /*
3999 * mgsl_free_frame_memory()
4000 *
4001 * Free the buffers associated with
4002 * each buffer entry of a buffer list.
4003 *
4004 * Arguments:
4005 *
4006 * info pointer to device instance data
4007 * BufferList pointer to list of buffer entries
4008 * Buffercount count of buffer entries in buffer list
4009 *
4010 * Return Value: None
4011 */
4012 void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
4013 {
4014 int i;
4015
4016 if ( BufferList ) {
4017 for ( i = 0 ; i < Buffercount ; i++ ) {
4018 if ( BufferList[i].virt_addr ) {
4019 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
4020 kfree(BufferList[i].virt_addr);
4021 BufferList[i].virt_addr = NULL;
4022 }
4023 }
4024 }
4025
4026 } /* end of mgsl_free_frame_memory() */
4027
4028 /* mgsl_free_dma_buffers()
4029 *
4030 * Free DMA buffers
4031 *
4032 * Arguments: info pointer to device instance data
4033 * Return Value: None
4034 */
4035 void mgsl_free_dma_buffers( struct mgsl_struct *info )
4036 {
4037 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
4038 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
4039 mgsl_free_buffer_list_memory( info );
4040
4041 } /* end of mgsl_free_dma_buffers() */
4042
4043
4044 /*
4045 * mgsl_alloc_intermediate_rxbuffer_memory()
4046 *
4047 * Allocate a buffer large enough to hold max_frame_size. This buffer
4048 * is used to pass an assembled frame to the line discipline.
4049 *
4050 * Arguments:
4051 *
4052 * info pointer to device instance data
4053 *
4054 * Return Value: 0 if success, otherwise -ENOMEM
4055 */
4056 int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
4057 {
4058 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
4059 if ( info->intermediate_rxbuffer == NULL )
4060 return -ENOMEM;
4061
4062 return 0;
4063
4064 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
4065
4066 /*
4067 * mgsl_free_intermediate_rxbuffer_memory()
4068 *
4069 *
4070 * Arguments:
4071 *
4072 * info pointer to device instance data
4073 *
4074 * Return Value: None
4075 */
4076 void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
4077 {
4078 if ( info->intermediate_rxbuffer )
4079 kfree(info->intermediate_rxbuffer);
4080
4081 info->intermediate_rxbuffer = NULL;
4082
4083 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
4084
4085 /*
4086 * mgsl_alloc_intermediate_txbuffer_memory()
4087 *
4088 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
4089 * This buffer is used to load transmit frames into the adapter's dma transfer
4090 * buffers when there is sufficient space.
4091 *
4092 * Arguments:
4093 *
4094 * info pointer to device instance data
4095 *
4096 * Return Value: 0 if success, otherwise -ENOMEM
4097 */
4098 int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
4099 {
4100 int i;
4101
4102 if ( debug_level >= DEBUG_LEVEL_INFO )
4103 printk("%s %s(%d) allocating %d tx holding buffers\n",
4104 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
4105
4106 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
4107
4108 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
4109 info->tx_holding_buffers[i].buffer =
4110 kmalloc(info->max_frame_size, GFP_KERNEL);
4111 if ( info->tx_holding_buffers[i].buffer == NULL )
4112 return -ENOMEM;
4113 }
4114
4115 return 0;
4116
4117 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
4118
4119 /*
4120 * mgsl_free_intermediate_txbuffer_memory()
4121 *
4122 *
4123 * Arguments:
4124 *
4125 * info pointer to device instance data
4126 *
4127 * Return Value: None
4128 */
4129 void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
4130 {
4131 int i;
4132
4133 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
4134 if ( info->tx_holding_buffers[i].buffer ) {
4135 kfree(info->tx_holding_buffers[i].buffer);
4136 info->tx_holding_buffers[i].buffer=NULL;
4137 }
4138 }
4139
4140 info->get_tx_holding_index = 0;
4141 info->put_tx_holding_index = 0;
4142 info->tx_holding_count = 0;
4143
4144 } /* end of mgsl_free_intermediate_txbuffer_memory() */
4145
4146
4147 /*
4148 * load_next_tx_holding_buffer()
4149 *
4150 * attempts to load the next buffered tx request into the
4151 * tx dma buffers
4152 *
4153 * Arguments:
4154 *
4155 * info pointer to device instance data
4156 *
4157 * Return Value: 1 if next buffered tx request loaded
4158 * into adapter's tx dma buffer,
4159 * 0 otherwise
4160 */
4161 int load_next_tx_holding_buffer(struct mgsl_struct *info)
4162 {
4163 int ret = 0;
4164
4165 if ( info->tx_holding_count ) {
4166 /* determine if we have enough tx dma buffers
4167 * to accommodate the next tx frame
4168 */
4169 struct tx_holding_buffer *ptx =
4170 &info->tx_holding_buffers[info->get_tx_holding_index];
4171 int num_free = num_free_tx_dma_buffers(info);
4172 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4173 if ( ptx->buffer_size % DMABUFFERSIZE )
4174 ++num_needed;
4175
4176 if (num_needed <= num_free) {
4177 info->xmit_cnt = ptx->buffer_size;
4178 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4179
4180 --info->tx_holding_count;
4181 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4182 info->get_tx_holding_index=0;
4183
4184 /* restart transmit timer */
4185 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4186
4187 ret = 1;
4188 }
4189 }
4190
4191 return ret;
4192 }
4193
4194 /*
4195 * save_tx_buffer_request()
4196 *
4197 * attempt to store transmit frame request for later transmission
4198 *
4199 * Arguments:
4200 *
4201 * info pointer to device instance data
4202 * Buffer pointer to buffer containing frame to load
4203 * BufferSize size in bytes of frame in Buffer
4204 *
4205 * Return Value: 1 if able to store, 0 otherwise
4206 */
4207 int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4208 {
4209 struct tx_holding_buffer *ptx;
4210
4211 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4212 return 0; /* all buffers in use */
4213 }
4214
4215 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4216 ptx->buffer_size = BufferSize;
4217 memcpy( ptx->buffer, Buffer, BufferSize);
4218
4219 ++info->tx_holding_count;
4220 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4221 info->put_tx_holding_index=0;
4222
4223 return 1;
4224 }
4225
4226 int mgsl_claim_resources(struct mgsl_struct *info)
4227 {
4228 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4229 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4230 __FILE__,__LINE__,info->device_name, info->io_base);
4231 return -ENODEV;
4232 }
4233 info->io_addr_requested = 1;
4234
4235 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4236 info->device_name, info ) < 0 ) {
4237 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4238 __FILE__,__LINE__,info->device_name, info->irq_level );
4239 goto errout;
4240 }
4241 info->irq_requested = 1;
4242
4243 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4244 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4245 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4246 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4247 goto errout;
4248 }
4249 info->shared_mem_requested = 1;
4250 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4251 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4252 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4253 goto errout;
4254 }
4255 info->lcr_mem_requested = 1;
4256
4257 info->memory_base = ioremap(info->phys_memory_base,0x40000);
4258 if (!info->memory_base) {
4259 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4260 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4261 goto errout;
4262 }
4263
4264 if ( !mgsl_memory_test(info) ) {
4265 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4266 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4267 goto errout;
4268 }
4269
4270 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE) + info->lcr_offset;
4271 if (!info->lcr_base) {
4272 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4273 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4274 goto errout;
4275 }
4276
4277 } else {
4278 /* claim DMA channel */
4279
4280 if (request_dma(info->dma_level,info->device_name) < 0){
4281 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4282 __FILE__,__LINE__,info->device_name, info->dma_level );
4283 mgsl_release_resources( info );
4284 return -ENODEV;
4285 }
4286 info->dma_requested = 1;
4287
4288 /* ISA adapter uses bus master DMA */
4289 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4290 enable_dma(info->dma_level);
4291 }
4292
4293 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4294 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4295 __FILE__,__LINE__,info->device_name, info->dma_level );
4296 goto errout;
4297 }
4298
4299 return 0;
4300 errout:
4301 mgsl_release_resources(info);
4302 return -ENODEV;
4303
4304 } /* end of mgsl_claim_resources() */
4305
4306 void mgsl_release_resources(struct mgsl_struct *info)
4307 {
4308 if ( debug_level >= DEBUG_LEVEL_INFO )
4309 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4310 __FILE__,__LINE__,info->device_name );
4311
4312 if ( info->irq_requested ) {
4313 free_irq(info->irq_level, info);
4314 info->irq_requested = 0;
4315 }
4316 if ( info->dma_requested ) {
4317 disable_dma(info->dma_level);
4318 free_dma(info->dma_level);
4319 info->dma_requested = 0;
4320 }
4321 mgsl_free_dma_buffers(info);
4322 mgsl_free_intermediate_rxbuffer_memory(info);
4323 mgsl_free_intermediate_txbuffer_memory(info);
4324
4325 if ( info->io_addr_requested ) {
4326 release_region(info->io_base,info->io_addr_size);
4327 info->io_addr_requested = 0;
4328 }
4329 if ( info->shared_mem_requested ) {
4330 release_mem_region(info->phys_memory_base,0x40000);
4331 info->shared_mem_requested = 0;
4332 }
4333 if ( info->lcr_mem_requested ) {
4334 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4335 info->lcr_mem_requested = 0;
4336 }
4337 if (info->memory_base){
4338 iounmap(info->memory_base);
4339 info->memory_base = NULL;
4340 }
4341 if (info->lcr_base){
4342 iounmap(info->lcr_base - info->lcr_offset);
4343 info->lcr_base = NULL;
4344 }
4345
4346 if ( debug_level >= DEBUG_LEVEL_INFO )
4347 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4348 __FILE__,__LINE__,info->device_name );
4349
4350 } /* end of mgsl_release_resources() */
4351
4352 /* mgsl_add_device()
4353 *
4354 * Add the specified device instance data structure to the
4355 * global linked list of devices and increment the device count.
4356 *
4357 * Arguments: info pointer to device instance data
4358 * Return Value: None
4359 */
4360 void mgsl_add_device( struct mgsl_struct *info )
4361 {
4362 info->next_device = NULL;
4363 info->line = mgsl_device_count;
4364 sprintf(info->device_name,"ttySL%d",info->line);
4365
4366 if (info->line < MAX_TOTAL_DEVICES) {
4367 if (maxframe[info->line])
4368 info->max_frame_size = maxframe[info->line];
4369 info->dosyncppp = dosyncppp[info->line];
4370
4371 if (txdmabufs[info->line]) {
4372 info->num_tx_dma_buffers = txdmabufs[info->line];
4373 if (info->num_tx_dma_buffers < 1)
4374 info->num_tx_dma_buffers = 1;
4375 }
4376
4377 if (txholdbufs[info->line]) {
4378 info->num_tx_holding_buffers = txholdbufs[info->line];
4379 if (info->num_tx_holding_buffers < 1)
4380 info->num_tx_holding_buffers = 1;
4381 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4382 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4383 }
4384 }
4385
4386 mgsl_device_count++;
4387
4388 if ( !mgsl_device_list )
4389 mgsl_device_list = info;
4390 else {
4391 struct mgsl_struct *current_dev = mgsl_device_list;
4392 while( current_dev->next_device )
4393 current_dev = current_dev->next_device;
4394 current_dev->next_device = info;
4395 }
4396
4397 if ( info->max_frame_size < 4096 )
4398 info->max_frame_size = 4096;
4399 else if ( info->max_frame_size > 65535 )
4400 info->max_frame_size = 65535;
4401
4402 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4403 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4404 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4405 info->phys_memory_base, info->phys_lcr_base,
4406 info->max_frame_size );
4407 } else {
4408 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4409 info->device_name, info->io_base, info->irq_level, info->dma_level,
4410 info->max_frame_size );
4411 }
4412
4413 #ifdef CONFIG_HDLC
4414 hdlcdev_init(info);
4415 #endif
4416
4417 } /* end of mgsl_add_device() */
4418
4419 /* mgsl_allocate_device()
4420 *
4421 * Allocate and initialize a device instance structure
4422 *
4423 * Arguments: none
4424 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4425 */
4426 struct mgsl_struct* mgsl_allocate_device(void)
4427 {
4428 struct mgsl_struct *info;
4429
4430 info = (struct mgsl_struct *)kmalloc(sizeof(struct mgsl_struct),
4431 GFP_KERNEL);
4432
4433 if (!info) {
4434 printk("Error can't allocate device instance data\n");
4435 } else {
4436 memset(info, 0, sizeof(struct mgsl_struct));
4437 info->magic = MGSL_MAGIC;
4438 INIT_WORK(&info->task, mgsl_bh_handler, info);
4439 info->max_frame_size = 4096;
4440 info->close_delay = 5*HZ/10;
4441 info->closing_wait = 30*HZ;
4442 init_waitqueue_head(&info->open_wait);
4443 init_waitqueue_head(&info->close_wait);
4444 init_waitqueue_head(&info->status_event_wait_q);
4445 init_waitqueue_head(&info->event_wait_q);
4446 spin_lock_init(&info->irq_spinlock);
4447 spin_lock_init(&info->netlock);
4448 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4449 info->idle_mode = HDLC_TXIDLE_FLAGS;
4450 info->num_tx_dma_buffers = 1;
4451 info->num_tx_holding_buffers = 0;
4452 }
4453
4454 return info;
4455
4456 } /* end of mgsl_allocate_device()*/
4457
4458 static struct tty_operations mgsl_ops = {
4459 .open = mgsl_open,
4460 .close = mgsl_close,
4461 .write = mgsl_write,
4462 .put_char = mgsl_put_char,
4463 .flush_chars = mgsl_flush_chars,
4464 .write_room = mgsl_write_room,
4465 .chars_in_buffer = mgsl_chars_in_buffer,
4466 .flush_buffer = mgsl_flush_buffer,
4467 .ioctl = mgsl_ioctl,
4468 .throttle = mgsl_throttle,
4469 .unthrottle = mgsl_unthrottle,
4470 .send_xchar = mgsl_send_xchar,
4471 .break_ctl = mgsl_break,
4472 .wait_until_sent = mgsl_wait_until_sent,
4473 .read_proc = mgsl_read_proc,
4474 .set_termios = mgsl_set_termios,
4475 .stop = mgsl_stop,
4476 .start = mgsl_start,
4477 .hangup = mgsl_hangup,
4478 .tiocmget = tiocmget,
4479 .tiocmset = tiocmset,
4480 };
4481
4482 /*
4483 * perform tty device initialization
4484 */
4485 static int mgsl_init_tty(void)
4486 {
4487 int rc;
4488
4489 serial_driver = alloc_tty_driver(128);
4490 if (!serial_driver)
4491 return -ENOMEM;
4492
4493 serial_driver->owner = THIS_MODULE;
4494 serial_driver->driver_name = "synclink";
4495 serial_driver->name = "ttySL";
4496 serial_driver->major = ttymajor;
4497 serial_driver->minor_start = 64;
4498 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4499 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4500 serial_driver->init_termios = tty_std_termios;
4501 serial_driver->init_termios.c_cflag =
4502 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4503 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4504 tty_set_operations(serial_driver, &mgsl_ops);
4505 if ((rc = tty_register_driver(serial_driver)) < 0) {
4506 printk("%s(%d):Couldn't register serial driver\n",
4507 __FILE__,__LINE__);
4508 put_tty_driver(serial_driver);
4509 serial_driver = NULL;
4510 return rc;
4511 }
4512
4513 printk("%s %s, tty major#%d\n",
4514 driver_name, driver_version,
4515 serial_driver->major);
4516 return 0;
4517 }
4518
4519 /* enumerate user specified ISA adapters
4520 */
4521 static void mgsl_enum_isa_devices(void)
4522 {
4523 struct mgsl_struct *info;
4524 int i;
4525
4526 /* Check for user specified ISA devices */
4527
4528 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4529 if ( debug_level >= DEBUG_LEVEL_INFO )
4530 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4531 io[i], irq[i], dma[i] );
4532
4533 info = mgsl_allocate_device();
4534 if ( !info ) {
4535 /* error allocating device instance data */
4536 if ( debug_level >= DEBUG_LEVEL_ERROR )
4537 printk( "can't allocate device instance data.\n");
4538 continue;
4539 }
4540
4541 /* Copy user configuration info to device instance data */
4542 info->io_base = (unsigned int)io[i];
4543 info->irq_level = (unsigned int)irq[i];
4544 info->irq_level = irq_canonicalize(info->irq_level);
4545 info->dma_level = (unsigned int)dma[i];
4546 info->bus_type = MGSL_BUS_TYPE_ISA;
4547 info->io_addr_size = 16;
4548 info->irq_flags = 0;
4549
4550 mgsl_add_device( info );
4551 }
4552 }
4553
4554 static void synclink_cleanup(void)
4555 {
4556 int rc;
4557 struct mgsl_struct *info;
4558 struct mgsl_struct *tmp;
4559
4560 printk("Unloading %s: %s\n", driver_name, driver_version);
4561
4562 if (serial_driver) {
4563 if ((rc = tty_unregister_driver(serial_driver)))
4564 printk("%s(%d) failed to unregister tty driver err=%d\n",
4565 __FILE__,__LINE__,rc);
4566 put_tty_driver(serial_driver);
4567 }
4568
4569 info = mgsl_device_list;
4570 while(info) {
4571 #ifdef CONFIG_HDLC
4572 hdlcdev_exit(info);
4573 #endif
4574 mgsl_release_resources(info);
4575 tmp = info;
4576 info = info->next_device;
4577 kfree(tmp);
4578 }
4579
4580 if (tmp_buf) {
4581 free_page((unsigned long) tmp_buf);
4582 tmp_buf = NULL;
4583 }
4584
4585 if (pci_registered)
4586 pci_unregister_driver(&synclink_pci_driver);
4587 }
4588
4589 static int __init synclink_init(void)
4590 {
4591 int rc;
4592
4593 if (break_on_load) {
4594 mgsl_get_text_ptr();
4595 BREAKPOINT();
4596 }
4597
4598 printk("%s %s\n", driver_name, driver_version);
4599
4600 mgsl_enum_isa_devices();
4601 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4602 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4603 else
4604 pci_registered = 1;
4605
4606 if ((rc = mgsl_init_tty()) < 0)
4607 goto error;
4608
4609 return 0;
4610
4611 error:
4612 synclink_cleanup();
4613 return rc;
4614 }
4615
4616 static void __exit synclink_exit(void)
4617 {
4618 synclink_cleanup();
4619 }
4620
4621 module_init(synclink_init);
4622 module_exit(synclink_exit);
4623
4624 /*
4625 * usc_RTCmd()
4626 *
4627 * Issue a USC Receive/Transmit command to the
4628 * Channel Command/Address Register (CCAR).
4629 *
4630 * Notes:
4631 *
4632 * The command is encoded in the most significant 5 bits <15..11>
4633 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4634 * and Bits <6..0> must be written as zeros.
4635 *
4636 * Arguments:
4637 *
4638 * info pointer to device information structure
4639 * Cmd command mask (use symbolic macros)
4640 *
4641 * Return Value:
4642 *
4643 * None
4644 */
4645 void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4646 {
4647 /* output command to CCAR in bits <15..11> */
4648 /* preserve bits <10..7>, bits <6..0> must be zero */
4649
4650 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4651
4652 /* Read to flush write to CCAR */
4653 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4654 inw( info->io_base + CCAR );
4655
4656 } /* end of usc_RTCmd() */
4657
4658 /*
4659 * usc_DmaCmd()
4660 *
4661 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4662 *
4663 * Arguments:
4664 *
4665 * info pointer to device information structure
4666 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4667 *
4668 * Return Value:
4669 *
4670 * None
4671 */
4672 void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4673 {
4674 /* write command mask to DCAR */
4675 outw( Cmd + info->mbre_bit, info->io_base );
4676
4677 /* Read to flush write to DCAR */
4678 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4679 inw( info->io_base );
4680
4681 } /* end of usc_DmaCmd() */
4682
4683 /*
4684 * usc_OutDmaReg()
4685 *
4686 * Write a 16-bit value to a USC DMA register
4687 *
4688 * Arguments:
4689 *
4690 * info pointer to device info structure
4691 * RegAddr register address (number) for write
4692 * RegValue 16-bit value to write to register
4693 *
4694 * Return Value:
4695 *
4696 * None
4697 *
4698 */
4699 void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4700 {
4701 /* Note: The DCAR is located at the adapter base address */
4702 /* Note: must preserve state of BIT8 in DCAR */
4703
4704 outw( RegAddr + info->mbre_bit, info->io_base );
4705 outw( RegValue, info->io_base );
4706
4707 /* Read to flush write to DCAR */
4708 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4709 inw( info->io_base );
4710
4711 } /* end of usc_OutDmaReg() */
4712
4713 /*
4714 * usc_InDmaReg()
4715 *
4716 * Read a 16-bit value from a DMA register
4717 *
4718 * Arguments:
4719 *
4720 * info pointer to device info structure
4721 * RegAddr register address (number) to read from
4722 *
4723 * Return Value:
4724 *
4725 * The 16-bit value read from register
4726 *
4727 */
4728 u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4729 {
4730 /* Note: The DCAR is located at the adapter base address */
4731 /* Note: must preserve state of BIT8 in DCAR */
4732
4733 outw( RegAddr + info->mbre_bit, info->io_base );
4734 return inw( info->io_base );
4735
4736 } /* end of usc_InDmaReg() */
4737
4738 /*
4739 *
4740 * usc_OutReg()
4741 *
4742 * Write a 16-bit value to a USC serial channel register
4743 *
4744 * Arguments:
4745 *
4746 * info pointer to device info structure
4747 * RegAddr register address (number) to write to
4748 * RegValue 16-bit value to write to register
4749 *
4750 * Return Value:
4751 *
4752 * None
4753 *
4754 */
4755 void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4756 {
4757 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4758 outw( RegValue, info->io_base + CCAR );
4759
4760 /* Read to flush write to CCAR */
4761 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4762 inw( info->io_base + CCAR );
4763
4764 } /* end of usc_OutReg() */
4765
4766 /*
4767 * usc_InReg()
4768 *
4769 * Reads a 16-bit value from a USC serial channel register
4770 *
4771 * Arguments:
4772 *
4773 * info pointer to device extension
4774 * RegAddr register address (number) to read from
4775 *
4776 * Return Value:
4777 *
4778 * 16-bit value read from register
4779 */
4780 u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4781 {
4782 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4783 return inw( info->io_base + CCAR );
4784
4785 } /* end of usc_InReg() */
4786
4787 /* usc_set_sdlc_mode()
4788 *
4789 * Set up the adapter for SDLC DMA communications.
4790 *
4791 * Arguments: info pointer to device instance data
4792 * Return Value: NONE
4793 */
4794 void usc_set_sdlc_mode( struct mgsl_struct *info )
4795 {
4796 u16 RegValue;
4797 int PreSL1660;
4798
4799 /*
4800 * determine if the IUSC on the adapter is pre-SL1660. If
4801 * not, take advantage of the UnderWait feature of more
4802 * modern chips. If an underrun occurs and this bit is set,
4803 * the transmitter will idle the programmed idle pattern
4804 * until the driver has time to service the underrun. Otherwise,
4805 * the dma controller may get the cycles previously requested
4806 * and begin transmitting queued tx data.
4807 */
4808 usc_OutReg(info,TMCR,0x1f);
4809 RegValue=usc_InReg(info,TMDR);
4810 if ( RegValue == IUSC_PRE_SL1660 )
4811 PreSL1660 = 1;
4812 else
4813 PreSL1660 = 0;
4814
4815
4816 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4817 {
4818 /*
4819 ** Channel Mode Register (CMR)
4820 **
4821 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4822 ** <13> 0 0 = Transmit Disabled (initially)
4823 ** <12> 0 1 = Consecutive Idles share common 0
4824 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4825 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4826 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4827 **
4828 ** 1000 1110 0000 0110 = 0x8e06
4829 */
4830 RegValue = 0x8e06;
4831
4832 /*--------------------------------------------------
4833 * ignore user options for UnderRun Actions and
4834 * preambles
4835 *--------------------------------------------------*/
4836 }
4837 else
4838 {
4839 /* Channel mode Register (CMR)
4840 *
4841 * <15..14> 00 Tx Sub modes, Underrun Action
4842 * <13> 0 1 = Send Preamble before opening flag
4843 * <12> 0 1 = Consecutive Idles share common 0
4844 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4845 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4846 * <3..0> 0110 Receiver mode = HDLC/SDLC
4847 *
4848 * 0000 0110 0000 0110 = 0x0606
4849 */
4850 if (info->params.mode == MGSL_MODE_RAW) {
4851 RegValue = 0x0001; /* Set Receive mode = external sync */
4852
4853 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4854 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4855
4856 /*
4857 * TxSubMode:
4858 * CMR <15> 0 Don't send CRC on Tx Underrun
4859 * CMR <14> x undefined
4860 * CMR <13> 0 Send preamble before openning sync
4861 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4862 *
4863 * TxMode:
4864 * CMR <11-8) 0100 MonoSync
4865 *
4866 * 0x00 0100 xxxx xxxx 04xx
4867 */
4868 RegValue |= 0x0400;
4869 }
4870 else {
4871
4872 RegValue = 0x0606;
4873
4874 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4875 RegValue |= BIT14;
4876 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4877 RegValue |= BIT15;
4878 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4879 RegValue |= BIT15 + BIT14;
4880 }
4881
4882 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4883 RegValue |= BIT13;
4884 }
4885
4886 if ( info->params.mode == MGSL_MODE_HDLC &&
4887 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4888 RegValue |= BIT12;
4889
4890 if ( info->params.addr_filter != 0xff )
4891 {
4892 /* set up receive address filtering */
4893 usc_OutReg( info, RSR, info->params.addr_filter );
4894 RegValue |= BIT4;
4895 }
4896
4897 usc_OutReg( info, CMR, RegValue );
4898 info->cmr_value = RegValue;
4899
4900 /* Receiver mode Register (RMR)
4901 *
4902 * <15..13> 000 encoding
4903 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4904 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4905 * <9> 0 1 = Include Receive chars in CRC
4906 * <8> 1 1 = Use Abort/PE bit as abort indicator
4907 * <7..6> 00 Even parity
4908 * <5> 0 parity disabled
4909 * <4..2> 000 Receive Char Length = 8 bits
4910 * <1..0> 00 Disable Receiver
4911 *
4912 * 0000 0101 0000 0000 = 0x0500
4913 */
4914
4915 RegValue = 0x0500;
4916
4917 switch ( info->params.encoding ) {
4918 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4919 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4920 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4921 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4922 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4923 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4924 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4925 }
4926
4927 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4928 RegValue |= BIT9;
4929 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4930 RegValue |= ( BIT12 | BIT10 | BIT9 );
4931
4932 usc_OutReg( info, RMR, RegValue );
4933
4934 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4935 /* When an opening flag of an SDLC frame is recognized the */
4936 /* Receive Character count (RCC) is loaded with the value in */
4937 /* RCLR. The RCC is decremented for each received byte. The */
4938 /* value of RCC is stored after the closing flag of the frame */
4939 /* allowing the frame size to be computed. */
4940
4941 usc_OutReg( info, RCLR, RCLRVALUE );
4942
4943 usc_RCmd( info, RCmd_SelectRicrdma_level );
4944
4945 /* Receive Interrupt Control Register (RICR)
4946 *
4947 * <15..8> ? RxFIFO DMA Request Level
4948 * <7> 0 Exited Hunt IA (Interrupt Arm)
4949 * <6> 0 Idle Received IA
4950 * <5> 0 Break/Abort IA
4951 * <4> 0 Rx Bound IA
4952 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4953 * <2> 0 Abort/PE IA
4954 * <1> 1 Rx Overrun IA
4955 * <0> 0 Select TC0 value for readback
4956 *
4957 * 0000 0000 0000 1000 = 0x000a
4958 */
4959
4960 /* Carry over the Exit Hunt and Idle Received bits */
4961 /* in case they have been armed by usc_ArmEvents. */
4962
4963 RegValue = usc_InReg( info, RICR ) & 0xc0;
4964
4965 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4966 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4967 else
4968 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4969
4970 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4971
4972 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4973 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4974
4975 /* Transmit mode Register (TMR)
4976 *
4977 * <15..13> 000 encoding
4978 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4979 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4980 * <9> 0 1 = Tx CRC Enabled
4981 * <8> 0 1 = Append CRC to end of transmit frame
4982 * <7..6> 00 Transmit parity Even
4983 * <5> 0 Transmit parity Disabled
4984 * <4..2> 000 Tx Char Length = 8 bits
4985 * <1..0> 00 Disable Transmitter
4986 *
4987 * 0000 0100 0000 0000 = 0x0400
4988 */
4989
4990 RegValue = 0x0400;
4991
4992 switch ( info->params.encoding ) {
4993 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4994 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4995 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4996 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4997 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4998 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4999 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
5000 }
5001
5002 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
5003 RegValue |= BIT9 + BIT8;
5004 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
5005 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
5006
5007 usc_OutReg( info, TMR, RegValue );
5008
5009 usc_set_txidle( info );
5010
5011
5012 usc_TCmd( info, TCmd_SelectTicrdma_level );
5013
5014 /* Transmit Interrupt Control Register (TICR)
5015 *
5016 * <15..8> ? Transmit FIFO DMA Level
5017 * <7> 0 Present IA (Interrupt Arm)
5018 * <6> 0 Idle Sent IA
5019 * <5> 1 Abort Sent IA
5020 * <4> 1 EOF/EOM Sent IA
5021 * <3> 0 CRC Sent IA
5022 * <2> 1 1 = Wait for SW Trigger to Start Frame
5023 * <1> 1 Tx Underrun IA
5024 * <0> 0 TC0 constant on read back
5025 *
5026 * 0000 0000 0011 0110 = 0x0036
5027 */
5028
5029 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5030 usc_OutReg( info, TICR, 0x0736 );
5031 else
5032 usc_OutReg( info, TICR, 0x1436 );
5033
5034 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5035 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5036
5037 /*
5038 ** Transmit Command/Status Register (TCSR)
5039 **
5040 ** <15..12> 0000 TCmd
5041 ** <11> 0/1 UnderWait
5042 ** <10..08> 000 TxIdle
5043 ** <7> x PreSent
5044 ** <6> x IdleSent
5045 ** <5> x AbortSent
5046 ** <4> x EOF/EOM Sent
5047 ** <3> x CRC Sent
5048 ** <2> x All Sent
5049 ** <1> x TxUnder
5050 ** <0> x TxEmpty
5051 **
5052 ** 0000 0000 0000 0000 = 0x0000
5053 */
5054 info->tcsr_value = 0;
5055
5056 if ( !PreSL1660 )
5057 info->tcsr_value |= TCSR_UNDERWAIT;
5058
5059 usc_OutReg( info, TCSR, info->tcsr_value );
5060
5061 /* Clock mode Control Register (CMCR)
5062 *
5063 * <15..14> 00 counter 1 Source = Disabled
5064 * <13..12> 00 counter 0 Source = Disabled
5065 * <11..10> 11 BRG1 Input is TxC Pin
5066 * <9..8> 11 BRG0 Input is TxC Pin
5067 * <7..6> 01 DPLL Input is BRG1 Output
5068 * <5..3> XXX TxCLK comes from Port 0
5069 * <2..0> XXX RxCLK comes from Port 1
5070 *
5071 * 0000 1111 0111 0111 = 0x0f77
5072 */
5073
5074 RegValue = 0x0f40;
5075
5076 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
5077 RegValue |= 0x0003; /* RxCLK from DPLL */
5078 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
5079 RegValue |= 0x0004; /* RxCLK from BRG0 */
5080 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
5081 RegValue |= 0x0006; /* RxCLK from TXC Input */
5082 else
5083 RegValue |= 0x0007; /* RxCLK from Port1 */
5084
5085 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
5086 RegValue |= 0x0018; /* TxCLK from DPLL */
5087 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
5088 RegValue |= 0x0020; /* TxCLK from BRG0 */
5089 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
5090 RegValue |= 0x0038; /* RxCLK from TXC Input */
5091 else
5092 RegValue |= 0x0030; /* TxCLK from Port0 */
5093
5094 usc_OutReg( info, CMCR, RegValue );
5095
5096
5097 /* Hardware Configuration Register (HCR)
5098 *
5099 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
5100 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
5101 * <12> 0 CVOK:0=report code violation in biphase
5102 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
5103 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
5104 * <7..6> 00 reserved
5105 * <5> 0 BRG1 mode:0=continuous,1=single cycle
5106 * <4> X BRG1 Enable
5107 * <3..2> 00 reserved
5108 * <1> 0 BRG0 mode:0=continuous,1=single cycle
5109 * <0> 0 BRG0 Enable
5110 */
5111
5112 RegValue = 0x0000;
5113
5114 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
5115 u32 XtalSpeed;
5116 u32 DpllDivisor;
5117 u16 Tc;
5118
5119 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
5120 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5121
5122 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5123 XtalSpeed = 11059200;
5124 else
5125 XtalSpeed = 14745600;
5126
5127 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
5128 DpllDivisor = 16;
5129 RegValue |= BIT10;
5130 }
5131 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
5132 DpllDivisor = 8;
5133 RegValue |= BIT11;
5134 }
5135 else
5136 DpllDivisor = 32;
5137
5138 /* Tc = (Xtal/Speed) - 1 */
5139 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5140 /* then rounding up gives a more precise time constant. Instead */
5141 /* of rounding up and then subtracting 1 we just don't subtract */
5142 /* the one in this case. */
5143
5144 /*--------------------------------------------------
5145 * ejz: for DPLL mode, application should use the
5146 * same clock speed as the partner system, even
5147 * though clocking is derived from the input RxData.
5148 * In case the user uses a 0 for the clock speed,
5149 * default to 0xffffffff and don't try to divide by
5150 * zero
5151 *--------------------------------------------------*/
5152 if ( info->params.clock_speed )
5153 {
5154 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
5155 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
5156 / info->params.clock_speed) )
5157 Tc--;
5158 }
5159 else
5160 Tc = -1;
5161
5162
5163 /* Write 16-bit Time Constant for BRG1 */
5164 usc_OutReg( info, TC1R, Tc );
5165
5166 RegValue |= BIT4; /* enable BRG1 */
5167
5168 switch ( info->params.encoding ) {
5169 case HDLC_ENCODING_NRZ:
5170 case HDLC_ENCODING_NRZB:
5171 case HDLC_ENCODING_NRZI_MARK:
5172 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5173 case HDLC_ENCODING_BIPHASE_MARK:
5174 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5175 case HDLC_ENCODING_BIPHASE_LEVEL:
5176 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5177 }
5178 }
5179
5180 usc_OutReg( info, HCR, RegValue );
5181
5182
5183 /* Channel Control/status Register (CCSR)
5184 *
5185 * <15> X RCC FIFO Overflow status (RO)
5186 * <14> X RCC FIFO Not Empty status (RO)
5187 * <13> 0 1 = Clear RCC FIFO (WO)
5188 * <12> X DPLL Sync (RW)
5189 * <11> X DPLL 2 Missed Clocks status (RO)
5190 * <10> X DPLL 1 Missed Clock status (RO)
5191 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5192 * <7> X SDLC Loop On status (RO)
5193 * <6> X SDLC Loop Send status (RO)
5194 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5195 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5196 * <1..0> 00 reserved
5197 *
5198 * 0000 0000 0010 0000 = 0x0020
5199 */
5200
5201 usc_OutReg( info, CCSR, 0x1020 );
5202
5203
5204 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5205 usc_OutReg( info, SICR,
5206 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5207 }
5208
5209
5210 /* enable Master Interrupt Enable bit (MIE) */
5211 usc_EnableMasterIrqBit( info );
5212
5213 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5214 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5215
5216 /* arm RCC underflow interrupt */
5217 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5218 usc_EnableInterrupts(info, MISC);
5219
5220 info->mbre_bit = 0;
5221 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5222 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5223 info->mbre_bit = BIT8;
5224 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5225
5226 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5227 /* Enable DMAEN (Port 7, Bit 14) */
5228 /* This connects the DMA request signal to the ISA bus */
5229 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5230 }
5231
5232 /* DMA Control Register (DCR)
5233 *
5234 * <15..14> 10 Priority mode = Alternating Tx/Rx
5235 * 01 Rx has priority
5236 * 00 Tx has priority
5237 *
5238 * <13> 1 Enable Priority Preempt per DCR<15..14>
5239 * (WARNING DCR<11..10> must be 00 when this is 1)
5240 * 0 Choose activate channel per DCR<11..10>
5241 *
5242 * <12> 0 Little Endian for Array/List
5243 * <11..10> 00 Both Channels can use each bus grant
5244 * <9..6> 0000 reserved
5245 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5246 * <4> 0 1 = drive D/C and S/D pins
5247 * <3> 1 1 = Add one wait state to all DMA cycles.
5248 * <2> 0 1 = Strobe /UAS on every transfer.
5249 * <1..0> 11 Addr incrementing only affects LS24 bits
5250 *
5251 * 0110 0000 0000 1011 = 0x600b
5252 */
5253
5254 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5255 /* PCI adapter does not need DMA wait state */
5256 usc_OutDmaReg( info, DCR, 0xa00b );
5257 }
5258 else
5259 usc_OutDmaReg( info, DCR, 0x800b );
5260
5261
5262 /* Receive DMA mode Register (RDMR)
5263 *
5264 * <15..14> 11 DMA mode = Linked List Buffer mode
5265 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5266 * <12> 1 Clear count of List Entry after fetching
5267 * <11..10> 00 Address mode = Increment
5268 * <9> 1 Terminate Buffer on RxBound
5269 * <8> 0 Bus Width = 16bits
5270 * <7..0> ? status Bits (write as 0s)
5271 *
5272 * 1111 0010 0000 0000 = 0xf200
5273 */
5274
5275 usc_OutDmaReg( info, RDMR, 0xf200 );
5276
5277
5278 /* Transmit DMA mode Register (TDMR)
5279 *
5280 * <15..14> 11 DMA mode = Linked List Buffer mode
5281 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5282 * <12> 1 Clear count of List Entry after fetching
5283 * <11..10> 00 Address mode = Increment
5284 * <9> 1 Terminate Buffer on end of frame
5285 * <8> 0 Bus Width = 16bits
5286 * <7..0> ? status Bits (Read Only so write as 0)
5287 *
5288 * 1111 0010 0000 0000 = 0xf200
5289 */
5290
5291 usc_OutDmaReg( info, TDMR, 0xf200 );
5292
5293
5294 /* DMA Interrupt Control Register (DICR)
5295 *
5296 * <15> 1 DMA Interrupt Enable
5297 * <14> 0 1 = Disable IEO from USC
5298 * <13> 0 1 = Don't provide vector during IntAck
5299 * <12> 1 1 = Include status in Vector
5300 * <10..2> 0 reserved, Must be 0s
5301 * <1> 0 1 = Rx DMA Interrupt Enabled
5302 * <0> 0 1 = Tx DMA Interrupt Enabled
5303 *
5304 * 1001 0000 0000 0000 = 0x9000
5305 */
5306
5307 usc_OutDmaReg( info, DICR, 0x9000 );
5308
5309 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5310 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5311 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5312
5313 /* Channel Control Register (CCR)
5314 *
5315 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5316 * <13> 0 Trigger Tx on SW Command Disabled
5317 * <12> 0 Flag Preamble Disabled
5318 * <11..10> 00 Preamble Length
5319 * <9..8> 00 Preamble Pattern
5320 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5321 * <5> 0 Trigger Rx on SW Command Disabled
5322 * <4..0> 0 reserved
5323 *
5324 * 1000 0000 1000 0000 = 0x8080
5325 */
5326
5327 RegValue = 0x8080;
5328
5329 switch ( info->params.preamble_length ) {
5330 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5331 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5332 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5333 }
5334
5335 switch ( info->params.preamble ) {
5336 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5337 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5338 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5339 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5340 }
5341
5342 usc_OutReg( info, CCR, RegValue );
5343
5344
5345 /*
5346 * Burst/Dwell Control Register
5347 *
5348 * <15..8> 0x20 Maximum number of transfers per bus grant
5349 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5350 */
5351
5352 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5353 /* don't limit bus occupancy on PCI adapter */
5354 usc_OutDmaReg( info, BDCR, 0x0000 );
5355 }
5356 else
5357 usc_OutDmaReg( info, BDCR, 0x2000 );
5358
5359 usc_stop_transmitter(info);
5360 usc_stop_receiver(info);
5361
5362 } /* end of usc_set_sdlc_mode() */
5363
5364 /* usc_enable_loopback()
5365 *
5366 * Set the 16C32 for internal loopback mode.
5367 * The TxCLK and RxCLK signals are generated from the BRG0 and
5368 * the TxD is looped back to the RxD internally.
5369 *
5370 * Arguments: info pointer to device instance data
5371 * enable 1 = enable loopback, 0 = disable
5372 * Return Value: None
5373 */
5374 void usc_enable_loopback(struct mgsl_struct *info, int enable)
5375 {
5376 if (enable) {
5377 /* blank external TXD output */
5378 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5379
5380 /* Clock mode Control Register (CMCR)
5381 *
5382 * <15..14> 00 counter 1 Disabled
5383 * <13..12> 00 counter 0 Disabled
5384 * <11..10> 11 BRG1 Input is TxC Pin
5385 * <9..8> 11 BRG0 Input is TxC Pin
5386 * <7..6> 01 DPLL Input is BRG1 Output
5387 * <5..3> 100 TxCLK comes from BRG0
5388 * <2..0> 100 RxCLK comes from BRG0
5389 *
5390 * 0000 1111 0110 0100 = 0x0f64
5391 */
5392
5393 usc_OutReg( info, CMCR, 0x0f64 );
5394
5395 /* Write 16-bit Time Constant for BRG0 */
5396 /* use clock speed if available, otherwise use 8 for diagnostics */
5397 if (info->params.clock_speed) {
5398 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5399 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5400 else
5401 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5402 } else
5403 usc_OutReg(info, TC0R, (u16)8);
5404
5405 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5406 mode = Continuous Set Bit 0 to enable BRG0. */
5407 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5408
5409 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5410 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5411
5412 /* set Internal Data loopback mode */
5413 info->loopback_bits = 0x300;
5414 outw( 0x0300, info->io_base + CCAR );
5415 } else {
5416 /* enable external TXD output */
5417 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5418
5419 /* clear Internal Data loopback mode */
5420 info->loopback_bits = 0;
5421 outw( 0,info->io_base + CCAR );
5422 }
5423
5424 } /* end of usc_enable_loopback() */
5425
5426 /* usc_enable_aux_clock()
5427 *
5428 * Enabled the AUX clock output at the specified frequency.
5429 *
5430 * Arguments:
5431 *
5432 * info pointer to device extension
5433 * data_rate data rate of clock in bits per second
5434 * A data rate of 0 disables the AUX clock.
5435 *
5436 * Return Value: None
5437 */
5438 void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5439 {
5440 u32 XtalSpeed;
5441 u16 Tc;
5442
5443 if ( data_rate ) {
5444 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5445 XtalSpeed = 11059200;
5446 else
5447 XtalSpeed = 14745600;
5448
5449
5450 /* Tc = (Xtal/Speed) - 1 */
5451 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5452 /* then rounding up gives a more precise time constant. Instead */
5453 /* of rounding up and then subtracting 1 we just don't subtract */
5454 /* the one in this case. */
5455
5456
5457 Tc = (u16)(XtalSpeed/data_rate);
5458 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5459 Tc--;
5460
5461 /* Write 16-bit Time Constant for BRG0 */
5462 usc_OutReg( info, TC0R, Tc );
5463
5464 /*
5465 * Hardware Configuration Register (HCR)
5466 * Clear Bit 1, BRG0 mode = Continuous
5467 * Set Bit 0 to enable BRG0.
5468 */
5469
5470 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5471
5472 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5473 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5474 } else {
5475 /* data rate == 0 so turn off BRG0 */
5476 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5477 }
5478
5479 } /* end of usc_enable_aux_clock() */
5480
5481 /*
5482 *
5483 * usc_process_rxoverrun_sync()
5484 *
5485 * This function processes a receive overrun by resetting the
5486 * receive DMA buffers and issuing a Purge Rx FIFO command
5487 * to allow the receiver to continue receiving.
5488 *
5489 * Arguments:
5490 *
5491 * info pointer to device extension
5492 *
5493 * Return Value: None
5494 */
5495 void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5496 {
5497 int start_index;
5498 int end_index;
5499 int frame_start_index;
5500 int start_of_frame_found = FALSE;
5501 int end_of_frame_found = FALSE;
5502 int reprogram_dma = FALSE;
5503
5504 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5505 u32 phys_addr;
5506
5507 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5508 usc_RCmd( info, RCmd_EnterHuntmode );
5509 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5510
5511 /* CurrentRxBuffer points to the 1st buffer of the next */
5512 /* possibly available receive frame. */
5513
5514 frame_start_index = start_index = end_index = info->current_rx_buffer;
5515
5516 /* Search for an unfinished string of buffers. This means */
5517 /* that a receive frame started (at least one buffer with */
5518 /* count set to zero) but there is no terminiting buffer */
5519 /* (status set to non-zero). */
5520
5521 while( !buffer_list[end_index].count )
5522 {
5523 /* Count field has been reset to zero by 16C32. */
5524 /* This buffer is currently in use. */
5525
5526 if ( !start_of_frame_found )
5527 {
5528 start_of_frame_found = TRUE;
5529 frame_start_index = end_index;
5530 end_of_frame_found = FALSE;
5531 }
5532
5533 if ( buffer_list[end_index].status )
5534 {
5535 /* Status field has been set by 16C32. */
5536 /* This is the last buffer of a received frame. */
5537
5538 /* We want to leave the buffers for this frame intact. */
5539 /* Move on to next possible frame. */
5540
5541 start_of_frame_found = FALSE;
5542 end_of_frame_found = TRUE;
5543 }
5544
5545 /* advance to next buffer entry in linked list */
5546 end_index++;
5547 if ( end_index == info->rx_buffer_count )
5548 end_index = 0;
5549
5550 if ( start_index == end_index )
5551 {
5552 /* The entire list has been searched with all Counts == 0 and */
5553 /* all Status == 0. The receive buffers are */
5554 /* completely screwed, reset all receive buffers! */
5555 mgsl_reset_rx_dma_buffers( info );
5556 frame_start_index = 0;
5557 start_of_frame_found = FALSE;
5558 reprogram_dma = TRUE;
5559 break;
5560 }
5561 }
5562
5563 if ( start_of_frame_found && !end_of_frame_found )
5564 {
5565 /* There is an unfinished string of receive DMA buffers */
5566 /* as a result of the receiver overrun. */
5567
5568 /* Reset the buffers for the unfinished frame */
5569 /* and reprogram the receive DMA controller to start */
5570 /* at the 1st buffer of unfinished frame. */
5571
5572 start_index = frame_start_index;
5573
5574 do
5575 {
5576 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5577
5578 /* Adjust index for wrap around. */
5579 if ( start_index == info->rx_buffer_count )
5580 start_index = 0;
5581
5582 } while( start_index != end_index );
5583
5584 reprogram_dma = TRUE;
5585 }
5586
5587 if ( reprogram_dma )
5588 {
5589 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5590 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5591 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5592
5593 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5594
5595 /* This empties the receive FIFO and loads the RCC with RCLR */
5596 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5597
5598 /* program 16C32 with physical address of 1st DMA buffer entry */
5599 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5600 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5601 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5602
5603 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5604 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5605 usc_EnableInterrupts( info, RECEIVE_STATUS );
5606
5607 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5608 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5609
5610 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5611 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5612 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5613 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5614 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5615 else
5616 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5617 }
5618 else
5619 {
5620 /* This empties the receive FIFO and loads the RCC with RCLR */
5621 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5622 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5623 }
5624
5625 } /* end of usc_process_rxoverrun_sync() */
5626
5627 /* usc_stop_receiver()
5628 *
5629 * Disable USC receiver
5630 *
5631 * Arguments: info pointer to device instance data
5632 * Return Value: None
5633 */
5634 void usc_stop_receiver( struct mgsl_struct *info )
5635 {
5636 if (debug_level >= DEBUG_LEVEL_ISR)
5637 printk("%s(%d):usc_stop_receiver(%s)\n",
5638 __FILE__,__LINE__, info->device_name );
5639
5640 /* Disable receive DMA channel. */
5641 /* This also disables receive DMA channel interrupts */
5642 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5643
5644 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5645 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5646 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5647
5648 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5649
5650 /* This empties the receive FIFO and loads the RCC with RCLR */
5651 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5652 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5653
5654 info->rx_enabled = 0;
5655 info->rx_overflow = 0;
5656 info->rx_rcc_underrun = 0;
5657
5658 } /* end of stop_receiver() */
5659
5660 /* usc_start_receiver()
5661 *
5662 * Enable the USC receiver
5663 *
5664 * Arguments: info pointer to device instance data
5665 * Return Value: None
5666 */
5667 void usc_start_receiver( struct mgsl_struct *info )
5668 {
5669 u32 phys_addr;
5670
5671 if (debug_level >= DEBUG_LEVEL_ISR)
5672 printk("%s(%d):usc_start_receiver(%s)\n",
5673 __FILE__,__LINE__, info->device_name );
5674
5675 mgsl_reset_rx_dma_buffers( info );
5676 usc_stop_receiver( info );
5677
5678 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5679 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5680
5681 if ( info->params.mode == MGSL_MODE_HDLC ||
5682 info->params.mode == MGSL_MODE_RAW ) {
5683 /* DMA mode Transfers */
5684 /* Program the DMA controller. */
5685 /* Enable the DMA controller end of buffer interrupt. */
5686
5687 /* program 16C32 with physical address of 1st DMA buffer entry */
5688 phys_addr = info->rx_buffer_list[0].phys_entry;
5689 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5690 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5691
5692 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5693 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5694 usc_EnableInterrupts( info, RECEIVE_STATUS );
5695
5696 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5697 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5698
5699 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5700 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5701 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5702 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5703 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5704 else
5705 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5706 } else {
5707 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5708 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5709 usc_EnableInterrupts(info, RECEIVE_DATA);
5710
5711 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5712 usc_RCmd( info, RCmd_EnterHuntmode );
5713
5714 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5715 }
5716
5717 usc_OutReg( info, CCSR, 0x1020 );
5718
5719 info->rx_enabled = 1;
5720
5721 } /* end of usc_start_receiver() */
5722
5723 /* usc_start_transmitter()
5724 *
5725 * Enable the USC transmitter and send a transmit frame if
5726 * one is loaded in the DMA buffers.
5727 *
5728 * Arguments: info pointer to device instance data
5729 * Return Value: None
5730 */
5731 void usc_start_transmitter( struct mgsl_struct *info )
5732 {
5733 u32 phys_addr;
5734 unsigned int FrameSize;
5735
5736 if (debug_level >= DEBUG_LEVEL_ISR)
5737 printk("%s(%d):usc_start_transmitter(%s)\n",
5738 __FILE__,__LINE__, info->device_name );
5739
5740 if ( info->xmit_cnt ) {
5741
5742 /* If auto RTS enabled and RTS is inactive, then assert */
5743 /* RTS and set a flag indicating that the driver should */
5744 /* negate RTS when the transmission completes. */
5745
5746 info->drop_rts_on_tx_done = 0;
5747
5748 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5749 usc_get_serial_signals( info );
5750 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5751 info->serial_signals |= SerialSignal_RTS;
5752 usc_set_serial_signals( info );
5753 info->drop_rts_on_tx_done = 1;
5754 }
5755 }
5756
5757
5758 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5759 if ( !info->tx_active ) {
5760 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5761 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5762 usc_EnableInterrupts(info, TRANSMIT_DATA);
5763 usc_load_txfifo(info);
5764 }
5765 } else {
5766 /* Disable transmit DMA controller while programming. */
5767 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5768
5769 /* Transmit DMA buffer is loaded, so program USC */
5770 /* to send the frame contained in the buffers. */
5771
5772 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5773
5774 /* if operating in Raw sync mode, reset the rcc component
5775 * of the tx dma buffer entry, otherwise, the serial controller
5776 * will send a closing sync char after this count.
5777 */
5778 if ( info->params.mode == MGSL_MODE_RAW )
5779 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5780
5781 /* Program the Transmit Character Length Register (TCLR) */
5782 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5783 usc_OutReg( info, TCLR, (u16)FrameSize );
5784
5785 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5786
5787 /* Program the address of the 1st DMA Buffer Entry in linked list */
5788 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5789 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5790 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5791
5792 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5793 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5794 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5795
5796 if ( info->params.mode == MGSL_MODE_RAW &&
5797 info->num_tx_dma_buffers > 1 ) {
5798 /* When running external sync mode, attempt to 'stream' transmit */
5799 /* by filling tx dma buffers as they become available. To do this */
5800 /* we need to enable Tx DMA EOB Status interrupts : */
5801 /* */
5802 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5803 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5804
5805 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5806 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5807 }
5808
5809 /* Initialize Transmit DMA Channel */
5810 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5811
5812 usc_TCmd( info, TCmd_SendFrame );
5813
5814 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
5815 add_timer(&info->tx_timer);
5816 }
5817 info->tx_active = 1;
5818 }
5819
5820 if ( !info->tx_enabled ) {
5821 info->tx_enabled = 1;
5822 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5823 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5824 else
5825 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5826 }
5827
5828 } /* end of usc_start_transmitter() */
5829
5830 /* usc_stop_transmitter()
5831 *
5832 * Stops the transmitter and DMA
5833 *
5834 * Arguments: info pointer to device isntance data
5835 * Return Value: None
5836 */
5837 void usc_stop_transmitter( struct mgsl_struct *info )
5838 {
5839 if (debug_level >= DEBUG_LEVEL_ISR)
5840 printk("%s(%d):usc_stop_transmitter(%s)\n",
5841 __FILE__,__LINE__, info->device_name );
5842
5843 del_timer(&info->tx_timer);
5844
5845 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5846 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5847 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5848
5849 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5850 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5851 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5852
5853 info->tx_enabled = 0;
5854 info->tx_active = 0;
5855
5856 } /* end of usc_stop_transmitter() */
5857
5858 /* usc_load_txfifo()
5859 *
5860 * Fill the transmit FIFO until the FIFO is full or
5861 * there is no more data to load.
5862 *
5863 * Arguments: info pointer to device extension (instance data)
5864 * Return Value: None
5865 */
5866 void usc_load_txfifo( struct mgsl_struct *info )
5867 {
5868 int Fifocount;
5869 u8 TwoBytes[2];
5870
5871 if ( !info->xmit_cnt && !info->x_char )
5872 return;
5873
5874 /* Select transmit FIFO status readback in TICR */
5875 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5876
5877 /* load the Transmit FIFO until FIFOs full or all data sent */
5878
5879 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5880 /* there is more space in the transmit FIFO and */
5881 /* there is more data in transmit buffer */
5882
5883 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5884 /* write a 16-bit word from transmit buffer to 16C32 */
5885
5886 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5887 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5888 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5889 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5890
5891 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5892
5893 info->xmit_cnt -= 2;
5894 info->icount.tx += 2;
5895 } else {
5896 /* only 1 byte left to transmit or 1 FIFO slot left */
5897
5898 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5899 info->io_base + CCAR );
5900
5901 if (info->x_char) {
5902 /* transmit pending high priority char */
5903 outw( info->x_char,info->io_base + CCAR );
5904 info->x_char = 0;
5905 } else {
5906 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5907 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5908 info->xmit_cnt--;
5909 }
5910 info->icount.tx++;
5911 }
5912 }
5913
5914 } /* end of usc_load_txfifo() */
5915
5916 /* usc_reset()
5917 *
5918 * Reset the adapter to a known state and prepare it for further use.
5919 *
5920 * Arguments: info pointer to device instance data
5921 * Return Value: None
5922 */
5923 void usc_reset( struct mgsl_struct *info )
5924 {
5925 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5926 int i;
5927 u32 readval;
5928
5929 /* Set BIT30 of Misc Control Register */
5930 /* (Local Control Register 0x50) to force reset of USC. */
5931
5932 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5933 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5934
5935 info->misc_ctrl_value |= BIT30;
5936 *MiscCtrl = info->misc_ctrl_value;
5937
5938 /*
5939 * Force at least 170ns delay before clearing
5940 * reset bit. Each read from LCR takes at least
5941 * 30ns so 10 times for 300ns to be safe.
5942 */
5943 for(i=0;i<10;i++)
5944 readval = *MiscCtrl;
5945
5946 info->misc_ctrl_value &= ~BIT30;
5947 *MiscCtrl = info->misc_ctrl_value;
5948
5949 *LCR0BRDR = BUS_DESCRIPTOR(
5950 1, // Write Strobe Hold (0-3)
5951 2, // Write Strobe Delay (0-3)
5952 2, // Read Strobe Delay (0-3)
5953 0, // NWDD (Write data-data) (0-3)
5954 4, // NWAD (Write Addr-data) (0-31)
5955 0, // NXDA (Read/Write Data-Addr) (0-3)
5956 0, // NRDD (Read Data-Data) (0-3)
5957 5 // NRAD (Read Addr-Data) (0-31)
5958 );
5959 } else {
5960 /* do HW reset */
5961 outb( 0,info->io_base + 8 );
5962 }
5963
5964 info->mbre_bit = 0;
5965 info->loopback_bits = 0;
5966 info->usc_idle_mode = 0;
5967
5968 /*
5969 * Program the Bus Configuration Register (BCR)
5970 *
5971 * <15> 0 Don't use separate address
5972 * <14..6> 0 reserved
5973 * <5..4> 00 IAckmode = Default, don't care
5974 * <3> 1 Bus Request Totem Pole output
5975 * <2> 1 Use 16 Bit data bus
5976 * <1> 0 IRQ Totem Pole output
5977 * <0> 0 Don't Shift Right Addr
5978 *
5979 * 0000 0000 0000 1100 = 0x000c
5980 *
5981 * By writing to io_base + SDPIN the Wait/Ack pin is
5982 * programmed to work as a Wait pin.
5983 */
5984
5985 outw( 0x000c,info->io_base + SDPIN );
5986
5987
5988 outw( 0,info->io_base );
5989 outw( 0,info->io_base + CCAR );
5990
5991 /* select little endian byte ordering */
5992 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5993
5994
5995 /* Port Control Register (PCR)
5996 *
5997 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5998 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5999 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
6000 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
6001 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
6002 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
6003 * <3..2> 01 Port 1 is Input (Dedicated RxC)
6004 * <1..0> 01 Port 0 is Input (Dedicated TxC)
6005 *
6006 * 1111 0000 1111 0101 = 0xf0f5
6007 */
6008
6009 usc_OutReg( info, PCR, 0xf0f5 );
6010
6011
6012 /*
6013 * Input/Output Control Register
6014 *
6015 * <15..14> 00 CTS is active low input
6016 * <13..12> 00 DCD is active low input
6017 * <11..10> 00 TxREQ pin is input (DSR)
6018 * <9..8> 00 RxREQ pin is input (RI)
6019 * <7..6> 00 TxD is output (Transmit Data)
6020 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
6021 * <2..0> 100 RxC is Output (drive with BRG0)
6022 *
6023 * 0000 0000 0000 0100 = 0x0004
6024 */
6025
6026 usc_OutReg( info, IOCR, 0x0004 );
6027
6028 } /* end of usc_reset() */
6029
6030 /* usc_set_async_mode()
6031 *
6032 * Program adapter for asynchronous communications.
6033 *
6034 * Arguments: info pointer to device instance data
6035 * Return Value: None
6036 */
6037 void usc_set_async_mode( struct mgsl_struct *info )
6038 {
6039 u16 RegValue;
6040
6041 /* disable interrupts while programming USC */
6042 usc_DisableMasterIrqBit( info );
6043
6044 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
6045 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
6046
6047 usc_loopback_frame( info );
6048
6049 /* Channel mode Register (CMR)
6050 *
6051 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
6052 * <13..12> 00 00 = 16X Clock
6053 * <11..8> 0000 Transmitter mode = Asynchronous
6054 * <7..6> 00 reserved?
6055 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
6056 * <3..0> 0000 Receiver mode = Asynchronous
6057 *
6058 * 0000 0000 0000 0000 = 0x0
6059 */
6060
6061 RegValue = 0;
6062 if ( info->params.stop_bits != 1 )
6063 RegValue |= BIT14;
6064 usc_OutReg( info, CMR, RegValue );
6065
6066
6067 /* Receiver mode Register (RMR)
6068 *
6069 * <15..13> 000 encoding = None
6070 * <12..08> 00000 reserved (Sync Only)
6071 * <7..6> 00 Even parity
6072 * <5> 0 parity disabled
6073 * <4..2> 000 Receive Char Length = 8 bits
6074 * <1..0> 00 Disable Receiver
6075 *
6076 * 0000 0000 0000 0000 = 0x0
6077 */
6078
6079 RegValue = 0;
6080
6081 if ( info->params.data_bits != 8 )
6082 RegValue |= BIT4+BIT3+BIT2;
6083
6084 if ( info->params.parity != ASYNC_PARITY_NONE ) {
6085 RegValue |= BIT5;
6086 if ( info->params.parity != ASYNC_PARITY_ODD )
6087 RegValue |= BIT6;
6088 }
6089
6090 usc_OutReg( info, RMR, RegValue );
6091
6092
6093 /* Set IRQ trigger level */
6094
6095 usc_RCmd( info, RCmd_SelectRicrIntLevel );
6096
6097
6098 /* Receive Interrupt Control Register (RICR)
6099 *
6100 * <15..8> ? RxFIFO IRQ Request Level
6101 *
6102 * Note: For async mode the receive FIFO level must be set
6103 * to 0 to aviod the situation where the FIFO contains fewer bytes
6104 * than the trigger level and no more data is expected.
6105 *
6106 * <7> 0 Exited Hunt IA (Interrupt Arm)
6107 * <6> 0 Idle Received IA
6108 * <5> 0 Break/Abort IA
6109 * <4> 0 Rx Bound IA
6110 * <3> 0 Queued status reflects oldest byte in FIFO
6111 * <2> 0 Abort/PE IA
6112 * <1> 0 Rx Overrun IA
6113 * <0> 0 Select TC0 value for readback
6114 *
6115 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
6116 */
6117
6118 usc_OutReg( info, RICR, 0x0000 );
6119
6120 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
6121 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
6122
6123
6124 /* Transmit mode Register (TMR)
6125 *
6126 * <15..13> 000 encoding = None
6127 * <12..08> 00000 reserved (Sync Only)
6128 * <7..6> 00 Transmit parity Even
6129 * <5> 0 Transmit parity Disabled
6130 * <4..2> 000 Tx Char Length = 8 bits
6131 * <1..0> 00 Disable Transmitter
6132 *
6133 * 0000 0000 0000 0000 = 0x0
6134 */
6135
6136 RegValue = 0;
6137
6138 if ( info->params.data_bits != 8 )
6139 RegValue |= BIT4+BIT3+BIT2;
6140
6141 if ( info->params.parity != ASYNC_PARITY_NONE ) {
6142 RegValue |= BIT5;
6143 if ( info->params.parity != ASYNC_PARITY_ODD )
6144 RegValue |= BIT6;
6145 }
6146
6147 usc_OutReg( info, TMR, RegValue );
6148
6149 usc_set_txidle( info );
6150
6151
6152 /* Set IRQ trigger level */
6153
6154 usc_TCmd( info, TCmd_SelectTicrIntLevel );
6155
6156
6157 /* Transmit Interrupt Control Register (TICR)
6158 *
6159 * <15..8> ? Transmit FIFO IRQ Level
6160 * <7> 0 Present IA (Interrupt Arm)
6161 * <6> 1 Idle Sent IA
6162 * <5> 0 Abort Sent IA
6163 * <4> 0 EOF/EOM Sent IA
6164 * <3> 0 CRC Sent IA
6165 * <2> 0 1 = Wait for SW Trigger to Start Frame
6166 * <1> 0 Tx Underrun IA
6167 * <0> 0 TC0 constant on read back
6168 *
6169 * 0000 0000 0100 0000 = 0x0040
6170 */
6171
6172 usc_OutReg( info, TICR, 0x1f40 );
6173
6174 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6175 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6176
6177 usc_enable_async_clock( info, info->params.data_rate );
6178
6179
6180 /* Channel Control/status Register (CCSR)
6181 *
6182 * <15> X RCC FIFO Overflow status (RO)
6183 * <14> X RCC FIFO Not Empty status (RO)
6184 * <13> 0 1 = Clear RCC FIFO (WO)
6185 * <12> X DPLL in Sync status (RO)
6186 * <11> X DPLL 2 Missed Clocks status (RO)
6187 * <10> X DPLL 1 Missed Clock status (RO)
6188 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6189 * <7> X SDLC Loop On status (RO)
6190 * <6> X SDLC Loop Send status (RO)
6191 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6192 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6193 * <1..0> 00 reserved
6194 *
6195 * 0000 0000 0010 0000 = 0x0020
6196 */
6197
6198 usc_OutReg( info, CCSR, 0x0020 );
6199
6200 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6201 RECEIVE_DATA + RECEIVE_STATUS );
6202
6203 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6204 RECEIVE_DATA + RECEIVE_STATUS );
6205
6206 usc_EnableMasterIrqBit( info );
6207
6208 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6209 /* Enable INTEN (Port 6, Bit12) */
6210 /* This connects the IRQ request signal to the ISA bus */
6211 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6212 }
6213
6214 } /* end of usc_set_async_mode() */
6215
6216 /* usc_loopback_frame()
6217 *
6218 * Loop back a small (2 byte) dummy SDLC frame.
6219 * Interrupts and DMA are NOT used. The purpose of this is to
6220 * clear any 'stale' status info left over from running in async mode.
6221 *
6222 * The 16C32 shows the strange behaviour of marking the 1st
6223 * received SDLC frame with a CRC error even when there is no
6224 * CRC error. To get around this a small dummy from of 2 bytes
6225 * is looped back when switching from async to sync mode.
6226 *
6227 * Arguments: info pointer to device instance data
6228 * Return Value: None
6229 */
6230 void usc_loopback_frame( struct mgsl_struct *info )
6231 {
6232 int i;
6233 unsigned long oldmode = info->params.mode;
6234
6235 info->params.mode = MGSL_MODE_HDLC;
6236
6237 usc_DisableMasterIrqBit( info );
6238
6239 usc_set_sdlc_mode( info );
6240 usc_enable_loopback( info, 1 );
6241
6242 /* Write 16-bit Time Constant for BRG0 */
6243 usc_OutReg( info, TC0R, 0 );
6244
6245 /* Channel Control Register (CCR)
6246 *
6247 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6248 * <13> 0 Trigger Tx on SW Command Disabled
6249 * <12> 0 Flag Preamble Disabled
6250 * <11..10> 00 Preamble Length = 8-Bits
6251 * <9..8> 01 Preamble Pattern = flags
6252 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6253 * <5> 0 Trigger Rx on SW Command Disabled
6254 * <4..0> 0 reserved
6255 *
6256 * 0000 0001 0000 0000 = 0x0100
6257 */
6258
6259 usc_OutReg( info, CCR, 0x0100 );
6260
6261 /* SETUP RECEIVER */
6262 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6263 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6264
6265 /* SETUP TRANSMITTER */
6266 /* Program the Transmit Character Length Register (TCLR) */
6267 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6268 usc_OutReg( info, TCLR, 2 );
6269 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6270
6271 /* unlatch Tx status bits, and start transmit channel. */
6272 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6273 outw(0,info->io_base + DATAREG);
6274
6275 /* ENABLE TRANSMITTER */
6276 usc_TCmd( info, TCmd_SendFrame );
6277 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6278
6279 /* WAIT FOR RECEIVE COMPLETE */
6280 for (i=0 ; i<1000 ; i++)
6281 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6282 break;
6283
6284 /* clear Internal Data loopback mode */
6285 usc_enable_loopback(info, 0);
6286
6287 usc_EnableMasterIrqBit(info);
6288
6289 info->params.mode = oldmode;
6290
6291 } /* end of usc_loopback_frame() */
6292
6293 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6294 *
6295 * Arguments: info pointer to adapter info structure
6296 * Return Value: None
6297 */
6298 void usc_set_sync_mode( struct mgsl_struct *info )
6299 {
6300 usc_loopback_frame( info );
6301 usc_set_sdlc_mode( info );
6302
6303 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6304 /* Enable INTEN (Port 6, Bit12) */
6305 /* This connects the IRQ request signal to the ISA bus */
6306 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6307 }
6308
6309 usc_enable_aux_clock(info, info->params.clock_speed);
6310
6311 if (info->params.loopback)
6312 usc_enable_loopback(info,1);
6313
6314 } /* end of mgsl_set_sync_mode() */
6315
6316 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6317 *
6318 * Arguments: info pointer to device instance data
6319 * Return Value: None
6320 */
6321 void usc_set_txidle( struct mgsl_struct *info )
6322 {
6323 u16 usc_idle_mode = IDLEMODE_FLAGS;
6324
6325 /* Map API idle mode to USC register bits */
6326
6327 switch( info->idle_mode ){
6328 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6329 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6330 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6331 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6332 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6333 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6334 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6335 }
6336
6337 info->usc_idle_mode = usc_idle_mode;
6338 //usc_OutReg(info, TCSR, usc_idle_mode);
6339 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6340 info->tcsr_value += usc_idle_mode;
6341 usc_OutReg(info, TCSR, info->tcsr_value);
6342
6343 /*
6344 * if SyncLink WAN adapter is running in external sync mode, the
6345 * transmitter has been set to Monosync in order to try to mimic
6346 * a true raw outbound bit stream. Monosync still sends an open/close
6347 * sync char at the start/end of a frame. Try to match those sync
6348 * patterns to the idle mode set here
6349 */
6350 if ( info->params.mode == MGSL_MODE_RAW ) {
6351 unsigned char syncpat = 0;
6352 switch( info->idle_mode ) {
6353 case HDLC_TXIDLE_FLAGS:
6354 syncpat = 0x7e;
6355 break;
6356 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6357 syncpat = 0x55;
6358 break;
6359 case HDLC_TXIDLE_ZEROS:
6360 case HDLC_TXIDLE_SPACE:
6361 syncpat = 0x00;
6362 break;
6363 case HDLC_TXIDLE_ONES:
6364 case HDLC_TXIDLE_MARK:
6365 syncpat = 0xff;
6366 break;
6367 case HDLC_TXIDLE_ALT_MARK_SPACE:
6368 syncpat = 0xaa;
6369 break;
6370 }
6371
6372 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6373 }
6374
6375 } /* end of usc_set_txidle() */
6376
6377 /* usc_get_serial_signals()
6378 *
6379 * Query the adapter for the state of the V24 status (input) signals.
6380 *
6381 * Arguments: info pointer to device instance data
6382 * Return Value: None
6383 */
6384 void usc_get_serial_signals( struct mgsl_struct *info )
6385 {
6386 u16 status;
6387
6388 /* clear all serial signals except DTR and RTS */
6389 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6390
6391 /* Read the Misc Interrupt status Register (MISR) to get */
6392 /* the V24 status signals. */
6393
6394 status = usc_InReg( info, MISR );
6395
6396 /* set serial signal bits to reflect MISR */
6397
6398 if ( status & MISCSTATUS_CTS )
6399 info->serial_signals |= SerialSignal_CTS;
6400
6401 if ( status & MISCSTATUS_DCD )
6402 info->serial_signals |= SerialSignal_DCD;
6403
6404 if ( status & MISCSTATUS_RI )
6405 info->serial_signals |= SerialSignal_RI;
6406
6407 if ( status & MISCSTATUS_DSR )
6408 info->serial_signals |= SerialSignal_DSR;
6409
6410 } /* end of usc_get_serial_signals() */
6411
6412 /* usc_set_serial_signals()
6413 *
6414 * Set the state of DTR and RTS based on contents of
6415 * serial_signals member of device extension.
6416 *
6417 * Arguments: info pointer to device instance data
6418 * Return Value: None
6419 */
6420 void usc_set_serial_signals( struct mgsl_struct *info )
6421 {
6422 u16 Control;
6423 unsigned char V24Out = info->serial_signals;
6424
6425 /* get the current value of the Port Control Register (PCR) */
6426
6427 Control = usc_InReg( info, PCR );
6428
6429 if ( V24Out & SerialSignal_RTS )
6430 Control &= ~(BIT6);
6431 else
6432 Control |= BIT6;
6433
6434 if ( V24Out & SerialSignal_DTR )
6435 Control &= ~(BIT4);
6436 else
6437 Control |= BIT4;
6438
6439 usc_OutReg( info, PCR, Control );
6440
6441 } /* end of usc_set_serial_signals() */
6442
6443 /* usc_enable_async_clock()
6444 *
6445 * Enable the async clock at the specified frequency.
6446 *
6447 * Arguments: info pointer to device instance data
6448 * data_rate data rate of clock in bps
6449 * 0 disables the AUX clock.
6450 * Return Value: None
6451 */
6452 void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6453 {
6454 if ( data_rate ) {
6455 /*
6456 * Clock mode Control Register (CMCR)
6457 *
6458 * <15..14> 00 counter 1 Disabled
6459 * <13..12> 00 counter 0 Disabled
6460 * <11..10> 11 BRG1 Input is TxC Pin
6461 * <9..8> 11 BRG0 Input is TxC Pin
6462 * <7..6> 01 DPLL Input is BRG1 Output
6463 * <5..3> 100 TxCLK comes from BRG0
6464 * <2..0> 100 RxCLK comes from BRG0
6465 *
6466 * 0000 1111 0110 0100 = 0x0f64
6467 */
6468
6469 usc_OutReg( info, CMCR, 0x0f64 );
6470
6471
6472 /*
6473 * Write 16-bit Time Constant for BRG0
6474 * Time Constant = (ClkSpeed / data_rate) - 1
6475 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6476 */
6477
6478 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6479 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6480 else
6481 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6482
6483
6484 /*
6485 * Hardware Configuration Register (HCR)
6486 * Clear Bit 1, BRG0 mode = Continuous
6487 * Set Bit 0 to enable BRG0.
6488 */
6489
6490 usc_OutReg( info, HCR,
6491 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6492
6493
6494 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6495
6496 usc_OutReg( info, IOCR,
6497 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6498 } else {
6499 /* data rate == 0 so turn off BRG0 */
6500 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6501 }
6502
6503 } /* end of usc_enable_async_clock() */
6504
6505 /*
6506 * Buffer Structures:
6507 *
6508 * Normal memory access uses virtual addresses that can make discontiguous
6509 * physical memory pages appear to be contiguous in the virtual address
6510 * space (the processors memory mapping handles the conversions).
6511 *
6512 * DMA transfers require physically contiguous memory. This is because
6513 * the DMA system controller and DMA bus masters deal with memory using
6514 * only physical addresses.
6515 *
6516 * This causes a problem under Windows NT when large DMA buffers are
6517 * needed. Fragmentation of the nonpaged pool prevents allocations of
6518 * physically contiguous buffers larger than the PAGE_SIZE.
6519 *
6520 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6521 * allows DMA transfers to physically discontiguous buffers. Information
6522 * about each data transfer buffer is contained in a memory structure
6523 * called a 'buffer entry'. A list of buffer entries is maintained
6524 * to track and control the use of the data transfer buffers.
6525 *
6526 * To support this strategy we will allocate sufficient PAGE_SIZE
6527 * contiguous memory buffers to allow for the total required buffer
6528 * space.
6529 *
6530 * The 16C32 accesses the list of buffer entries using Bus Master
6531 * DMA. Control information is read from the buffer entries by the
6532 * 16C32 to control data transfers. status information is written to
6533 * the buffer entries by the 16C32 to indicate the status of completed
6534 * transfers.
6535 *
6536 * The CPU writes control information to the buffer entries to control
6537 * the 16C32 and reads status information from the buffer entries to
6538 * determine information about received and transmitted frames.
6539 *
6540 * Because the CPU and 16C32 (adapter) both need simultaneous access
6541 * to the buffer entries, the buffer entry memory is allocated with
6542 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6543 * entry list to PAGE_SIZE.
6544 *
6545 * The actual data buffers on the other hand will only be accessed
6546 * by the CPU or the adapter but not by both simultaneously. This allows
6547 * Scatter/Gather packet based DMA procedures for using physically
6548 * discontiguous pages.
6549 */
6550
6551 /*
6552 * mgsl_reset_tx_dma_buffers()
6553 *
6554 * Set the count for all transmit buffers to 0 to indicate the
6555 * buffer is available for use and set the current buffer to the
6556 * first buffer. This effectively makes all buffers free and
6557 * discards any data in buffers.
6558 *
6559 * Arguments: info pointer to device instance data
6560 * Return Value: None
6561 */
6562 void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6563 {
6564 unsigned int i;
6565
6566 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6567 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6568 }
6569
6570 info->current_tx_buffer = 0;
6571 info->start_tx_dma_buffer = 0;
6572 info->tx_dma_buffers_used = 0;
6573
6574 info->get_tx_holding_index = 0;
6575 info->put_tx_holding_index = 0;
6576 info->tx_holding_count = 0;
6577
6578 } /* end of mgsl_reset_tx_dma_buffers() */
6579
6580 /*
6581 * num_free_tx_dma_buffers()
6582 *
6583 * returns the number of free tx dma buffers available
6584 *
6585 * Arguments: info pointer to device instance data
6586 * Return Value: number of free tx dma buffers
6587 */
6588 int num_free_tx_dma_buffers(struct mgsl_struct *info)
6589 {
6590 return info->tx_buffer_count - info->tx_dma_buffers_used;
6591 }
6592
6593 /*
6594 * mgsl_reset_rx_dma_buffers()
6595 *
6596 * Set the count for all receive buffers to DMABUFFERSIZE
6597 * and set the current buffer to the first buffer. This effectively
6598 * makes all buffers free and discards any data in buffers.
6599 *
6600 * Arguments: info pointer to device instance data
6601 * Return Value: None
6602 */
6603 void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6604 {
6605 unsigned int i;
6606
6607 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6608 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6609 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6610 // info->rx_buffer_list[i].status = 0;
6611 }
6612
6613 info->current_rx_buffer = 0;
6614
6615 } /* end of mgsl_reset_rx_dma_buffers() */
6616
6617 /*
6618 * mgsl_free_rx_frame_buffers()
6619 *
6620 * Free the receive buffers used by a received SDLC
6621 * frame such that the buffers can be reused.
6622 *
6623 * Arguments:
6624 *
6625 * info pointer to device instance data
6626 * StartIndex index of 1st receive buffer of frame
6627 * EndIndex index of last receive buffer of frame
6628 *
6629 * Return Value: None
6630 */
6631 void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6632 {
6633 int Done = 0;
6634 DMABUFFERENTRY *pBufEntry;
6635 unsigned int Index;
6636
6637 /* Starting with 1st buffer entry of the frame clear the status */
6638 /* field and set the count field to DMA Buffer Size. */
6639
6640 Index = StartIndex;
6641
6642 while( !Done ) {
6643 pBufEntry = &(info->rx_buffer_list[Index]);
6644
6645 if ( Index == EndIndex ) {
6646 /* This is the last buffer of the frame! */
6647 Done = 1;
6648 }
6649
6650 /* reset current buffer for reuse */
6651 // pBufEntry->status = 0;
6652 // pBufEntry->count = DMABUFFERSIZE;
6653 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6654
6655 /* advance to next buffer entry in linked list */
6656 Index++;
6657 if ( Index == info->rx_buffer_count )
6658 Index = 0;
6659 }
6660
6661 /* set current buffer to next buffer after last buffer of frame */
6662 info->current_rx_buffer = Index;
6663
6664 } /* end of free_rx_frame_buffers() */
6665
6666 /* mgsl_get_rx_frame()
6667 *
6668 * This function attempts to return a received SDLC frame from the
6669 * receive DMA buffers. Only frames received without errors are returned.
6670 *
6671 * Arguments: info pointer to device extension
6672 * Return Value: 1 if frame returned, otherwise 0
6673 */
6674 int mgsl_get_rx_frame(struct mgsl_struct *info)
6675 {
6676 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6677 unsigned short status;
6678 DMABUFFERENTRY *pBufEntry;
6679 unsigned int framesize = 0;
6680 int ReturnCode = 0;
6681 unsigned long flags;
6682 struct tty_struct *tty = info->tty;
6683 int return_frame = 0;
6684
6685 /*
6686 * current_rx_buffer points to the 1st buffer of the next available
6687 * receive frame. To find the last buffer of the frame look for
6688 * a non-zero status field in the buffer entries. (The status
6689 * field is set by the 16C32 after completing a receive frame.
6690 */
6691
6692 StartIndex = EndIndex = info->current_rx_buffer;
6693
6694 while( !info->rx_buffer_list[EndIndex].status ) {
6695 /*
6696 * If the count field of the buffer entry is non-zero then
6697 * this buffer has not been used. (The 16C32 clears the count
6698 * field when it starts using the buffer.) If an unused buffer
6699 * is encountered then there are no frames available.
6700 */
6701
6702 if ( info->rx_buffer_list[EndIndex].count )
6703 goto Cleanup;
6704
6705 /* advance to next buffer entry in linked list */
6706 EndIndex++;
6707 if ( EndIndex == info->rx_buffer_count )
6708 EndIndex = 0;
6709
6710 /* if entire list searched then no frame available */
6711 if ( EndIndex == StartIndex ) {
6712 /* If this occurs then something bad happened,
6713 * all buffers have been 'used' but none mark
6714 * the end of a frame. Reset buffers and receiver.
6715 */
6716
6717 if ( info->rx_enabled ){
6718 spin_lock_irqsave(&info->irq_spinlock,flags);
6719 usc_start_receiver(info);
6720 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6721 }
6722 goto Cleanup;
6723 }
6724 }
6725
6726
6727 /* check status of receive frame */
6728
6729 status = info->rx_buffer_list[EndIndex].status;
6730
6731 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6732 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6733 if ( status & RXSTATUS_SHORT_FRAME )
6734 info->icount.rxshort++;
6735 else if ( status & RXSTATUS_ABORT )
6736 info->icount.rxabort++;
6737 else if ( status & RXSTATUS_OVERRUN )
6738 info->icount.rxover++;
6739 else {
6740 info->icount.rxcrc++;
6741 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6742 return_frame = 1;
6743 }
6744 framesize = 0;
6745 #ifdef CONFIG_HDLC
6746 {
6747 struct net_device_stats *stats = hdlc_stats(info->netdev);
6748 stats->rx_errors++;
6749 stats->rx_frame_errors++;
6750 }
6751 #endif
6752 } else
6753 return_frame = 1;
6754
6755 if ( return_frame ) {
6756 /* receive frame has no errors, get frame size.
6757 * The frame size is the starting value of the RCC (which was
6758 * set to 0xffff) minus the ending value of the RCC (decremented
6759 * once for each receive character) minus 2 for the 16-bit CRC.
6760 */
6761
6762 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6763
6764 /* adjust frame size for CRC if any */
6765 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6766 framesize -= 2;
6767 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6768 framesize -= 4;
6769 }
6770
6771 if ( debug_level >= DEBUG_LEVEL_BH )
6772 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6773 __FILE__,__LINE__,info->device_name,status,framesize);
6774
6775 if ( debug_level >= DEBUG_LEVEL_DATA )
6776 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6777 min_t(int, framesize, DMABUFFERSIZE),0);
6778
6779 if (framesize) {
6780 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6781 ((framesize+1) > info->max_frame_size) ) ||
6782 (framesize > info->max_frame_size) )
6783 info->icount.rxlong++;
6784 else {
6785 /* copy dma buffer(s) to contiguous intermediate buffer */
6786 int copy_count = framesize;
6787 int index = StartIndex;
6788 unsigned char *ptmp = info->intermediate_rxbuffer;
6789
6790 if ( !(status & RXSTATUS_CRC_ERROR))
6791 info->icount.rxok++;
6792
6793 while(copy_count) {
6794 int partial_count;
6795 if ( copy_count > DMABUFFERSIZE )
6796 partial_count = DMABUFFERSIZE;
6797 else
6798 partial_count = copy_count;
6799
6800 pBufEntry = &(info->rx_buffer_list[index]);
6801 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6802 ptmp += partial_count;
6803 copy_count -= partial_count;
6804
6805 if ( ++index == info->rx_buffer_count )
6806 index = 0;
6807 }
6808
6809 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6810 ++framesize;
6811 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6812 RX_CRC_ERROR :
6813 RX_OK);
6814
6815 if ( debug_level >= DEBUG_LEVEL_DATA )
6816 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6817 __FILE__,__LINE__,info->device_name,
6818 *ptmp);
6819 }
6820
6821 #ifdef CONFIG_HDLC
6822 if (info->netcount)
6823 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6824 else
6825 #endif
6826 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6827 }
6828 }
6829 /* Free the buffers used by this frame. */
6830 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6831
6832 ReturnCode = 1;
6833
6834 Cleanup:
6835
6836 if ( info->rx_enabled && info->rx_overflow ) {
6837 /* The receiver needs to restarted because of
6838 * a receive overflow (buffer or FIFO). If the
6839 * receive buffers are now empty, then restart receiver.
6840 */
6841
6842 if ( !info->rx_buffer_list[EndIndex].status &&
6843 info->rx_buffer_list[EndIndex].count ) {
6844 spin_lock_irqsave(&info->irq_spinlock,flags);
6845 usc_start_receiver(info);
6846 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6847 }
6848 }
6849
6850 return ReturnCode;
6851
6852 } /* end of mgsl_get_rx_frame() */
6853
6854 /* mgsl_get_raw_rx_frame()
6855 *
6856 * This function attempts to return a received frame from the
6857 * receive DMA buffers when running in external loop mode. In this mode,
6858 * we will return at most one DMABUFFERSIZE frame to the application.
6859 * The USC receiver is triggering off of DCD going active to start a new
6860 * frame, and DCD going inactive to terminate the frame (similar to
6861 * processing a closing flag character).
6862 *
6863 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6864 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6865 * status field and the RCC field will indicate the length of the
6866 * entire received frame. We take this RCC field and get the modulus
6867 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6868 * last Rx DMA buffer and return that last portion of the frame.
6869 *
6870 * Arguments: info pointer to device extension
6871 * Return Value: 1 if frame returned, otherwise 0
6872 */
6873 int mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6874 {
6875 unsigned int CurrentIndex, NextIndex;
6876 unsigned short status;
6877 DMABUFFERENTRY *pBufEntry;
6878 unsigned int framesize = 0;
6879 int ReturnCode = 0;
6880 unsigned long flags;
6881 struct tty_struct *tty = info->tty;
6882
6883 /*
6884 * current_rx_buffer points to the 1st buffer of the next available
6885 * receive frame. The status field is set by the 16C32 after
6886 * completing a receive frame. If the status field of this buffer
6887 * is zero, either the USC is still filling this buffer or this
6888 * is one of a series of buffers making up a received frame.
6889 *
6890 * If the count field of this buffer is zero, the USC is either
6891 * using this buffer or has used this buffer. Look at the count
6892 * field of the next buffer. If that next buffer's count is
6893 * non-zero, the USC is still actively using the current buffer.
6894 * Otherwise, if the next buffer's count field is zero, the
6895 * current buffer is complete and the USC is using the next
6896 * buffer.
6897 */
6898 CurrentIndex = NextIndex = info->current_rx_buffer;
6899 ++NextIndex;
6900 if ( NextIndex == info->rx_buffer_count )
6901 NextIndex = 0;
6902
6903 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6904 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6905 info->rx_buffer_list[NextIndex].count == 0)) {
6906 /*
6907 * Either the status field of this dma buffer is non-zero
6908 * (indicating the last buffer of a receive frame) or the next
6909 * buffer is marked as in use -- implying this buffer is complete
6910 * and an intermediate buffer for this received frame.
6911 */
6912
6913 status = info->rx_buffer_list[CurrentIndex].status;
6914
6915 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6916 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6917 if ( status & RXSTATUS_SHORT_FRAME )
6918 info->icount.rxshort++;
6919 else if ( status & RXSTATUS_ABORT )
6920 info->icount.rxabort++;
6921 else if ( status & RXSTATUS_OVERRUN )
6922 info->icount.rxover++;
6923 else
6924 info->icount.rxcrc++;
6925 framesize = 0;
6926 } else {
6927 /*
6928 * A receive frame is available, get frame size and status.
6929 *
6930 * The frame size is the starting value of the RCC (which was
6931 * set to 0xffff) minus the ending value of the RCC (decremented
6932 * once for each receive character) minus 2 or 4 for the 16-bit
6933 * or 32-bit CRC.
6934 *
6935 * If the status field is zero, this is an intermediate buffer.
6936 * It's size is 4K.
6937 *
6938 * If the DMA Buffer Entry's Status field is non-zero, the
6939 * receive operation completed normally (ie: DCD dropped). The
6940 * RCC field is valid and holds the received frame size.
6941 * It is possible that the RCC field will be zero on a DMA buffer
6942 * entry with a non-zero status. This can occur if the total
6943 * frame size (number of bytes between the time DCD goes active
6944 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6945 * case the 16C32 has underrun on the RCC count and appears to
6946 * stop updating this counter to let us know the actual received
6947 * frame size. If this happens (non-zero status and zero RCC),
6948 * simply return the entire RxDMA Buffer
6949 */
6950 if ( status ) {
6951 /*
6952 * In the event that the final RxDMA Buffer is
6953 * terminated with a non-zero status and the RCC
6954 * field is zero, we interpret this as the RCC
6955 * having underflowed (received frame > 65535 bytes).
6956 *
6957 * Signal the event to the user by passing back
6958 * a status of RxStatus_CrcError returning the full
6959 * buffer and let the app figure out what data is
6960 * actually valid
6961 */
6962 if ( info->rx_buffer_list[CurrentIndex].rcc )
6963 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6964 else
6965 framesize = DMABUFFERSIZE;
6966 }
6967 else
6968 framesize = DMABUFFERSIZE;
6969 }
6970
6971 if ( framesize > DMABUFFERSIZE ) {
6972 /*
6973 * if running in raw sync mode, ISR handler for
6974 * End Of Buffer events terminates all buffers at 4K.
6975 * If this frame size is said to be >4K, get the
6976 * actual number of bytes of the frame in this buffer.
6977 */
6978 framesize = framesize % DMABUFFERSIZE;
6979 }
6980
6981
6982 if ( debug_level >= DEBUG_LEVEL_BH )
6983 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6984 __FILE__,__LINE__,info->device_name,status,framesize);
6985
6986 if ( debug_level >= DEBUG_LEVEL_DATA )
6987 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6988 min_t(int, framesize, DMABUFFERSIZE),0);
6989
6990 if (framesize) {
6991 /* copy dma buffer(s) to contiguous intermediate buffer */
6992 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6993
6994 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6995 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6996 info->icount.rxok++;
6997
6998 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6999 }
7000
7001 /* Free the buffers used by this frame. */
7002 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
7003
7004 ReturnCode = 1;
7005 }
7006
7007
7008 if ( info->rx_enabled && info->rx_overflow ) {
7009 /* The receiver needs to restarted because of
7010 * a receive overflow (buffer or FIFO). If the
7011 * receive buffers are now empty, then restart receiver.
7012 */
7013
7014 if ( !info->rx_buffer_list[CurrentIndex].status &&
7015 info->rx_buffer_list[CurrentIndex].count ) {
7016 spin_lock_irqsave(&info->irq_spinlock,flags);
7017 usc_start_receiver(info);
7018 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7019 }
7020 }
7021
7022 return ReturnCode;
7023
7024 } /* end of mgsl_get_raw_rx_frame() */
7025
7026 /* mgsl_load_tx_dma_buffer()
7027 *
7028 * Load the transmit DMA buffer with the specified data.
7029 *
7030 * Arguments:
7031 *
7032 * info pointer to device extension
7033 * Buffer pointer to buffer containing frame to load
7034 * BufferSize size in bytes of frame in Buffer
7035 *
7036 * Return Value: None
7037 */
7038 void mgsl_load_tx_dma_buffer(struct mgsl_struct *info, const char *Buffer,
7039 unsigned int BufferSize)
7040 {
7041 unsigned short Copycount;
7042 unsigned int i = 0;
7043 DMABUFFERENTRY *pBufEntry;
7044
7045 if ( debug_level >= DEBUG_LEVEL_DATA )
7046 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
7047
7048 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7049 /* set CMR:13 to start transmit when
7050 * next GoAhead (abort) is received
7051 */
7052 info->cmr_value |= BIT13;
7053 }
7054
7055 /* begin loading the frame in the next available tx dma
7056 * buffer, remember it's starting location for setting
7057 * up tx dma operation
7058 */
7059 i = info->current_tx_buffer;
7060 info->start_tx_dma_buffer = i;
7061
7062 /* Setup the status and RCC (Frame Size) fields of the 1st */
7063 /* buffer entry in the transmit DMA buffer list. */
7064
7065 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
7066 info->tx_buffer_list[i].rcc = BufferSize;
7067 info->tx_buffer_list[i].count = BufferSize;
7068
7069 /* Copy frame data from 1st source buffer to the DMA buffers. */
7070 /* The frame data may span multiple DMA buffers. */
7071
7072 while( BufferSize ){
7073 /* Get a pointer to next DMA buffer entry. */
7074 pBufEntry = &info->tx_buffer_list[i++];
7075
7076 if ( i == info->tx_buffer_count )
7077 i=0;
7078
7079 /* Calculate the number of bytes that can be copied from */
7080 /* the source buffer to this DMA buffer. */
7081 if ( BufferSize > DMABUFFERSIZE )
7082 Copycount = DMABUFFERSIZE;
7083 else
7084 Copycount = BufferSize;
7085
7086 /* Actually copy data from source buffer to DMA buffer. */
7087 /* Also set the data count for this individual DMA buffer. */
7088 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
7089 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
7090 else
7091 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
7092
7093 pBufEntry->count = Copycount;
7094
7095 /* Advance source pointer and reduce remaining data count. */
7096 Buffer += Copycount;
7097 BufferSize -= Copycount;
7098
7099 ++info->tx_dma_buffers_used;
7100 }
7101
7102 /* remember next available tx dma buffer */
7103 info->current_tx_buffer = i;
7104
7105 } /* end of mgsl_load_tx_dma_buffer() */
7106
7107 /*
7108 * mgsl_register_test()
7109 *
7110 * Performs a register test of the 16C32.
7111 *
7112 * Arguments: info pointer to device instance data
7113 * Return Value: TRUE if test passed, otherwise FALSE
7114 */
7115 BOOLEAN mgsl_register_test( struct mgsl_struct *info )
7116 {
7117 static unsigned short BitPatterns[] =
7118 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
7119 static unsigned int Patterncount = sizeof(BitPatterns)/sizeof(unsigned short);
7120 unsigned int i;
7121 BOOLEAN rc = TRUE;
7122 unsigned long flags;
7123
7124 spin_lock_irqsave(&info->irq_spinlock,flags);
7125 usc_reset(info);
7126
7127 /* Verify the reset state of some registers. */
7128
7129 if ( (usc_InReg( info, SICR ) != 0) ||
7130 (usc_InReg( info, IVR ) != 0) ||
7131 (usc_InDmaReg( info, DIVR ) != 0) ){
7132 rc = FALSE;
7133 }
7134
7135 if ( rc == TRUE ){
7136 /* Write bit patterns to various registers but do it out of */
7137 /* sync, then read back and verify values. */
7138
7139 for ( i = 0 ; i < Patterncount ; i++ ) {
7140 usc_OutReg( info, TC0R, BitPatterns[i] );
7141 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
7142 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
7143 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
7144 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
7145 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
7146
7147 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
7148 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
7149 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
7150 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
7151 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
7152 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
7153 rc = FALSE;
7154 break;
7155 }
7156 }
7157 }
7158
7159 usc_reset(info);
7160 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7161
7162 return rc;
7163
7164 } /* end of mgsl_register_test() */
7165
7166 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7167 *
7168 * Arguments: info pointer to device instance data
7169 * Return Value: TRUE if test passed, otherwise FALSE
7170 */
7171 BOOLEAN mgsl_irq_test( struct mgsl_struct *info )
7172 {
7173 unsigned long EndTime;
7174 unsigned long flags;
7175
7176 spin_lock_irqsave(&info->irq_spinlock,flags);
7177 usc_reset(info);
7178
7179 /*
7180 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7181 * The ISR sets irq_occurred to 1.
7182 */
7183
7184 info->irq_occurred = FALSE;
7185
7186 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7187 /* Enable INTEN (Port 6, Bit12) */
7188 /* This connects the IRQ request signal to the ISA bus */
7189 /* on the ISA adapter. This has no effect for the PCI adapter */
7190 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7191
7192 usc_EnableMasterIrqBit(info);
7193 usc_EnableInterrupts(info, IO_PIN);
7194 usc_ClearIrqPendingBits(info, IO_PIN);
7195
7196 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7197 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7198
7199 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7200
7201 EndTime=100;
7202 while( EndTime-- && !info->irq_occurred ) {
7203 set_current_state(TASK_INTERRUPTIBLE);
7204 schedule_timeout(msecs_to_jiffies(10));
7205 }
7206
7207 spin_lock_irqsave(&info->irq_spinlock,flags);
7208 usc_reset(info);
7209 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7210
7211 if ( !info->irq_occurred )
7212 return FALSE;
7213 else
7214 return TRUE;
7215
7216 } /* end of mgsl_irq_test() */
7217
7218 /* mgsl_dma_test()
7219 *
7220 * Perform a DMA test of the 16C32. A small frame is
7221 * transmitted via DMA from a transmit buffer to a receive buffer
7222 * using single buffer DMA mode.
7223 *
7224 * Arguments: info pointer to device instance data
7225 * Return Value: TRUE if test passed, otherwise FALSE
7226 */
7227 BOOLEAN mgsl_dma_test( struct mgsl_struct *info )
7228 {
7229 unsigned short FifoLevel;
7230 unsigned long phys_addr;
7231 unsigned int FrameSize;
7232 unsigned int i;
7233 char *TmpPtr;
7234 BOOLEAN rc = TRUE;
7235 unsigned short status=0;
7236 unsigned long EndTime;
7237 unsigned long flags;
7238 MGSL_PARAMS tmp_params;
7239
7240 /* save current port options */
7241 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7242 /* load default port options */
7243 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7244
7245 #define TESTFRAMESIZE 40
7246
7247 spin_lock_irqsave(&info->irq_spinlock,flags);
7248
7249 /* setup 16C32 for SDLC DMA transfer mode */
7250
7251 usc_reset(info);
7252 usc_set_sdlc_mode(info);
7253 usc_enable_loopback(info,1);
7254
7255 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7256 * field of the buffer entry after fetching buffer address. This
7257 * way we can detect a DMA failure for a DMA read (which should be
7258 * non-destructive to system memory) before we try and write to
7259 * memory (where a failure could corrupt system memory).
7260 */
7261
7262 /* Receive DMA mode Register (RDMR)
7263 *
7264 * <15..14> 11 DMA mode = Linked List Buffer mode
7265 * <13> 1 RSBinA/L = store Rx status Block in List entry
7266 * <12> 0 1 = Clear count of List Entry after fetching
7267 * <11..10> 00 Address mode = Increment
7268 * <9> 1 Terminate Buffer on RxBound
7269 * <8> 0 Bus Width = 16bits
7270 * <7..0> ? status Bits (write as 0s)
7271 *
7272 * 1110 0010 0000 0000 = 0xe200
7273 */
7274
7275 usc_OutDmaReg( info, RDMR, 0xe200 );
7276
7277 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7278
7279
7280 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7281
7282 FrameSize = TESTFRAMESIZE;
7283
7284 /* setup 1st transmit buffer entry: */
7285 /* with frame size and transmit control word */
7286
7287 info->tx_buffer_list[0].count = FrameSize;
7288 info->tx_buffer_list[0].rcc = FrameSize;
7289 info->tx_buffer_list[0].status = 0x4000;
7290
7291 /* build a transmit frame in 1st transmit DMA buffer */
7292
7293 TmpPtr = info->tx_buffer_list[0].virt_addr;
7294 for (i = 0; i < FrameSize; i++ )
7295 *TmpPtr++ = i;
7296
7297 /* setup 1st receive buffer entry: */
7298 /* clear status, set max receive buffer size */
7299
7300 info->rx_buffer_list[0].status = 0;
7301 info->rx_buffer_list[0].count = FrameSize + 4;
7302
7303 /* zero out the 1st receive buffer */
7304
7305 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7306
7307 /* Set count field of next buffer entries to prevent */
7308 /* 16C32 from using buffers after the 1st one. */
7309
7310 info->tx_buffer_list[1].count = 0;
7311 info->rx_buffer_list[1].count = 0;
7312
7313
7314 /***************************/
7315 /* Program 16C32 receiver. */
7316 /***************************/
7317
7318 spin_lock_irqsave(&info->irq_spinlock,flags);
7319
7320 /* setup DMA transfers */
7321 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7322
7323 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7324 phys_addr = info->rx_buffer_list[0].phys_entry;
7325 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7326 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7327
7328 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7329 usc_InDmaReg( info, RDMR );
7330 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7331
7332 /* Enable Receiver (RMR <1..0> = 10) */
7333 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7334
7335 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7336
7337
7338 /*************************************************************/
7339 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7340 /*************************************************************/
7341
7342 /* Wait 100ms for interrupt. */
7343 EndTime = jiffies + msecs_to_jiffies(100);
7344
7345 for(;;) {
7346 if (time_after(jiffies, EndTime)) {
7347 rc = FALSE;
7348 break;
7349 }
7350
7351 spin_lock_irqsave(&info->irq_spinlock,flags);
7352 status = usc_InDmaReg( info, RDMR );
7353 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7354
7355 if ( !(status & BIT4) && (status & BIT5) ) {
7356 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7357 /* BUSY (BIT 5) is active (channel still active). */
7358 /* This means the buffer entry read has completed. */
7359 break;
7360 }
7361 }
7362
7363
7364 /******************************/
7365 /* Program 16C32 transmitter. */
7366 /******************************/
7367
7368 spin_lock_irqsave(&info->irq_spinlock,flags);
7369
7370 /* Program the Transmit Character Length Register (TCLR) */
7371 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7372
7373 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7374 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7375
7376 /* Program the address of the 1st DMA Buffer Entry in linked list */
7377
7378 phys_addr = info->tx_buffer_list[0].phys_entry;
7379 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7380 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7381
7382 /* unlatch Tx status bits, and start transmit channel. */
7383
7384 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7385 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7386
7387 /* wait for DMA controller to fill transmit FIFO */
7388
7389 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7390
7391 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7392
7393
7394 /**********************************/
7395 /* WAIT FOR TRANSMIT FIFO TO FILL */
7396 /**********************************/
7397
7398 /* Wait 100ms */
7399 EndTime = jiffies + msecs_to_jiffies(100);
7400
7401 for(;;) {
7402 if (time_after(jiffies, EndTime)) {
7403 rc = FALSE;
7404 break;
7405 }
7406
7407 spin_lock_irqsave(&info->irq_spinlock,flags);
7408 FifoLevel = usc_InReg(info, TICR) >> 8;
7409 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7410
7411 if ( FifoLevel < 16 )
7412 break;
7413 else
7414 if ( FrameSize < 32 ) {
7415 /* This frame is smaller than the entire transmit FIFO */
7416 /* so wait for the entire frame to be loaded. */
7417 if ( FifoLevel <= (32 - FrameSize) )
7418 break;
7419 }
7420 }
7421
7422
7423 if ( rc == TRUE )
7424 {
7425 /* Enable 16C32 transmitter. */
7426
7427 spin_lock_irqsave(&info->irq_spinlock,flags);
7428
7429 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7430 usc_TCmd( info, TCmd_SendFrame );
7431 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7432
7433 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7434
7435
7436 /******************************/
7437 /* WAIT FOR TRANSMIT COMPLETE */
7438 /******************************/
7439
7440 /* Wait 100ms */
7441 EndTime = jiffies + msecs_to_jiffies(100);
7442
7443 /* While timer not expired wait for transmit complete */
7444
7445 spin_lock_irqsave(&info->irq_spinlock,flags);
7446 status = usc_InReg( info, TCSR );
7447 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7448
7449 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7450 if (time_after(jiffies, EndTime)) {
7451 rc = FALSE;
7452 break;
7453 }
7454
7455 spin_lock_irqsave(&info->irq_spinlock,flags);
7456 status = usc_InReg( info, TCSR );
7457 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7458 }
7459 }
7460
7461
7462 if ( rc == TRUE ){
7463 /* CHECK FOR TRANSMIT ERRORS */
7464 if ( status & (BIT5 + BIT1) )
7465 rc = FALSE;
7466 }
7467
7468 if ( rc == TRUE ) {
7469 /* WAIT FOR RECEIVE COMPLETE */
7470
7471 /* Wait 100ms */
7472 EndTime = jiffies + msecs_to_jiffies(100);
7473
7474 /* Wait for 16C32 to write receive status to buffer entry. */
7475 status=info->rx_buffer_list[0].status;
7476 while ( status == 0 ) {
7477 if (time_after(jiffies, EndTime)) {
7478 rc = FALSE;
7479 break;
7480 }
7481 status=info->rx_buffer_list[0].status;
7482 }
7483 }
7484
7485
7486 if ( rc == TRUE ) {
7487 /* CHECK FOR RECEIVE ERRORS */
7488 status = info->rx_buffer_list[0].status;
7489
7490 if ( status & (BIT8 + BIT3 + BIT1) ) {
7491 /* receive error has occurred */
7492 rc = FALSE;
7493 } else {
7494 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7495 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7496 rc = FALSE;
7497 }
7498 }
7499 }
7500
7501 spin_lock_irqsave(&info->irq_spinlock,flags);
7502 usc_reset( info );
7503 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7504
7505 /* restore current port options */
7506 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7507
7508 return rc;
7509
7510 } /* end of mgsl_dma_test() */
7511
7512 /* mgsl_adapter_test()
7513 *
7514 * Perform the register, IRQ, and DMA tests for the 16C32.
7515 *
7516 * Arguments: info pointer to device instance data
7517 * Return Value: 0 if success, otherwise -ENODEV
7518 */
7519 int mgsl_adapter_test( struct mgsl_struct *info )
7520 {
7521 if ( debug_level >= DEBUG_LEVEL_INFO )
7522 printk( "%s(%d):Testing device %s\n",
7523 __FILE__,__LINE__,info->device_name );
7524
7525 if ( !mgsl_register_test( info ) ) {
7526 info->init_error = DiagStatus_AddressFailure;
7527 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7528 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7529 return -ENODEV;
7530 }
7531
7532 if ( !mgsl_irq_test( info ) ) {
7533 info->init_error = DiagStatus_IrqFailure;
7534 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7535 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7536 return -ENODEV;
7537 }
7538
7539 if ( !mgsl_dma_test( info ) ) {
7540 info->init_error = DiagStatus_DmaFailure;
7541 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7542 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7543 return -ENODEV;
7544 }
7545
7546 if ( debug_level >= DEBUG_LEVEL_INFO )
7547 printk( "%s(%d):device %s passed diagnostics\n",
7548 __FILE__,__LINE__,info->device_name );
7549
7550 return 0;
7551
7552 } /* end of mgsl_adapter_test() */
7553
7554 /* mgsl_memory_test()
7555 *
7556 * Test the shared memory on a PCI adapter.
7557 *
7558 * Arguments: info pointer to device instance data
7559 * Return Value: TRUE if test passed, otherwise FALSE
7560 */
7561 BOOLEAN mgsl_memory_test( struct mgsl_struct *info )
7562 {
7563 static unsigned long BitPatterns[] = { 0x0, 0x55555555, 0xaaaaaaaa,
7564 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7565 unsigned long Patterncount = sizeof(BitPatterns)/sizeof(unsigned long);
7566 unsigned long i;
7567 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7568 unsigned long * TestAddr;
7569
7570 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7571 return TRUE;
7572
7573 TestAddr = (unsigned long *)info->memory_base;
7574
7575 /* Test data lines with test pattern at one location. */
7576
7577 for ( i = 0 ; i < Patterncount ; i++ ) {
7578 *TestAddr = BitPatterns[i];
7579 if ( *TestAddr != BitPatterns[i] )
7580 return FALSE;
7581 }
7582
7583 /* Test address lines with incrementing pattern over */
7584 /* entire address range. */
7585
7586 for ( i = 0 ; i < TestLimit ; i++ ) {
7587 *TestAddr = i * 4;
7588 TestAddr++;
7589 }
7590
7591 TestAddr = (unsigned long *)info->memory_base;
7592
7593 for ( i = 0 ; i < TestLimit ; i++ ) {
7594 if ( *TestAddr != i * 4 )
7595 return FALSE;
7596 TestAddr++;
7597 }
7598
7599 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7600
7601 return TRUE;
7602
7603 } /* End Of mgsl_memory_test() */
7604
7605
7606 /* mgsl_load_pci_memory()
7607 *
7608 * Load a large block of data into the PCI shared memory.
7609 * Use this instead of memcpy() or memmove() to move data
7610 * into the PCI shared memory.
7611 *
7612 * Notes:
7613 *
7614 * This function prevents the PCI9050 interface chip from hogging
7615 * the adapter local bus, which can starve the 16C32 by preventing
7616 * 16C32 bus master cycles.
7617 *
7618 * The PCI9050 documentation says that the 9050 will always release
7619 * control of the local bus after completing the current read
7620 * or write operation.
7621 *
7622 * It appears that as long as the PCI9050 write FIFO is full, the
7623 * PCI9050 treats all of the writes as a single burst transaction
7624 * and will not release the bus. This causes DMA latency problems
7625 * at high speeds when copying large data blocks to the shared
7626 * memory.
7627 *
7628 * This function in effect, breaks the a large shared memory write
7629 * into multiple transations by interleaving a shared memory read
7630 * which will flush the write FIFO and 'complete' the write
7631 * transation. This allows any pending DMA request to gain control
7632 * of the local bus in a timely fasion.
7633 *
7634 * Arguments:
7635 *
7636 * TargetPtr pointer to target address in PCI shared memory
7637 * SourcePtr pointer to source buffer for data
7638 * count count in bytes of data to copy
7639 *
7640 * Return Value: None
7641 */
7642 void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7643 unsigned short count )
7644 {
7645 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7646 #define PCI_LOAD_INTERVAL 64
7647
7648 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7649 unsigned short Index;
7650 unsigned long Dummy;
7651
7652 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7653 {
7654 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7655 Dummy = *((volatile unsigned long *)TargetPtr);
7656 TargetPtr += PCI_LOAD_INTERVAL;
7657 SourcePtr += PCI_LOAD_INTERVAL;
7658 }
7659
7660 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7661
7662 } /* End Of mgsl_load_pci_memory() */
7663
7664 void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7665 {
7666 int i;
7667 int linecount;
7668 if (xmit)
7669 printk("%s tx data:\n",info->device_name);
7670 else
7671 printk("%s rx data:\n",info->device_name);
7672
7673 while(count) {
7674 if (count > 16)
7675 linecount = 16;
7676 else
7677 linecount = count;
7678
7679 for(i=0;i<linecount;i++)
7680 printk("%02X ",(unsigned char)data[i]);
7681 for(;i<17;i++)
7682 printk(" ");
7683 for(i=0;i<linecount;i++) {
7684 if (data[i]>=040 && data[i]<=0176)
7685 printk("%c",data[i]);
7686 else
7687 printk(".");
7688 }
7689 printk("\n");
7690
7691 data += linecount;
7692 count -= linecount;
7693 }
7694 } /* end of mgsl_trace_block() */
7695
7696 /* mgsl_tx_timeout()
7697 *
7698 * called when HDLC frame times out
7699 * update stats and do tx completion processing
7700 *
7701 * Arguments: context pointer to device instance data
7702 * Return Value: None
7703 */
7704 void mgsl_tx_timeout(unsigned long context)
7705 {
7706 struct mgsl_struct *info = (struct mgsl_struct*)context;
7707 unsigned long flags;
7708
7709 if ( debug_level >= DEBUG_LEVEL_INFO )
7710 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7711 __FILE__,__LINE__,info->device_name);
7712 if(info->tx_active &&
7713 (info->params.mode == MGSL_MODE_HDLC ||
7714 info->params.mode == MGSL_MODE_RAW) ) {
7715 info->icount.txtimeout++;
7716 }
7717 spin_lock_irqsave(&info->irq_spinlock,flags);
7718 info->tx_active = 0;
7719 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7720
7721 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7722 usc_loopmode_cancel_transmit( info );
7723
7724 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7725
7726 #ifdef CONFIG_HDLC
7727 if (info->netcount)
7728 hdlcdev_tx_done(info);
7729 else
7730 #endif
7731 mgsl_bh_transmit(info);
7732
7733 } /* end of mgsl_tx_timeout() */
7734
7735 /* signal that there are no more frames to send, so that
7736 * line is 'released' by echoing RxD to TxD when current
7737 * transmission is complete (or immediately if no tx in progress).
7738 */
7739 static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7740 {
7741 unsigned long flags;
7742
7743 spin_lock_irqsave(&info->irq_spinlock,flags);
7744 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7745 if (info->tx_active)
7746 info->loopmode_send_done_requested = TRUE;
7747 else
7748 usc_loopmode_send_done(info);
7749 }
7750 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7751
7752 return 0;
7753 }
7754
7755 /* release the line by echoing RxD to TxD
7756 * upon completion of a transmit frame
7757 */
7758 void usc_loopmode_send_done( struct mgsl_struct * info )
7759 {
7760 info->loopmode_send_done_requested = FALSE;
7761 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7762 info->cmr_value &= ~BIT13;
7763 usc_OutReg(info, CMR, info->cmr_value);
7764 }
7765
7766 /* abort a transmit in progress while in HDLC LoopMode
7767 */
7768 void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7769 {
7770 /* reset tx dma channel and purge TxFifo */
7771 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7772 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7773 usc_loopmode_send_done( info );
7774 }
7775
7776 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7777 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7778 * we must clear CMR:13 to begin repeating TxData to RxData
7779 */
7780 void usc_loopmode_insert_request( struct mgsl_struct * info )
7781 {
7782 info->loopmode_insert_requested = TRUE;
7783
7784 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7785 * begin repeating TxData on RxData (complete insertion)
7786 */
7787 usc_OutReg( info, RICR,
7788 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7789
7790 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7791 info->cmr_value |= BIT13;
7792 usc_OutReg(info, CMR, info->cmr_value);
7793 }
7794
7795 /* return 1 if station is inserted into the loop, otherwise 0
7796 */
7797 int usc_loopmode_active( struct mgsl_struct * info)
7798 {
7799 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7800 }
7801
7802 /* return 1 if USC is in loop send mode, otherwise 0
7803 */
7804 int usc_loopmode_send_active( struct mgsl_struct * info )
7805 {
7806 return usc_InReg( info, CCSR ) & BIT6 ? 1 : 0 ;
7807 }
7808
7809 #ifdef CONFIG_HDLC
7810
7811 /**
7812 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7813 * set encoding and frame check sequence (FCS) options
7814 *
7815 * dev pointer to network device structure
7816 * encoding serial encoding setting
7817 * parity FCS setting
7818 *
7819 * returns 0 if success, otherwise error code
7820 */
7821 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7822 unsigned short parity)
7823 {
7824 struct mgsl_struct *info = dev_to_port(dev);
7825 unsigned char new_encoding;
7826 unsigned short new_crctype;
7827
7828 /* return error if TTY interface open */
7829 if (info->count)
7830 return -EBUSY;
7831
7832 switch (encoding)
7833 {
7834 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7835 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7836 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7837 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7838 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7839 default: return -EINVAL;
7840 }
7841
7842 switch (parity)
7843 {
7844 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7845 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7846 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7847 default: return -EINVAL;
7848 }
7849
7850 info->params.encoding = new_encoding;
7851 info->params.crc_type = new_crctype;;
7852
7853 /* if network interface up, reprogram hardware */
7854 if (info->netcount)
7855 mgsl_program_hw(info);
7856
7857 return 0;
7858 }
7859
7860 /**
7861 * called by generic HDLC layer to send frame
7862 *
7863 * skb socket buffer containing HDLC frame
7864 * dev pointer to network device structure
7865 *
7866 * returns 0 if success, otherwise error code
7867 */
7868 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
7869 {
7870 struct mgsl_struct *info = dev_to_port(dev);
7871 struct net_device_stats *stats = hdlc_stats(dev);
7872 unsigned long flags;
7873
7874 if (debug_level >= DEBUG_LEVEL_INFO)
7875 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7876
7877 /* stop sending until this frame completes */
7878 netif_stop_queue(dev);
7879
7880 /* copy data to device buffers */
7881 info->xmit_cnt = skb->len;
7882 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7883
7884 /* update network statistics */
7885 stats->tx_packets++;
7886 stats->tx_bytes += skb->len;
7887
7888 /* done with socket buffer, so free it */
7889 dev_kfree_skb(skb);
7890
7891 /* save start time for transmit timeout detection */
7892 dev->trans_start = jiffies;
7893
7894 /* start hardware transmitter if necessary */
7895 spin_lock_irqsave(&info->irq_spinlock,flags);
7896 if (!info->tx_active)
7897 usc_start_transmitter(info);
7898 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7899
7900 return 0;
7901 }
7902
7903 /**
7904 * called by network layer when interface enabled
7905 * claim resources and initialize hardware
7906 *
7907 * dev pointer to network device structure
7908 *
7909 * returns 0 if success, otherwise error code
7910 */
7911 static int hdlcdev_open(struct net_device *dev)
7912 {
7913 struct mgsl_struct *info = dev_to_port(dev);
7914 int rc;
7915 unsigned long flags;
7916
7917 if (debug_level >= DEBUG_LEVEL_INFO)
7918 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7919
7920 /* generic HDLC layer open processing */
7921 if ((rc = hdlc_open(dev)))
7922 return rc;
7923
7924 /* arbitrate between network and tty opens */
7925 spin_lock_irqsave(&info->netlock, flags);
7926 if (info->count != 0 || info->netcount != 0) {
7927 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7928 spin_unlock_irqrestore(&info->netlock, flags);
7929 return -EBUSY;
7930 }
7931 info->netcount=1;
7932 spin_unlock_irqrestore(&info->netlock, flags);
7933
7934 /* claim resources and init adapter */
7935 if ((rc = startup(info)) != 0) {
7936 spin_lock_irqsave(&info->netlock, flags);
7937 info->netcount=0;
7938 spin_unlock_irqrestore(&info->netlock, flags);
7939 return rc;
7940 }
7941
7942 /* assert DTR and RTS, apply hardware settings */
7943 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7944 mgsl_program_hw(info);
7945
7946 /* enable network layer transmit */
7947 dev->trans_start = jiffies;
7948 netif_start_queue(dev);
7949
7950 /* inform generic HDLC layer of current DCD status */
7951 spin_lock_irqsave(&info->irq_spinlock, flags);
7952 usc_get_serial_signals(info);
7953 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7954 hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, dev);
7955
7956 return 0;
7957 }
7958
7959 /**
7960 * called by network layer when interface is disabled
7961 * shutdown hardware and release resources
7962 *
7963 * dev pointer to network device structure
7964 *
7965 * returns 0 if success, otherwise error code
7966 */
7967 static int hdlcdev_close(struct net_device *dev)
7968 {
7969 struct mgsl_struct *info = dev_to_port(dev);
7970 unsigned long flags;
7971
7972 if (debug_level >= DEBUG_LEVEL_INFO)
7973 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7974
7975 netif_stop_queue(dev);
7976
7977 /* shutdown adapter and release resources */
7978 shutdown(info);
7979
7980 hdlc_close(dev);
7981
7982 spin_lock_irqsave(&info->netlock, flags);
7983 info->netcount=0;
7984 spin_unlock_irqrestore(&info->netlock, flags);
7985
7986 return 0;
7987 }
7988
7989 /**
7990 * called by network layer to process IOCTL call to network device
7991 *
7992 * dev pointer to network device structure
7993 * ifr pointer to network interface request structure
7994 * cmd IOCTL command code
7995 *
7996 * returns 0 if success, otherwise error code
7997 */
7998 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7999 {
8000 const size_t size = sizeof(sync_serial_settings);
8001 sync_serial_settings new_line;
8002 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
8003 struct mgsl_struct *info = dev_to_port(dev);
8004 unsigned int flags;
8005
8006 if (debug_level >= DEBUG_LEVEL_INFO)
8007 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
8008
8009 /* return error if TTY interface open */
8010 if (info->count)
8011 return -EBUSY;
8012
8013 if (cmd != SIOCWANDEV)
8014 return hdlc_ioctl(dev, ifr, cmd);
8015
8016 switch(ifr->ifr_settings.type) {
8017 case IF_GET_IFACE: /* return current sync_serial_settings */
8018
8019 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
8020 if (ifr->ifr_settings.size < size) {
8021 ifr->ifr_settings.size = size; /* data size wanted */
8022 return -ENOBUFS;
8023 }
8024
8025 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
8026 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
8027 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
8028 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
8029
8030 switch (flags){
8031 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
8032 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
8033 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
8034 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
8035 default: new_line.clock_type = CLOCK_DEFAULT;
8036 }
8037
8038 new_line.clock_rate = info->params.clock_speed;
8039 new_line.loopback = info->params.loopback ? 1:0;
8040
8041 if (copy_to_user(line, &new_line, size))
8042 return -EFAULT;
8043 return 0;
8044
8045 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
8046
8047 if(!capable(CAP_NET_ADMIN))
8048 return -EPERM;
8049 if (copy_from_user(&new_line, line, size))
8050 return -EFAULT;
8051
8052 switch (new_line.clock_type)
8053 {
8054 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
8055 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
8056 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
8057 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
8058 case CLOCK_DEFAULT: flags = info->params.flags &
8059 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
8060 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
8061 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
8062 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
8063 default: return -EINVAL;
8064 }
8065
8066 if (new_line.loopback != 0 && new_line.loopback != 1)
8067 return -EINVAL;
8068
8069 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
8070 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
8071 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
8072 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
8073 info->params.flags |= flags;
8074
8075 info->params.loopback = new_line.loopback;
8076
8077 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
8078 info->params.clock_speed = new_line.clock_rate;
8079 else
8080 info->params.clock_speed = 0;
8081
8082 /* if network interface up, reprogram hardware */
8083 if (info->netcount)
8084 mgsl_program_hw(info);
8085 return 0;
8086
8087 default:
8088 return hdlc_ioctl(dev, ifr, cmd);
8089 }
8090 }
8091
8092 /**
8093 * called by network layer when transmit timeout is detected
8094 *
8095 * dev pointer to network device structure
8096 */
8097 static void hdlcdev_tx_timeout(struct net_device *dev)
8098 {
8099 struct mgsl_struct *info = dev_to_port(dev);
8100 struct net_device_stats *stats = hdlc_stats(dev);
8101 unsigned long flags;
8102
8103 if (debug_level >= DEBUG_LEVEL_INFO)
8104 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
8105
8106 stats->tx_errors++;
8107 stats->tx_aborted_errors++;
8108
8109 spin_lock_irqsave(&info->irq_spinlock,flags);
8110 usc_stop_transmitter(info);
8111 spin_unlock_irqrestore(&info->irq_spinlock,flags);
8112
8113 netif_wake_queue(dev);
8114 }
8115
8116 /**
8117 * called by device driver when transmit completes
8118 * reenable network layer transmit if stopped
8119 *
8120 * info pointer to device instance information
8121 */
8122 static void hdlcdev_tx_done(struct mgsl_struct *info)
8123 {
8124 if (netif_queue_stopped(info->netdev))
8125 netif_wake_queue(info->netdev);
8126 }
8127
8128 /**
8129 * called by device driver when frame received
8130 * pass frame to network layer
8131 *
8132 * info pointer to device instance information
8133 * buf pointer to buffer contianing frame data
8134 * size count of data bytes in buf
8135 */
8136 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
8137 {
8138 struct sk_buff *skb = dev_alloc_skb(size);
8139 struct net_device *dev = info->netdev;
8140 struct net_device_stats *stats = hdlc_stats(dev);
8141
8142 if (debug_level >= DEBUG_LEVEL_INFO)
8143 printk("hdlcdev_rx(%s)\n",dev->name);
8144
8145 if (skb == NULL) {
8146 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
8147 stats->rx_dropped++;
8148 return;
8149 }
8150
8151 memcpy(skb_put(skb, size),buf,size);
8152
8153 skb->dev = info->netdev;
8154 skb->mac.raw = skb->data;
8155 skb->protocol = hdlc_type_trans(skb, skb->dev);
8156
8157 stats->rx_packets++;
8158 stats->rx_bytes += size;
8159
8160 netif_rx(skb);
8161
8162 info->netdev->last_rx = jiffies;
8163 }
8164
8165 /**
8166 * called by device driver when adding device instance
8167 * do generic HDLC initialization
8168 *
8169 * info pointer to device instance information
8170 *
8171 * returns 0 if success, otherwise error code
8172 */
8173 static int hdlcdev_init(struct mgsl_struct *info)
8174 {
8175 int rc;
8176 struct net_device *dev;
8177 hdlc_device *hdlc;
8178
8179 /* allocate and initialize network and HDLC layer objects */
8180
8181 if (!(dev = alloc_hdlcdev(info))) {
8182 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8183 return -ENOMEM;
8184 }
8185
8186 /* for network layer reporting purposes only */
8187 dev->base_addr = info->io_base;
8188 dev->irq = info->irq_level;
8189 dev->dma = info->dma_level;
8190
8191 /* network layer callbacks and settings */
8192 dev->do_ioctl = hdlcdev_ioctl;
8193 dev->open = hdlcdev_open;
8194 dev->stop = hdlcdev_close;
8195 dev->tx_timeout = hdlcdev_tx_timeout;
8196 dev->watchdog_timeo = 10*HZ;
8197 dev->tx_queue_len = 50;
8198
8199 /* generic HDLC layer callbacks and settings */
8200 hdlc = dev_to_hdlc(dev);
8201 hdlc->attach = hdlcdev_attach;
8202 hdlc->xmit = hdlcdev_xmit;
8203
8204 /* register objects with HDLC layer */
8205 if ((rc = register_hdlc_device(dev))) {
8206 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8207 free_netdev(dev);
8208 return rc;
8209 }
8210
8211 info->netdev = dev;
8212 return 0;
8213 }
8214
8215 /**
8216 * called by device driver when removing device instance
8217 * do generic HDLC cleanup
8218 *
8219 * info pointer to device instance information
8220 */
8221 static void hdlcdev_exit(struct mgsl_struct *info)
8222 {
8223 unregister_hdlc_device(info->netdev);
8224 free_netdev(info->netdev);
8225 info->netdev = NULL;
8226 }
8227
8228 #endif /* CONFIG_HDLC */
8229
8230
8231 static int __devinit synclink_init_one (struct pci_dev *dev,
8232 const struct pci_device_id *ent)
8233 {
8234 struct mgsl_struct *info;
8235
8236 if (pci_enable_device(dev)) {
8237 printk("error enabling pci device %p\n", dev);
8238 return -EIO;
8239 }
8240
8241 if (!(info = mgsl_allocate_device())) {
8242 printk("can't allocate device instance data.\n");
8243 return -EIO;
8244 }
8245
8246 /* Copy user configuration info to device instance data */
8247
8248 info->io_base = pci_resource_start(dev, 2);
8249 info->irq_level = dev->irq;
8250 info->phys_memory_base = pci_resource_start(dev, 3);
8251
8252 /* Because veremap only works on page boundaries we must map
8253 * a larger area than is actually implemented for the LCR
8254 * memory range. We map a full page starting at the page boundary.
8255 */
8256 info->phys_lcr_base = pci_resource_start(dev, 0);
8257 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8258 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8259
8260 info->bus_type = MGSL_BUS_TYPE_PCI;
8261 info->io_addr_size = 8;
8262 info->irq_flags = SA_SHIRQ;
8263
8264 if (dev->device == 0x0210) {
8265 /* Version 1 PCI9030 based universal PCI adapter */
8266 info->misc_ctrl_value = 0x007c4080;
8267 info->hw_version = 1;
8268 } else {
8269 /* Version 0 PCI9050 based 5V PCI adapter
8270 * A PCI9050 bug prevents reading LCR registers if
8271 * LCR base address bit 7 is set. Maintain shadow
8272 * value so we can write to LCR misc control reg.
8273 */
8274 info->misc_ctrl_value = 0x087e4546;
8275 info->hw_version = 0;
8276 }
8277
8278 mgsl_add_device(info);
8279
8280 return 0;
8281 }
8282
8283 static void __devexit synclink_remove_one (struct pci_dev *dev)
8284 {
8285 }
8286
MOXA 2.6.9 from sdlinux-moxaart.tgz