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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / sound / oss / i810_audio.c
blob47e5bed02bb0715911be378d3b58833acfd4deac
1 /*
2 * Intel i810 and friends ICH driver for Linux
3 * Alan Cox <alan@redhat.com>
4 *
5 * Built from:
6 * Low level code: Zach Brown (original nonworking i810 OSS driver)
7 * Jaroslav Kysela <perex@suse.cz> (working ALSA driver)
8 *
9 * Framework: Thomas Sailer <sailer@ife.ee.ethz.ch>
10 * Extended by: Zach Brown <zab@redhat.com>
11 * and others..
12 *
13 * Hardware Provided By:
14 * Analog Devices (A major AC97 codec maker)
15 * Intel Corp (you've probably heard of them already)
16 *
17 * AC97 clues and assistance provided by
18 * Analog Devices
19 * Zach 'Fufu' Brown
20 * Jeff Garzik
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License as published by
24 * the Free Software Foundation; either version 2 of the License, or
25 * (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
31 *
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
35 *
36 *
37 * Intel 810 theory of operation
38 *
39 * The chipset provides three DMA channels that talk to an AC97
40 * CODEC (AC97 is a digital/analog mixer standard). At its simplest
41 * you get 48Khz audio with basic volume and mixer controls. At the
42 * best you get rate adaption in the codec. We set the card up so
43 * that we never take completion interrupts but instead keep the card
44 * chasing its tail around a ring buffer. This is needed for mmap
45 * mode audio and happens to work rather well for non-mmap modes too.
46 *
47 * The board has one output channel for PCM audio (supported) and
48 * a stereo line in and mono microphone input. Again these are normally
49 * locked to 48Khz only. Right now recording is not finished.
50 *
51 * There is no midi support, no synth support. Use timidity. To get
52 * esd working you need to use esd -r 48000 as it won't probe 48KHz
53 * by default. mpg123 can't handle 48Khz only audio so use xmms.
54 *
55 * Fix The Sound On Dell
56 *
57 * Not everyone uses 48KHz. We know of no way to detect this reliably
58 * and certainly not to get the right data. If your i810 audio sounds
59 * stupid you may need to investigate other speeds. According to Analog
60 * they tend to use a 14.318MHz clock which gives you a base rate of
61 * 41194Hz.
62 *
63 * This is available via the 'ftsodell=1' option.
64 *
65 * If you need to force a specific rate set the clocking= option
66 *
67 * This driver is cursed. (Ben LaHaise)
68 *
69 * ICH 3 caveats
70 * Intel errata #7 for ICH3 IO. We need to disable SMI stuff
71 * when codec probing. [Not Yet Done]
72 *
73 * ICH 4 caveats
74 *
75 * The ICH4 has the feature, that the codec ID doesn't have to be
76 * congruent with the IO connection.
77 *
78 * Therefore, from driver version 0.23 on, there is a "codec ID" <->
79 * "IO register base offset" mapping (card->ac97_id_map) field.
80 *
81 * Juergen "George" Sawinski (jsaw)
82 */
83
84 #include <linux/module.h>
85 #include <linux/string.h>
86 #include <linux/ctype.h>
87 #include <linux/ioport.h>
88 #include <linux/sched.h>
89 #include <linux/delay.h>
90 #include <linux/sound.h>
91 #include <linux/slab.h>
92 #include <linux/soundcard.h>
93 #include <linux/pci.h>
94 #include <linux/interrupt.h>
95 #include <asm/io.h>
96 #include <asm/dma.h>
97 #include <linux/init.h>
98 #include <linux/poll.h>
99 #include <linux/spinlock.h>
100 #include <linux/smp_lock.h>
101 #include <linux/ac97_codec.h>
102 #include <linux/bitops.h>
103 #include <asm/uaccess.h>
104
105 #define DRIVER_VERSION "1.01"
106
107 #define MODULOP2(a, b) ((a) & ((b) - 1))
108 #define MASKP2(a, b) ((a) & ~((b) - 1))
109
110 static int ftsodell;
111 static int strict_clocking;
112 static unsigned int clocking;
113 static int spdif_locked;
114
115 //#define DEBUG
116 //#define DEBUG2
117 //#define DEBUG_INTERRUPTS
118 //#define DEBUG_MMAP
119 //#define DEBUG_MMIO
120
121 #define ADC_RUNNING 1
122 #define DAC_RUNNING 2
123
124 #define I810_FMT_16BIT 1
125 #define I810_FMT_STEREO 2
126 #define I810_FMT_MASK 3
127
128 #define SPDIF_ON 0x0004
129 #define SURR_ON 0x0010
130 #define CENTER_LFE_ON 0x0020
131 #define VOL_MUTED 0x8000
132
133 /* the 810's array of pointers to data buffers */
134
135 struct sg_item {
136 #define BUSADDR_MASK 0xFFFFFFFE
137 u32 busaddr;
138 #define CON_IOC 0x80000000 /* interrupt on completion */
139 #define CON_BUFPAD 0x40000000 /* pad underrun with last sample, else 0 */
140 #define CON_BUFLEN_MASK 0x0000ffff /* buffer length in samples */
141 u32 control;
142 };
143
144 /* an instance of the i810 channel */
145 #define SG_LEN 32
146 struct i810_channel
147 {
148 /* these sg guys should probably be allocated
149 separately as nocache. Must be 8 byte aligned */
150 struct sg_item sg[SG_LEN]; /* 32*8 */
151 u32 offset; /* 4 */
152 u32 port; /* 4 */
153 u32 used;
154 u32 num;
155 };
156
157 /*
158 * we have 3 separate dma engines. pcm in, pcm out, and mic.
159 * each dma engine has controlling registers. These goofy
160 * names are from the datasheet, but make it easy to write
161 * code while leafing through it.
162 *
163 * ICH4 has 6 dma engines, pcm in, pcm out, mic, pcm in 2,
164 * mic in 2, s/pdif. Of special interest is the fact that
165 * the upper 3 DMA engines on the ICH4 *must* be accessed
166 * via mmio access instead of pio access.
167 */
168
169 #define ENUM_ENGINE(PRE,DIG) \
170 enum { \
171 PRE##_BASE = 0x##DIG##0, /* Base Address */ \
172 PRE##_BDBAR = 0x##DIG##0, /* Buffer Descriptor list Base Address */ \
173 PRE##_CIV = 0x##DIG##4, /* Current Index Value */ \
174 PRE##_LVI = 0x##DIG##5, /* Last Valid Index */ \
175 PRE##_SR = 0x##DIG##6, /* Status Register */ \
176 PRE##_PICB = 0x##DIG##8, /* Position In Current Buffer */ \
177 PRE##_PIV = 0x##DIG##a, /* Prefetched Index Value */ \
178 PRE##_CR = 0x##DIG##b /* Control Register */ \
179 }
180
181 ENUM_ENGINE(OFF,0); /* Offsets */
182 ENUM_ENGINE(PI,0); /* PCM In */
183 ENUM_ENGINE(PO,1); /* PCM Out */
184 ENUM_ENGINE(MC,2); /* Mic In */
185
186 enum {
187 GLOB_CNT = 0x2c, /* Global Control */
188 GLOB_STA = 0x30, /* Global Status */
189 CAS = 0x34 /* Codec Write Semaphore Register */
190 };
191
192 ENUM_ENGINE(MC2,4); /* Mic In 2 */
193 ENUM_ENGINE(PI2,5); /* PCM In 2 */
194 ENUM_ENGINE(SP,6); /* S/PDIF */
195
196 enum {
197 SDM = 0x80 /* SDATA_IN Map Register */
198 };
199
200 /* interrupts for a dma engine */
201 #define DMA_INT_FIFO (1<<4) /* fifo under/over flow */
202 #define DMA_INT_COMPLETE (1<<3) /* buffer read/write complete and ioc set */
203 #define DMA_INT_LVI (1<<2) /* last valid done */
204 #define DMA_INT_CELV (1<<1) /* last valid is current */
205 #define DMA_INT_DCH (1) /* DMA Controller Halted (happens on LVI interrupts) */
206 #define DMA_INT_MASK (DMA_INT_FIFO|DMA_INT_COMPLETE|DMA_INT_LVI)
207
208 /* interrupts for the whole chip */
209 #define INT_SEC (1<<11)
210 #define INT_PRI (1<<10)
211 #define INT_MC (1<<7)
212 #define INT_PO (1<<6)
213 #define INT_PI (1<<5)
214 #define INT_MO (1<<2)
215 #define INT_NI (1<<1)
216 #define INT_GPI (1<<0)
217 #define INT_MASK (INT_SEC|INT_PRI|INT_MC|INT_PO|INT_PI|INT_MO|INT_NI|INT_GPI)
218
219 /* magic numbers to protect our data structures */
220 #define I810_CARD_MAGIC 0x5072696E /* "Prin" */
221 #define I810_STATE_MAGIC 0x63657373 /* "cess" */
222 #define I810_DMA_MASK 0xffffffff /* DMA buffer mask for pci_alloc_consist */
223 #define NR_HW_CH 3
224
225 /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */
226 #define NR_AC97 4
227
228 /* Please note that an 8bit mono stream is not valid on this card, you must have a 16bit */
229 /* stream at a minimum for this card to be happy */
230 static const unsigned sample_size[] = { 1, 2, 2, 4 };
231 /* Samples are 16bit values, so we are shifting to a word, not to a byte, hence shift */
232 /* values are one less than might be expected */
233 static const unsigned sample_shift[] = { -1, 0, 0, 1 };
234
235 enum {
236 ICH82801AA = 0,
237 ICH82901AB,
238 INTEL440MX,
239 INTELICH2,
240 INTELICH3,
241 INTELICH4,
242 INTELICH5,
243 SI7012,
244 NVIDIA_NFORCE,
245 AMD768,
246 AMD8111
247 };
248
249 static char * card_names[] = {
250 "Intel ICH 82801AA",
251 "Intel ICH 82901AB",
252 "Intel 440MX",
253 "Intel ICH2",
254 "Intel ICH3",
255 "Intel ICH4",
256 "Intel ICH5",
257 "SiS 7012",
258 "NVIDIA nForce Audio",
259 "AMD 768",
260 "AMD-8111 IOHub"
261 };
262
263 /* These are capabilities (and bugs) the chipsets _can_ have */
264 static struct {
265 int16_t nr_ac97;
266 #define CAP_MMIO 0x0001
267 #define CAP_20BIT_AUDIO_SUPPORT 0x0002
268 u_int16_t flags;
269 } card_cap[] = {
270 { 1, 0x0000 }, /* ICH82801AA */
271 { 1, 0x0000 }, /* ICH82901AB */
272 { 1, 0x0000 }, /* INTEL440MX */
273 { 1, 0x0000 }, /* INTELICH2 */
274 { 2, 0x0000 }, /* INTELICH3 */
275 { 3, 0x0003 }, /* INTELICH4 */
276 { 3, 0x0003 }, /* INTELICH5 */
277 /*@FIXME to be verified*/ { 2, 0x0000 }, /* SI7012 */
278 /*@FIXME to be verified*/ { 2, 0x0000 }, /* NVIDIA_NFORCE */
279 /*@FIXME to be verified*/ { 2, 0x0000 }, /* AMD768 */
280 /*@FIXME to be verified*/ { 3, 0x0001 }, /* AMD8111 */
281 };
282
283 static struct pci_device_id i810_pci_tbl [] = {
284 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_5,
285 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82801AA},
286 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_5,
287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82901AB},
288 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_440MX,
289 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTEL440MX},
290 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_4,
291 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH2},
292 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_5,
293 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH3},
294 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_5,
295 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
296 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_5,
297 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH5},
298 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_7012,
299 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SI7012},
300 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO,
301 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
302 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO,
303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
304 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO,
305 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
306 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7445,
307 PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD768},
308 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_AUDIO,
309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD8111},
310 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_5,
311 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
312 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_18,
313 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
314
315 {0,}
316 };
317
318 MODULE_DEVICE_TABLE (pci, i810_pci_tbl);
319
320 #ifdef CONFIG_PM
321 #define PM_SUSPENDED(card) (card->pm_suspended)
322 #else
323 #define PM_SUSPENDED(card) (0)
324 #endif
325
326 /* "software" or virtual channel, an instance of opened /dev/dsp */
327 struct i810_state {
328 unsigned int magic;
329 struct i810_card *card; /* Card info */
330
331 /* single open lock mechanism, only used for recording */
332 struct semaphore open_sem;
333 wait_queue_head_t open_wait;
334
335 /* file mode */
336 mode_t open_mode;
337
338 /* virtual channel number */
339 int virt;
340
341 #ifdef CONFIG_PM
342 unsigned int pm_saved_dac_rate,pm_saved_adc_rate;
343 #endif
344 struct dmabuf {
345 /* wave sample stuff */
346 unsigned int rate;
347 unsigned char fmt, enable, trigger;
348
349 /* hardware channel */
350 struct i810_channel *read_channel;
351 struct i810_channel *write_channel;
352
353 /* OSS buffer management stuff */
354 void *rawbuf;
355 dma_addr_t dma_handle;
356 unsigned buforder;
357 unsigned numfrag;
358 unsigned fragshift;
359
360 /* our buffer acts like a circular ring */
361 unsigned hwptr; /* where dma last started, updated by update_ptr */
362 unsigned swptr; /* where driver last clear/filled, updated by read/write */
363 int count; /* bytes to be consumed or been generated by dma machine */
364 unsigned total_bytes; /* total bytes dmaed by hardware */
365
366 unsigned error; /* number of over/underruns */
367 wait_queue_head_t wait; /* put process on wait queue when no more space in buffer */
368
369 /* redundant, but makes calculations easier */
370 /* what the hardware uses */
371 unsigned dmasize;
372 unsigned fragsize;
373 unsigned fragsamples;
374
375 /* what we tell the user to expect */
376 unsigned userfrags;
377 unsigned userfragsize;
378
379 /* OSS stuff */
380 unsigned mapped:1;
381 unsigned ready:1;
382 unsigned update_flag;
383 unsigned ossfragsize;
384 unsigned ossmaxfrags;
385 unsigned subdivision;
386 } dmabuf;
387 };
388
389
390 struct i810_card {
391 unsigned int magic;
392
393 /* We keep i810 cards in a linked list */
394 struct i810_card *next;
395
396 /* The i810 has a certain amount of cross channel interaction
397 so we use a single per card lock */
398 spinlock_t lock;
399
400 /* Control AC97 access serialization */
401 spinlock_t ac97_lock;
402
403 /* PCI device stuff */
404 struct pci_dev * pci_dev;
405 u16 pci_id;
406 u16 pci_id_internal; /* used to access card_cap[] */
407 #ifdef CONFIG_PM
408 u16 pm_suspended;
409 u32 pm_save_state[64/sizeof(u32)];
410 int pm_saved_mixer_settings[SOUND_MIXER_NRDEVICES][NR_AC97];
411 #endif
412 /* soundcore stuff */
413 int dev_audio;
414
415 /* structures for abstraction of hardware facilities, codecs, banks and channels*/
416 u16 ac97_id_map[NR_AC97];
417 struct ac97_codec *ac97_codec[NR_AC97];
418 struct i810_state *states[NR_HW_CH];
419 struct i810_channel *channel; /* 1:1 to states[] but diff. lifetime */
420 dma_addr_t chandma;
421
422 u16 ac97_features;
423 u16 ac97_status;
424 u16 channels;
425
426 /* hardware resources */
427 unsigned long ac97base;
428 unsigned long iobase;
429 u32 irq;
430
431 unsigned long ac97base_mmio_phys;
432 unsigned long iobase_mmio_phys;
433 u_int8_t *ac97base_mmio;
434 u_int8_t *iobase_mmio;
435
436 int use_mmio;
437
438 /* Function support */
439 struct i810_channel *(*alloc_pcm_channel)(struct i810_card *);
440 struct i810_channel *(*alloc_rec_pcm_channel)(struct i810_card *);
441 struct i810_channel *(*alloc_rec_mic_channel)(struct i810_card *);
442 void (*free_pcm_channel)(struct i810_card *, int chan);
443
444 /* We have a *very* long init time possibly, so use this to block */
445 /* attempts to open our devices before we are ready (stops oops'es) */
446 int initializing;
447 };
448
449 /* extract register offset from codec struct */
450 #define IO_REG_OFF(codec) (((struct i810_card *) codec->private_data)->ac97_id_map[codec->id])
451
452 #define I810_IOREAD(size, type, card, off) \
453 ({ \
454 type val; \
455 if (card->use_mmio) \
456 val=read##size(card->iobase_mmio+off); \
457 else \
458 val=in##size(card->iobase+off); \
459 val; \
460 })
461
462 #define I810_IOREADL(card, off) I810_IOREAD(l, u32, card, off)
463 #define I810_IOREADW(card, off) I810_IOREAD(w, u16, card, off)
464 #define I810_IOREADB(card, off) I810_IOREAD(b, u8, card, off)
465
466 #define I810_IOWRITE(size, val, card, off) \
467 ({ \
468 if (card->use_mmio) \
469 write##size(val, card->iobase_mmio+off); \
470 else \
471 out##size(val, card->iobase+off); \
472 })
473
474 #define I810_IOWRITEL(val, card, off) I810_IOWRITE(l, val, card, off)
475 #define I810_IOWRITEW(val, card, off) I810_IOWRITE(w, val, card, off)
476 #define I810_IOWRITEB(val, card, off) I810_IOWRITE(b, val, card, off)
477
478 #define GET_CIV(card, port) MODULOP2(I810_IOREADB((card), (port) + OFF_CIV), SG_LEN)
479 #define GET_LVI(card, port) MODULOP2(I810_IOREADB((card), (port) + OFF_LVI), SG_LEN)
480
481 /* set LVI from CIV */
482 #define CIV_TO_LVI(card, port, off) \
483 I810_IOWRITEB(MODULOP2(GET_CIV((card), (port)) + (off), SG_LEN), (card), (port) + OFF_LVI)
484
485 static struct i810_card *devs = NULL;
486
487 static int i810_open_mixdev(struct inode *inode, struct file *file);
488 static int i810_ioctl_mixdev(struct inode *inode, struct file *file,
489 unsigned int cmd, unsigned long arg);
490 static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg);
491 static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data);
492 static u16 i810_ac97_get_mmio(struct ac97_codec *dev, u8 reg);
493 static void i810_ac97_set_mmio(struct ac97_codec *dev, u8 reg, u16 data);
494 static u16 i810_ac97_get_io(struct ac97_codec *dev, u8 reg);
495 static void i810_ac97_set_io(struct ac97_codec *dev, u8 reg, u16 data);
496
497 static struct i810_channel *i810_alloc_pcm_channel(struct i810_card *card)
498 {
499 if(card->channel[1].used==1)
500 return NULL;
501 card->channel[1].used=1;
502 return &card->channel[1];
503 }
504
505 static struct i810_channel *i810_alloc_rec_pcm_channel(struct i810_card *card)
506 {
507 if(card->channel[0].used==1)
508 return NULL;
509 card->channel[0].used=1;
510 return &card->channel[0];
511 }
512
513 static struct i810_channel *i810_alloc_rec_mic_channel(struct i810_card *card)
514 {
515 if(card->channel[2].used==1)
516 return NULL;
517 card->channel[2].used=1;
518 return &card->channel[2];
519 }
520
521 static void i810_free_pcm_channel(struct i810_card *card, int channel)
522 {
523 card->channel[channel].used=0;
524 }
525
526 static int i810_valid_spdif_rate ( struct ac97_codec *codec, int rate )
527 {
528 unsigned long id = 0L;
529
530 id = (i810_ac97_get(codec, AC97_VENDOR_ID1) << 16);
531 id |= i810_ac97_get(codec, AC97_VENDOR_ID2) & 0xffff;
532 #ifdef DEBUG
533 printk ( "i810_audio: codec = %s, codec_id = 0x%08lx\n", codec->name, id);
534 #endif
535 switch ( id ) {
536 case 0x41445361: /* AD1886 */
537 if (rate == 48000) {
538 return 1;
539 }
540 break;
541 default: /* all other codecs, until we know otherwiae */
542 if (rate == 48000 || rate == 44100 || rate == 32000) {
543 return 1;
544 }
545 break;
546 }
547 return (0);
548 }
549
550 /* i810_set_spdif_output
551 *
552 * Configure the S/PDIF output transmitter. When we turn on
553 * S/PDIF, we turn off the analog output. This may not be
554 * the right thing to do.
555 *
556 * Assumptions:
557 * The DSP sample rate must already be set to a supported
558 * S/PDIF rate (32kHz, 44.1kHz, or 48kHz) or we abort.
559 */
560 static int i810_set_spdif_output(struct i810_state *state, int slots, int rate)
561 {
562 int vol;
563 int aud_reg;
564 int r = 0;
565 struct ac97_codec *codec = state->card->ac97_codec[0];
566
567 if(!codec->codec_ops->digital) {
568 state->card->ac97_status &= ~SPDIF_ON;
569 } else {
570 if ( slots == -1 ) { /* Turn off S/PDIF */
571 codec->codec_ops->digital(codec, 0, 0, 0);
572 /* If the volume wasn't muted before we turned on S/PDIF, unmute it */
573 if ( !(state->card->ac97_status & VOL_MUTED) ) {
574 aud_reg = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO);
575 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (aud_reg & ~VOL_MUTED));
576 }
577 state->card->ac97_status &= ~(VOL_MUTED | SPDIF_ON);
578 return 0;
579 }
580
581 vol = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO);
582 state->card->ac97_status = vol & VOL_MUTED;
583
584 r = codec->codec_ops->digital(codec, slots, rate, 0);
585
586 if(r)
587 state->card->ac97_status |= SPDIF_ON;
588 else
589 state->card->ac97_status &= ~SPDIF_ON;
590
591 /* Mute the analog output */
592 /* Should this only mute the PCM volume??? */
593 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (vol | VOL_MUTED));
594 }
595 return r;
596 }
597
598 /* i810_set_dac_channels
599 *
600 * Configure the codec's multi-channel DACs
601 *
602 * The logic is backwards. Setting the bit to 1 turns off the DAC.
603 *
604 * What about the ICH? We currently configure it using the
605 * SNDCTL_DSP_CHANNELS ioctl. If we're turnning on the DAC,
606 * does that imply that we want the ICH set to support
607 * these channels?
608 *
609 * TODO:
610 * vailidate that the codec really supports these DACs
611 * before turning them on.
612 */
613 static void i810_set_dac_channels(struct i810_state *state, int channel)
614 {
615 int aud_reg;
616 struct ac97_codec *codec = state->card->ac97_codec[0];
617
618 /* No codec, no setup */
619
620 if(codec == NULL)
621 return;
622
623 aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS);
624 aud_reg |= AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK;
625 state->card->ac97_status &= ~(SURR_ON | CENTER_LFE_ON);
626
627 switch ( channel ) {
628 case 2: /* always enabled */
629 break;
630 case 4:
631 aud_reg &= ~AC97_EA_PRJ;
632 state->card->ac97_status |= SURR_ON;
633 break;
634 case 6:
635 aud_reg &= ~(AC97_EA_PRJ | AC97_EA_PRI | AC97_EA_PRK);
636 state->card->ac97_status |= SURR_ON | CENTER_LFE_ON;
637 break;
638 default:
639 break;
640 }
641 i810_ac97_set(codec, AC97_EXTENDED_STATUS, aud_reg);
642
643 }
644
645
646 /* set playback sample rate */
647 static unsigned int i810_set_dac_rate(struct i810_state * state, unsigned int rate)
648 {
649 struct dmabuf *dmabuf = &state->dmabuf;
650 u32 new_rate;
651 struct ac97_codec *codec=state->card->ac97_codec[0];
652
653 if(!(state->card->ac97_features&0x0001))
654 {
655 dmabuf->rate = clocking;
656 #ifdef DEBUG
657 printk("Asked for %d Hz, but ac97_features says we only do %dHz. Sorry!\n",
658 rate,clocking);
659 #endif
660 return clocking;
661 }
662
663 if (rate > 48000)
664 rate = 48000;
665 if (rate < 8000)
666 rate = 8000;
667 dmabuf->rate = rate;
668
669 /*
670 * Adjust for misclocked crap
671 */
672 rate = ( rate * clocking)/48000;
673 if(strict_clocking && rate < 8000) {
674 rate = 8000;
675 dmabuf->rate = (rate * 48000)/clocking;
676 }
677
678 new_rate=ac97_set_dac_rate(codec, rate);
679 if(new_rate != rate) {
680 dmabuf->rate = (new_rate * 48000)/clocking;
681 }
682 #ifdef DEBUG
683 printk("i810_audio: called i810_set_dac_rate : asked for %d, got %d\n", rate, dmabuf->rate);
684 #endif
685 rate = new_rate;
686 return dmabuf->rate;
687 }
688
689 /* set recording sample rate */
690 static unsigned int i810_set_adc_rate(struct i810_state * state, unsigned int rate)
691 {
692 struct dmabuf *dmabuf = &state->dmabuf;
693 u32 new_rate;
694 struct ac97_codec *codec=state->card->ac97_codec[0];
695
696 if(!(state->card->ac97_features&0x0001))
697 {
698 dmabuf->rate = clocking;
699 return clocking;
700 }
701
702 if (rate > 48000)
703 rate = 48000;
704 if (rate < 8000)
705 rate = 8000;
706 dmabuf->rate = rate;
707
708 /*
709 * Adjust for misclocked crap
710 */
711
712 rate = ( rate * clocking)/48000;
713 if(strict_clocking && rate < 8000) {
714 rate = 8000;
715 dmabuf->rate = (rate * 48000)/clocking;
716 }
717
718 new_rate = ac97_set_adc_rate(codec, rate);
719
720 if(new_rate != rate) {
721 dmabuf->rate = (new_rate * 48000)/clocking;
722 rate = new_rate;
723 }
724 #ifdef DEBUG
725 printk("i810_audio: called i810_set_adc_rate : rate = %d/%d\n", dmabuf->rate, rate);
726 #endif
727 return dmabuf->rate;
728 }
729
730 /* get current playback/recording dma buffer pointer (byte offset from LBA),
731 called with spinlock held! */
732
733 static inline unsigned i810_get_dma_addr(struct i810_state *state, int rec)
734 {
735 struct dmabuf *dmabuf = &state->dmabuf;
736 unsigned int civ, offset, port, port_picb, bytes = 2;
737
738 if (!dmabuf->enable)
739 return 0;
740
741 if (rec)
742 port = dmabuf->read_channel->port;
743 else
744 port = dmabuf->write_channel->port;
745
746 if(state->card->pci_id == PCI_DEVICE_ID_SI_7012) {
747 port_picb = port + OFF_SR;
748 bytes = 1;
749 } else
750 port_picb = port + OFF_PICB;
751
752 do {
753 civ = GET_CIV(state->card, port);
754 offset = I810_IOREADW(state->card, port_picb);
755 /* Must have a delay here! */
756 if(offset == 0)
757 udelay(1);
758 /* Reread both registers and make sure that that total
759 * offset from the first reading to the second is 0.
760 * There is an issue with SiS hardware where it will count
761 * picb down to 0, then update civ to the next value,
762 * then set the new picb to fragsize bytes. We can catch
763 * it between the civ update and the picb update, making
764 * it look as though we are 1 fragsize ahead of where we
765 * are. The next to we get the address though, it will
766 * be back in the right place, and we will suddenly think
767 * we just went forward dmasize - fragsize bytes, causing
768 * totally stupid *huge* dma overrun messages. We are
769 * assuming that the 1us delay is more than long enough
770 * that we won't have to worry about the chip still being
771 * out of sync with reality ;-)
772 */
773 } while (civ != GET_CIV(state->card, port) || offset != I810_IOREADW(state->card, port_picb));
774
775 return (((civ + 1) * dmabuf->fragsize - (bytes * offset))
776 % dmabuf->dmasize);
777 }
778
779 /* Stop recording (lock held) */
780 static inline void __stop_adc(struct i810_state *state)
781 {
782 struct dmabuf *dmabuf = &state->dmabuf;
783 struct i810_card *card = state->card;
784
785 dmabuf->enable &= ~ADC_RUNNING;
786 I810_IOWRITEB(0, card, PI_CR);
787 // wait for the card to acknowledge shutdown
788 while( I810_IOREADB(card, PI_CR) != 0 ) ;
789 // now clear any latent interrupt bits (like the halt bit)
790 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
791 I810_IOWRITEB( I810_IOREADB(card, PI_PICB), card, PI_PICB );
792 else
793 I810_IOWRITEB( I810_IOREADB(card, PI_SR), card, PI_SR );
794 I810_IOWRITEL( I810_IOREADL(card, GLOB_STA) & INT_PI, card, GLOB_STA);
795 }
796
797 static void stop_adc(struct i810_state *state)
798 {
799 struct i810_card *card = state->card;
800 unsigned long flags;
801
802 spin_lock_irqsave(&card->lock, flags);
803 __stop_adc(state);
804 spin_unlock_irqrestore(&card->lock, flags);
805 }
806
807 static inline void __start_adc(struct i810_state *state)
808 {
809 struct dmabuf *dmabuf = &state->dmabuf;
810
811 if (dmabuf->count < dmabuf->dmasize && dmabuf->ready && !dmabuf->enable &&
812 (dmabuf->trigger & PCM_ENABLE_INPUT)) {
813 dmabuf->enable |= ADC_RUNNING;
814 // Interrupt enable, LVI enable, DMA enable
815 I810_IOWRITEB(0x10 | 0x04 | 0x01, state->card, PI_CR);
816 }
817 }
818
819 static void start_adc(struct i810_state *state)
820 {
821 struct i810_card *card = state->card;
822 unsigned long flags;
823
824 spin_lock_irqsave(&card->lock, flags);
825 __start_adc(state);
826 spin_unlock_irqrestore(&card->lock, flags);
827 }
828
829 /* stop playback (lock held) */
830 static inline void __stop_dac(struct i810_state *state)
831 {
832 struct dmabuf *dmabuf = &state->dmabuf;
833 struct i810_card *card = state->card;
834
835 dmabuf->enable &= ~DAC_RUNNING;
836 I810_IOWRITEB(0, card, PO_CR);
837 // wait for the card to acknowledge shutdown
838 while( I810_IOREADB(card, PO_CR) != 0 ) ;
839 // now clear any latent interrupt bits (like the halt bit)
840 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
841 I810_IOWRITEB( I810_IOREADB(card, PO_PICB), card, PO_PICB );
842 else
843 I810_IOWRITEB( I810_IOREADB(card, PO_SR), card, PO_SR );
844 I810_IOWRITEL( I810_IOREADL(card, GLOB_STA) & INT_PO, card, GLOB_STA);
845 }
846
847 static void stop_dac(struct i810_state *state)
848 {
849 struct i810_card *card = state->card;
850 unsigned long flags;
851
852 spin_lock_irqsave(&card->lock, flags);
853 __stop_dac(state);
854 spin_unlock_irqrestore(&card->lock, flags);
855 }
856
857 static inline void __start_dac(struct i810_state *state)
858 {
859 struct dmabuf *dmabuf = &state->dmabuf;
860
861 if (dmabuf->count > 0 && dmabuf->ready && !dmabuf->enable &&
862 (dmabuf->trigger & PCM_ENABLE_OUTPUT)) {
863 dmabuf->enable |= DAC_RUNNING;
864 // Interrupt enable, LVI enable, DMA enable
865 I810_IOWRITEB(0x10 | 0x04 | 0x01, state->card, PO_CR);
866 }
867 }
868 static void start_dac(struct i810_state *state)
869 {
870 struct i810_card *card = state->card;
871 unsigned long flags;
872
873 spin_lock_irqsave(&card->lock, flags);
874 __start_dac(state);
875 spin_unlock_irqrestore(&card->lock, flags);
876 }
877
878 #define DMABUF_DEFAULTORDER (16-PAGE_SHIFT)
879 #define DMABUF_MINORDER 1
880
881 /* allocate DMA buffer, playback and recording buffer should be allocated separately */
882 static int alloc_dmabuf(struct i810_state *state)
883 {
884 struct dmabuf *dmabuf = &state->dmabuf;
885 void *rawbuf= NULL;
886 int order, size;
887 struct page *page, *pend;
888
889 /* If we don't have any oss frag params, then use our default ones */
890 if(dmabuf->ossmaxfrags == 0)
891 dmabuf->ossmaxfrags = 4;
892 if(dmabuf->ossfragsize == 0)
893 dmabuf->ossfragsize = (PAGE_SIZE<<DMABUF_DEFAULTORDER)/dmabuf->ossmaxfrags;
894 size = dmabuf->ossfragsize * dmabuf->ossmaxfrags;
895
896 if(dmabuf->rawbuf && (PAGE_SIZE << dmabuf->buforder) == size)
897 return 0;
898 /* alloc enough to satisfy the oss params */
899 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--) {
900 if ( (PAGE_SIZE<<order) > size )
901 continue;
902 if ((rawbuf = pci_alloc_consistent(state->card->pci_dev,
903 PAGE_SIZE << order,
904 &dmabuf->dma_handle)))
905 break;
906 }
907 if (!rawbuf)
908 return -ENOMEM;
909
910
911 #ifdef DEBUG
912 printk("i810_audio: allocated %ld (order = %d) bytes at %p\n",
913 PAGE_SIZE << order, order, rawbuf);
914 #endif
915
916 dmabuf->ready = dmabuf->mapped = 0;
917 dmabuf->rawbuf = rawbuf;
918 dmabuf->buforder = order;
919
920 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
921 pend = virt_to_page(rawbuf + (PAGE_SIZE << order) - 1);
922 for (page = virt_to_page(rawbuf); page <= pend; page++)
923 SetPageReserved(page);
924
925 return 0;
926 }
927
928 /* free DMA buffer */
929 static void dealloc_dmabuf(struct i810_state *state)
930 {
931 struct dmabuf *dmabuf = &state->dmabuf;
932 struct page *page, *pend;
933
934 if (dmabuf->rawbuf) {
935 /* undo marking the pages as reserved */
936 pend = virt_to_page(dmabuf->rawbuf + (PAGE_SIZE << dmabuf->buforder) - 1);
937 for (page = virt_to_page(dmabuf->rawbuf); page <= pend; page++)
938 ClearPageReserved(page);
939 pci_free_consistent(state->card->pci_dev, PAGE_SIZE << dmabuf->buforder,
940 dmabuf->rawbuf, dmabuf->dma_handle);
941 }
942 dmabuf->rawbuf = NULL;
943 dmabuf->mapped = dmabuf->ready = 0;
944 }
945
946 static int prog_dmabuf(struct i810_state *state, unsigned rec)
947 {
948 struct dmabuf *dmabuf = &state->dmabuf;
949 struct i810_channel *c;
950 struct sg_item *sg;
951 unsigned long flags;
952 int ret;
953 unsigned fragint;
954 int i;
955
956 spin_lock_irqsave(&state->card->lock, flags);
957 if(dmabuf->enable & DAC_RUNNING)
958 __stop_dac(state);
959 if(dmabuf->enable & ADC_RUNNING)
960 __stop_adc(state);
961 dmabuf->total_bytes = 0;
962 dmabuf->count = dmabuf->error = 0;
963 dmabuf->swptr = dmabuf->hwptr = 0;
964 spin_unlock_irqrestore(&state->card->lock, flags);
965
966 /* allocate DMA buffer, let alloc_dmabuf determine if we are already
967 * allocated well enough or if we should replace the current buffer
968 * (assuming one is already allocated, if it isn't, then allocate it).
969 */
970 if ((ret = alloc_dmabuf(state)))
971 return ret;
972
973 /* FIXME: figure out all this OSS fragment stuff */
974 /* I did, it now does what it should according to the OSS API. DL */
975 /* We may not have realloced our dmabuf, but the fragment size to
976 * fragment number ratio may have changed, so go ahead and reprogram
977 * things
978 */
979 dmabuf->dmasize = PAGE_SIZE << dmabuf->buforder;
980 dmabuf->numfrag = SG_LEN;
981 dmabuf->fragsize = dmabuf->dmasize/dmabuf->numfrag;
982 dmabuf->fragsamples = dmabuf->fragsize >> 1;
983 dmabuf->fragshift = ffs(dmabuf->fragsize) - 1;
984 dmabuf->userfragsize = dmabuf->ossfragsize;
985 dmabuf->userfrags = dmabuf->dmasize/dmabuf->ossfragsize;
986
987 memset(dmabuf->rawbuf, 0, dmabuf->dmasize);
988
989 if(dmabuf->ossmaxfrags == 4) {
990 fragint = 8;
991 } else if (dmabuf->ossmaxfrags == 8) {
992 fragint = 4;
993 } else if (dmabuf->ossmaxfrags == 16) {
994 fragint = 2;
995 } else {
996 fragint = 1;
997 }
998 /*
999 * Now set up the ring
1000 */
1001 if(dmabuf->read_channel)
1002 c = dmabuf->read_channel;
1003 else
1004 c = dmabuf->write_channel;
1005 while(c != NULL) {
1006 sg=&c->sg[0];
1007 /*
1008 * Load up 32 sg entries and take an interrupt at half
1009 * way (we might want more interrupts later..)
1010 */
1011
1012 for(i=0;i<dmabuf->numfrag;i++)
1013 {
1014 sg->busaddr=(u32)dmabuf->dma_handle+dmabuf->fragsize*i;
1015 // the card will always be doing 16bit stereo
1016 sg->control=dmabuf->fragsamples;
1017 if(state->card->pci_id == PCI_DEVICE_ID_SI_7012)
1018 sg->control <<= 1;
1019 sg->control|=CON_BUFPAD;
1020 // set us up to get IOC interrupts as often as needed to
1021 // satisfy numfrag requirements, no more
1022 if( ((i+1) % fragint) == 0) {
1023 sg->control|=CON_IOC;
1024 }
1025 sg++;
1026 }
1027 spin_lock_irqsave(&state->card->lock, flags);
1028 I810_IOWRITEB(2, state->card, c->port+OFF_CR); /* reset DMA machine */
1029 while( I810_IOREADB(state->card, c->port+OFF_CR) & 0x02 ) ;
1030 I810_IOWRITEL((u32)state->card->chandma +
1031 c->num*sizeof(struct i810_channel),
1032 state->card, c->port+OFF_BDBAR);
1033 CIV_TO_LVI(state->card, c->port, 0);
1034
1035 spin_unlock_irqrestore(&state->card->lock, flags);
1036
1037 if(c != dmabuf->write_channel)
1038 c = dmabuf->write_channel;
1039 else
1040 c = NULL;
1041 }
1042
1043 /* set the ready flag for the dma buffer */
1044 dmabuf->ready = 1;
1045
1046 #ifdef DEBUG
1047 printk("i810_audio: prog_dmabuf, sample rate = %d, format = %d,\n\tnumfrag = %d, "
1048 "fragsize = %d dmasize = %d\n",
1049 dmabuf->rate, dmabuf->fmt, dmabuf->numfrag,
1050 dmabuf->fragsize, dmabuf->dmasize);
1051 #endif
1052
1053 return 0;
1054 }
1055
1056 static void __i810_update_lvi(struct i810_state *state, int rec)
1057 {
1058 struct dmabuf *dmabuf = &state->dmabuf;
1059 int x, port;
1060 int trigger;
1061 int count, fragsize;
1062 void (*start)(struct i810_state *);
1063
1064 count = dmabuf->count;
1065 if (rec) {
1066 port = dmabuf->read_channel->port;
1067 trigger = PCM_ENABLE_INPUT;
1068 start = __start_adc;
1069 count = dmabuf->dmasize - count;
1070 } else {
1071 port = dmabuf->write_channel->port;
1072 trigger = PCM_ENABLE_OUTPUT;
1073 start = __start_dac;
1074 }
1075
1076 /* Do not process partial fragments. */
1077 fragsize = dmabuf->fragsize;
1078 if (count < fragsize)
1079 return;
1080
1081 if (!dmabuf->enable && dmabuf->ready) {
1082 if (!(dmabuf->trigger & trigger))
1083 return;
1084
1085 start(state);
1086 while (!(I810_IOREADB(state->card, port + OFF_CR) & ((1<<4) | (1<<2))))
1087 ;
1088 }
1089
1090 /* MASKP2(swptr, fragsize) - 1 is the tail of our transfer */
1091 x = MODULOP2(MASKP2(dmabuf->swptr, fragsize) - 1, dmabuf->dmasize);
1092 x >>= dmabuf->fragshift;
1093 I810_IOWRITEB(x, state->card, port + OFF_LVI);
1094 }
1095
1096 static void i810_update_lvi(struct i810_state *state, int rec)
1097 {
1098 struct dmabuf *dmabuf = &state->dmabuf;
1099 unsigned long flags;
1100
1101 if(!dmabuf->ready)
1102 return;
1103 spin_lock_irqsave(&state->card->lock, flags);
1104 __i810_update_lvi(state, rec);
1105 spin_unlock_irqrestore(&state->card->lock, flags);
1106 }
1107
1108 /* update buffer manangement pointers, especially, dmabuf->count and dmabuf->hwptr */
1109 static void i810_update_ptr(struct i810_state *state)
1110 {
1111 struct dmabuf *dmabuf = &state->dmabuf;
1112 unsigned hwptr;
1113 unsigned fragmask, dmamask;
1114 int diff;
1115
1116 fragmask = MASKP2(~0, dmabuf->fragsize);
1117 dmamask = MODULOP2(~0, dmabuf->dmasize);
1118
1119 /* error handling and process wake up for ADC */
1120 if (dmabuf->enable == ADC_RUNNING) {
1121 /* update hardware pointer */
1122 hwptr = i810_get_dma_addr(state, 1) & fragmask;
1123 diff = (hwptr - dmabuf->hwptr) & dmamask;
1124 #if defined(DEBUG_INTERRUPTS) || defined(DEBUG_MMAP)
1125 printk("ADC HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff);
1126 #endif
1127 dmabuf->hwptr = hwptr;
1128 dmabuf->total_bytes += diff;
1129 dmabuf->count += diff;
1130 if (dmabuf->count > dmabuf->dmasize) {
1131 /* buffer underrun or buffer overrun */
1132 /* this is normal for the end of a read */
1133 /* only give an error if we went past the */
1134 /* last valid sg entry */
1135 if (GET_CIV(state->card, PI_BASE) !=
1136 GET_LVI(state->card, PI_BASE)) {
1137 printk(KERN_WARNING "i810_audio: DMA overrun on read\n");
1138 dmabuf->error++;
1139 }
1140 }
1141 if (diff)
1142 wake_up(&dmabuf->wait);
1143 }
1144 /* error handling and process wake up for DAC */
1145 if (dmabuf->enable == DAC_RUNNING) {
1146 /* update hardware pointer */
1147 hwptr = i810_get_dma_addr(state, 0) & fragmask;
1148 diff = (hwptr - dmabuf->hwptr) & dmamask;
1149 #if defined(DEBUG_INTERRUPTS) || defined(DEBUG_MMAP)
1150 printk("DAC HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff);
1151 #endif
1152 dmabuf->hwptr = hwptr;
1153 dmabuf->total_bytes += diff;
1154 dmabuf->count -= diff;
1155 if (dmabuf->count < 0) {
1156 /* buffer underrun or buffer overrun */
1157 /* this is normal for the end of a write */
1158 /* only give an error if we went past the */
1159 /* last valid sg entry */
1160 if (GET_CIV(state->card, PO_BASE) !=
1161 GET_LVI(state->card, PO_BASE)) {
1162 printk(KERN_WARNING "i810_audio: DMA overrun on write\n");
1163 printk("i810_audio: CIV %d, LVI %d, hwptr %x, "
1164 "count %d\n",
1165 GET_CIV(state->card, PO_BASE),
1166 GET_LVI(state->card, PO_BASE),
1167 dmabuf->hwptr, dmabuf->count);
1168 dmabuf->error++;
1169 }
1170 }
1171 if (diff)
1172 wake_up(&dmabuf->wait);
1173 }
1174 }
1175
1176 static inline int i810_get_free_write_space(struct i810_state *state)
1177 {
1178 struct dmabuf *dmabuf = &state->dmabuf;
1179 int free;
1180
1181 i810_update_ptr(state);
1182 // catch underruns during playback
1183 if (dmabuf->count < 0) {
1184 dmabuf->count = 0;
1185 dmabuf->swptr = dmabuf->hwptr;
1186 }
1187 free = dmabuf->dmasize - dmabuf->count;
1188 if(free < 0)
1189 return(0);
1190 return(free);
1191 }
1192
1193 static inline int i810_get_available_read_data(struct i810_state *state)
1194 {
1195 struct dmabuf *dmabuf = &state->dmabuf;
1196 int avail;
1197
1198 i810_update_ptr(state);
1199 // catch overruns during record
1200 if (dmabuf->count > dmabuf->dmasize) {
1201 dmabuf->count = dmabuf->dmasize;
1202 dmabuf->swptr = dmabuf->hwptr;
1203 }
1204 avail = dmabuf->count;
1205 if(avail < 0)
1206 return(0);
1207 return(avail);
1208 }
1209
1210 static inline void fill_partial_frag(struct dmabuf *dmabuf)
1211 {
1212 unsigned fragsize;
1213 unsigned swptr, len;
1214
1215 fragsize = dmabuf->fragsize;
1216 swptr = dmabuf->swptr;
1217 len = fragsize - MODULOP2(dmabuf->swptr, fragsize);
1218 if (len == fragsize)
1219 return;
1220
1221 memset(dmabuf->rawbuf + swptr, '\0', len);
1222 dmabuf->swptr = MODULOP2(swptr + len, dmabuf->dmasize);
1223 dmabuf->count += len;
1224 }
1225
1226 static int drain_dac(struct i810_state *state, int signals_allowed)
1227 {
1228 DECLARE_WAITQUEUE(wait, current);
1229 struct dmabuf *dmabuf = &state->dmabuf;
1230 unsigned long flags;
1231 unsigned long tmo;
1232 int count;
1233
1234 if (!dmabuf->ready)
1235 return 0;
1236 if(dmabuf->mapped) {
1237 stop_dac(state);
1238 return 0;
1239 }
1240
1241 spin_lock_irqsave(&state->card->lock, flags);
1242
1243 fill_partial_frag(dmabuf);
1244
1245 /*
1246 * This will make sure that our LVI is correct, that our
1247 * pointer is updated, and that the DAC is running. We
1248 * have to force the setting of dmabuf->trigger to avoid
1249 * any possible deadlocks.
1250 */
1251 dmabuf->trigger = PCM_ENABLE_OUTPUT;
1252 __i810_update_lvi(state, 0);
1253
1254 spin_unlock_irqrestore(&state->card->lock, flags);
1255
1256 add_wait_queue(&dmabuf->wait, &wait);
1257 for (;;) {
1258
1259 spin_lock_irqsave(&state->card->lock, flags);
1260 i810_update_ptr(state);
1261 count = dmabuf->count;
1262
1263 /* It seems that we have to set the current state to
1264 * TASK_INTERRUPTIBLE every time to make the process
1265 * really go to sleep. This also has to be *after* the
1266 * update_ptr() call because update_ptr is likely to
1267 * do a wake_up() which will unset this before we ever
1268 * try to sleep, resuling in a tight loop in this code
1269 * instead of actually sleeping and waiting for an
1270 * interrupt to wake us up!
1271 */
1272 __set_current_state(signals_allowed ?
1273 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1274 spin_unlock_irqrestore(&state->card->lock, flags);
1275
1276 if (count <= 0)
1277 break;
1278
1279 if (signal_pending(current) && signals_allowed) {
1280 break;
1281 }
1282
1283 /*
1284 * set the timeout to significantly longer than it *should*
1285 * take for the DAC to drain the DMA buffer
1286 */
1287 tmo = (count * HZ) / (dmabuf->rate);
1288 if (!schedule_timeout(tmo >= 2 ? tmo : 2)){
1289 printk(KERN_ERR "i810_audio: drain_dac, dma timeout?\n");
1290 count = 0;
1291 break;
1292 }
1293 }
1294 set_current_state(TASK_RUNNING);
1295 remove_wait_queue(&dmabuf->wait, &wait);
1296 if(count > 0 && signal_pending(current) && signals_allowed)
1297 return -ERESTARTSYS;
1298 stop_dac(state);
1299 return 0;
1300 }
1301
1302 static void i810_channel_interrupt(struct i810_card *card)
1303 {
1304 int i, count;
1305
1306 #ifdef DEBUG_INTERRUPTS
1307 printk("CHANNEL ");
1308 #endif
1309 for(i=0;i<NR_HW_CH;i++)
1310 {
1311 struct i810_state *state = card->states[i];
1312 struct i810_channel *c;
1313 struct dmabuf *dmabuf;
1314 unsigned long port;
1315 u16 status;
1316
1317 if(!state)
1318 continue;
1319 if(!state->dmabuf.ready)
1320 continue;
1321 dmabuf = &state->dmabuf;
1322 if(dmabuf->enable & DAC_RUNNING) {
1323 c=dmabuf->write_channel;
1324 } else if(dmabuf->enable & ADC_RUNNING) {
1325 c=dmabuf->read_channel;
1326 } else /* This can occur going from R/W to close */
1327 continue;
1328
1329 port = c->port;
1330
1331 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
1332 status = I810_IOREADW(card, port + OFF_PICB);
1333 else
1334 status = I810_IOREADW(card, port + OFF_SR);
1335
1336 #ifdef DEBUG_INTERRUPTS
1337 printk("NUM %d PORT %X IRQ ( ST%d ", c->num, c->port, status);
1338 #endif
1339 if(status & DMA_INT_COMPLETE)
1340 {
1341 /* only wake_up() waiters if this interrupt signals
1342 * us being beyond a userfragsize of data open or
1343 * available, and i810_update_ptr() does that for
1344 * us
1345 */
1346 i810_update_ptr(state);
1347 #ifdef DEBUG_INTERRUPTS
1348 printk("COMP %d ", dmabuf->hwptr /
1349 dmabuf->fragsize);
1350 #endif
1351 }
1352 if(status & (DMA_INT_LVI | DMA_INT_DCH))
1353 {
1354 /* wake_up() unconditionally on LVI and DCH */
1355 i810_update_ptr(state);
1356 wake_up(&dmabuf->wait);
1357 #ifdef DEBUG_INTERRUPTS
1358 if(status & DMA_INT_LVI)
1359 printk("LVI ");
1360 if(status & DMA_INT_DCH)
1361 printk("DCH -");
1362 #endif
1363 count = dmabuf->count;
1364 if(dmabuf->enable & ADC_RUNNING)
1365 count = dmabuf->dmasize - count;
1366 if (count >= (int)dmabuf->fragsize) {
1367 I810_IOWRITEB(I810_IOREADB(card, port+OFF_CR) | 1, card, port+OFF_CR);
1368 #ifdef DEBUG_INTERRUPTS
1369 printk(" CONTINUE ");
1370 #endif
1371 } else {
1372 if (dmabuf->enable & DAC_RUNNING)
1373 __stop_dac(state);
1374 if (dmabuf->enable & ADC_RUNNING)
1375 __stop_adc(state);
1376 dmabuf->enable = 0;
1377 #ifdef DEBUG_INTERRUPTS
1378 printk(" STOP ");
1379 #endif
1380 }
1381 }
1382 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
1383 I810_IOWRITEW(status & DMA_INT_MASK, card, port + OFF_PICB);
1384 else
1385 I810_IOWRITEW(status & DMA_INT_MASK, card, port + OFF_SR);
1386 }
1387 #ifdef DEBUG_INTERRUPTS
1388 printk(")\n");
1389 #endif
1390 }
1391
1392 static irqreturn_t i810_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1393 {
1394 struct i810_card *card = (struct i810_card *)dev_id;
1395 u32 status;
1396
1397 spin_lock(&card->lock);
1398
1399 status = I810_IOREADL(card, GLOB_STA);
1400
1401 if(!(status & INT_MASK))
1402 {
1403 spin_unlock(&card->lock);
1404 return IRQ_NONE; /* not for us */
1405 }
1406
1407 if(status & (INT_PO|INT_PI|INT_MC))
1408 i810_channel_interrupt(card);
1409
1410 /* clear 'em */
1411 I810_IOWRITEL(status & INT_MASK, card, GLOB_STA);
1412 spin_unlock(&card->lock);
1413 return IRQ_HANDLED;
1414 }
1415
1416 /* in this loop, dmabuf.count signifies the amount of data that is
1417 waiting to be copied to the user's buffer. It is filled by the dma
1418 machine and drained by this loop. */
1419
1420 static ssize_t i810_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1421 {
1422 struct i810_state *state = (struct i810_state *)file->private_data;
1423 struct i810_card *card=state ? state->card : NULL;
1424 struct dmabuf *dmabuf = &state->dmabuf;
1425 ssize_t ret;
1426 unsigned long flags;
1427 unsigned int swptr;
1428 int cnt;
1429 int pending;
1430 DECLARE_WAITQUEUE(waita, current);
1431
1432 #ifdef DEBUG2
1433 printk("i810_audio: i810_read called, count = %d\n", count);
1434 #endif
1435
1436 if (dmabuf->mapped)
1437 return -ENXIO;
1438 if (dmabuf->enable & DAC_RUNNING)
1439 return -ENODEV;
1440 if (!dmabuf->read_channel) {
1441 dmabuf->ready = 0;
1442 dmabuf->read_channel = card->alloc_rec_pcm_channel(card);
1443 if (!dmabuf->read_channel) {
1444 return -EBUSY;
1445 }
1446 }
1447 if (!dmabuf->ready && (ret = prog_dmabuf(state, 1)))
1448 return ret;
1449 if (!access_ok(VERIFY_WRITE, buffer, count))
1450 return -EFAULT;
1451 ret = 0;
1452
1453 pending = 0;
1454
1455 add_wait_queue(&dmabuf->wait, &waita);
1456 while (count > 0) {
1457 set_current_state(TASK_INTERRUPTIBLE);
1458 spin_lock_irqsave(&card->lock, flags);
1459 if (PM_SUSPENDED(card)) {
1460 spin_unlock_irqrestore(&card->lock, flags);
1461 schedule();
1462 if (signal_pending(current)) {
1463 if (!ret) ret = -EAGAIN;
1464 break;
1465 }
1466 continue;
1467 }
1468 cnt = i810_get_available_read_data(state);
1469 swptr = dmabuf->swptr;
1470 // this is to make the copy_to_user simpler below
1471 if(cnt > (dmabuf->dmasize - swptr))
1472 cnt = dmabuf->dmasize - swptr;
1473 spin_unlock_irqrestore(&card->lock, flags);
1474
1475 if (cnt > count)
1476 cnt = count;
1477 if (cnt <= 0) {
1478 unsigned long tmo;
1479 /*
1480 * Don't let us deadlock. The ADC won't start if
1481 * dmabuf->trigger isn't set. A call to SETTRIGGER
1482 * could have turned it off after we set it to on
1483 * previously.
1484 */
1485 dmabuf->trigger = PCM_ENABLE_INPUT;
1486 /*
1487 * This does three things. Updates LVI to be correct,
1488 * makes sure the ADC is running, and updates the
1489 * hwptr.
1490 */
1491 i810_update_lvi(state,1);
1492 if (file->f_flags & O_NONBLOCK) {
1493 if (!ret) ret = -EAGAIN;
1494 goto done;
1495 }
1496 /* Set the timeout to how long it would take to fill
1497 * two of our buffers. If we haven't been woke up
1498 * by then, then we know something is wrong.
1499 */
1500 tmo = (dmabuf->dmasize * HZ * 2) / (dmabuf->rate * 4);
1501 /* There are two situations when sleep_on_timeout returns, one is when
1502 the interrupt is serviced correctly and the process is waked up by
1503 ISR ON TIME. Another is when timeout is expired, which means that
1504 either interrupt is NOT serviced correctly (pending interrupt) or it
1505 is TOO LATE for the process to be scheduled to run (scheduler latency)
1506 which results in a (potential) buffer overrun. And worse, there is
1507 NOTHING we can do to prevent it. */
1508 if (!schedule_timeout(tmo >= 2 ? tmo : 2)) {
1509 #ifdef DEBUG
1510 printk(KERN_ERR "i810_audio: recording schedule timeout, "
1511 "dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1512 dmabuf->dmasize, dmabuf->fragsize, dmabuf->count,
1513 dmabuf->hwptr, dmabuf->swptr);
1514 #endif
1515 /* a buffer overrun, we delay the recovery until next time the
1516 while loop begin and we REALLY have space to record */
1517 }
1518 if (signal_pending(current)) {
1519 ret = ret ? ret : -ERESTARTSYS;
1520 goto done;
1521 }
1522 continue;
1523 }
1524
1525 if (copy_to_user(buffer, dmabuf->rawbuf + swptr, cnt)) {
1526 if (!ret) ret = -EFAULT;
1527 goto done;
1528 }
1529
1530 swptr = MODULOP2(swptr + cnt, dmabuf->dmasize);
1531
1532 spin_lock_irqsave(&card->lock, flags);
1533
1534 if (PM_SUSPENDED(card)) {
1535 spin_unlock_irqrestore(&card->lock, flags);
1536 continue;
1537 }
1538 dmabuf->swptr = swptr;
1539 pending = dmabuf->count -= cnt;
1540 spin_unlock_irqrestore(&card->lock, flags);
1541
1542 count -= cnt;
1543 buffer += cnt;
1544 ret += cnt;
1545 }
1546 done:
1547 pending = dmabuf->dmasize - pending;
1548 if (dmabuf->enable || pending >= dmabuf->userfragsize)
1549 i810_update_lvi(state, 1);
1550 set_current_state(TASK_RUNNING);
1551 remove_wait_queue(&dmabuf->wait, &waita);
1552
1553 return ret;
1554 }
1555
1556 /* in this loop, dmabuf.count signifies the amount of data that is waiting to be dma to
1557 the soundcard. it is drained by the dma machine and filled by this loop. */
1558 static ssize_t i810_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1559 {
1560 struct i810_state *state = (struct i810_state *)file->private_data;
1561 struct i810_card *card=state ? state->card : NULL;
1562 struct dmabuf *dmabuf = &state->dmabuf;
1563 ssize_t ret;
1564 unsigned long flags;
1565 unsigned int swptr = 0;
1566 int pending;
1567 int cnt;
1568 DECLARE_WAITQUEUE(waita, current);
1569
1570 #ifdef DEBUG2
1571 printk("i810_audio: i810_write called, count = %d\n", count);
1572 #endif
1573
1574 if (dmabuf->mapped)
1575 return -ENXIO;
1576 if (dmabuf->enable & ADC_RUNNING)
1577 return -ENODEV;
1578 if (!dmabuf->write_channel) {
1579 dmabuf->ready = 0;
1580 dmabuf->write_channel = card->alloc_pcm_channel(card);
1581 if(!dmabuf->write_channel)
1582 return -EBUSY;
1583 }
1584 if (!dmabuf->ready && (ret = prog_dmabuf(state, 0)))
1585 return ret;
1586 if (!access_ok(VERIFY_READ, buffer, count))
1587 return -EFAULT;
1588 ret = 0;
1589
1590 pending = 0;
1591
1592 add_wait_queue(&dmabuf->wait, &waita);
1593 while (count > 0) {
1594 set_current_state(TASK_INTERRUPTIBLE);
1595 spin_lock_irqsave(&state->card->lock, flags);
1596 if (PM_SUSPENDED(card)) {
1597 spin_unlock_irqrestore(&card->lock, flags);
1598 schedule();
1599 if (signal_pending(current)) {
1600 if (!ret) ret = -EAGAIN;
1601 break;
1602 }
1603 continue;
1604 }
1605
1606 cnt = i810_get_free_write_space(state);
1607 swptr = dmabuf->swptr;
1608 /* Bound the maximum size to how much we can copy to the
1609 * dma buffer before we hit the end. If we have more to
1610 * copy then it will get done in a second pass of this
1611 * loop starting from the beginning of the buffer.
1612 */
1613 if(cnt > (dmabuf->dmasize - swptr))
1614 cnt = dmabuf->dmasize - swptr;
1615 spin_unlock_irqrestore(&state->card->lock, flags);
1616
1617 #ifdef DEBUG2
1618 printk(KERN_INFO "i810_audio: i810_write: %d bytes available space\n", cnt);
1619 #endif
1620 if (cnt > count)
1621 cnt = count;
1622 if (cnt <= 0) {
1623 unsigned long tmo;
1624 // There is data waiting to be played
1625 /*
1626 * Force the trigger setting since we would
1627 * deadlock with it set any other way
1628 */
1629 dmabuf->trigger = PCM_ENABLE_OUTPUT;
1630 i810_update_lvi(state,0);
1631 if (file->f_flags & O_NONBLOCK) {
1632 if (!ret) ret = -EAGAIN;
1633 goto ret;
1634 }
1635 /* Not strictly correct but works */
1636 tmo = (dmabuf->dmasize * HZ * 2) / (dmabuf->rate * 4);
1637 /* There are two situations when sleep_on_timeout returns, one is when
1638 the interrupt is serviced correctly and the process is waked up by
1639 ISR ON TIME. Another is when timeout is expired, which means that
1640 either interrupt is NOT serviced correctly (pending interrupt) or it
1641 is TOO LATE for the process to be scheduled to run (scheduler latency)
1642 which results in a (potential) buffer underrun. And worse, there is
1643 NOTHING we can do to prevent it. */
1644 if (!schedule_timeout(tmo >= 2 ? tmo : 2)) {
1645 #ifdef DEBUG
1646 printk(KERN_ERR "i810_audio: playback schedule timeout, "
1647 "dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1648 dmabuf->dmasize, dmabuf->fragsize, dmabuf->count,
1649 dmabuf->hwptr, dmabuf->swptr);
1650 #endif
1651 /* a buffer underrun, we delay the recovery until next time the
1652 while loop begin and we REALLY have data to play */
1653 //return ret;
1654 }
1655 if (signal_pending(current)) {
1656 if (!ret) ret = -ERESTARTSYS;
1657 goto ret;
1658 }
1659 continue;
1660 }
1661 if (copy_from_user(dmabuf->rawbuf+swptr,buffer,cnt)) {
1662 if (!ret) ret = -EFAULT;
1663 goto ret;
1664 }
1665
1666 swptr = MODULOP2(swptr + cnt, dmabuf->dmasize);
1667
1668 spin_lock_irqsave(&state->card->lock, flags);
1669 if (PM_SUSPENDED(card)) {
1670 spin_unlock_irqrestore(&card->lock, flags);
1671 continue;
1672 }
1673
1674 dmabuf->swptr = swptr;
1675 pending = dmabuf->count += cnt;
1676
1677 count -= cnt;
1678 buffer += cnt;
1679 ret += cnt;
1680 spin_unlock_irqrestore(&state->card->lock, flags);
1681 }
1682 ret:
1683 if (dmabuf->enable || pending >= dmabuf->userfragsize)
1684 i810_update_lvi(state, 0);
1685 set_current_state(TASK_RUNNING);
1686 remove_wait_queue(&dmabuf->wait, &waita);
1687
1688 return ret;
1689 }
1690
1691 /* No kernel lock - we have our own spinlock */
1692 static unsigned int i810_poll(struct file *file, struct poll_table_struct *wait)
1693 {
1694 struct i810_state *state = (struct i810_state *)file->private_data;
1695 struct dmabuf *dmabuf = &state->dmabuf;
1696 unsigned long flags;
1697 unsigned int mask = 0;
1698
1699 if(!dmabuf->ready)
1700 return 0;
1701 poll_wait(file, &dmabuf->wait, wait);
1702 spin_lock_irqsave(&state->card->lock, flags);
1703 if (dmabuf->enable & ADC_RUNNING ||
1704 dmabuf->trigger & PCM_ENABLE_INPUT) {
1705 if (i810_get_available_read_data(state) >=
1706 (signed)dmabuf->userfragsize)
1707 mask |= POLLIN | POLLRDNORM;
1708 }
1709 if (dmabuf->enable & DAC_RUNNING ||
1710 dmabuf->trigger & PCM_ENABLE_OUTPUT) {
1711 if (i810_get_free_write_space(state) >=
1712 (signed)dmabuf->userfragsize)
1713 mask |= POLLOUT | POLLWRNORM;
1714 }
1715 spin_unlock_irqrestore(&state->card->lock, flags);
1716 return mask;
1717 }
1718
1719 static int i810_mmap(struct file *file, struct vm_area_struct *vma)
1720 {
1721 struct i810_state *state = (struct i810_state *)file->private_data;
1722 struct dmabuf *dmabuf = &state->dmabuf;
1723 int ret = -EINVAL;
1724 unsigned long size;
1725
1726 lock_kernel();
1727 if (vma->vm_flags & VM_WRITE) {
1728 if (!dmabuf->write_channel &&
1729 (dmabuf->write_channel =
1730 state->card->alloc_pcm_channel(state->card)) == NULL) {
1731 ret = -EBUSY;
1732 goto out;
1733 }
1734 }
1735 if (vma->vm_flags & VM_READ) {
1736 if (!dmabuf->read_channel &&
1737 (dmabuf->read_channel =
1738 state->card->alloc_rec_pcm_channel(state->card)) == NULL) {
1739 ret = -EBUSY;
1740 goto out;
1741 }
1742 }
1743 if ((ret = prog_dmabuf(state, 0)) != 0)
1744 goto out;
1745
1746 ret = -EINVAL;
1747 if (vma->vm_pgoff != 0)
1748 goto out;
1749 size = vma->vm_end - vma->vm_start;
1750 if (size > (PAGE_SIZE << dmabuf->buforder))
1751 goto out;
1752 ret = -EAGAIN;
1753 if (remap_page_range(vma, vma->vm_start, virt_to_phys(dmabuf->rawbuf),
1754 size, vma->vm_page_prot))
1755 goto out;
1756 dmabuf->mapped = 1;
1757 dmabuf->trigger = 0;
1758 ret = 0;
1759 #ifdef DEBUG_MMAP
1760 printk("i810_audio: mmap'ed %ld bytes of data space\n", size);
1761 #endif
1762 out:
1763 unlock_kernel();
1764 return ret;
1765 }
1766
1767 static int i810_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1768 {
1769 struct i810_state *state = (struct i810_state *)file->private_data;
1770 struct i810_channel *c = NULL;
1771 struct dmabuf *dmabuf = &state->dmabuf;
1772 unsigned long flags;
1773 audio_buf_info abinfo;
1774 count_info cinfo;
1775 unsigned int i_glob_cnt;
1776 int val = 0, ret;
1777 struct ac97_codec *codec = state->card->ac97_codec[0];
1778 void __user *argp = (void __user *)arg;
1779 int __user *p = argp;
1780
1781 #ifdef DEBUG
1782 printk("i810_audio: i810_ioctl, arg=0x%x, cmd=", arg ? *p : 0);
1783 #endif
1784
1785 switch (cmd)
1786 {
1787 case OSS_GETVERSION:
1788 #ifdef DEBUG
1789 printk("OSS_GETVERSION\n");
1790 #endif
1791 return put_user(SOUND_VERSION, p);
1792
1793 case SNDCTL_DSP_RESET:
1794 #ifdef DEBUG
1795 printk("SNDCTL_DSP_RESET\n");
1796 #endif
1797 spin_lock_irqsave(&state->card->lock, flags);
1798 if (dmabuf->enable == DAC_RUNNING) {
1799 c = dmabuf->write_channel;
1800 __stop_dac(state);
1801 }
1802 if (dmabuf->enable == ADC_RUNNING) {
1803 c = dmabuf->read_channel;
1804 __stop_adc(state);
1805 }
1806 if (c != NULL) {
1807 I810_IOWRITEB(2, state->card, c->port+OFF_CR); /* reset DMA machine */
1808 while ( I810_IOREADB(state->card, c->port+OFF_CR) & 2 )
1809 cpu_relax();
1810 I810_IOWRITEL((u32)state->card->chandma +
1811 c->num*sizeof(struct i810_channel),
1812 state->card, c->port+OFF_BDBAR);
1813 CIV_TO_LVI(state->card, c->port, 0);
1814 }
1815
1816 spin_unlock_irqrestore(&state->card->lock, flags);
1817 synchronize_irq(state->card->pci_dev->irq);
1818 dmabuf->ready = 0;
1819 dmabuf->swptr = dmabuf->hwptr = 0;
1820 dmabuf->count = dmabuf->total_bytes = 0;
1821 return 0;
1822
1823 case SNDCTL_DSP_SYNC:
1824 #ifdef DEBUG
1825 printk("SNDCTL_DSP_SYNC\n");
1826 #endif
1827 if (dmabuf->enable != DAC_RUNNING || file->f_flags & O_NONBLOCK)
1828 return 0;
1829 if((val = drain_dac(state, 1)))
1830 return val;
1831 dmabuf->total_bytes = 0;
1832 return 0;
1833
1834 case SNDCTL_DSP_SPEED: /* set smaple rate */
1835 #ifdef DEBUG
1836 printk("SNDCTL_DSP_SPEED\n");
1837 #endif
1838 if (get_user(val, p))
1839 return -EFAULT;
1840 if (val >= 0) {
1841 if (file->f_mode & FMODE_WRITE) {
1842 if ( (state->card->ac97_status & SPDIF_ON) ) { /* S/PDIF Enabled */
1843 /* AD1886 only supports 48000, need to check that */
1844 if ( i810_valid_spdif_rate ( codec, val ) ) {
1845 /* Set DAC rate */
1846 i810_set_spdif_output ( state, -1, 0 );
1847 stop_dac(state);
1848 dmabuf->ready = 0;
1849 spin_lock_irqsave(&state->card->lock, flags);
1850 i810_set_dac_rate(state, val);
1851 spin_unlock_irqrestore(&state->card->lock, flags);
1852 /* Set S/PDIF transmitter rate. */
1853 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, val );
1854 if ( ! (state->card->ac97_status & SPDIF_ON) ) {
1855 val = dmabuf->rate;
1856 }
1857 } else { /* Not a valid rate for S/PDIF, ignore it */
1858 val = dmabuf->rate;
1859 }
1860 } else {
1861 stop_dac(state);
1862 dmabuf->ready = 0;
1863 spin_lock_irqsave(&state->card->lock, flags);
1864 i810_set_dac_rate(state, val);
1865 spin_unlock_irqrestore(&state->card->lock, flags);
1866 }
1867 }
1868 if (file->f_mode & FMODE_READ) {
1869 stop_adc(state);
1870 dmabuf->ready = 0;
1871 spin_lock_irqsave(&state->card->lock, flags);
1872 i810_set_adc_rate(state, val);
1873 spin_unlock_irqrestore(&state->card->lock, flags);
1874 }
1875 }
1876 return put_user(dmabuf->rate, p);
1877
1878 case SNDCTL_DSP_STEREO: /* set stereo or mono channel */
1879 #ifdef DEBUG
1880 printk("SNDCTL_DSP_STEREO\n");
1881 #endif
1882 if (dmabuf->enable & DAC_RUNNING) {
1883 stop_dac(state);
1884 }
1885 if (dmabuf->enable & ADC_RUNNING) {
1886 stop_adc(state);
1887 }
1888 return put_user(1, p);
1889
1890 case SNDCTL_DSP_GETBLKSIZE:
1891 if (file->f_mode & FMODE_WRITE) {
1892 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)))
1893 return val;
1894 }
1895 if (file->f_mode & FMODE_READ) {
1896 if (!dmabuf->ready && (val = prog_dmabuf(state, 1)))
1897 return val;
1898 }
1899 #ifdef DEBUG
1900 printk("SNDCTL_DSP_GETBLKSIZE %d\n", dmabuf->userfragsize);
1901 #endif
1902 return put_user(dmabuf->userfragsize, p);
1903
1904 case SNDCTL_DSP_GETFMTS: /* Returns a mask of supported sample format*/
1905 #ifdef DEBUG
1906 printk("SNDCTL_DSP_GETFMTS\n");
1907 #endif
1908 return put_user(AFMT_S16_LE, p);
1909
1910 case SNDCTL_DSP_SETFMT: /* Select sample format */
1911 #ifdef DEBUG
1912 printk("SNDCTL_DSP_SETFMT\n");
1913 #endif
1914 return put_user(AFMT_S16_LE, p);
1915
1916 case SNDCTL_DSP_CHANNELS:
1917 #ifdef DEBUG
1918 printk("SNDCTL_DSP_CHANNELS\n");
1919 #endif
1920 if (get_user(val, p))
1921 return -EFAULT;
1922
1923 if (val > 0) {
1924 if (dmabuf->enable & DAC_RUNNING) {
1925 stop_dac(state);
1926 }
1927 if (dmabuf->enable & ADC_RUNNING) {
1928 stop_adc(state);
1929 }
1930 } else {
1931 return put_user(state->card->channels, p);
1932 }
1933
1934 /* ICH and ICH0 only support 2 channels */
1935 if ( state->card->pci_id == PCI_DEVICE_ID_INTEL_82801AA_5
1936 || state->card->pci_id == PCI_DEVICE_ID_INTEL_82801AB_5)
1937 return put_user(2, p);
1938
1939 /* Multi-channel support was added with ICH2. Bits in */
1940 /* Global Status and Global Control register are now */
1941 /* used to indicate this. */
1942
1943 i_glob_cnt = I810_IOREADL(state->card, GLOB_CNT);
1944
1945 /* Current # of channels enabled */
1946 if ( i_glob_cnt & 0x0100000 )
1947 ret = 4;
1948 else if ( i_glob_cnt & 0x0200000 )
1949 ret = 6;
1950 else
1951 ret = 2;
1952
1953 switch ( val ) {
1954 case 2: /* 2 channels is always supported */
1955 I810_IOWRITEL(i_glob_cnt & 0xffcfffff,
1956 state->card, GLOB_CNT);
1957 /* Do we need to change mixer settings???? */
1958 break;
1959 case 4: /* Supported on some chipsets, better check first */
1960 if ( state->card->channels >= 4 ) {
1961 I810_IOWRITEL((i_glob_cnt & 0xffcfffff) | 0x100000,
1962 state->card, GLOB_CNT);
1963 /* Do we need to change mixer settings??? */
1964 } else {
1965 val = ret;
1966 }
1967 break;
1968 case 6: /* Supported on some chipsets, better check first */
1969 if ( state->card->channels >= 6 ) {
1970 I810_IOWRITEL((i_glob_cnt & 0xffcfffff) | 0x200000,
1971 state->card, GLOB_CNT);
1972 /* Do we need to change mixer settings??? */
1973 } else {
1974 val = ret;
1975 }
1976 break;
1977 default: /* nothing else is ever supported by the chipset */
1978 val = ret;
1979 break;
1980 }
1981
1982 return put_user(val, p);
1983
1984 case SNDCTL_DSP_POST: /* the user has sent all data and is notifying us */
1985 /* we update the swptr to the end of the last sg segment then return */
1986 #ifdef DEBUG
1987 printk("SNDCTL_DSP_POST\n");
1988 #endif
1989 if(!dmabuf->ready || (dmabuf->enable != DAC_RUNNING))
1990 return 0;
1991 if((dmabuf->swptr % dmabuf->fragsize) != 0) {
1992 val = dmabuf->fragsize - (dmabuf->swptr % dmabuf->fragsize);
1993 dmabuf->swptr += val;
1994 dmabuf->count += val;
1995 }
1996 return 0;
1997
1998 case SNDCTL_DSP_SUBDIVIDE:
1999 if (dmabuf->subdivision)
2000 return -EINVAL;
2001 if (get_user(val, p))
2002 return -EFAULT;
2003 if (val != 1 && val != 2 && val != 4)
2004 return -EINVAL;
2005 #ifdef DEBUG
2006 printk("SNDCTL_DSP_SUBDIVIDE %d\n", val);
2007 #endif
2008 dmabuf->subdivision = val;
2009 dmabuf->ready = 0;
2010 return 0;
2011
2012 case SNDCTL_DSP_SETFRAGMENT:
2013 if (get_user(val, p))
2014 return -EFAULT;
2015
2016 dmabuf->ossfragsize = 1<<(val & 0xffff);
2017 dmabuf->ossmaxfrags = (val >> 16) & 0xffff;
2018 if (!dmabuf->ossfragsize || !dmabuf->ossmaxfrags)
2019 return -EINVAL;
2020 /*
2021 * Bound the frag size into our allowed range of 256 - 4096
2022 */
2023 if (dmabuf->ossfragsize < 256)
2024 dmabuf->ossfragsize = 256;
2025 else if (dmabuf->ossfragsize > 4096)
2026 dmabuf->ossfragsize = 4096;
2027 /*
2028 * The numfrags could be something reasonable, or it could
2029 * be 0xffff meaning "Give me as much as possible". So,
2030 * we check the numfrags * fragsize doesn't exceed our
2031 * 64k buffer limit, nor is it less than our 8k minimum.
2032 * If it fails either one of these checks, then adjust the
2033 * number of fragments, not the size of them. It's OK if
2034 * our number of fragments doesn't equal 32 or anything
2035 * like our hardware based number now since we are using
2036 * a different frag count for the hardware. Before we get
2037 * into this though, bound the maxfrags to avoid overflow
2038 * issues. A reasonable bound would be 64k / 256 since our
2039 * maximum buffer size is 64k and our minimum frag size is
2040 * 256. On the other end, our minimum buffer size is 8k and
2041 * our maximum frag size is 4k, so the lower bound should
2042 * be 2.
2043 */
2044
2045 if(dmabuf->ossmaxfrags > 256)
2046 dmabuf->ossmaxfrags = 256;
2047 else if (dmabuf->ossmaxfrags < 2)
2048 dmabuf->ossmaxfrags = 2;
2049
2050 val = dmabuf->ossfragsize * dmabuf->ossmaxfrags;
2051 while (val < 8192) {
2052 val <<= 1;
2053 dmabuf->ossmaxfrags <<= 1;
2054 }
2055 while (val > 65536) {
2056 val >>= 1;
2057 dmabuf->ossmaxfrags >>= 1;
2058 }
2059 dmabuf->ready = 0;
2060 #ifdef DEBUG
2061 printk("SNDCTL_DSP_SETFRAGMENT 0x%x, %d, %d\n", val,
2062 dmabuf->ossfragsize, dmabuf->ossmaxfrags);
2063 #endif
2064
2065 return 0;
2066
2067 case SNDCTL_DSP_GETOSPACE:
2068 if (!(file->f_mode & FMODE_WRITE))
2069 return -EINVAL;
2070 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2071 return val;
2072 spin_lock_irqsave(&state->card->lock, flags);
2073 i810_update_ptr(state);
2074 abinfo.fragsize = dmabuf->userfragsize;
2075 abinfo.fragstotal = dmabuf->userfrags;
2076 if (dmabuf->mapped)
2077 abinfo.bytes = dmabuf->dmasize;
2078 else
2079 abinfo.bytes = i810_get_free_write_space(state);
2080 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize;
2081 spin_unlock_irqrestore(&state->card->lock, flags);
2082 #if defined(DEBUG) || defined(DEBUG_MMAP)
2083 printk("SNDCTL_DSP_GETOSPACE %d, %d, %d, %d\n", abinfo.bytes,
2084 abinfo.fragsize, abinfo.fragments, abinfo.fragstotal);
2085 #endif
2086 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2087
2088 case SNDCTL_DSP_GETOPTR:
2089 if (!(file->f_mode & FMODE_WRITE))
2090 return -EINVAL;
2091 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2092 return val;
2093 spin_lock_irqsave(&state->card->lock, flags);
2094 val = i810_get_free_write_space(state);
2095 cinfo.bytes = dmabuf->total_bytes;
2096 cinfo.ptr = dmabuf->hwptr;
2097 cinfo.blocks = val/dmabuf->userfragsize;
2098 if (dmabuf->mapped && (dmabuf->trigger & PCM_ENABLE_OUTPUT)) {
2099 dmabuf->count += val;
2100 dmabuf->swptr = (dmabuf->swptr + val) % dmabuf->dmasize;
2101 __i810_update_lvi(state, 0);
2102 }
2103 spin_unlock_irqrestore(&state->card->lock, flags);
2104 #if defined(DEBUG) || defined(DEBUG_MMAP)
2105 printk("SNDCTL_DSP_GETOPTR %d, %d, %d, %d\n", cinfo.bytes,
2106 cinfo.blocks, cinfo.ptr, dmabuf->count);
2107 #endif
2108 return copy_to_user(argp, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2109
2110 case SNDCTL_DSP_GETISPACE:
2111 if (!(file->f_mode & FMODE_READ))
2112 return -EINVAL;
2113 if (!dmabuf->ready && (val = prog_dmabuf(state, 1)) != 0)
2114 return val;
2115 spin_lock_irqsave(&state->card->lock, flags);
2116 abinfo.bytes = i810_get_available_read_data(state);
2117 abinfo.fragsize = dmabuf->userfragsize;
2118 abinfo.fragstotal = dmabuf->userfrags;
2119 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize;
2120 spin_unlock_irqrestore(&state->card->lock, flags);
2121 #if defined(DEBUG) || defined(DEBUG_MMAP)
2122 printk("SNDCTL_DSP_GETISPACE %d, %d, %d, %d\n", abinfo.bytes,
2123 abinfo.fragsize, abinfo.fragments, abinfo.fragstotal);
2124 #endif
2125 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2126
2127 case SNDCTL_DSP_GETIPTR:
2128 if (!(file->f_mode & FMODE_READ))
2129 return -EINVAL;
2130 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2131 return val;
2132 spin_lock_irqsave(&state->card->lock, flags);
2133 val = i810_get_available_read_data(state);
2134 cinfo.bytes = dmabuf->total_bytes;
2135 cinfo.blocks = val/dmabuf->userfragsize;
2136 cinfo.ptr = dmabuf->hwptr;
2137 if (dmabuf->mapped && (dmabuf->trigger & PCM_ENABLE_INPUT)) {
2138 dmabuf->count -= val;
2139 dmabuf->swptr = (dmabuf->swptr + val) % dmabuf->dmasize;
2140 __i810_update_lvi(state, 1);
2141 }
2142 spin_unlock_irqrestore(&state->card->lock, flags);
2143 #if defined(DEBUG) || defined(DEBUG_MMAP)
2144 printk("SNDCTL_DSP_GETIPTR %d, %d, %d, %d\n", cinfo.bytes,
2145 cinfo.blocks, cinfo.ptr, dmabuf->count);
2146 #endif
2147 return copy_to_user(argp, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2148
2149 case SNDCTL_DSP_NONBLOCK:
2150 #ifdef DEBUG
2151 printk("SNDCTL_DSP_NONBLOCK\n");
2152 #endif
2153 file->f_flags |= O_NONBLOCK;
2154 return 0;
2155
2156 case SNDCTL_DSP_GETCAPS:
2157 #ifdef DEBUG
2158 printk("SNDCTL_DSP_GETCAPS\n");
2159 #endif
2160 return put_user(DSP_CAP_REALTIME|DSP_CAP_TRIGGER|DSP_CAP_MMAP|DSP_CAP_BIND,
2161 p);
2162
2163 case SNDCTL_DSP_GETTRIGGER:
2164 val = 0;
2165 #ifdef DEBUG
2166 printk("SNDCTL_DSP_GETTRIGGER 0x%x\n", dmabuf->trigger);
2167 #endif
2168 return put_user(dmabuf->trigger, p);
2169
2170 case SNDCTL_DSP_SETTRIGGER:
2171 if (get_user(val, p))
2172 return -EFAULT;
2173 #if defined(DEBUG) || defined(DEBUG_MMAP)
2174 printk("SNDCTL_DSP_SETTRIGGER 0x%x\n", val);
2175 #endif
2176 /* silently ignore invalid PCM_ENABLE_xxx bits,
2177 * like the other drivers do
2178 */
2179 if (!(file->f_mode & FMODE_READ ))
2180 val &= ~PCM_ENABLE_INPUT;
2181 if (!(file->f_mode & FMODE_WRITE ))
2182 val &= ~PCM_ENABLE_OUTPUT;
2183 if((file->f_mode & FMODE_READ) && !(val & PCM_ENABLE_INPUT) && dmabuf->enable == ADC_RUNNING) {
2184 stop_adc(state);
2185 }
2186 if((file->f_mode & FMODE_WRITE) && !(val & PCM_ENABLE_OUTPUT) && dmabuf->enable == DAC_RUNNING) {
2187 stop_dac(state);
2188 }
2189 dmabuf->trigger = val;
2190 if((val & PCM_ENABLE_OUTPUT) && !(dmabuf->enable & DAC_RUNNING)) {
2191 if (!dmabuf->write_channel) {
2192 dmabuf->ready = 0;
2193 dmabuf->write_channel = state->card->alloc_pcm_channel(state->card);
2194 if (!dmabuf->write_channel)
2195 return -EBUSY;
2196 }
2197 if (!dmabuf->ready && (ret = prog_dmabuf(state, 0)))
2198 return ret;
2199 if (dmabuf->mapped) {
2200 spin_lock_irqsave(&state->card->lock, flags);
2201 i810_update_ptr(state);
2202 dmabuf->count = 0;
2203 dmabuf->swptr = dmabuf->hwptr;
2204 dmabuf->count = i810_get_free_write_space(state);
2205 dmabuf->swptr = (dmabuf->swptr + dmabuf->count) % dmabuf->dmasize;
2206 spin_unlock_irqrestore(&state->card->lock, flags);
2207 }
2208 i810_update_lvi(state, 0);
2209 start_dac(state);
2210 }
2211 if((val & PCM_ENABLE_INPUT) && !(dmabuf->enable & ADC_RUNNING)) {
2212 if (!dmabuf->read_channel) {
2213 dmabuf->ready = 0;
2214 dmabuf->read_channel = state->card->alloc_rec_pcm_channel(state->card);
2215 if (!dmabuf->read_channel)
2216 return -EBUSY;
2217 }
2218 if (!dmabuf->ready && (ret = prog_dmabuf(state, 1)))
2219 return ret;
2220 if (dmabuf->mapped) {
2221 spin_lock_irqsave(&state->card->lock, flags);
2222 i810_update_ptr(state);
2223 dmabuf->swptr = dmabuf->hwptr;
2224 dmabuf->count = 0;
2225 spin_unlock_irqrestore(&state->card->lock, flags);
2226 }
2227 i810_update_lvi(state, 1);
2228 start_adc(state);
2229 }
2230 return 0;
2231
2232 case SNDCTL_DSP_SETDUPLEX:
2233 #ifdef DEBUG
2234 printk("SNDCTL_DSP_SETDUPLEX\n");
2235 #endif
2236 return -EINVAL;
2237
2238 case SNDCTL_DSP_GETODELAY:
2239 if (!(file->f_mode & FMODE_WRITE))
2240 return -EINVAL;
2241 spin_lock_irqsave(&state->card->lock, flags);
2242 i810_update_ptr(state);
2243 val = dmabuf->count;
2244 spin_unlock_irqrestore(&state->card->lock, flags);
2245 #ifdef DEBUG
2246 printk("SNDCTL_DSP_GETODELAY %d\n", dmabuf->count);
2247 #endif
2248 return put_user(val, p);
2249
2250 case SOUND_PCM_READ_RATE:
2251 #ifdef DEBUG
2252 printk("SOUND_PCM_READ_RATE %d\n", dmabuf->rate);
2253 #endif
2254 return put_user(dmabuf->rate, p);
2255
2256 case SOUND_PCM_READ_CHANNELS:
2257 #ifdef DEBUG
2258 printk("SOUND_PCM_READ_CHANNELS\n");
2259 #endif
2260 return put_user(2, p);
2261
2262 case SOUND_PCM_READ_BITS:
2263 #ifdef DEBUG
2264 printk("SOUND_PCM_READ_BITS\n");
2265 #endif
2266 return put_user(AFMT_S16_LE, p);
2267
2268 case SNDCTL_DSP_SETSPDIF: /* Set S/PDIF Control register */
2269 #ifdef DEBUG
2270 printk("SNDCTL_DSP_SETSPDIF\n");
2271 #endif
2272 if (get_user(val, p))
2273 return -EFAULT;
2274
2275 /* Check to make sure the codec supports S/PDIF transmitter */
2276
2277 if((state->card->ac97_features & 4)) {
2278 /* mask out the transmitter speed bits so the user can't set them */
2279 val &= ~0x3000;
2280
2281 /* Add the current transmitter speed bits to the passed value */
2282 ret = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
2283 val |= (ret & 0x3000);
2284
2285 i810_ac97_set(codec, AC97_SPDIF_CONTROL, val);
2286 if(i810_ac97_get(codec, AC97_SPDIF_CONTROL) != val ) {
2287 printk(KERN_ERR "i810_audio: Unable to set S/PDIF configuration to 0x%04x.\n", val);
2288 return -EFAULT;
2289 }
2290 }
2291 #ifdef DEBUG
2292 else
2293 printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
2294 #endif
2295 return put_user(val, p);
2296
2297 case SNDCTL_DSP_GETSPDIF: /* Get S/PDIF Control register */
2298 #ifdef DEBUG
2299 printk("SNDCTL_DSP_GETSPDIF\n");
2300 #endif
2301 if (get_user(val, p))
2302 return -EFAULT;
2303
2304 /* Check to make sure the codec supports S/PDIF transmitter */
2305
2306 if(!(state->card->ac97_features & 4)) {
2307 #ifdef DEBUG
2308 printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
2309 #endif
2310 val = 0;
2311 } else {
2312 val = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
2313 }
2314 //return put_user((val & 0xcfff), p);
2315 return put_user(val, p);
2316
2317 case SNDCTL_DSP_GETCHANNELMASK:
2318 #ifdef DEBUG
2319 printk("SNDCTL_DSP_GETCHANNELMASK\n");
2320 #endif
2321 if (get_user(val, p))
2322 return -EFAULT;
2323
2324 /* Based on AC'97 DAC support, not ICH hardware */
2325 val = DSP_BIND_FRONT;
2326 if ( state->card->ac97_features & 0x0004 )
2327 val |= DSP_BIND_SPDIF;
2328
2329 if ( state->card->ac97_features & 0x0080 )
2330 val |= DSP_BIND_SURR;
2331 if ( state->card->ac97_features & 0x0140 )
2332 val |= DSP_BIND_CENTER_LFE;
2333
2334 return put_user(val, p);
2335
2336 case SNDCTL_DSP_BIND_CHANNEL:
2337 #ifdef DEBUG
2338 printk("SNDCTL_DSP_BIND_CHANNEL\n");
2339 #endif
2340 if (get_user(val, p))
2341 return -EFAULT;
2342 if ( val == DSP_BIND_QUERY ) {
2343 val = DSP_BIND_FRONT; /* Always report this as being enabled */
2344 if ( state->card->ac97_status & SPDIF_ON )
2345 val |= DSP_BIND_SPDIF;
2346 else {
2347 if ( state->card->ac97_status & SURR_ON )
2348 val |= DSP_BIND_SURR;
2349 if ( state->card->ac97_status & CENTER_LFE_ON )
2350 val |= DSP_BIND_CENTER_LFE;
2351 }
2352 } else { /* Not a query, set it */
2353 if (!(file->f_mode & FMODE_WRITE))
2354 return -EINVAL;
2355 if ( dmabuf->enable == DAC_RUNNING ) {
2356 stop_dac(state);
2357 }
2358 if ( val & DSP_BIND_SPDIF ) { /* Turn on SPDIF */
2359 /* Ok, this should probably define what slots
2360 * to use. For now, we'll only set it to the
2361 * defaults:
2362 *
2363 * non multichannel codec maps to slots 3&4
2364 * 2 channel codec maps to slots 7&8
2365 * 4 channel codec maps to slots 6&9
2366 * 6 channel codec maps to slots 10&11
2367 *
2368 * there should be some way for the app to
2369 * select the slot assignment.
2370 */
2371
2372 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, dmabuf->rate );
2373 if ( !(state->card->ac97_status & SPDIF_ON) )
2374 val &= ~DSP_BIND_SPDIF;
2375 } else {
2376 int mask;
2377 int channels;
2378
2379 /* Turn off S/PDIF if it was on */
2380 if ( state->card->ac97_status & SPDIF_ON )
2381 i810_set_spdif_output ( state, -1, 0 );
2382
2383 mask = val & (DSP_BIND_FRONT | DSP_BIND_SURR | DSP_BIND_CENTER_LFE);
2384 switch (mask) {
2385 case DSP_BIND_FRONT:
2386 channels = 2;
2387 break;
2388 case DSP_BIND_FRONT|DSP_BIND_SURR:
2389 channels = 4;
2390 break;
2391 case DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE:
2392 channels = 6;
2393 break;
2394 default:
2395 val = DSP_BIND_FRONT;
2396 channels = 2;
2397 break;
2398 }
2399 i810_set_dac_channels ( state, channels );
2400
2401 /* check that they really got turned on */
2402 if (!(state->card->ac97_status & SURR_ON))
2403 val &= ~DSP_BIND_SURR;
2404 if (!(state->card->ac97_status & CENTER_LFE_ON))
2405 val &= ~DSP_BIND_CENTER_LFE;
2406 }
2407 }
2408 return put_user(val, p);
2409
2410 case SNDCTL_DSP_MAPINBUF:
2411 case SNDCTL_DSP_MAPOUTBUF:
2412 case SNDCTL_DSP_SETSYNCRO:
2413 case SOUND_PCM_WRITE_FILTER:
2414 case SOUND_PCM_READ_FILTER:
2415 #ifdef DEBUG
2416 printk("SNDCTL_* -EINVAL\n");
2417 #endif
2418 return -EINVAL;
2419 }
2420 return -EINVAL;
2421 }
2422
2423 static int i810_open(struct inode *inode, struct file *file)
2424 {
2425 int i = 0;
2426 struct i810_card *card = devs;
2427 struct i810_state *state = NULL;
2428 struct dmabuf *dmabuf = NULL;
2429
2430 /* find an avaiable virtual channel (instance of /dev/dsp) */
2431 while (card != NULL) {
2432 /*
2433 * If we are initializing and then fail, card could go
2434 * away unuexpectedly while we are in the for() loop.
2435 * So, check for card on each iteration before we check
2436 * for card->initializing to avoid a possible oops.
2437 * This usually only matters for times when the driver is
2438 * autoloaded by kmod.
2439 */
2440 for (i = 0; i < 50 && card && card->initializing; i++) {
2441 set_current_state(TASK_UNINTERRUPTIBLE);
2442 schedule_timeout(HZ/20);
2443 }
2444 for (i = 0; i < NR_HW_CH && card && !card->initializing; i++) {
2445 if (card->states[i] == NULL) {
2446 state = card->states[i] = (struct i810_state *)
2447 kmalloc(sizeof(struct i810_state), GFP_KERNEL);
2448 if (state == NULL)
2449 return -ENOMEM;
2450 memset(state, 0, sizeof(struct i810_state));
2451 dmabuf = &state->dmabuf;
2452 goto found_virt;
2453 }
2454 }
2455 card = card->next;
2456 }
2457 /* no more virtual channel avaiable */
2458 if (!state)
2459 return -ENODEV;
2460
2461 found_virt:
2462 /* initialize the virtual channel */
2463 state->virt = i;
2464 state->card = card;
2465 state->magic = I810_STATE_MAGIC;
2466 init_waitqueue_head(&dmabuf->wait);
2467 init_MUTEX(&state->open_sem);
2468 file->private_data = state;
2469 dmabuf->trigger = 0;
2470
2471 /* allocate hardware channels */
2472 if(file->f_mode & FMODE_READ) {
2473 if((dmabuf->read_channel = card->alloc_rec_pcm_channel(card)) == NULL) {
2474 kfree (card->states[i]);
2475 card->states[i] = NULL;
2476 return -EBUSY;
2477 }
2478 dmabuf->trigger |= PCM_ENABLE_INPUT;
2479 i810_set_adc_rate(state, 8000);
2480 }
2481 if(file->f_mode & FMODE_WRITE) {
2482 if((dmabuf->write_channel = card->alloc_pcm_channel(card)) == NULL) {
2483 /* make sure we free the record channel allocated above */
2484 if(file->f_mode & FMODE_READ)
2485 card->free_pcm_channel(card,dmabuf->read_channel->num);
2486 kfree (card->states[i]);
2487 card->states[i] = NULL;
2488 return -EBUSY;
2489 }
2490 /* Initialize to 8kHz? What if we don't support 8kHz? */
2491 /* Let's change this to check for S/PDIF stuff */
2492
2493 dmabuf->trigger |= PCM_ENABLE_OUTPUT;
2494 if ( spdif_locked ) {
2495 i810_set_dac_rate(state, spdif_locked);
2496 i810_set_spdif_output(state, AC97_EA_SPSA_3_4, spdif_locked);
2497 } else {
2498 i810_set_dac_rate(state, 8000);
2499 /* Put the ACLink in 2 channel mode by default */
2500 i = I810_IOREADL(card, GLOB_CNT);
2501 I810_IOWRITEL(i & 0xffcfffff, card, GLOB_CNT);
2502 }
2503 }
2504
2505 /* set default sample format. According to OSS Programmer's Guide /dev/dsp
2506 should be default to unsigned 8-bits, mono, with sample rate 8kHz and
2507 /dev/dspW will accept 16-bits sample, but we don't support those so we
2508 set it immediately to stereo and 16bit, which is all we do support */
2509 dmabuf->fmt |= I810_FMT_16BIT | I810_FMT_STEREO;
2510 dmabuf->ossfragsize = 0;
2511 dmabuf->ossmaxfrags = 0;
2512 dmabuf->subdivision = 0;
2513
2514 state->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2515
2516 return nonseekable_open(inode, file);
2517 }
2518
2519 static int i810_release(struct inode *inode, struct file *file)
2520 {
2521 struct i810_state *state = (struct i810_state *)file->private_data;
2522 struct i810_card *card = state->card;
2523 struct dmabuf *dmabuf = &state->dmabuf;
2524 unsigned long flags;
2525
2526 lock_kernel();
2527
2528 /* stop DMA state machine and free DMA buffers/channels */
2529 if(dmabuf->trigger & PCM_ENABLE_OUTPUT) {
2530 drain_dac(state, 0);
2531 }
2532 if(dmabuf->trigger & PCM_ENABLE_INPUT) {
2533 stop_adc(state);
2534 }
2535 spin_lock_irqsave(&card->lock, flags);
2536 dealloc_dmabuf(state);
2537 if (file->f_mode & FMODE_WRITE) {
2538 state->card->free_pcm_channel(state->card, dmabuf->write_channel->num);
2539 }
2540 if (file->f_mode & FMODE_READ) {
2541 state->card->free_pcm_channel(state->card, dmabuf->read_channel->num);
2542 }
2543
2544 state->card->states[state->virt] = NULL;
2545 kfree(state);
2546 spin_unlock_irqrestore(&card->lock, flags);
2547 unlock_kernel();
2548
2549 return 0;
2550 }
2551
2552 static /*const*/ struct file_operations i810_audio_fops = {
2553 .owner = THIS_MODULE,
2554 .llseek = no_llseek,
2555 .read = i810_read,
2556 .write = i810_write,
2557 .poll = i810_poll,
2558 .ioctl = i810_ioctl,
2559 .mmap = i810_mmap,
2560 .open = i810_open,
2561 .release = i810_release,
2562 };
2563
2564 /* Write AC97 codec registers */
2565
2566 static u16 i810_ac97_get_mmio(struct ac97_codec *dev, u8 reg)
2567 {
2568 struct i810_card *card = dev->private_data;
2569 int count = 100;
2570 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2571
2572 while(count-- && (readb(card->iobase_mmio + CAS) & 1))
2573 udelay(1);
2574
2575 #ifdef DEBUG_MMIO
2576 {
2577 u16 ans = readw(card->ac97base_mmio + reg_set);
2578 printk(KERN_DEBUG "i810_audio: ac97_get_mmio(%d) -> 0x%04X\n", ((int) reg_set) & 0xffff, (u32) ans);
2579 return ans;
2580 }
2581 #else
2582 return readw(card->ac97base_mmio + reg_set);
2583 #endif
2584 }
2585
2586 static u16 i810_ac97_get_io(struct ac97_codec *dev, u8 reg)
2587 {
2588 struct i810_card *card = dev->private_data;
2589 int count = 100;
2590 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2591
2592 while(count-- && (I810_IOREADB(card, CAS) & 1))
2593 udelay(1);
2594
2595 return inw(card->ac97base + reg_set);
2596 }
2597
2598 static void i810_ac97_set_mmio(struct ac97_codec *dev, u8 reg, u16 data)
2599 {
2600 struct i810_card *card = dev->private_data;
2601 int count = 100;
2602 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2603
2604 while(count-- && (readb(card->iobase_mmio + CAS) & 1))
2605 udelay(1);
2606
2607 writew(data, card->ac97base_mmio + reg_set);
2608
2609 #ifdef DEBUG_MMIO
2610 printk(KERN_DEBUG "i810_audio: ac97_set_mmio(0x%04X, %d)\n", (u32) data, ((int) reg_set) & 0xffff);
2611 #endif
2612 }
2613
2614 static void i810_ac97_set_io(struct ac97_codec *dev, u8 reg, u16 data)
2615 {
2616 struct i810_card *card = dev->private_data;
2617 int count = 100;
2618 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2619
2620 while(count-- && (I810_IOREADB(card, CAS) & 1))
2621 udelay(1);
2622
2623 outw(data, card->ac97base + reg_set);
2624 }
2625
2626 static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg)
2627 {
2628 struct i810_card *card = dev->private_data;
2629 u16 ret;
2630
2631 spin_lock(&card->ac97_lock);
2632 if (card->use_mmio) {
2633 ret = i810_ac97_get_mmio(dev, reg);
2634 }
2635 else {
2636 ret = i810_ac97_get_io(dev, reg);
2637 }
2638 spin_unlock(&card->ac97_lock);
2639
2640 return ret;
2641 }
2642
2643 static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data)
2644 {
2645 struct i810_card *card = dev->private_data;
2646
2647 spin_lock(&card->ac97_lock);
2648 if (card->use_mmio) {
2649 i810_ac97_set_mmio(dev, reg, data);
2650 }
2651 else {
2652 i810_ac97_set_io(dev, reg, data);
2653 }
2654 spin_unlock(&card->ac97_lock);
2655 }
2656
2657
2658 /* OSS /dev/mixer file operation methods */
2659
2660 static int i810_open_mixdev(struct inode *inode, struct file *file)
2661 {
2662 int i;
2663 int minor = iminor(inode);
2664 struct i810_card *card = devs;
2665
2666 for (card = devs; card != NULL; card = card->next) {
2667 /*
2668 * If we are initializing and then fail, card could go
2669 * away unuexpectedly while we are in the for() loop.
2670 * So, check for card on each iteration before we check
2671 * for card->initializing to avoid a possible oops.
2672 * This usually only matters for times when the driver is
2673 * autoloaded by kmod.
2674 */
2675 for (i = 0; i < 50 && card && card->initializing; i++) {
2676 set_current_state(TASK_UNINTERRUPTIBLE);
2677 schedule_timeout(HZ/20);
2678 }
2679 for (i = 0; i < NR_AC97 && card && !card->initializing; i++)
2680 if (card->ac97_codec[i] != NULL &&
2681 card->ac97_codec[i]->dev_mixer == minor) {
2682 file->private_data = card->ac97_codec[i];
2683 return nonseekable_open(inode, file);
2684 }
2685 }
2686 return -ENODEV;
2687 }
2688
2689 static int i810_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd,
2690 unsigned long arg)
2691 {
2692 struct ac97_codec *codec = (struct ac97_codec *)file->private_data;
2693
2694 return codec->mixer_ioctl(codec, cmd, arg);
2695 }
2696
2697 static /*const*/ struct file_operations i810_mixer_fops = {
2698 .owner = THIS_MODULE,
2699 .llseek = no_llseek,
2700 .ioctl = i810_ioctl_mixdev,
2701 .open = i810_open_mixdev,
2702 };
2703
2704 /* AC97 codec initialisation. These small functions exist so we don't
2705 duplicate code between module init and apm resume */
2706
2707 static inline int i810_ac97_exists(struct i810_card *card, int ac97_number)
2708 {
2709 u32 reg = I810_IOREADL(card, GLOB_STA);
2710 switch (ac97_number) {
2711 case 0:
2712 return reg & (1<<8);
2713 case 1:
2714 return reg & (1<<9);
2715 case 2:
2716 return reg & (1<<28);
2717 }
2718 return 0;
2719 }
2720
2721 static inline int i810_ac97_enable_variable_rate(struct ac97_codec *codec)
2722 {
2723 i810_ac97_set(codec, AC97_EXTENDED_STATUS, 9);
2724 i810_ac97_set(codec,AC97_EXTENDED_STATUS,
2725 i810_ac97_get(codec, AC97_EXTENDED_STATUS)|0xE800);
2726
2727 return (i810_ac97_get(codec, AC97_EXTENDED_STATUS)&1);
2728 }
2729
2730
2731 static int i810_ac97_probe_and_powerup(struct i810_card *card,struct ac97_codec *codec)
2732 {
2733 /* Returns 0 on failure */
2734 int i;
2735
2736 if (ac97_probe_codec(codec) == 0) return 0;
2737
2738 /* power it all up */
2739 i810_ac97_set(codec, AC97_POWER_CONTROL,
2740 i810_ac97_get(codec, AC97_POWER_CONTROL) & ~0x7f00);
2741
2742 /* wait for analog ready */
2743 for (i=100; i && ((i810_ac97_get(codec, AC97_POWER_CONTROL) & 0xf) != 0xf); i--)
2744 {
2745 set_current_state(TASK_UNINTERRUPTIBLE);
2746 schedule_timeout(HZ/20);
2747 }
2748 return i;
2749 }
2750
2751 static int is_new_ich(u16 pci_id)
2752 {
2753 switch (pci_id) {
2754 case PCI_DEVICE_ID_INTEL_82801DB_5:
2755 case PCI_DEVICE_ID_INTEL_82801EB_5:
2756 case PCI_DEVICE_ID_INTEL_ESB_5:
2757 case PCI_DEVICE_ID_INTEL_ICH6_18:
2758 return 1;
2759 default:
2760 break;
2761 }
2762
2763 return 0;
2764 }
2765
2766 static inline int ich_use_mmio(struct i810_card *card)
2767 {
2768 return is_new_ich(card->pci_id) && card->use_mmio;
2769 }
2770
2771 /**
2772 * i810_ac97_power_up_bus - bring up AC97 link
2773 * @card : ICH audio device to power up
2774 *
2775 * Bring up the ACLink AC97 codec bus
2776 */
2777
2778 static int i810_ac97_power_up_bus(struct i810_card *card)
2779 {
2780 u32 reg = I810_IOREADL(card, GLOB_CNT);
2781 int i;
2782 int primary_codec_id = 0;
2783
2784 if((reg&2)==0) /* Cold required */
2785 reg|=2;
2786 else
2787 reg|=4; /* Warm */
2788
2789 reg&=~8; /* ACLink on */
2790
2791 /* At this point we deassert AC_RESET # */
2792 I810_IOWRITEL(reg , card, GLOB_CNT);
2793
2794 /* We must now allow time for the Codec initialisation.
2795 600mS is the specified time */
2796
2797 for(i=0;i<10;i++)
2798 {
2799 if((I810_IOREADL(card, GLOB_CNT)&4)==0)
2800 break;
2801
2802 set_current_state(TASK_UNINTERRUPTIBLE);
2803 schedule_timeout(HZ/20);
2804 }
2805 if(i==10)
2806 {
2807 printk(KERN_ERR "i810_audio: AC'97 reset failed.\n");
2808 return 0;
2809 }
2810
2811 set_current_state(TASK_UNINTERRUPTIBLE);
2812 schedule_timeout(HZ/2);
2813
2814 /*
2815 * See if the primary codec comes ready. This must happen
2816 * before we start doing DMA stuff
2817 */
2818 /* see i810_ac97_init for the next 10 lines (jsaw) */
2819 if (card->use_mmio)
2820 readw(card->ac97base_mmio);
2821 else
2822 inw(card->ac97base);
2823 if (ich_use_mmio(card)) {
2824 primary_codec_id = (int) readl(card->iobase_mmio + SDM) & 0x3;
2825 printk(KERN_INFO "i810_audio: Primary codec has ID %d\n",
2826 primary_codec_id);
2827 }
2828
2829 if(! i810_ac97_exists(card, primary_codec_id))
2830 {
2831 printk(KERN_INFO "i810_audio: Codec not ready.. wait.. ");
2832 set_current_state(TASK_UNINTERRUPTIBLE);
2833 schedule_timeout(HZ); /* actually 600mS by the spec */
2834
2835 if(i810_ac97_exists(card, primary_codec_id))
2836 printk("OK\n");
2837 else
2838 printk("no response.\n");
2839 }
2840 if (card->use_mmio)
2841 readw(card->ac97base_mmio);
2842 else
2843 inw(card->ac97base);
2844 return 1;
2845 }
2846
2847 static int __devinit i810_ac97_init(struct i810_card *card)
2848 {
2849 int num_ac97 = 0;
2850 int ac97_id;
2851 int total_channels = 0;
2852 int nr_ac97_max = card_cap[card->pci_id_internal].nr_ac97;
2853 struct ac97_codec *codec;
2854 u16 eid;
2855 u32 reg;
2856
2857 if(!i810_ac97_power_up_bus(card)) return 0;
2858
2859 /* Number of channels supported */
2860 /* What about the codec? Just because the ICH supports */
2861 /* multiple channels doesn't mean the codec does. */
2862 /* we'll have to modify this in the codec section below */
2863 /* to reflect what the codec has. */
2864 /* ICH and ICH0 only support 2 channels so don't bother */
2865 /* to check.... */
2866
2867 card->channels = 2;
2868 reg = I810_IOREADL(card, GLOB_STA);
2869 if ( reg & 0x0200000 )
2870 card->channels = 6;
2871 else if ( reg & 0x0100000 )
2872 card->channels = 4;
2873 printk(KERN_INFO "i810_audio: Audio Controller supports %d channels.\n", card->channels);
2874 printk(KERN_INFO "i810_audio: Defaulting to base 2 channel mode.\n");
2875 reg = I810_IOREADL(card, GLOB_CNT);
2876 I810_IOWRITEL(reg & 0xffcfffff, card, GLOB_CNT);
2877
2878 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++)
2879 card->ac97_codec[num_ac97] = NULL;
2880
2881 /*@FIXME I don't know, if I'm playing to safe here... (jsaw) */
2882 if ((nr_ac97_max > 2) && !card->use_mmio) nr_ac97_max = 2;
2883
2884 for (num_ac97 = 0; num_ac97 < nr_ac97_max; num_ac97++) {
2885 /* codec reset */
2886 printk(KERN_INFO "i810_audio: Resetting connection %d\n", num_ac97);
2887 if (card->use_mmio)
2888 readw(card->ac97base_mmio + 0x80*num_ac97);
2889 else
2890 inw(card->ac97base + 0x80*num_ac97);
2891
2892 /* If we have the SDATA_IN Map Register, as on ICH4, we
2893 do not loop thru all possible codec IDs but thru all
2894 possible IO channels. Bit 0:1 of SDM then holds the
2895 last codec ID spoken to.
2896 */
2897 if (ich_use_mmio(card)) {
2898 ac97_id = (int) readl(card->iobase_mmio + SDM) & 0x3;
2899 printk(KERN_INFO "i810_audio: Connection %d with codec id %d\n",
2900 num_ac97, ac97_id);
2901 }
2902 else {
2903 ac97_id = num_ac97;
2904 }
2905
2906 /* The ICH programmer's reference says you should */
2907 /* check the ready status before probing. So we chk */
2908 /* What do we do if it's not ready? Wait and try */
2909 /* again, or abort? */
2910 if (!i810_ac97_exists(card, ac97_id)) {
2911 if(num_ac97 == 0)
2912 printk(KERN_ERR "i810_audio: Primary codec not ready.\n");
2913 }
2914
2915 if ((codec = ac97_alloc_codec()) == NULL)
2916 return -ENOMEM;
2917
2918 /* initialize some basic codec information, other fields will be filled
2919 in ac97_probe_codec */
2920 codec->private_data = card;
2921 codec->id = ac97_id;
2922 card->ac97_id_map[ac97_id] = num_ac97 * 0x80;
2923
2924 if (card->use_mmio) {
2925 codec->codec_read = i810_ac97_get_mmio;
2926 codec->codec_write = i810_ac97_set_mmio;
2927 }
2928 else {
2929 codec->codec_read = i810_ac97_get_io;
2930 codec->codec_write = i810_ac97_set_io;
2931 }
2932
2933 if(!i810_ac97_probe_and_powerup(card,codec)) {
2934 printk(KERN_ERR "i810_audio: timed out waiting for codec %d analog ready.\n", ac97_id);
2935 ac97_release_codec(codec);
2936 break; /* it didn't work */
2937 }
2938 /* Store state information about S/PDIF transmitter */
2939 card->ac97_status = 0;
2940
2941 /* Don't attempt to get eid until powerup is complete */
2942 eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
2943
2944 if(eid==0xFFFF)
2945 {
2946 printk(KERN_WARNING "i810_audio: no codec attached ?\n");
2947 ac97_release_codec(codec);
2948 break;
2949 }
2950
2951 /* Check for an AC97 1.0 soft modem (ID1) */
2952
2953 if(codec->modem)
2954 {
2955 printk(KERN_WARNING "i810_audio: codec %d is a softmodem - skipping.\n", ac97_id);
2956 ac97_release_codec(codec);
2957 continue;
2958 }
2959
2960 card->ac97_features = eid;
2961
2962 /* Now check the codec for useful features to make up for
2963 the dumbness of the 810 hardware engine */
2964
2965 if(!(eid&0x0001))
2966 printk(KERN_WARNING "i810_audio: only 48Khz playback available.\n");
2967 else
2968 {
2969 if(!i810_ac97_enable_variable_rate(codec)) {
2970 printk(KERN_WARNING "i810_audio: Codec refused to allow VRA, using 48Khz only.\n");
2971 card->ac97_features&=~1;
2972 }
2973 }
2974
2975 /* Turn on the amplifier */
2976
2977 codec->codec_write(codec, AC97_POWER_CONTROL,
2978 codec->codec_read(codec, AC97_POWER_CONTROL) & ~0x8000);
2979
2980 /* Determine how many channels the codec(s) support */
2981 /* - The primary codec always supports 2 */
2982 /* - If the codec supports AMAP, surround DACs will */
2983 /* automaticlly get assigned to slots. */
2984 /* * Check for surround DACs and increment if */
2985 /* found. */
2986 /* - Else check if the codec is revision 2.2 */
2987 /* * If surround DACs exist, assign them to slots */
2988 /* and increment channel count. */
2989
2990 /* All of this only applies to ICH2 and above. ICH */
2991 /* and ICH0 only support 2 channels. ICH2 will only */
2992 /* support multiple codecs in a "split audio" config. */
2993 /* as described above. */
2994
2995 /* TODO: Remove all the debugging messages! */
2996
2997 if((eid & 0xc000) == 0) /* primary codec */
2998 total_channels += 2;
2999
3000 if(eid & 0x200) { /* GOOD, AMAP support */
3001 if (eid & 0x0080) /* L/R Surround channels */
3002 total_channels += 2;
3003 if (eid & 0x0140) /* LFE and Center channels */
3004 total_channels += 2;
3005 printk("i810_audio: AC'97 codec %d supports AMAP, total channels = %d\n", ac97_id, total_channels);
3006 } else if (eid & 0x0400) { /* this only works on 2.2 compliant codecs */
3007 eid &= 0xffcf;
3008 if((eid & 0xc000) != 0) {
3009 switch ( total_channels ) {
3010 case 2:
3011 /* Set dsa1, dsa0 to 01 */
3012 eid |= 0x0010;
3013 break;
3014 case 4:
3015 /* Set dsa1, dsa0 to 10 */
3016 eid |= 0x0020;
3017 break;
3018 case 6:
3019 /* Set dsa1, dsa0 to 11 */
3020 eid |= 0x0030;
3021 break;
3022 }
3023 total_channels += 2;
3024 }
3025 i810_ac97_set(codec, AC97_EXTENDED_ID, eid);
3026 eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
3027 printk("i810_audio: AC'97 codec %d, new EID value = 0x%04x\n", ac97_id, eid);
3028 if (eid & 0x0080) /* L/R Surround channels */
3029 total_channels += 2;
3030 if (eid & 0x0140) /* LFE and Center channels */
3031 total_channels += 2;
3032 printk("i810_audio: AC'97 codec %d, DAC map configured, total channels = %d\n", ac97_id, total_channels);
3033 } else {
3034 printk("i810_audio: AC'97 codec %d Unable to map surround DAC's (or DAC's not present), total channels = %d\n", ac97_id, total_channels);
3035 }
3036
3037 if ((codec->dev_mixer = register_sound_mixer(&i810_mixer_fops, -1)) < 0) {
3038 printk(KERN_ERR "i810_audio: couldn't register mixer!\n");
3039 ac97_release_codec(codec);
3040 break;
3041 }
3042
3043 card->ac97_codec[num_ac97] = codec;
3044 }
3045
3046 /* pick the minimum of channels supported by ICHx or codec(s) */
3047 card->channels = (card->channels > total_channels)?total_channels:card->channels;
3048
3049 return num_ac97;
3050 }
3051
3052 static void __devinit i810_configure_clocking (void)
3053 {
3054 struct i810_card *card;
3055 struct i810_state *state;
3056 struct dmabuf *dmabuf;
3057 unsigned int i, offset, new_offset;
3058 unsigned long flags;
3059
3060 card = devs;
3061 /* We could try to set the clocking for multiple cards, but can you even have
3062 * more than one i810 in a machine? Besides, clocking is global, so unless
3063 * someone actually thinks more than one i810 in a machine is possible and
3064 * decides to rewrite that little bit, setting the rate for more than one card
3065 * is a waste of time.
3066 */
3067 if(card != NULL) {
3068 state = card->states[0] = (struct i810_state *)
3069 kmalloc(sizeof(struct i810_state), GFP_KERNEL);
3070 if (state == NULL)
3071 return;
3072 memset(state, 0, sizeof(struct i810_state));
3073 dmabuf = &state->dmabuf;
3074
3075 dmabuf->write_channel = card->alloc_pcm_channel(card);
3076 state->virt = 0;
3077 state->card = card;
3078 state->magic = I810_STATE_MAGIC;
3079 init_waitqueue_head(&dmabuf->wait);
3080 init_MUTEX(&state->open_sem);
3081 dmabuf->fmt = I810_FMT_STEREO | I810_FMT_16BIT;
3082 dmabuf->trigger = PCM_ENABLE_OUTPUT;
3083 i810_set_spdif_output(state, -1, 0);
3084 i810_set_dac_channels(state, 2);
3085 i810_set_dac_rate(state, 48000);
3086 if(prog_dmabuf(state, 0) != 0) {
3087 goto config_out_nodmabuf;
3088 }
3089 if(dmabuf->dmasize < 16384) {
3090 goto config_out;
3091 }
3092 dmabuf->count = dmabuf->dmasize;
3093 CIV_TO_LVI(card, dmabuf->write_channel->port, -1);
3094 local_irq_save(flags);
3095 start_dac(state);
3096 offset = i810_get_dma_addr(state, 0);
3097 mdelay(50);
3098 new_offset = i810_get_dma_addr(state, 0);
3099 stop_dac(state);
3100 local_irq_restore(flags);
3101 i = new_offset - offset;
3102 #ifdef DEBUG_INTERRUPTS
3103 printk("i810_audio: %d bytes in 50 milliseconds\n", i);
3104 #endif
3105 if(i == 0)
3106 goto config_out;
3107 i = i / 4 * 20;
3108 if (i > 48500 || i < 47500) {
3109 clocking = clocking * clocking / i;
3110 printk("i810_audio: setting clocking to %d\n", clocking);
3111 }
3112 config_out:
3113 dealloc_dmabuf(state);
3114 config_out_nodmabuf:
3115 state->card->free_pcm_channel(state->card,state->dmabuf.write_channel->num);
3116 kfree(state);
3117 card->states[0] = NULL;
3118 }
3119 }
3120
3121 /* install the driver, we do not allocate hardware channel nor DMA buffer now, they are defered
3122 until "ACCESS" time (in prog_dmabuf called by open/read/write/ioctl/mmap) */
3123
3124 static int __devinit i810_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_id)
3125 {
3126 struct i810_card *card;
3127
3128 if (pci_enable_device(pci_dev))
3129 return -EIO;
3130
3131 if (pci_set_dma_mask(pci_dev, I810_DMA_MASK)) {
3132 printk(KERN_ERR "i810_audio: architecture does not support"
3133 " 32bit PCI busmaster DMA\n");
3134 return -ENODEV;
3135 }
3136
3137 if ((card = kmalloc(sizeof(struct i810_card), GFP_KERNEL)) == NULL) {
3138 printk(KERN_ERR "i810_audio: out of memory\n");
3139 return -ENOMEM;
3140 }
3141 memset(card, 0, sizeof(*card));
3142
3143 card->initializing = 1;
3144 card->pci_dev = pci_dev;
3145 card->pci_id = pci_id->device;
3146 card->ac97base = pci_resource_start (pci_dev, 0);
3147 card->iobase = pci_resource_start (pci_dev, 1);
3148
3149 if (!(card->ac97base) || !(card->iobase)) {
3150 card->ac97base = 0;
3151 card->iobase = 0;
3152 }
3153
3154 /* if chipset could have mmio capability, check it */
3155 if (card_cap[pci_id->driver_data].flags & CAP_MMIO) {
3156 card->ac97base_mmio_phys = pci_resource_start (pci_dev, 2);
3157 card->iobase_mmio_phys = pci_resource_start (pci_dev, 3);
3158
3159 if ((card->ac97base_mmio_phys) && (card->iobase_mmio_phys)) {
3160 card->use_mmio = 1;
3161 }
3162 else {
3163 card->ac97base_mmio_phys = 0;
3164 card->iobase_mmio_phys = 0;
3165 }
3166 }
3167
3168 if (!(card->use_mmio) && (!(card->iobase) || !(card->ac97base))) {
3169 printk(KERN_ERR "i810_audio: No I/O resources available.\n");
3170 goto out_mem;
3171 }
3172
3173 card->irq = pci_dev->irq;
3174 card->next = devs;
3175 card->magic = I810_CARD_MAGIC;
3176 #ifdef CONFIG_PM
3177 card->pm_suspended=0;
3178 #endif
3179 spin_lock_init(&card->lock);
3180 spin_lock_init(&card->ac97_lock);
3181 devs = card;
3182
3183 pci_set_master(pci_dev);
3184
3185 printk(KERN_INFO "i810: %s found at IO 0x%04lx and 0x%04lx, "
3186 "MEM 0x%04lx and 0x%04lx, IRQ %d\n",
3187 card_names[pci_id->driver_data],
3188 card->iobase, card->ac97base,
3189 card->ac97base_mmio_phys, card->iobase_mmio_phys,
3190 card->irq);
3191
3192 card->alloc_pcm_channel = i810_alloc_pcm_channel;
3193 card->alloc_rec_pcm_channel = i810_alloc_rec_pcm_channel;
3194 card->alloc_rec_mic_channel = i810_alloc_rec_mic_channel;
3195 card->free_pcm_channel = i810_free_pcm_channel;
3196
3197 if ((card->channel = pci_alloc_consistent(pci_dev,
3198 sizeof(struct i810_channel)*NR_HW_CH, &card->chandma)) == NULL) {
3199 printk(KERN_ERR "i810: cannot allocate channel DMA memory\n");
3200 goto out_mem;
3201 }
3202
3203 { /* We may dispose of this altogether some time soon, so... */
3204 struct i810_channel *cp = card->channel;
3205
3206 cp[0].offset = 0;
3207 cp[0].port = 0x00;
3208 cp[0].num = 0;
3209 cp[1].offset = 0;
3210 cp[1].port = 0x10;
3211 cp[1].num = 1;
3212 cp[2].offset = 0;
3213 cp[2].port = 0x20;
3214 cp[2].num = 2;
3215 }
3216
3217 /* claim our iospace and irq */
3218 if (!request_region(card->iobase, 64, card_names[pci_id->driver_data])) {
3219 printk(KERN_ERR "i810_audio: unable to allocate region %lx\n", card->iobase);
3220 goto out_region1;
3221 }
3222 if (!request_region(card->ac97base, 256, card_names[pci_id->driver_data])) {
3223 printk(KERN_ERR "i810_audio: unable to allocate region %lx\n", card->ac97base);
3224 goto out_region2;
3225 }
3226
3227 if (request_irq(card->irq, &i810_interrupt, SA_SHIRQ,
3228 card_names[pci_id->driver_data], card)) {
3229 printk(KERN_ERR "i810_audio: unable to allocate irq %d\n", card->irq);
3230 goto out_pio;
3231 }
3232
3233 if (card->use_mmio) {
3234 if (request_mem_region(card->ac97base_mmio_phys, 512, "ich_audio MMBAR")) {
3235 if ((card->ac97base_mmio = ioremap(card->ac97base_mmio_phys, 512))) { /*@FIXME can ioremap fail? don't know (jsaw) */
3236 if (request_mem_region(card->iobase_mmio_phys, 256, "ich_audio MBBAR")) {
3237 if ((card->iobase_mmio = ioremap(card->iobase_mmio_phys, 256))) {
3238 printk(KERN_INFO "i810: %s mmio at 0x%04lx and 0x%04lx\n",
3239 card_names[pci_id->driver_data],
3240 (unsigned long) card->ac97base_mmio,
3241 (unsigned long) card->iobase_mmio);
3242 }
3243 else {
3244 iounmap(card->ac97base_mmio);
3245 release_mem_region(card->ac97base_mmio_phys, 512);
3246 release_mem_region(card->iobase_mmio_phys, 512);
3247 card->use_mmio = 0;
3248 }
3249 }
3250 else {
3251 iounmap(card->ac97base_mmio);
3252 release_mem_region(card->ac97base_mmio_phys, 512);
3253 card->use_mmio = 0;
3254 }
3255 }
3256 }
3257 else {
3258 card->use_mmio = 0;
3259 }
3260 }
3261
3262 /* initialize AC97 codec and register /dev/mixer */
3263 if (i810_ac97_init(card) <= 0) {
3264 free_irq(card->irq, card);
3265 goto out_iospace;
3266 }
3267 pci_set_drvdata(pci_dev, card);
3268
3269 if(clocking == 0) {
3270 clocking = 48000;
3271 i810_configure_clocking();
3272 }
3273
3274 /* register /dev/dsp */
3275 if ((card->dev_audio = register_sound_dsp(&i810_audio_fops, -1)) < 0) {
3276 int i;
3277 printk(KERN_ERR "i810_audio: couldn't register DSP device!\n");
3278 free_irq(card->irq, card);
3279 for (i = 0; i < NR_AC97; i++)
3280 if (card->ac97_codec[i] != NULL) {
3281 unregister_sound_mixer(card->ac97_codec[i]->dev_mixer);
3282 ac97_release_codec(card->ac97_codec[i]);
3283 }
3284 goto out_iospace;
3285 }
3286
3287 card->initializing = 0;
3288 return 0;
3289
3290 out_iospace:
3291 if (card->use_mmio) {
3292 iounmap(card->ac97base_mmio);
3293 iounmap(card->iobase_mmio);
3294 release_mem_region(card->ac97base_mmio_phys, 512);
3295 release_mem_region(card->iobase_mmio_phys, 256);
3296 }
3297 out_pio:
3298 release_region(card->iobase, 64);
3299 out_region2:
3300 release_region(card->ac97base, 256);
3301 out_region1:
3302 pci_free_consistent(pci_dev, sizeof(struct i810_channel)*NR_HW_CH,
3303 card->channel, card->chandma);
3304 out_mem:
3305 kfree(card);
3306 return -ENODEV;
3307 }
3308
3309 static void __devexit i810_remove(struct pci_dev *pci_dev)
3310 {
3311 int i;
3312 struct i810_card *card = pci_get_drvdata(pci_dev);
3313 /* free hardware resources */
3314 free_irq(card->irq, devs);
3315 release_region(card->iobase, 64);
3316 release_region(card->ac97base, 256);
3317 pci_free_consistent(pci_dev, sizeof(struct i810_channel)*NR_HW_CH,
3318 card->channel, card->chandma);
3319 if (card->use_mmio) {
3320 iounmap(card->ac97base_mmio);
3321 iounmap(card->iobase_mmio);
3322 release_mem_region(card->ac97base_mmio_phys, 512);
3323 release_mem_region(card->iobase_mmio_phys, 256);
3324 }
3325
3326 /* unregister audio devices */
3327 for (i = 0; i < NR_AC97; i++)
3328 if (card->ac97_codec[i] != NULL) {
3329 unregister_sound_mixer(card->ac97_codec[i]->dev_mixer);
3330 ac97_release_codec(card->ac97_codec[i]);
3331 card->ac97_codec[i] = NULL;
3332 }
3333 unregister_sound_dsp(card->dev_audio);
3334 kfree(card);
3335 }
3336
3337 #ifdef CONFIG_PM
3338 static int i810_pm_suspend(struct pci_dev *dev, u32 pm_state)
3339 {
3340 struct i810_card *card = pci_get_drvdata(dev);
3341 struct i810_state *state;
3342 unsigned long flags;
3343 struct dmabuf *dmabuf;
3344 int i,num_ac97;
3345 #ifdef DEBUG
3346 printk("i810_audio: i810_pm_suspend called\n");
3347 #endif
3348 if(!card) return 0;
3349 spin_lock_irqsave(&card->lock, flags);
3350 card->pm_suspended=1;
3351 for(i=0;i<NR_HW_CH;i++) {
3352 state = card->states[i];
3353 if(!state) continue;
3354 /* this happens only if there are open files */
3355 dmabuf = &state->dmabuf;
3356 if(dmabuf->enable & DAC_RUNNING ||
3357 (dmabuf->count && (dmabuf->trigger & PCM_ENABLE_OUTPUT))) {
3358 state->pm_saved_dac_rate=dmabuf->rate;
3359 stop_dac(state);
3360 } else {
3361 state->pm_saved_dac_rate=0;
3362 }
3363 if(dmabuf->enable & ADC_RUNNING) {
3364 state->pm_saved_adc_rate=dmabuf->rate;
3365 stop_adc(state);
3366 } else {
3367 state->pm_saved_adc_rate=0;
3368 }
3369 dmabuf->ready = 0;
3370 dmabuf->swptr = dmabuf->hwptr = 0;
3371 dmabuf->count = dmabuf->total_bytes = 0;
3372 }
3373
3374 spin_unlock_irqrestore(&card->lock, flags);
3375
3376 /* save mixer settings */
3377 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
3378 struct ac97_codec *codec = card->ac97_codec[num_ac97];
3379 if(!codec) continue;
3380 for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) {
3381 if((supported_mixer(codec,i)) &&
3382 (codec->read_mixer)) {
3383 card->pm_saved_mixer_settings[i][num_ac97]=
3384 codec->read_mixer(codec,i);
3385 }
3386 }
3387 }
3388 pci_save_state(dev,card->pm_save_state); /* XXX do we need this? */
3389 pci_disable_device(dev); /* disable busmastering */
3390 pci_set_power_state(dev,3); /* Zzz. */
3391
3392 return 0;
3393 }
3394
3395
3396 static int i810_pm_resume(struct pci_dev *dev)
3397 {
3398 int num_ac97,i=0;
3399 struct i810_card *card=pci_get_drvdata(dev);
3400 pci_enable_device(dev);
3401 pci_restore_state (dev,card->pm_save_state);
3402
3403 /* observation of a toshiba portege 3440ct suggests that the
3404 hardware has to be more or less completely reinitialized from
3405 scratch after an apm suspend. Works For Me. -dan */
3406
3407 i810_ac97_power_up_bus(card);
3408
3409 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
3410 struct ac97_codec *codec = card->ac97_codec[num_ac97];
3411 /* check they haven't stolen the hardware while we were
3412 away */
3413 if(!codec || !i810_ac97_exists(card,num_ac97)) {
3414 if(num_ac97) continue;
3415 else BUG();
3416 }
3417 if(!i810_ac97_probe_and_powerup(card,codec)) BUG();
3418
3419 if((card->ac97_features&0x0001)) {
3420 /* at probe time we found we could do variable
3421 rates, but APM suspend has made it forget
3422 its magical powers */
3423 if(!i810_ac97_enable_variable_rate(codec)) BUG();
3424 }
3425 /* we lost our mixer settings, so restore them */
3426 for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) {
3427 if(supported_mixer(codec,i)){
3428 int val=card->
3429 pm_saved_mixer_settings[i][num_ac97];
3430 codec->mixer_state[i]=val;
3431 codec->write_mixer(codec,i,
3432 (val & 0xff) ,
3433 ((val >> 8) & 0xff) );
3434 }
3435 }
3436 }
3437
3438 /* we need to restore the sample rate from whatever it was */
3439 for(i=0;i<NR_HW_CH;i++) {
3440 struct i810_state * state=card->states[i];
3441 if(state) {
3442 if(state->pm_saved_adc_rate)
3443 i810_set_adc_rate(state,state->pm_saved_adc_rate);
3444 if(state->pm_saved_dac_rate)
3445 i810_set_dac_rate(state,state->pm_saved_dac_rate);
3446 }
3447 }
3448
3449
3450 card->pm_suspended = 0;
3451
3452 /* any processes that were reading/writing during the suspend
3453 probably ended up here */
3454 for(i=0;i<NR_HW_CH;i++) {
3455 struct i810_state *state = card->states[i];
3456 if(state) wake_up(&state->dmabuf.wait);
3457 }
3458
3459 return 0;
3460 }
3461 #endif /* CONFIG_PM */
3462
3463 MODULE_AUTHOR("");
3464 MODULE_DESCRIPTION("Intel 810 audio support");
3465 MODULE_LICENSE("GPL");
3466 MODULE_PARM(ftsodell, "i");
3467 MODULE_PARM(clocking, "i");
3468 MODULE_PARM(strict_clocking, "i");
3469 MODULE_PARM(spdif_locked, "i");
3470
3471 #define I810_MODULE_NAME "intel810_audio"
3472
3473 static struct pci_driver i810_pci_driver = {
3474 .name = I810_MODULE_NAME,
3475 .id_table = i810_pci_tbl,
3476 .probe = i810_probe,
3477 .remove = __devexit_p(i810_remove),
3478 #ifdef CONFIG_PM
3479 .suspend = i810_pm_suspend,
3480 .resume = i810_pm_resume,
3481 #endif /* CONFIG_PM */
3482 };
3483
3484
3485 static int __init i810_init_module (void)
3486 {
3487 printk(KERN_INFO "Intel 810 + AC97 Audio, version "
3488 DRIVER_VERSION ", " __TIME__ " " __DATE__ "\n");
3489
3490 if (!pci_register_driver(&i810_pci_driver)) {
3491 pci_unregister_driver(&i810_pci_driver);
3492 return -ENODEV;
3493 }
3494 if(ftsodell != 0) {
3495 printk("i810_audio: ftsodell is now a deprecated option.\n");
3496 }
3497 if(spdif_locked > 0 ) {
3498 if(spdif_locked == 32000 || spdif_locked == 44100 || spdif_locked == 48000) {
3499 printk("i810_audio: Enabling S/PDIF at sample rate %dHz.\n", spdif_locked);
3500 } else {
3501 printk("i810_audio: S/PDIF can only be locked to 32000, 44100, or 48000Hz.\n");
3502 spdif_locked = 0;
3503 }
3504 }
3505
3506 return 0;
3507 }
3508
3509 static void __exit i810_cleanup_module (void)
3510 {
3511 pci_unregister_driver(&i810_pci_driver);
3512 }
3513
3514 module_init(i810_init_module);
3515 module_exit(i810_cleanup_module);
3516
3517 /*
3518 Local Variables:
3519 c-basic-offset: 8
3520 End:
3521 */
MOXA 2.6.9 from sdlinux-moxaart.tgz