arch/sh/drivers/pci/pci-st40.c

   1 /*
   2  * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
   3  *
   4  * May be copied or modified under the terms of the GNU General Public
   5  * License.  See linux/COPYING for more information.
   6  *
   7  * Support functions for the ST40 PCI hardware.
   8  */
   9
  10 #include <linux/config.h>
  11 #include <linux/kernel.h>
  12 #include <linux/smp.h>
  13 #include <linux/smp_lock.h>
  14 #include <linux/init.h>
  15 #include <linux/errno.h>
  16 #include <linux/pci.h>
  17 #include <linux/delay.h>
  18 #include <linux/types.h>
  19 #include <asm/pci.h>
  20 #include <linux/irq.h>
  21
  22 #include "pci-st40.h"
  23
  24 /* This is in P2 of course */
  25 #define ST40PCI_BASE_ADDRESS     (0xb0000000)
  26 #define ST40PCI_MEM_ADDRESS      (ST40PCI_BASE_ADDRESS+0x0)
  27 #define ST40PCI_IO_ADDRESS       (ST40PCI_BASE_ADDRESS+0x06000000)
  28 #define ST40PCI_REG_ADDRESS      (ST40PCI_BASE_ADDRESS+0x07000000)
  29
  30 #define ST40PCI_REG(x) (ST40PCI_REG_ADDRESS+(ST40PCI_##x))
  31
  32 #define ST40PCI_WRITE(reg,val) writel((val),ST40PCI_REG(reg))
  33 #define ST40PCI_WRITE_SHORT(reg,val) writew((val),ST40PCI_REG(reg))
  34 #define ST40PCI_WRITE_BYTE(reg,val) writeb((val),ST40PCI_REG(reg))
  35
  36 #define ST40PCI_READ(reg) readl(ST40PCI_REG(reg))
  37 #define ST40PCI_READ_SHORT(reg) readw(ST40PCI_REG(reg))
  38 #define ST40PCI_READ_BYTE(reg) readb(ST40PCI_REG(reg))
  39
  40 #define ST40PCI_SERR_IRQ        64
  41 #define ST40PCI_SERR_INT_GROUP  0
  42 #define ST40PCI_SERR_INT_POS    0
  43 #define ST40PCI_SERR_INT_PRI    15
  44
  45 #define ST40PCI_ERR_IRQ        65
  46 #define ST40PCI_ERR_INT_GROUP   1
  47 #define ST40PCI_ERR_INT_POS     1
  48 #define ST40PCI_ERR_INT_PRI     14
  49
  50
  51 /* Macros to extract PLL params */
  52 #define PLL_MDIV(reg)  ( ((unsigned)reg) & 0xff )
  53 #define PLL_NDIV(reg) ( (((unsigned)reg)>>8) & 0xff )
  54 #define PLL_PDIV(reg) ( (((unsigned)reg)>>16) & 0x3 )
  55 #define PLL_SETUP(reg) ( (((unsigned)reg)>>19) & 0x1ff )
  56
  57 /* Build up the appropriate settings */
  58 #define PLL_SET(mdiv,ndiv,pdiv,setup) \
  59 ( ((mdiv)&0xff) | (((ndiv)&0xff)<<8) | (((pdiv)&3)<<16)| (((setup)&0x1ff)<<19))
  60
  61 #define PLLPCICR (0xbb040000+0x10)
  62
  63 #define PLLPCICR_POWERON (1<<28)
  64 #define PLLPCICR_OUT_EN (1<<29)
  65 #define PLLPCICR_LOCKSELECT (1<<30)
  66 #define PLLPCICR_LOCK (1<<31)
  67
  68
  69 #define PLL_25MHZ 0x793c8512
  70 #define PLL_33MHZ PLL_SET(18,88,3,295)
  71
  72
  73 static __init void SetPCIPLL(void)
  74 {
  75         /* Stop the PLL */
  76         writel(0, PLLPCICR);
  77
  78         /* Always run at 33Mhz. The PCI clock is totally async
  79          * to the rest of the system
  80          */
  81         writel(PLL_33MHZ | PLLPCICR_POWERON, PLLPCICR);
  82
  83         printk("ST40PCI: Waiting for PCI PLL to lock\n");
  84         while ((readl(PLLPCICR) & PLLPCICR_LOCK) == 0);
  85         writel(readl(PLLPCICR) | PLLPCICR_OUT_EN, PLLPCICR);
  86 }
  87
  88
  89 static irqreturn_t st40_pci_irq(int irq, void *dev_instance, struct pt_regs *regs)
  90 {
  91
  92         unsigned pci_int, pci_air, pci_cir, pci_aint;
  93
  94         pci_int = ST40PCI_READ(INT);
  95         pci_cir = ST40PCI_READ(CIR);
  96         pci_air = ST40PCI_READ(AIR);
  97
  98         if (pci_int) {
  99                 printk("PCI INTERRUPT!\n");
 100                 printk("PCI INT -> 0x%x\n", pci_int & 0xffff);
 101                 printk("PCI AIR -> 0x%x\n", pci_air);
 102                 printk("PCI CIR -> 0x%x\n", pci_cir);
 103                 ST40PCI_WRITE(INT, ~0);
 104         }
 105
 106         pci_aint = ST40PCI_READ(AINT);
 107         if (pci_aint) {
 108                 printk("PCI ARB INTERRUPT!\n");
 109                 printk("PCI AINT -> 0x%x\n", pci_aint);
 110                 printk("PCI AIR -> 0x%x\n", pci_air);
 111                 printk("PCI CIR -> 0x%x\n", pci_cir);
 112                 ST40PCI_WRITE(AINT, ~0);
 113         }
 114
 115         return IRQ_HANDLED;
 116 }
 117
 118
 119 /* Rounds a number UP to the nearest power of two. Used for
 120  * sizing the PCI window.
 121  */
 122 static u32 __init r2p2(u32 num)
 123 {
 124         int i = 31;
 125         u32 tmp = num;
 126
 127         if (num == 0)
 128                 return 0;
 129
 130         do {
 131                 if (tmp & (1 << 31))
 132                         break;
 133                 i--;
 134                 tmp <<= 1;
 135         } while (i >= 0);
 136
 137         tmp = 1 << i;
 138         /* If the original number isn't a power of 2, round it up */
 139         if (tmp != num)
 140                 tmp <<= 1;
 141
 142         return tmp;
 143 }
 144
 145 static void __init pci_fixup_ide_bases(struct pci_dev *d)
 146 {
 147         int i;
 148
 149         /*
 150          * PCI IDE controllers use non-standard I/O port decoding, respect it.
 151          */
 152         if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
 153                 return;
 154         printk("PCI: IDE base address fixup for %s\n", d->slot_name);
 155         for(i=0; i<4; i++) {
 156                 struct resource *r = &d->resource[i];
 157                 if ((r->start & ~0x80) == 0x374) {
 158                         r->start |= 2;
 159                         r->end = r->start;
 160                 }
 161         }
 162 }
 163 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
 164
 165 int __init st40pci_init(unsigned memStart, unsigned memSize)
 166 {
 167         u32 lsr0;
 168
 169         SetPCIPLL();
 170
 171         /* Initialises the ST40 pci subsystem, performing a reset, then programming
 172          * up the address space decoders appropriately
 173          */
 174
 175         /* Should reset core here as well methink */
 176
 177         ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_SOFT_RESET);
 178
 179         /* Loop while core resets */
 180         while (ST40PCI_READ(CR) & CR_SOFT_RESET);
 181
 182         /* Now, lets reset all the cards on the bus with extreme prejudice */
 183         ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_RSTCTL);
 184         udelay(250);
 185
 186         /* Set bus active, take it out of reset */
 187         ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_CFINT | CR_PFCS | CR_PFE);
 188
 189         /* The PCI spec says that no access must be made to the bus until 1 second
 190          * after reset. This seem ludicrously long, but some delay is needed here
 191          */
 192         mdelay(1000);
 193
 194         /* Switch off interrupts */
 195         ST40PCI_WRITE(INTM, 0);
 196         ST40PCI_WRITE(AINT, 0);
 197
 198         /* Allow it to be a master */
 199
 200         ST40PCI_WRITE_SHORT(CSR_CMD,
 201                             PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 202                             PCI_COMMAND_IO);
 203
 204         /* Accesse to the 0xb0000000 -> 0xb6000000 area will go through to 0x10000000 -> 0x16000000
 205          * on the PCI bus. This allows a nice 1-1 bus to phys mapping.
 206          */
 207
 208
 209         ST40PCI_WRITE(MBR, 0x10000000);
 210         /* Always set the max size 128M (actually, it is only 96MB wide) */
 211         ST40PCI_WRITE(MBMR, 0x07ff0000);
 212
 213         /* I/O addresses are mapped at 0xb6000000 -> 0xb7000000. These are changed to 0, to
 214          * allow cards that have legacy io such as vga to function correctly. This gives a
 215          * maximum of 64K of io/space as only the bottom 16 bits of the address are copied
 216          * over to the bus  when the transaction is made. 64K of io space is more than enough
 217          */
 218         ST40PCI_WRITE(IOBR, 0x0);
 219         /* Set up the 64K window */
 220         ST40PCI_WRITE(IOBMR, 0x0);
 221
 222         /* Now we set up the mbars so the PCI bus can see the memory of the machine */
 223
 224         if (memSize < (64 * 1024)) {
 225                 printk("Ridiculous memory size of 0x%x?\n",memSize);
 226                 return 0;
 227         }
 228
 229         lsr0 =
 230             (memSize >
 231              (512 * 1024 * 1024)) ? 0x1fff0001 : ((r2p2(memSize) -
 232                                                    0x10000) | 0x1);
 233
 234         ST40PCI_WRITE(LSR0, lsr0);
 235
 236         ST40PCI_WRITE(CSR_MBAR0, memStart);
 237         ST40PCI_WRITE(LAR0, memStart);
 238
 239         /* Maximise timeout values */
 240         ST40PCI_WRITE_BYTE(CSR_TRDY, 0xff);
 241         ST40PCI_WRITE_BYTE(CSR_RETRY, 0xff);
 242         ST40PCI_WRITE_BYTE(CSR_MIT, 0xff);
 243
 244
 245         /* Install the pci interrupt handlers */
 246         make_intc2_irq(ST40PCI_SERR_IRQ, INTC2_BASE0,
 247                        ST40PCI_SERR_INT_GROUP, ST40PCI_SERR_INT_POS,
 248                        ST40PCI_SERR_INT_PRI);
 249
 250         make_intc2_irq(ST40PCI_ERR_IRQ, INTC2_BASE0, ST40PCI_ERR_INT_GROUP,
 251                        ST40PCI_ERR_INT_POS, ST40PCI_ERR_INT_PRI);
 252
 253
 254         return 1;
 255 }
 256
 257 char * __init pcibios_setup(char *str)
 258 {
 259         return str;
 260 }
 261
 262
 263 #define SET_CONFIG_BITS(bus,devfn,where)\
 264   (((bus) << 16) | ((devfn) << 8) | ((where) & ~3) | (bus!=0))
 265
 266 #define CONFIG_CMD(bus, devfn, where) SET_CONFIG_BITS(bus->number,devfn,where)
 267
 268
 269 static int CheckForMasterAbort(void)
 270 {
 271         if (ST40PCI_READ(INT) & INT_MADIM) {
 272                 /* Should we clear config space version as well ??? */
 273                 ST40PCI_WRITE(INT, INT_MADIM);
 274                 ST40PCI_WRITE_SHORT(CSR_STATUS, 0);
 275                 return 1;
 276         }
 277
 278         return 0;
 279 }
 280
 281 /* Write to config register */
 282 static int st40pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
 283 {
 284         ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
 285         switch (size) {
 286                 case 1:
 287                         *val = (u8)ST40PCI_READ_BYTE(PDR + (where & 3));
 288                         break;
 289                 case 2:
 290                         *val = (u16)ST40PCI_READ_SHORT(PDR + (where & 2));
 291                         break;
 292                 case 4:
 293                         *val = ST40PCI_READ(PDR);
 294                         break;
 295         }
 296
 297         if (CheckForMasterAbort()){
 298                 switch (size) {
 299                         case 1:
 300                                 *val = (u8)0xff;
 301                                 break;
 302                         case 2:
 303                                 *val = (u16)0xffff;
 304                                 break;
 305                         case 4:
 306                                 *val = 0xffffffff;
 307                                 break;
 308                 }
 309         }
 310
 311         return PCIBIOS_SUCCESSFUL;
 312 }
 313
 314 static int st40pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 315 {
 316         ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
 317
 318         switch (size) {
 319                 case 1:
 320                         ST40PCI_WRITE_BYTE(PDR + (where & 3), (u8)val);
 321                         break;
 322                 case 2:
 323                         ST40PCI_WRITE_SHORT(PDR + (where & 2), (u16)val);
 324                         break;
 325                 case 4:
 326                         ST40PCI_WRITE(PDR, val);
 327                         break;
 328         }
 329
 330         CheckForMasterAbort();
 331
 332         return PCIBIOS_SUCCESSFUL;
 333 }
 334
 335 static struct pci_ops pci_config_ops = {
 336         .read =         st40pci_read,
 337         .write =        st40pci_write,
 338 };
 339
 340
 341 /* Everything hangs off this */
 342 static struct pci_bus *pci_root_bus;
 343
 344
 345 static u8 __init no_swizzle(struct pci_dev *dev, u8 * pin)
 346 {
 347         return PCI_SLOT(dev->devfn);
 348 }
 349
 350
 351 /* This needs to be shunted out of here into the board specific bit */
 352 #define HARP_PCI_IRQ    1
 353 #define HARP_BRIDGE_IRQ 2
 354 #define OVERDRIVE_SLOT0_IRQ 0
 355
 356 static int __init map_harp_irq(struct pci_dev *dev, u8 slot, u8 pin)
 357 {
 358         switch (slot) {
 359 #ifdef CONFIG_SH_STB1_HARP
 360         case 2:         /*This is the PCI slot on the */
 361                 return HARP_PCI_IRQ;
 362         case 1:         /* this is the bridge */
 363                 return HARP_BRIDGE_IRQ;
 364 #elif defined(CONFIG_SH_STB1_OVERDRIVE)
 365         case 1:
 366         case 2:
 367         case 3:
 368                 return slot - 1;
 369 #else
 370 #error Unknown board
 371 #endif
 372         default:
 373                 return -1;
 374         }
 375 }
 376
 377 void __init pcibios_init(void)
 378 {
 379         extern unsigned long memory_start, memory_end;
 380
 381         if (sh_mv.mv_init_pci != NULL) {
 382                 sh_mv.mv_init_pci();
 383         }
 384
 385         /* The pci subsytem needs to know where memory is and how much
 386          * of it there is. I've simply made these globals. A better mechanism
 387          * is probably needed.
 388          */
 389         st40pci_init(PHYSADDR(memory_start),
 390                      PHYSADDR(memory_end) - PHYSADDR(memory_start));
 391
 392         if (request_irq(ST40PCI_ERR_IRQ, st40_pci_irq,
 393                         SA_INTERRUPT, "st40pci", NULL)) {
 394                 printk(KERN_ERR "st40pci: Cannot hook interrupt\n");
 395                 return;
 396         }
 397
 398         /* Enable the PCI interrupts on the device */
 399         ST40PCI_WRITE(INTM, ~0);
 400         ST40PCI_WRITE(AINT, ~0);
 401
 402         /* Map the io address apprioately */
 403 #ifdef CONFIG_HD64465
 404         hd64465_port_map(PCIBIOS_MIN_IO, (64 * 1024) - PCIBIOS_MIN_IO + 1,
 405                          ST40_IO_ADDR + PCIBIOS_MIN_IO, 0);
 406 #endif
 407
 408         /* ok, do the scan man */
 409         pci_root_bus = pci_scan_bus(0, &pci_config_ops, NULL);
 410         pci_assign_unassigned_resources();
 411         pci_fixup_irqs(no_swizzle, map_harp_irq);
 412
 413 }
 414
 415 void __init pcibios_fixup_bus(struct pci_bus *bus)
 416 {
 417 }