include/asm-arm/cacheflush.h

   1 /*
   2  *  linux/include/asm-arm/cacheflush.h
   3  *
   4  *  Copyright (C) 1999-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef _ASMARM_CACHEFLUSH_H
  11 #define _ASMARM_CACHEFLUSH_H
  12
  13 #include <linux/config.h>
  14 #include <linux/sched.h>
  15 #include <linux/mm.h>
  16
  17 #include <asm/mman.h>
  18 #include <asm/glue.h>
  19
  20 /*
  21  *      Cache Model
  22  *      ===========
  23  */
  24 #undef _CACHE
  25 #undef MULTI_CACHE
  26
  27 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
  28 # ifdef _CACHE
  29 #  define MULTI_CACHE 1
  30 # else
  31 #  define _CACHE v3
  32 # endif
  33 #endif
  34
  35 #if defined(CONFIG_CPU_ARM720T)
  36 # ifdef _CACHE
  37 #  define MULTI_CACHE 1
  38 # else
  39 #  define _CACHE v4
  40 # endif
  41 #endif
  42
  43 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
  44     defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
  45 # define MULTI_CACHE 1
  46 #endif
  47
  48 #if defined(CONFIG_CPU_ARM926T)
  49 # ifdef _CACHE
  50 #  define MULTI_CACHE 1
  51 # else
  52 #  define _CACHE arm926
  53 # endif
  54 #endif
  55
  56 #if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
  57 # ifdef _CACHE
  58 #  define MULTI_CACHE 1
  59 # else
  60 #  define _CACHE v4wb
  61 # endif
  62 #endif
  63
  64 #if defined(CONFIG_CPU_XSCALE)
  65 # ifdef _CACHE
  66 #  define MULTI_CACHE 1
  67 # else
  68 #  define _CACHE xscale
  69 # endif
  70 #endif
  71
  72 #if defined(CONFIG_CPU_V6)
  73 //# ifdef _CACHE
  74 #  define MULTI_CACHE 1
  75 //# else
  76 //#  define _CACHE v6
  77 //# endif
  78 #endif
  79
  80 #if 1   // add by Victor Yu. 06-08-2005
  81 #if defined(CONFIG_CPU_FA520) || defined(CONFIG_CPU_FA526) || defined(CONFIG_CPU_FA626)
  82 # ifdef _CACHE
  83 #  define MULTI_CACHE 1
  84 # else
  85 #  define _CACHE fa
  86 # endif
  87 #endif
  88 #endif
  89
  90 #if !defined(_CACHE) && !defined(MULTI_CACHE)
  91 #error Unknown cache maintainence model
  92 #endif
  93
  94 /*
  95  * This flag is used to indicate that the page pointed to by a pte
  96  * is dirty and requires cleaning before returning it to the user.
  97  */
  98 #define PG_dcache_dirty PG_arch_1
  99
 100 /*
 101  *      MM Cache Management
 102  *      ===================
 103  *
 104  *      The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
 105  *      implement these methods.
 106  *
 107  *      Start addresses are inclusive and end addresses are exclusive;
 108  *      start addresses should be rounded down, end addresses up.
 109  *
 110  *      See Documentation/cachetlb.txt for more information.
 111  *      Please note that the implementation of these, and the required
 112  *      effects are cache-type (VIVT/VIPT/PIPT) specific.
 113  *
 114  *      flush_cache_kern_all()
 115  *
 116  *              Unconditionally clean and invalidate the entire cache.
 117  *
 118  *      flush_cache_user_mm(mm)
 119  *
 120  *              Clean and invalidate all user space cache entries
 121  *              before a change of page tables.
 122  *
 123  *      flush_cache_user_range(start, end, flags)
 124  *
 125  *              Clean and invalidate a range of cache entries in the
 126  *              specified address space before a change of page tables.
 127  *              - start - user start address (inclusive, page aligned)
 128  *              - end   - user end address   (exclusive, page aligned)
 129  *              - flags - vma->vm_flags field
 130  *
 131  *      coherent_kern_range(start, end)
 132  *
 133  *              Ensure coherency between the Icache and the Dcache in the
 134  *              region described by start, end.  If you have non-snooping
 135  *              Harvard caches, you need to implement this function.
 136  *              - start  - virtual start address
 137  *              - end    - virtual end address
 138  *
 139  *      DMA Cache Coherency
 140  *      ===================
 141  *
 142  *      dma_inv_range(start, end)
 143  *
 144  *              Invalidate (discard) the specified virtual address range.
 145  *              May not write back any entries.  If 'start' or 'end'
 146  *              are not cache line aligned, those lines must be written
 147  *              back.
 148  *              - start  - virtual start address
 149  *              - end    - virtual end address
 150  *
 151  *      dma_clean_range(start, end)
 152  *
 153  *              Clean (write back) the specified virtual address range.
 154  *              - start  - virtual start address
 155  *              - end    - virtual end address
 156  *
 157  *      dma_flush_range(start, end)
 158  *
 159  *              Clean and invalidate the specified virtual address range.
 160  *              - start  - virtual start address
 161  *              - end    - virtual end address
 162  */
 163
 164 struct cpu_cache_fns {
 165         void (*flush_kern_all)(void);
 166         void (*flush_user_all)(void);
 167         void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
 168
 169         void (*coherent_kern_range)(unsigned long, unsigned long);
 170         void (*coherent_user_range)(unsigned long, unsigned long);
 171         void (*flush_kern_dcache_page)(void *);
 172
 173         void (*dma_inv_range)(unsigned long, unsigned long);
 174         void (*dma_clean_range)(unsigned long, unsigned long);
 175         void (*dma_flush_range)(unsigned long, unsigned long);
 176 };
 177
 178 /*
 179  * Select the calling method
 180  */
 181 #ifdef MULTI_CACHE
 182
 183 extern struct cpu_cache_fns cpu_cache;
 184
 185 #define __cpuc_flush_kern_all           cpu_cache.flush_kern_all
 186 #define __cpuc_flush_user_all           cpu_cache.flush_user_all
 187 #define __cpuc_flush_user_range         cpu_cache.flush_user_range
 188 #define __cpuc_coherent_kern_range      cpu_cache.coherent_kern_range
 189 #define __cpuc_coherent_user_range      cpu_cache.coherent_user_range
 190 #define __cpuc_flush_dcache_page        cpu_cache.flush_kern_dcache_page
 191
 192 /*
 193  * These are private to the dma-mapping API.  Do not use directly.
 194  * Their sole purpose is to ensure that data held in the cache
 195  * is visible to DMA, or data written by DMA to system memory is
 196  * visible to the CPU.
 197  */
 198 #define dmac_inv_range                  cpu_cache.dma_inv_range
 199 #define dmac_clean_range                cpu_cache.dma_clean_range
 200 #define dmac_flush_range                cpu_cache.dma_flush_range
 201
 202 #else
 203
 204 #define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
 205 #define __cpuc_flush_user_all           __glue(_CACHE,_flush_user_cache_all)
 206 #define __cpuc_flush_user_range         __glue(_CACHE,_flush_user_cache_range)
 207 #define __cpuc_coherent_kern_range      __glue(_CACHE,_coherent_kern_range)
 208 #define __cpuc_coherent_user_range      __glue(_CACHE,_coherent_user_range)
 209 #define __cpuc_flush_dcache_page        __glue(_CACHE,_flush_kern_dcache_page)
 210
 211 extern void __cpuc_flush_kern_all(void);
 212 extern void __cpuc_flush_user_all(void);
 213 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
 214 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
 215 extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
 216 extern void __cpuc_flush_dcache_page(void *);
 217
 218 /*
 219  * These are private to the dma-mapping API.  Do not use directly.
 220  * Their sole purpose is to ensure that data held in the cache
 221  * is visible to DMA, or data written by DMA to system memory is
 222  * visible to the CPU.
 223  */
 224 #define dmac_inv_range                  __glue(_CACHE,_dma_inv_range)
 225 #define dmac_clean_range                __glue(_CACHE,_dma_clean_range)
 226 #define dmac_flush_range                __glue(_CACHE,_dma_flush_range)
 227
 228 extern void dmac_inv_range(unsigned long, unsigned long);
 229 extern void dmac_clean_range(unsigned long, unsigned long);
 230 extern void dmac_flush_range(unsigned long, unsigned long);
 231
 232 #endif
 233
 234 /*
 235  * flush_cache_vmap() is used when creating mappings (eg, via vmap,
 236  * vmalloc, ioremap etc) in kernel space for pages.  Since the
 237  * direct-mappings of these pages may contain cached data, we need
 238  * to do a full cache flush to ensure that writebacks don't corrupt
 239  * data placed into these pages via the new mappings.
 240  */
 241 #define flush_cache_vmap(start, end)            flush_cache_all()
 242 #define flush_cache_vunmap(start, end)          flush_cache_all()
 243
 244 /*
 245  * Copy user data from/to a page which is mapped into a different
 246  * processes address space.  Really, we want to allow our "user
 247  * space" model to handle this.
 248  */
 249 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
 250         do {                                    \
 251                 flush_cache_page(vma, vaddr);   \
 252                 memcpy(dst, src, len);          \
 253                 flush_dcache_page(page);        \
 254         } while (0)
 255
 256 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 257         do {                                    \
 258                 flush_cache_page(vma, vaddr);   \
 259                 memcpy(dst, src, len);          \
 260         } while (0)
 261
 262 /*
 263  * Convert calls to our calling convention.
 264  */
 265 #define flush_cache_all()               __cpuc_flush_kern_all()
 266
 267 static inline void flush_cache_mm(struct mm_struct *mm)
 268 {
 269         if (current->active_mm == mm)
 270                 __cpuc_flush_user_all();
 271 }
 272
 273 static inline void
 274 flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 275 {
 276         if (current->active_mm == vma->vm_mm)
 277                 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
 278                                         vma->vm_flags);
 279 }
 280
 281 static inline void
 282 flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr)
 283 {
 284         if (current->active_mm == vma->vm_mm) {
 285                 unsigned long addr = user_addr & PAGE_MASK;
 286                 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
 287         }
 288 }
 289
 290 /*
 291  * flush_cache_user_range is used when we want to ensure that the
 292  * Harvard caches are synchronised for the user space address range.
 293  * This is used for the ARM private sys_cacheflush system call.
 294  */
 295 #define flush_cache_user_range(vma,start,end) \
 296         __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
 297
 298 /*
 299  * Perform necessary cache operations to ensure that data previously
 300  * stored within this range of addresses can be executed by the CPU.
 301  */
 302 #define flush_icache_range(s,e)         __cpuc_coherent_kern_range(s,e)
 303
 304 /*
 305  * Perform necessary cache operations to ensure that the TLB will
 306  * see data written in the specified area.
 307  */
 308 #define clean_dcache_area(start,size)   cpu_dcache_clean_area(start, size)
 309
 310 /*
 311  * flush_dcache_page is used when the kernel has written to the page
 312  * cache page at virtual address page->virtual.
 313  *
 314  * If this page isn't mapped (ie, page_mapping == NULL), or it might
 315  * have userspace mappings, then we _must_ always clean + invalidate
 316  * the dcache entries associated with the kernel mapping.
 317  *
 318  * Otherwise we can defer the operation, and clean the cache when we are
 319  * about to change to user space.  This is the same method as used on SPARC64.
 320  * See update_mmu_cache for the user space part.
 321  */
 322 extern void flush_dcache_page(struct page *);
 323
 324 #define flush_dcache_mmap_lock(mapping) \
 325         spin_lock_irq(&(mapping)->tree_lock)
 326 #define flush_dcache_mmap_unlock(mapping) \
 327         spin_unlock_irq(&(mapping)->tree_lock)
 328
 329 #define flush_icache_user_range(vma,page,addr,len) \
 330         flush_dcache_page(page)
 331
 332 /*
 333  * We don't appear to need to do anything here.  In fact, if we did, we'd
 334  * duplicate cache flushing elsewhere performed by flush_dcache_page().
 335  */
 336 #define flush_icache_page(vma,page)     do { } while (0)
 337
 338 #endif