drivers/scsi/sata_vsc.c

   1 /*
   2  *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
   3  *
   4  *  Maintained by:  Jeremy Higdon @ SGI
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2004 SGI
   9  *
  10  *  Bits from Jeff Garzik, Copyright RedHat, Inc.
  11  *
  12  *  This file is subject to the terms and conditions of the GNU General Public
  13  *  License.  See the file "COPYING" in the main directory of this archive
  14  *  for more details.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/init.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/delay.h>
  23 #include <linux/interrupt.h>
  24 #include "scsi.h"
  25 #include <scsi/scsi_host.h>
  26 #include <linux/libata.h>
  27
  28 #define DRV_NAME        "sata_vsc"
  29 #define DRV_VERSION     "0.01"
  30
  31 /* Interrupt register offsets (from chip base address) */
  32 #define VSC_SATA_INT_STAT_OFFSET        0x00
  33 #define VSC_SATA_INT_MASK_OFFSET        0x04
  34
  35 /* Taskfile registers offsets */
  36 #define VSC_SATA_TF_CMD_OFFSET          0x00
  37 #define VSC_SATA_TF_DATA_OFFSET         0x00
  38 #define VSC_SATA_TF_ERROR_OFFSET        0x04
  39 #define VSC_SATA_TF_FEATURE_OFFSET      0x06
  40 #define VSC_SATA_TF_NSECT_OFFSET        0x08
  41 #define VSC_SATA_TF_LBAL_OFFSET         0x0c
  42 #define VSC_SATA_TF_LBAM_OFFSET         0x10
  43 #define VSC_SATA_TF_LBAH_OFFSET         0x14
  44 #define VSC_SATA_TF_DEVICE_OFFSET       0x18
  45 #define VSC_SATA_TF_STATUS_OFFSET       0x1c
  46 #define VSC_SATA_TF_COMMAND_OFFSET      0x1d
  47 #define VSC_SATA_TF_ALTSTATUS_OFFSET    0x28
  48 #define VSC_SATA_TF_CTL_OFFSET          0x29
  49
  50 /* DMA base */
  51 #define VSC_SATA_UP_DESCRIPTOR_OFFSET   0x64
  52 #define VSC_SATA_UP_DATA_BUFFER_OFFSET  0x6C
  53 #define VSC_SATA_DMA_CMD_OFFSET         0x70
  54
  55 /* SCRs base */
  56 #define VSC_SATA_SCR_STATUS_OFFSET      0x100
  57 #define VSC_SATA_SCR_ERROR_OFFSET       0x104
  58 #define VSC_SATA_SCR_CONTROL_OFFSET     0x108
  59
  60 /* Port stride */
  61 #define VSC_SATA_PORT_OFFSET            0x200
  62
  63
  64 static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
  65 {
  66         if (sc_reg > SCR_CONTROL)
  67                 return 0xffffffffU;
  68         return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
  69 }
  70
  71
  72 static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
  73                                u32 val)
  74 {
  75         if (sc_reg > SCR_CONTROL)
  76                 return;
  77         writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
  78 }
  79
  80
  81 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
  82 {
  83         unsigned long mask_addr;
  84         u8 mask;
  85
  86         mask_addr = (unsigned long) ap->host_set->mmio_base +
  87                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
  88         mask = readb(mask_addr);
  89         if (ctl & ATA_NIEN)
  90                 mask |= 0x80;
  91         else
  92                 mask &= 0x7F;
  93         writeb(mask, mask_addr);
  94 }
  95
  96
  97 static void vsc_sata_tf_load(struct ata_port *ap, struct ata_taskfile *tf)
  98 {
  99         struct ata_ioports *ioaddr = &ap->ioaddr;
 100         unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
 101
 102         /*
 103          * The only thing the ctl register is used for is SRST.
 104          * That is not enabled or disabled via tf_load.
 105          * However, if ATA_NIEN is changed, then we need to change the interrupt register.
 106          */
 107         if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
 108                 ap->last_ctl = tf->ctl;
 109                 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
 110         }
 111         if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
 112                 writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
 113                 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
 114                 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
 115                 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
 116                 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
 117         } else if (is_addr) {
 118                 writew(tf->feature, ioaddr->feature_addr);
 119                 writew(tf->nsect, ioaddr->nsect_addr);
 120                 writew(tf->lbal, ioaddr->lbal_addr);
 121                 writew(tf->lbam, ioaddr->lbam_addr);
 122                 writew(tf->lbah, ioaddr->lbah_addr);
 123         }
 124
 125         if (tf->flags & ATA_TFLAG_DEVICE)
 126                 writeb(tf->device, ioaddr->device_addr);
 127
 128         ata_wait_idle(ap);
 129 }
 130
 131
 132 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 133 {
 134         struct ata_ioports *ioaddr = &ap->ioaddr;
 135         u16 nsect, lbal, lbam, lbah;
 136
 137         nsect = tf->nsect = readw(ioaddr->nsect_addr);
 138         lbal = tf->lbal = readw(ioaddr->lbal_addr);
 139         lbam = tf->lbam = readw(ioaddr->lbam_addr);
 140         lbah = tf->lbah = readw(ioaddr->lbah_addr);
 141         tf->device = readw(ioaddr->device_addr);
 142
 143         if (tf->flags & ATA_TFLAG_LBA48) {
 144                 tf->hob_feature = readb(ioaddr->error_addr);
 145                 tf->hob_nsect = nsect >> 8;
 146                 tf->hob_lbal = lbal >> 8;
 147                 tf->hob_lbam = lbam >> 8;
 148                 tf->hob_lbah = lbah >> 8;
 149         }
 150 }
 151
 152
 153 /*
 154  * vsc_sata_interrupt
 155  *
 156  * Read the interrupt register and process for the devices that have them pending.
 157  */
 158 irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
 159 {
 160         struct ata_host_set *host_set = dev_instance;
 161         unsigned int i;
 162         unsigned int handled = 0;
 163         u32 int_status;
 164
 165         spin_lock(&host_set->lock);
 166
 167         int_status = readl(host_set->mmio_base + VSC_SATA_INT_STAT_OFFSET);
 168
 169         for (i = 0; i < host_set->n_ports; i++) {
 170                 if (int_status & ((u32) 0xFF << (8 * i))) {
 171                         struct ata_port *ap;
 172
 173                         ap = host_set->ports[i];
 174                         if (ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
 175                                 struct ata_queued_cmd *qc;
 176
 177                                 qc = ata_qc_from_tag(ap, ap->active_tag);
 178                                 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
 179                                         handled += ata_host_intr(ap, qc);
 180                         }
 181                 }
 182         }
 183
 184         spin_unlock(&host_set->lock);
 185
 186         return IRQ_RETVAL(handled);
 187 }
 188
 189
 190 static Scsi_Host_Template vsc_sata_sht = {
 191         .module                 = THIS_MODULE,
 192         .name                   = DRV_NAME,
 193         .ioctl                  = ata_scsi_ioctl,
 194         .queuecommand           = ata_scsi_queuecmd,
 195         .eh_strategy_handler    = ata_scsi_error,
 196         .can_queue              = ATA_DEF_QUEUE,
 197         .this_id                = ATA_SHT_THIS_ID,
 198         .sg_tablesize           = LIBATA_MAX_PRD,
 199         .max_sectors            = ATA_MAX_SECTORS,
 200         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 201         .emulated               = ATA_SHT_EMULATED,
 202         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 203         .proc_name              = DRV_NAME,
 204         .dma_boundary           = ATA_DMA_BOUNDARY,
 205         .slave_configure        = ata_scsi_slave_config,
 206         .bios_param             = ata_std_bios_param,
 207 };
 208
 209
 210 static struct ata_port_operations vsc_sata_ops = {
 211         .port_disable           = ata_port_disable,
 212         .tf_load                = vsc_sata_tf_load,
 213         .tf_read                = vsc_sata_tf_read,
 214         .exec_command           = ata_exec_command,
 215         .check_status           = ata_check_status,
 216         .dev_select             = ata_std_dev_select,
 217         .phy_reset              = sata_phy_reset,
 218         .bmdma_setup            = ata_bmdma_setup,
 219         .bmdma_start            = ata_bmdma_start,
 220         .qc_prep                = ata_qc_prep,
 221         .qc_issue               = ata_qc_issue_prot,
 222         .eng_timeout            = ata_eng_timeout,
 223         .irq_handler            = vsc_sata_interrupt,
 224         .irq_clear              = ata_bmdma_irq_clear,
 225         .scr_read               = vsc_sata_scr_read,
 226         .scr_write              = vsc_sata_scr_write,
 227         .port_start             = ata_port_start,
 228         .port_stop              = ata_port_stop,
 229 };
 230
 231 static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
 232 {
 233         port->cmd_addr          = base + VSC_SATA_TF_CMD_OFFSET;
 234         port->data_addr         = base + VSC_SATA_TF_DATA_OFFSET;
 235         port->error_addr        = base + VSC_SATA_TF_ERROR_OFFSET;
 236         port->feature_addr      = base + VSC_SATA_TF_FEATURE_OFFSET;
 237         port->nsect_addr        = base + VSC_SATA_TF_NSECT_OFFSET;
 238         port->lbal_addr         = base + VSC_SATA_TF_LBAL_OFFSET;
 239         port->lbam_addr         = base + VSC_SATA_TF_LBAM_OFFSET;
 240         port->lbah_addr         = base + VSC_SATA_TF_LBAH_OFFSET;
 241         port->device_addr       = base + VSC_SATA_TF_DEVICE_OFFSET;
 242         port->status_addr       = base + VSC_SATA_TF_STATUS_OFFSET;
 243         port->command_addr      = base + VSC_SATA_TF_COMMAND_OFFSET;
 244         port->altstatus_addr    = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
 245         port->ctl_addr          = base + VSC_SATA_TF_CTL_OFFSET;
 246         port->bmdma_addr        = base + VSC_SATA_DMA_CMD_OFFSET;
 247         port->scr_addr          = base + VSC_SATA_SCR_STATUS_OFFSET;
 248         writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
 249         writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
 250 }
 251
 252
 253 static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 254 {
 255         static int printed_version;
 256         struct ata_probe_ent *probe_ent = NULL;
 257         unsigned long base;
 258         void *mmio_base;
 259         int rc;
 260
 261         if (!printed_version++)
 262                 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
 263
 264         rc = pci_enable_device(pdev);
 265         if (rc)
 266                 return rc;
 267
 268         /*
 269          * Check if we have needed resource mapped.
 270          */
 271         if (pci_resource_len(pdev, 0) == 0) {
 272                 rc = -ENODEV;
 273                 goto err_out;
 274         }
 275
 276         rc = pci_request_regions(pdev, DRV_NAME);
 277         if (rc)
 278                 goto err_out;
 279
 280         /*
 281          * Use 32 bit DMA mask, because 64 bit address support is poor.
 282          */
 283         rc = pci_set_dma_mask(pdev, 0xFFFFFFFFULL);
 284         if (rc)
 285                 goto err_out_regions;
 286         rc = pci_set_consistent_dma_mask(pdev, 0xFFFFFFFFULL);
 287         if (rc)
 288                 goto err_out_regions;
 289
 290         probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
 291         if (probe_ent == NULL) {
 292                 rc = -ENOMEM;
 293                 goto err_out_regions;
 294         }
 295         memset(probe_ent, 0, sizeof(*probe_ent));
 296         probe_ent->pdev = pdev;
 297         INIT_LIST_HEAD(&probe_ent->node);
 298
 299         mmio_base = ioremap(pci_resource_start(pdev, 0),
 300                             pci_resource_len(pdev, 0));
 301         if (mmio_base == NULL) {
 302                 rc = -ENOMEM;
 303                 goto err_out_free_ent;
 304         }
 305         base = (unsigned long) mmio_base;
 306
 307         /*
 308          * Due to a bug in the chip, the default cache line size can't be used
 309          */
 310         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
 311
 312         probe_ent->sht = &vsc_sata_sht;
 313         probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 314                                 ATA_FLAG_MMIO | ATA_FLAG_SATA_RESET;
 315         probe_ent->port_ops = &vsc_sata_ops;
 316         probe_ent->n_ports = 4;
 317         probe_ent->irq = pdev->irq;
 318         probe_ent->irq_flags = SA_SHIRQ;
 319         probe_ent->mmio_base = mmio_base;
 320
 321         /* We don't care much about the PIO/UDMA masks, but the core won't like us
 322          * if we don't fill these
 323          */
 324         probe_ent->pio_mask = 0x1f;
 325         probe_ent->mwdma_mask = 0x07;
 326         probe_ent->udma_mask = 0x7f;
 327
 328         /* We have 4 ports per PCI function */
 329         vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
 330         vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
 331         vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
 332         vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);
 333
 334         pci_set_master(pdev);
 335
 336         /* FIXME: check ata_device_add return value */
 337         ata_device_add(probe_ent);
 338         kfree(probe_ent);
 339
 340         return 0;
 341
 342 err_out_free_ent:
 343         kfree(probe_ent);
 344 err_out_regions:
 345         pci_release_regions(pdev);
 346 err_out:
 347         pci_disable_device(pdev);
 348         return rc;
 349 }
 350
 351
 352 /*
 353  * 0x1725/0x7174 is the Vitesse VSC-7174
 354  * 0x8086/0x3200 is the Intel 31244, which is supposed to be identical
 355  * compatibility is untested as of yet
 356  */
 357 static struct pci_device_id vsc_sata_pci_tbl[] = {
 358         { 0x1725, 0x7174, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
 359         { 0x8086, 0x3200, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
 360         { }
 361 };
 362
 363
 364 static struct pci_driver vsc_sata_pci_driver = {
 365         .name                   = DRV_NAME,
 366         .id_table               = vsc_sata_pci_tbl,
 367         .probe                  = vsc_sata_init_one,
 368         .remove                 = ata_pci_remove_one,
 369 };
 370
 371
 372 static int __init vsc_sata_init(void)
 373 {
 374         return pci_module_init(&vsc_sata_pci_driver);
 375 }
 376
 377
 378 static void __exit vsc_sata_exit(void)
 379 {
 380         pci_unregister_driver(&vsc_sata_pci_driver);
 381 }
 382
 383
 384 MODULE_AUTHOR("Jeremy Higdon");
 385 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
 386 MODULE_LICENSE("GPL");
 387 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
 388
 389 module_init(vsc_sata_init);
 390 module_exit(vsc_sata_exit);