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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / scsi / sata_promise.c
blob67bdfb910560502c4756db9feb1d8ed759d6d8c0
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 * The contents of this file are subject to the Open
11 * Software License version 1.1 that can be found at
12 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
13 * by reference.
14 *
15 * Alternatively, the contents of this file may be used under the terms
16 * of the GNU General Public License version 2 (the "GPL") as distributed
17 * in the kernel source COPYING file, in which case the provisions of
18 * the GPL are applicable instead of the above. If you wish to allow
19 * the use of your version of this file only under the terms of the
20 * GPL and not to allow others to use your version of this file under
21 * the OSL, indicate your decision by deleting the provisions above and
22 * replace them with the notice and other provisions required by the GPL.
23 * If you do not delete the provisions above, a recipient may use your
24 * version of this file under either the OSL or the GPL.
25 *
26 */
27
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/blkdev.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
36 #include "scsi.h"
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
39 #include <asm/io.h>
40 #include "sata_promise.h"
41
42 #define DRV_NAME "sata_promise"
43 #define DRV_VERSION "1.00"
44
45
46 enum {
47 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
48 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
49 PDC_TBG_MODE = 0x41, /* TBG mode */
50 PDC_FLASH_CTL = 0x44, /* Flash control register */
51 PDC_PCI_CTL = 0x48, /* PCI control and status register */
52 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
53 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
54 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
55 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
56
57 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
58 (1<<8) | (1<<9) | (1<<10),
59
60 board_2037x = 0, /* FastTrak S150 TX2plus */
61 board_20319 = 1, /* FastTrak S150 TX4 */
62
63 PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */
64
65 PDC_RESET = (1 << 11), /* HDMA reset */
66 };
67
68
69 struct pdc_port_priv {
70 u8 *pkt;
71 dma_addr_t pkt_dma;
72 };
73
74 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
75 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
76 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
77 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
78 static void pdc_eng_timeout(struct ata_port *ap);
79 static int pdc_port_start(struct ata_port *ap);
80 static void pdc_port_stop(struct ata_port *ap);
81 static void pdc_phy_reset(struct ata_port *ap);
82 static void pdc_qc_prep(struct ata_queued_cmd *qc);
83 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
84 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
85 static void pdc_irq_clear(struct ata_port *ap);
86 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
87
88 static Scsi_Host_Template pdc_sata_sht = {
89 .module = THIS_MODULE,
90 .name = DRV_NAME,
91 .ioctl = ata_scsi_ioctl,
92 .queuecommand = ata_scsi_queuecmd,
93 .eh_strategy_handler = ata_scsi_error,
94 .can_queue = ATA_DEF_QUEUE,
95 .this_id = ATA_SHT_THIS_ID,
96 .sg_tablesize = LIBATA_MAX_PRD,
97 .max_sectors = ATA_MAX_SECTORS,
98 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
99 .emulated = ATA_SHT_EMULATED,
100 .use_clustering = ATA_SHT_USE_CLUSTERING,
101 .proc_name = DRV_NAME,
102 .dma_boundary = ATA_DMA_BOUNDARY,
103 .slave_configure = ata_scsi_slave_config,
104 .bios_param = ata_std_bios_param,
105 };
106
107 static struct ata_port_operations pdc_sata_ops = {
108 .port_disable = ata_port_disable,
109 .tf_load = pdc_tf_load_mmio,
110 .tf_read = ata_tf_read,
111 .check_status = ata_check_status,
112 .exec_command = pdc_exec_command_mmio,
113 .dev_select = ata_std_dev_select,
114 .phy_reset = pdc_phy_reset,
115 .qc_prep = pdc_qc_prep,
116 .qc_issue = pdc_qc_issue_prot,
117 .eng_timeout = pdc_eng_timeout,
118 .irq_handler = pdc_interrupt,
119 .irq_clear = pdc_irq_clear,
120 .scr_read = pdc_sata_scr_read,
121 .scr_write = pdc_sata_scr_write,
122 .port_start = pdc_port_start,
123 .port_stop = pdc_port_stop,
124 };
125
126 static struct ata_port_info pdc_port_info[] = {
127 /* board_2037x */
128 {
129 .sht = &pdc_sata_sht,
130 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
131 ATA_FLAG_SRST | ATA_FLAG_MMIO,
132 .pio_mask = 0x1f, /* pio0-4 */
133 .mwdma_mask = 0x07, /* mwdma0-2 */
134 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
135 .port_ops = &pdc_sata_ops,
136 },
137
138 /* board_20319 */
139 {
140 .sht = &pdc_sata_sht,
141 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
142 ATA_FLAG_SRST | ATA_FLAG_MMIO,
143 .pio_mask = 0x1f, /* pio0-4 */
144 .mwdma_mask = 0x07, /* mwdma0-2 */
145 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
146 .port_ops = &pdc_sata_ops,
147 },
148 };
149
150 static struct pci_device_id pdc_sata_pci_tbl[] = {
151 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
152 board_2037x },
153 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
154 board_2037x },
155 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
156 board_2037x },
157 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
158 board_2037x },
159 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
160 board_20319 },
161 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
162 board_20319 },
163 { } /* terminate list */
164 };
165
166
167 static struct pci_driver pdc_sata_pci_driver = {
168 .name = DRV_NAME,
169 .id_table = pdc_sata_pci_tbl,
170 .probe = pdc_sata_init_one,
171 .remove = ata_pci_remove_one,
172 };
173
174
175 static int pdc_port_start(struct ata_port *ap)
176 {
177 struct pci_dev *pdev = ap->host_set->pdev;
178 struct pdc_port_priv *pp;
179 int rc;
180
181 rc = ata_port_start(ap);
182 if (rc)
183 return rc;
184
185 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
186 if (!pp) {
187 rc = -ENOMEM;
188 goto err_out;
189 }
190 memset(pp, 0, sizeof(*pp));
191
192 pp->pkt = pci_alloc_consistent(pdev, 128, &pp->pkt_dma);
193 if (!pp->pkt) {
194 rc = -ENOMEM;
195 goto err_out_kfree;
196 }
197
198 ap->private_data = pp;
199
200 return 0;
201
202 err_out_kfree:
203 kfree(pp);
204 err_out:
205 ata_port_stop(ap);
206 return rc;
207 }
208
209
210 static void pdc_port_stop(struct ata_port *ap)
211 {
212 struct pci_dev *pdev = ap->host_set->pdev;
213 struct pdc_port_priv *pp = ap->private_data;
214
215 ap->private_data = NULL;
216 pci_free_consistent(pdev, 128, pp->pkt, pp->pkt_dma);
217 kfree(pp);
218 ata_port_stop(ap);
219 }
220
221
222 static void pdc_reset_port(struct ata_port *ap)
223 {
224 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
225 unsigned int i;
226 u32 tmp;
227
228 for (i = 11; i > 0; i--) {
229 tmp = readl(mmio);
230 if (tmp & PDC_RESET)
231 break;
232
233 udelay(100);
234
235 tmp |= PDC_RESET;
236 writel(tmp, mmio);
237 }
238
239 tmp &= ~PDC_RESET;
240 writel(tmp, mmio);
241 readl(mmio); /* flush */
242 }
243
244 static void pdc_phy_reset(struct ata_port *ap)
245 {
246 pdc_reset_port(ap);
247 sata_phy_reset(ap);
248 }
249
250 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
251 {
252 if (sc_reg > SCR_CONTROL)
253 return 0xffffffffU;
254 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
255 }
256
257
258 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
259 u32 val)
260 {
261 if (sc_reg > SCR_CONTROL)
262 return;
263 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
264 }
265
266 static void pdc_qc_prep(struct ata_queued_cmd *qc)
267 {
268 struct pdc_port_priv *pp = qc->ap->private_data;
269 unsigned int i;
270
271 VPRINTK("ENTER\n");
272
273 switch (qc->tf.protocol) {
274 case ATA_PROT_DMA:
275 ata_qc_prep(qc);
276 /* fall through */
277
278 case ATA_PROT_NODATA:
279 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
280 qc->dev->devno, pp->pkt);
281
282 if (qc->tf.flags & ATA_TFLAG_LBA48)
283 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
284 else
285 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
286
287 pdc_pkt_footer(&qc->tf, pp->pkt, i);
288 break;
289
290 default:
291 break;
292 }
293 }
294
295 static void pdc_eng_timeout(struct ata_port *ap)
296 {
297 u8 drv_stat;
298 struct ata_queued_cmd *qc;
299
300 DPRINTK("ENTER\n");
301
302 qc = ata_qc_from_tag(ap, ap->active_tag);
303 if (!qc) {
304 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
305 ap->id);
306 goto out;
307 }
308
309 /* hack alert! We cannot use the supplied completion
310 * function from inside the ->eh_strategy_handler() thread.
311 * libata is the only user of ->eh_strategy_handler() in
312 * any kernel, so the default scsi_done() assumes it is
313 * not being called from the SCSI EH.
314 */
315 qc->scsidone = scsi_finish_command;
316
317 switch (qc->tf.protocol) {
318 case ATA_PROT_DMA:
319 case ATA_PROT_NODATA:
320 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
321 ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR);
322 break;
323
324 default:
325 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
326
327 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
328 ap->id, qc->tf.command, drv_stat);
329
330 ata_qc_complete(qc, drv_stat);
331 break;
332 }
333
334 out:
335 DPRINTK("EXIT\n");
336 }
337
338 static inline unsigned int pdc_host_intr( struct ata_port *ap,
339 struct ata_queued_cmd *qc)
340 {
341 u8 status;
342 unsigned int handled = 0, have_err = 0;
343 u32 tmp;
344 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
345
346 tmp = readl(mmio);
347 if (tmp & PDC_ERR_MASK) {
348 have_err = 1;
349 pdc_reset_port(ap);
350 }
351
352 switch (qc->tf.protocol) {
353 case ATA_PROT_DMA:
354 case ATA_PROT_NODATA:
355 status = ata_wait_idle(ap);
356 if (have_err)
357 status |= ATA_ERR;
358 ata_qc_complete(qc, status);
359 handled = 1;
360 break;
361
362 default:
363 ap->stats.idle_irq++;
364 break;
365 }
366
367 return handled;
368 }
369
370 static void pdc_irq_clear(struct ata_port *ap)
371 {
372 struct ata_host_set *host_set = ap->host_set;
373 void *mmio = host_set->mmio_base;
374
375 readl(mmio + PDC_INT_SEQMASK);
376 }
377
378 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
379 {
380 struct ata_host_set *host_set = dev_instance;
381 struct ata_port *ap;
382 u32 mask = 0;
383 unsigned int i, tmp;
384 unsigned int handled = 0;
385 void *mmio_base;
386
387 VPRINTK("ENTER\n");
388
389 if (!host_set || !host_set->mmio_base) {
390 VPRINTK("QUICK EXIT\n");
391 return IRQ_NONE;
392 }
393
394 mmio_base = host_set->mmio_base;
395
396 /* reading should also clear interrupts */
397 mask = readl(mmio_base + PDC_INT_SEQMASK);
398
399 if (mask == 0xffffffff) {
400 VPRINTK("QUICK EXIT 2\n");
401 return IRQ_NONE;
402 }
403 mask &= 0xffff; /* only 16 tags possible */
404 if (!mask) {
405 VPRINTK("QUICK EXIT 3\n");
406 return IRQ_NONE;
407 }
408
409 spin_lock(&host_set->lock);
410
411 for (i = 0; i < host_set->n_ports; i++) {
412 VPRINTK("port %u\n", i);
413 ap = host_set->ports[i];
414 tmp = mask & (1 << (i + 1));
415 if (tmp && ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
416 struct ata_queued_cmd *qc;
417
418 qc = ata_qc_from_tag(ap, ap->active_tag);
419 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
420 handled += pdc_host_intr(ap, qc);
421 }
422 }
423
424 spin_unlock(&host_set->lock);
425
426 VPRINTK("EXIT\n");
427
428 return IRQ_RETVAL(handled);
429 }
430
431 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
432 {
433 struct ata_port *ap = qc->ap;
434 struct pdc_port_priv *pp = ap->private_data;
435 unsigned int port_no = ap->port_no;
436 u8 seq = (u8) (port_no + 1);
437
438 VPRINTK("ENTER, ap %p\n", ap);
439
440 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
441 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
442
443 pp->pkt[2] = seq;
444 wmb(); /* flush PRD, pkt writes */
445 writel(pp->pkt_dma, (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
446 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
447 }
448
449 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
450 {
451 switch (qc->tf.protocol) {
452 case ATA_PROT_DMA:
453 case ATA_PROT_NODATA:
454 pdc_packet_start(qc);
455 return 0;
456
457 case ATA_PROT_ATAPI_DMA:
458 BUG();
459 break;
460
461 default:
462 break;
463 }
464
465 return ata_qc_issue_prot(qc);
466 }
467
468 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
469 {
470 WARN_ON (tf->protocol == ATA_PROT_DMA ||
471 tf->protocol == ATA_PROT_NODATA);
472 ata_tf_load(ap, tf);
473 }
474
475
476 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
477 {
478 WARN_ON (tf->protocol == ATA_PROT_DMA ||
479 tf->protocol == ATA_PROT_NODATA);
480 ata_exec_command(ap, tf);
481 }
482
483
484 static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
485 {
486 port->cmd_addr = base;
487 port->data_addr = base;
488 port->feature_addr =
489 port->error_addr = base + 0x4;
490 port->nsect_addr = base + 0x8;
491 port->lbal_addr = base + 0xc;
492 port->lbam_addr = base + 0x10;
493 port->lbah_addr = base + 0x14;
494 port->device_addr = base + 0x18;
495 port->command_addr =
496 port->status_addr = base + 0x1c;
497 port->altstatus_addr =
498 port->ctl_addr = base + 0x38;
499 }
500
501
502 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
503 {
504 void *mmio = pe->mmio_base;
505 u32 tmp;
506
507 /*
508 * Except for the hotplug stuff, this is voodoo from the
509 * Promise driver. Label this entire section
510 * "TODO: figure out why we do this"
511 */
512
513 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
514 tmp = readl(mmio + PDC_FLASH_CTL);
515 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
516 writel(tmp, mmio + PDC_FLASH_CTL);
517
518 /* clear plug/unplug flags for all ports */
519 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
520 writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR);
521
522 /* mask plug/unplug ints */
523 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
524 writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR);
525
526 /* reduce TBG clock to 133 Mhz. */
527 tmp = readl(mmio + PDC_TBG_MODE);
528 tmp &= ~0x30000; /* clear bit 17, 16*/
529 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
530 writel(tmp, mmio + PDC_TBG_MODE);
531
532 readl(mmio + PDC_TBG_MODE); /* flush */
533 msleep(10);
534
535 /* adjust slew rate control register. */
536 tmp = readl(mmio + PDC_SLEW_CTL);
537 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
538 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
539 writel(tmp, mmio + PDC_SLEW_CTL);
540 }
541
542 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
543 {
544 static int printed_version;
545 struct ata_probe_ent *probe_ent = NULL;
546 unsigned long base;
547 void *mmio_base;
548 unsigned int board_idx = (unsigned int) ent->driver_data;
549 int rc;
550
551 if (!printed_version++)
552 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
553
554 /*
555 * If this driver happens to only be useful on Apple's K2, then
556 * we should check that here as it has a normal Serverworks ID
557 */
558 rc = pci_enable_device(pdev);
559 if (rc)
560 return rc;
561
562 rc = pci_request_regions(pdev, DRV_NAME);
563 if (rc)
564 goto err_out;
565
566 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
567 if (rc)
568 goto err_out_regions;
569 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
570 if (rc)
571 goto err_out_regions;
572
573 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
574 if (probe_ent == NULL) {
575 rc = -ENOMEM;
576 goto err_out_regions;
577 }
578
579 memset(probe_ent, 0, sizeof(*probe_ent));
580 probe_ent->pdev = pdev;
581 INIT_LIST_HEAD(&probe_ent->node);
582
583 mmio_base = ioremap(pci_resource_start(pdev, 3),
584 pci_resource_len(pdev, 3));
585 if (mmio_base == NULL) {
586 rc = -ENOMEM;
587 goto err_out_free_ent;
588 }
589 base = (unsigned long) mmio_base;
590
591 probe_ent->sht = pdc_port_info[board_idx].sht;
592 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
593 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
594 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
595 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
596 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
597
598 probe_ent->irq = pdev->irq;
599 probe_ent->irq_flags = SA_SHIRQ;
600 probe_ent->mmio_base = mmio_base;
601
602 pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
603 pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
604
605 probe_ent->port[0].scr_addr = base + 0x400;
606 probe_ent->port[1].scr_addr = base + 0x500;
607
608 /* notice 4-port boards */
609 switch (board_idx) {
610 case board_20319:
611 probe_ent->n_ports = 4;
612
613 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
614 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
615
616 probe_ent->port[2].scr_addr = base + 0x600;
617 probe_ent->port[3].scr_addr = base + 0x700;
618 break;
619 case board_2037x:
620 probe_ent->n_ports = 2;
621 break;
622 default:
623 BUG();
624 break;
625 }
626
627 pci_set_master(pdev);
628
629 /* initialize adapter */
630 pdc_host_init(board_idx, probe_ent);
631
632 /* FIXME: check ata_device_add return value */
633 ata_device_add(probe_ent);
634 kfree(probe_ent);
635
636 return 0;
637
638 err_out_free_ent:
639 kfree(probe_ent);
640 err_out_regions:
641 pci_release_regions(pdev);
642 err_out:
643 pci_disable_device(pdev);
644 return rc;
645 }
646
647
648 static int __init pdc_sata_init(void)
649 {
650 return pci_module_init(&pdc_sata_pci_driver);
651 }
652
653
654 static void __exit pdc_sata_exit(void)
655 {
656 pci_unregister_driver(&pdc_sata_pci_driver);
657 }
658
659
660 MODULE_AUTHOR("Jeff Garzik");
661 MODULE_DESCRIPTION("Promise SATA TX2/TX4 low-level driver");
662 MODULE_LICENSE("GPL");
663 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
664
665 module_init(pdc_sata_init);
666 module_exit(pdc_sata_exit);
MOXA 2.6.9 from sdlinux-moxaart.tgz