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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / scsi / qlogicisp.c
blob1be526c1c3a3b5eb8d46011a8905033cf3e9c0ff
1 /*
2 * QLogic ISP1020 Intelligent SCSI Processor Driver (PCI)
3 * Written by Erik H. Moe, ehm@cris.com
4 * Copyright 1995, Erik H. Moe
5 * Copyright 1996, 1997 Michael A. Griffith <grif@acm.org>
6 * Copyright 2000, Jayson C. Vantuyl <vantuyl@csc.smsu.edu>
7 * and Bryon W. Roche <bryon@csc.smsu.edu>
8 *
9 * 64-bit addressing added by Kanoj Sarcar <kanoj@sgi.com>
10 * and Leo Dagum <dagum@sgi.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2, or (at your option) any
15 * later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 */
22
23 #include <linux/blkdev.h>
24 #include <linux/config.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ioport.h>
28 #include <linux/sched.h>
29 #include <linux/types.h>
30 #include <linux/pci.h>
31 #include <linux/delay.h>
32 #include <linux/unistd.h>
33 #include <linux/spinlock.h>
34 #include <linux/interrupt.h>
35 #include <asm/io.h>
36 #include <asm/irq.h>
37 #include <asm/byteorder.h>
38 #include "scsi.h"
39 #include <scsi/scsi_host.h>
40 #include "qlogicisp.h"
41
42 /* Configuration section *****************************************************/
43
44 /* Set the following macro to 1 to reload the ISP1020's firmware. This is
45 the latest firmware provided by QLogic. This may be an earlier/later
46 revision than supplied by your board. */
47
48 #define RELOAD_FIRMWARE 1
49
50 /* Set the following macro to 1 to reload the ISP1020's defaults from nvram.
51 If you are not sure of your settings, leave this alone, the driver will
52 use a set of 'safe' defaults */
53
54 #define USE_NVRAM_DEFAULTS 0
55
56 /* Macros used for debugging */
57
58 #define DEBUG_ISP1020 0
59 #define DEBUG_ISP1020_INTR 0
60 #define DEBUG_ISP1020_SETUP 0
61 #define TRACE_ISP 0
62
63 #define DEFAULT_LOOP_COUNT 1000000
64
65 /* End Configuration section *************************************************/
66
67 #include <linux/module.h>
68
69 #if TRACE_ISP
70
71 # define TRACE_BUF_LEN (32*1024)
72
73 struct {
74 u_long next;
75 struct {
76 u_long time;
77 u_int index;
78 u_int addr;
79 u_char * name;
80 } buf[TRACE_BUF_LEN];
81 } trace;
82
83 #define TRACE(w, i, a) \
84 { \
85 unsigned long flags; \
86 \
87 trace.buf[trace.next].name = (w); \
88 trace.buf[trace.next].time = jiffies; \
89 trace.buf[trace.next].index = (i); \
90 trace.buf[trace.next].addr = (long) (a); \
91 trace.next = (trace.next + 1) & (TRACE_BUF_LEN - 1); \
92 }
93
94 #else
95 # define TRACE(w, i, a)
96 #endif
97
98 #if DEBUG_ISP1020
99 #define ENTER(x) printk("isp1020 : entering %s()\n", x);
100 #define LEAVE(x) printk("isp1020 : leaving %s()\n", x);
101 #define DEBUG(x) x
102 #else
103 #define ENTER(x)
104 #define LEAVE(x)
105 #define DEBUG(x)
106 #endif /* DEBUG_ISP1020 */
107
108 #if DEBUG_ISP1020_INTR
109 #define ENTER_INTR(x) printk("isp1020 : entering %s()\n", x);
110 #define LEAVE_INTR(x) printk("isp1020 : leaving %s()\n", x);
111 #define DEBUG_INTR(x) x
112 #else
113 #define ENTER_INTR(x)
114 #define LEAVE_INTR(x)
115 #define DEBUG_INTR(x)
116 #endif /* DEBUG ISP1020_INTR */
117
118 #define ISP1020_REV_ID 1
119
120 #define MAX_TARGETS 16
121 #define MAX_LUNS 8
122
123 /* host configuration and control registers */
124 #define HOST_HCCR 0xc0 /* host command and control */
125
126 /* pci bus interface registers */
127 #define PCI_ID_LOW 0x00 /* vendor id */
128 #define PCI_ID_HIGH 0x02 /* device id */
129 #define ISP_CFG0 0x04 /* configuration register #0 */
130 #define ISP_CFG0_HWMSK 0x000f /* Hardware revision mask */
131 #define ISP_CFG0_1020 0x0001 /* ISP1020 */
132 #define ISP_CFG0_1020A 0x0002 /* ISP1020A */
133 #define ISP_CFG0_1040 0x0003 /* ISP1040 */
134 #define ISP_CFG0_1040A 0x0004 /* ISP1040A */
135 #define ISP_CFG0_1040B 0x0005 /* ISP1040B */
136 #define ISP_CFG0_1040C 0x0006 /* ISP1040C */
137 #define ISP_CFG1 0x06 /* configuration register #1 */
138 #define ISP_CFG1_F128 0x0040 /* 128-byte FIFO threshold */
139 #define ISP_CFG1_F64 0x0030 /* 128-byte FIFO threshold */
140 #define ISP_CFG1_F32 0x0020 /* 128-byte FIFO threshold */
141 #define ISP_CFG1_F16 0x0010 /* 128-byte FIFO threshold */
142 #define ISP_CFG1_BENAB 0x0004 /* Global Bus burst enable */
143 #define ISP_CFG1_SXP 0x0001 /* SXP register select */
144 #define PCI_INTF_CTL 0x08 /* pci interface control */
145 #define PCI_INTF_STS 0x0a /* pci interface status */
146 #define PCI_SEMAPHORE 0x0c /* pci semaphore */
147 #define PCI_NVRAM 0x0e /* pci nvram interface */
148 #define CDMA_CONF 0x20 /* Command DMA Config */
149 #define DDMA_CONF 0x40 /* Data DMA Config */
150 #define DMA_CONF_SENAB 0x0008 /* SXP to DMA Data enable */
151 #define DMA_CONF_RIRQ 0x0004 /* RISC interrupt enable */
152 #define DMA_CONF_BENAB 0x0002 /* Bus burst enable */
153 #define DMA_CONF_DIR 0x0001 /* DMA direction (0=fifo->host 1=host->fifo) */
154
155 /* mailbox registers */
156 #define MBOX0 0x70 /* mailbox 0 */
157 #define MBOX1 0x72 /* mailbox 1 */
158 #define MBOX2 0x74 /* mailbox 2 */
159 #define MBOX3 0x76 /* mailbox 3 */
160 #define MBOX4 0x78 /* mailbox 4 */
161 #define MBOX5 0x7a /* mailbox 5 */
162 #define MBOX6 0x7c /* mailbox 6 */
163 #define MBOX7 0x7e /* mailbox 7 */
164
165 /* mailbox command complete status codes */
166 #define MBOX_COMMAND_COMPLETE 0x4000
167 #define INVALID_COMMAND 0x4001
168 #define HOST_INTERFACE_ERROR 0x4002
169 #define TEST_FAILED 0x4003
170 #define COMMAND_ERROR 0x4005
171 #define COMMAND_PARAM_ERROR 0x4006
172
173 /* async event status codes */
174 #define ASYNC_SCSI_BUS_RESET 0x8001
175 #define SYSTEM_ERROR 0x8002
176 #define REQUEST_TRANSFER_ERROR 0x8003
177 #define RESPONSE_TRANSFER_ERROR 0x8004
178 #define REQUEST_QUEUE_WAKEUP 0x8005
179 #define EXECUTION_TIMEOUT_RESET 0x8006
180
181 #ifdef CONFIG_QL_ISP_A64
182 #define IOCB_SEGS 2
183 #define CONTINUATION_SEGS 5
184 #define MAX_CONTINUATION_ENTRIES 254
185 #else
186 #define IOCB_SEGS 4
187 #define CONTINUATION_SEGS 7
188 #endif /* CONFIG_QL_ISP_A64 */
189
190 struct Entry_header {
191 u_char entry_type;
192 u_char entry_cnt;
193 u_char sys_def_1;
194 u_char flags;
195 };
196
197 /* entry header type commands */
198 #ifdef CONFIG_QL_ISP_A64
199 #define ENTRY_COMMAND 9
200 #define ENTRY_CONTINUATION 0xa
201 #else
202 #define ENTRY_COMMAND 1
203 #define ENTRY_CONTINUATION 2
204 #endif /* CONFIG_QL_ISP_A64 */
205
206 #define ENTRY_STATUS 3
207 #define ENTRY_MARKER 4
208 #define ENTRY_EXTENDED_COMMAND 5
209
210 /* entry header flag definitions */
211 #define EFLAG_CONTINUATION 1
212 #define EFLAG_BUSY 2
213 #define EFLAG_BAD_HEADER 4
214 #define EFLAG_BAD_PAYLOAD 8
215
216 struct dataseg {
217 u_int d_base;
218 #ifdef CONFIG_QL_ISP_A64
219 u_int d_base_hi;
220 #endif
221 u_int d_count;
222 };
223
224 struct Command_Entry {
225 struct Entry_header hdr;
226 u_int handle;
227 u_char target_lun;
228 u_char target_id;
229 u_short cdb_length;
230 u_short control_flags;
231 u_short rsvd;
232 u_short time_out;
233 u_short segment_cnt;
234 u_char cdb[12];
235 #ifdef CONFIG_QL_ISP_A64
236 u_int rsvd1;
237 u_int rsvd2;
238 #endif
239 struct dataseg dataseg[IOCB_SEGS];
240 };
241
242 /* command entry control flag definitions */
243 #define CFLAG_NODISC 0x01
244 #define CFLAG_HEAD_TAG 0x02
245 #define CFLAG_ORDERED_TAG 0x04
246 #define CFLAG_SIMPLE_TAG 0x08
247 #define CFLAG_TAR_RTN 0x10
248 #define CFLAG_READ 0x20
249 #define CFLAG_WRITE 0x40
250
251 struct Ext_Command_Entry {
252 struct Entry_header hdr;
253 u_int handle;
254 u_char target_lun;
255 u_char target_id;
256 u_short cdb_length;
257 u_short control_flags;
258 u_short rsvd;
259 u_short time_out;
260 u_short segment_cnt;
261 u_char cdb[44];
262 };
263
264 struct Continuation_Entry {
265 struct Entry_header hdr;
266 #ifndef CONFIG_QL_ISP_A64
267 u_int reserved;
268 #endif
269 struct dataseg dataseg[CONTINUATION_SEGS];
270 };
271
272 struct Marker_Entry {
273 struct Entry_header hdr;
274 u_int reserved;
275 u_char target_lun;
276 u_char target_id;
277 u_char modifier;
278 u_char rsvd;
279 u_char rsvds[52];
280 };
281
282 /* marker entry modifier definitions */
283 #define SYNC_DEVICE 0
284 #define SYNC_TARGET 1
285 #define SYNC_ALL 2
286
287 struct Status_Entry {
288 struct Entry_header hdr;
289 u_int handle;
290 u_short scsi_status;
291 u_short completion_status;
292 u_short state_flags;
293 u_short status_flags;
294 u_short time;
295 u_short req_sense_len;
296 u_int residual;
297 u_char rsvd[8];
298 u_char req_sense_data[32];
299 };
300
301 /* status entry completion status definitions */
302 #define CS_COMPLETE 0x0000
303 #define CS_INCOMPLETE 0x0001
304 #define CS_DMA_ERROR 0x0002
305 #define CS_TRANSPORT_ERROR 0x0003
306 #define CS_RESET_OCCURRED 0x0004
307 #define CS_ABORTED 0x0005
308 #define CS_TIMEOUT 0x0006
309 #define CS_DATA_OVERRUN 0x0007
310 #define CS_COMMAND_OVERRUN 0x0008
311 #define CS_STATUS_OVERRUN 0x0009
312 #define CS_BAD_MESSAGE 0x000a
313 #define CS_NO_MESSAGE_OUT 0x000b
314 #define CS_EXT_ID_FAILED 0x000c
315 #define CS_IDE_MSG_FAILED 0x000d
316 #define CS_ABORT_MSG_FAILED 0x000e
317 #define CS_REJECT_MSG_FAILED 0x000f
318 #define CS_NOP_MSG_FAILED 0x0010
319 #define CS_PARITY_ERROR_MSG_FAILED 0x0011
320 #define CS_DEVICE_RESET_MSG_FAILED 0x0012
321 #define CS_ID_MSG_FAILED 0x0013
322 #define CS_UNEXP_BUS_FREE 0x0014
323 #define CS_DATA_UNDERRUN 0x0015
324
325 /* status entry state flag definitions */
326 #define SF_GOT_BUS 0x0100
327 #define SF_GOT_TARGET 0x0200
328 #define SF_SENT_CDB 0x0400
329 #define SF_TRANSFERRED_DATA 0x0800
330 #define SF_GOT_STATUS 0x1000
331 #define SF_GOT_SENSE 0x2000
332
333 /* status entry status flag definitions */
334 #define STF_DISCONNECT 0x0001
335 #define STF_SYNCHRONOUS 0x0002
336 #define STF_PARITY_ERROR 0x0004
337 #define STF_BUS_RESET 0x0008
338 #define STF_DEVICE_RESET 0x0010
339 #define STF_ABORTED 0x0020
340 #define STF_TIMEOUT 0x0040
341 #define STF_NEGOTIATION 0x0080
342
343 /* interface control commands */
344 #define ISP_RESET 0x0001
345 #define ISP_EN_INT 0x0002
346 #define ISP_EN_RISC 0x0004
347
348 /* host control commands */
349 #define HCCR_NOP 0x0000
350 #define HCCR_RESET 0x1000
351 #define HCCR_PAUSE 0x2000
352 #define HCCR_RELEASE 0x3000
353 #define HCCR_SINGLE_STEP 0x4000
354 #define HCCR_SET_HOST_INTR 0x5000
355 #define HCCR_CLEAR_HOST_INTR 0x6000
356 #define HCCR_CLEAR_RISC_INTR 0x7000
357 #define HCCR_BP_ENABLE 0x8000
358 #define HCCR_BIOS_DISABLE 0x9000
359 #define HCCR_TEST_MODE 0xf000
360
361 #define RISC_BUSY 0x0004
362
363 /* mailbox commands */
364 #define MBOX_NO_OP 0x0000
365 #define MBOX_LOAD_RAM 0x0001
366 #define MBOX_EXEC_FIRMWARE 0x0002
367 #define MBOX_DUMP_RAM 0x0003
368 #define MBOX_WRITE_RAM_WORD 0x0004
369 #define MBOX_READ_RAM_WORD 0x0005
370 #define MBOX_MAILBOX_REG_TEST 0x0006
371 #define MBOX_VERIFY_CHECKSUM 0x0007
372 #define MBOX_ABOUT_FIRMWARE 0x0008
373 #define MBOX_CHECK_FIRMWARE 0x000e
374 #define MBOX_INIT_REQ_QUEUE 0x0010
375 #define MBOX_INIT_RES_QUEUE 0x0011
376 #define MBOX_EXECUTE_IOCB 0x0012
377 #define MBOX_WAKE_UP 0x0013
378 #define MBOX_STOP_FIRMWARE 0x0014
379 #define MBOX_ABORT 0x0015
380 #define MBOX_ABORT_DEVICE 0x0016
381 #define MBOX_ABORT_TARGET 0x0017
382 #define MBOX_BUS_RESET 0x0018
383 #define MBOX_STOP_QUEUE 0x0019
384 #define MBOX_START_QUEUE 0x001a
385 #define MBOX_SINGLE_STEP_QUEUE 0x001b
386 #define MBOX_ABORT_QUEUE 0x001c
387 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d
388 #define MBOX_GET_FIRMWARE_STATUS 0x001f
389 #define MBOX_GET_INIT_SCSI_ID 0x0020
390 #define MBOX_GET_SELECT_TIMEOUT 0x0021
391 #define MBOX_GET_RETRY_COUNT 0x0022
392 #define MBOX_GET_TAG_AGE_LIMIT 0x0023
393 #define MBOX_GET_CLOCK_RATE 0x0024
394 #define MBOX_GET_ACT_NEG_STATE 0x0025
395 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
396 #define MBOX_GET_PCI_PARAMS 0x0027
397 #define MBOX_GET_TARGET_PARAMS 0x0028
398 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
399 #define MBOX_SET_INIT_SCSI_ID 0x0030
400 #define MBOX_SET_SELECT_TIMEOUT 0x0031
401 #define MBOX_SET_RETRY_COUNT 0x0032
402 #define MBOX_SET_TAG_AGE_LIMIT 0x0033
403 #define MBOX_SET_CLOCK_RATE 0x0034
404 #define MBOX_SET_ACTIVE_NEG_STATE 0x0035
405 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
406 #define MBOX_SET_PCI_CONTROL_PARAMS 0x0037
407 #define MBOX_SET_TARGET_PARAMS 0x0038
408 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
409 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040
410 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041
411 #define MBOX_EXEC_BIOS_IOCB 0x0042
412
413 #ifdef CONFIG_QL_ISP_A64
414 #define MBOX_CMD_INIT_REQUEST_QUEUE_64 0x0052
415 #define MBOX_CMD_INIT_RESPONSE_QUEUE_64 0x0053
416 #endif /* CONFIG_QL_ISP_A64 */
417
418 #include "qlogicisp_asm.c"
419
420 #define PACKB(a, b) (((a)<<4)|(b))
421
422 static const u_char mbox_param[] = {
423 PACKB(1, 1), /* MBOX_NO_OP */
424 PACKB(5, 5), /* MBOX_LOAD_RAM */
425 PACKB(2, 0), /* MBOX_EXEC_FIRMWARE */
426 PACKB(5, 5), /* MBOX_DUMP_RAM */
427 PACKB(3, 3), /* MBOX_WRITE_RAM_WORD */
428 PACKB(2, 3), /* MBOX_READ_RAM_WORD */
429 PACKB(6, 6), /* MBOX_MAILBOX_REG_TEST */
430 PACKB(2, 3), /* MBOX_VERIFY_CHECKSUM */
431 PACKB(1, 3), /* MBOX_ABOUT_FIRMWARE */
432 PACKB(0, 0), /* 0x0009 */
433 PACKB(0, 0), /* 0x000a */
434 PACKB(0, 0), /* 0x000b */
435 PACKB(0, 0), /* 0x000c */
436 PACKB(0, 0), /* 0x000d */
437 PACKB(1, 2), /* MBOX_CHECK_FIRMWARE */
438 PACKB(0, 0), /* 0x000f */
439 PACKB(5, 5), /* MBOX_INIT_REQ_QUEUE */
440 PACKB(6, 6), /* MBOX_INIT_RES_QUEUE */
441 PACKB(4, 4), /* MBOX_EXECUTE_IOCB */
442 PACKB(2, 2), /* MBOX_WAKE_UP */
443 PACKB(1, 6), /* MBOX_STOP_FIRMWARE */
444 PACKB(4, 4), /* MBOX_ABORT */
445 PACKB(2, 2), /* MBOX_ABORT_DEVICE */
446 PACKB(3, 3), /* MBOX_ABORT_TARGET */
447 PACKB(2, 2), /* MBOX_BUS_RESET */
448 PACKB(2, 3), /* MBOX_STOP_QUEUE */
449 PACKB(2, 3), /* MBOX_START_QUEUE */
450 PACKB(2, 3), /* MBOX_SINGLE_STEP_QUEUE */
451 PACKB(2, 3), /* MBOX_ABORT_QUEUE */
452 PACKB(2, 4), /* MBOX_GET_DEV_QUEUE_STATUS */
453 PACKB(0, 0), /* 0x001e */
454 PACKB(1, 3), /* MBOX_GET_FIRMWARE_STATUS */
455 PACKB(1, 2), /* MBOX_GET_INIT_SCSI_ID */
456 PACKB(1, 2), /* MBOX_GET_SELECT_TIMEOUT */
457 PACKB(1, 3), /* MBOX_GET_RETRY_COUNT */
458 PACKB(1, 2), /* MBOX_GET_TAG_AGE_LIMIT */
459 PACKB(1, 2), /* MBOX_GET_CLOCK_RATE */
460 PACKB(1, 2), /* MBOX_GET_ACT_NEG_STATE */
461 PACKB(1, 2), /* MBOX_GET_ASYNC_DATA_SETUP_TIME */
462 PACKB(1, 3), /* MBOX_GET_PCI_PARAMS */
463 PACKB(2, 4), /* MBOX_GET_TARGET_PARAMS */
464 PACKB(2, 4), /* MBOX_GET_DEV_QUEUE_PARAMS */
465 PACKB(0, 0), /* 0x002a */
466 PACKB(0, 0), /* 0x002b */
467 PACKB(0, 0), /* 0x002c */
468 PACKB(0, 0), /* 0x002d */
469 PACKB(0, 0), /* 0x002e */
470 PACKB(0, 0), /* 0x002f */
471 PACKB(2, 2), /* MBOX_SET_INIT_SCSI_ID */
472 PACKB(2, 2), /* MBOX_SET_SELECT_TIMEOUT */
473 PACKB(3, 3), /* MBOX_SET_RETRY_COUNT */
474 PACKB(2, 2), /* MBOX_SET_TAG_AGE_LIMIT */
475 PACKB(2, 2), /* MBOX_SET_CLOCK_RATE */
476 PACKB(2, 2), /* MBOX_SET_ACTIVE_NEG_STATE */
477 PACKB(2, 2), /* MBOX_SET_ASYNC_DATA_SETUP_TIME */
478 PACKB(3, 3), /* MBOX_SET_PCI_CONTROL_PARAMS */
479 PACKB(4, 4), /* MBOX_SET_TARGET_PARAMS */
480 PACKB(4, 4), /* MBOX_SET_DEV_QUEUE_PARAMS */
481 PACKB(0, 0), /* 0x003a */
482 PACKB(0, 0), /* 0x003b */
483 PACKB(0, 0), /* 0x003c */
484 PACKB(0, 0), /* 0x003d */
485 PACKB(0, 0), /* 0x003e */
486 PACKB(0, 0), /* 0x003f */
487 PACKB(1, 2), /* MBOX_RETURN_BIOS_BLOCK_ADDR */
488 PACKB(6, 1), /* MBOX_WRITE_FOUR_RAM_WORDS */
489 PACKB(2, 3) /* MBOX_EXEC_BIOS_IOCB */
490 #ifdef CONFIG_QL_ISP_A64
491 ,PACKB(0, 0), /* 0x0043 */
492 PACKB(0, 0), /* 0x0044 */
493 PACKB(0, 0), /* 0x0045 */
494 PACKB(0, 0), /* 0x0046 */
495 PACKB(0, 0), /* 0x0047 */
496 PACKB(0, 0), /* 0x0048 */
497 PACKB(0, 0), /* 0x0049 */
498 PACKB(0, 0), /* 0x004a */
499 PACKB(0, 0), /* 0x004b */
500 PACKB(0, 0), /* 0x004c */
501 PACKB(0, 0), /* 0x004d */
502 PACKB(0, 0), /* 0x004e */
503 PACKB(0, 0), /* 0x004f */
504 PACKB(0, 0), /* 0x0050 */
505 PACKB(0, 0), /* 0x0051 */
506 PACKB(8, 8), /* MBOX_CMD_INIT_REQUEST_QUEUE_64 (0x0052) */
507 PACKB(8, 8) /* MBOX_CMD_INIT_RESPONSE_QUEUE_64 (0x0053) */
508 #endif /* CONFIG_QL_ISP_A64 */
509 };
510
511 #define MAX_MBOX_COMMAND (sizeof(mbox_param)/sizeof(u_short))
512
513 struct host_param {
514 u_short fifo_threshold;
515 u_short host_adapter_enable;
516 u_short initiator_scsi_id;
517 u_short bus_reset_delay;
518 u_short retry_count;
519 u_short retry_delay;
520 u_short async_data_setup_time;
521 u_short req_ack_active_negation;
522 u_short data_line_active_negation;
523 u_short data_dma_burst_enable;
524 u_short command_dma_burst_enable;
525 u_short tag_aging;
526 u_short selection_timeout;
527 u_short max_queue_depth;
528 };
529
530 /*
531 * Device Flags:
532 *
533 * Bit Name
534 * ---------
535 * 7 Disconnect Privilege
536 * 6 Parity Checking
537 * 5 Wide Data Transfers
538 * 4 Synchronous Data Transfers
539 * 3 Tagged Queuing
540 * 2 Automatic Request Sense
541 * 1 Stop Queue on Check Condition
542 * 0 Renegotiate on Error
543 */
544
545 struct dev_param {
546 u_short device_flags;
547 u_short execution_throttle;
548 u_short synchronous_period;
549 u_short synchronous_offset;
550 u_short device_enable;
551 u_short reserved; /* pad */
552 };
553
554 /*
555 * The result queue can be quite a bit smaller since continuation entries
556 * do not show up there:
557 */
558 #define RES_QUEUE_LEN ((QLOGICISP_REQ_QUEUE_LEN + 1) / 8 - 1)
559 #define QUEUE_ENTRY_LEN 64
560 #define QSIZE(entries) (((entries) + 1) * QUEUE_ENTRY_LEN)
561
562 struct isp_queue_entry {
563 char __opaque[QUEUE_ENTRY_LEN];
564 };
565
566 struct isp1020_hostdata {
567 u_long memaddr;
568 u_char revision;
569 struct host_param host_param;
570 struct dev_param dev_param[MAX_TARGETS];
571 struct pci_dev *pci_dev;
572
573 struct isp_queue_entry *res_cpu; /* CPU-side address of response queue. */
574 struct isp_queue_entry *req_cpu; /* CPU-size address of request queue. */
575
576 /* result and request queues (shared with isp1020): */
577 u_int req_in_ptr; /* index of next request slot */
578 u_int res_out_ptr; /* index of next result slot */
579
580 /* this is here so the queues are nicely aligned */
581 long send_marker; /* do we need to send a marker? */
582
583 /* The cmd->handle has a fixed size, and is only 32-bits. We
584 * need to take care to handle 64-bit systems correctly thus what
585 * we actually place in cmd->handle is an index to the following
586 * table. Kudos to Matt Jacob for the technique. -DaveM
587 */
588 Scsi_Cmnd *cmd_slots[QLOGICISP_REQ_QUEUE_LEN + 1];
589
590 dma_addr_t res_dma; /* PCI side view of response queue */
591 dma_addr_t req_dma; /* PCI side view of request queue */
592 };
593
594 /* queue length's _must_ be power of two: */
595 #define QUEUE_DEPTH(in, out, ql) ((in - out) & (ql))
596 #define REQ_QUEUE_DEPTH(in, out) QUEUE_DEPTH(in, out, \
597 QLOGICISP_REQ_QUEUE_LEN)
598 #define RES_QUEUE_DEPTH(in, out) QUEUE_DEPTH(in, out, RES_QUEUE_LEN)
599
600 static void isp1020_enable_irqs(struct Scsi_Host *);
601 static void isp1020_disable_irqs(struct Scsi_Host *);
602 static int isp1020_init(struct Scsi_Host *);
603 static int isp1020_reset_hardware(struct Scsi_Host *);
604 static int isp1020_set_defaults(struct Scsi_Host *);
605 static int isp1020_load_parameters(struct Scsi_Host *);
606 static int isp1020_mbox_command(struct Scsi_Host *, u_short []);
607 static int isp1020_return_status(struct Status_Entry *);
608 static void isp1020_intr_handler(int, void *, struct pt_regs *);
609 static irqreturn_t do_isp1020_intr_handler(int, void *, struct pt_regs *);
610
611 #if USE_NVRAM_DEFAULTS
612 static int isp1020_get_defaults(struct Scsi_Host *);
613 static int isp1020_verify_nvram(struct Scsi_Host *);
614 static u_short isp1020_read_nvram_word(struct Scsi_Host *, u_short);
615 #endif
616
617 #if DEBUG_ISP1020
618 static void isp1020_print_scsi_cmd(Scsi_Cmnd *);
619 #endif
620 #if DEBUG_ISP1020_INTR
621 static void isp1020_print_status_entry(struct Status_Entry *);
622 #endif
623
624 /* memaddr should be used to determine if memmapped port i/o is being used
625 * non-null memaddr == mmap'd
626 * JV 7-Jan-2000
627 */
628 static inline u_short isp_inw(struct Scsi_Host *host, long offset)
629 {
630 struct isp1020_hostdata *h = (struct isp1020_hostdata *)host->hostdata;
631 if (h->memaddr)
632 return readw(h->memaddr + offset);
633 else
634 return inw(host->io_port + offset);
635 }
636
637 static inline void isp_outw(u_short val, struct Scsi_Host *host, long offset)
638 {
639 struct isp1020_hostdata *h = (struct isp1020_hostdata *)host->hostdata;
640 if (h->memaddr)
641 writew(val, h->memaddr + offset);
642 else
643 outw(val, host->io_port + offset);
644 }
645
646 static inline void isp1020_enable_irqs(struct Scsi_Host *host)
647 {
648 isp_outw(ISP_EN_INT|ISP_EN_RISC, host, PCI_INTF_CTL);
649 }
650
651
652 static inline void isp1020_disable_irqs(struct Scsi_Host *host)
653 {
654 isp_outw(0x0, host, PCI_INTF_CTL);
655 }
656
657
658 int isp1020_detect(Scsi_Host_Template *tmpt)
659 {
660 int hosts = 0;
661 struct Scsi_Host *host;
662 struct isp1020_hostdata *hostdata;
663 struct pci_dev *pdev = NULL;
664
665 ENTER("isp1020_detect");
666
667 tmpt->proc_name = "isp1020";
668
669 while ((pdev = pci_find_device(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP1020, pdev)))
670 {
671 if (pci_enable_device(pdev))
672 continue;
673
674 host = scsi_register(tmpt, sizeof(struct isp1020_hostdata));
675 if (!host)
676 continue;
677
678 hostdata = (struct isp1020_hostdata *) host->hostdata;
679
680 memset(hostdata, 0, sizeof(struct isp1020_hostdata));
681
682 hostdata->pci_dev = pdev;
683 scsi_set_device(host, &pdev->dev);
684
685 if (isp1020_init(host))
686 goto fail_and_unregister;
687
688 if (isp1020_reset_hardware(host)
689 #if USE_NVRAM_DEFAULTS
690 || isp1020_get_defaults(host)
691 #else
692 || isp1020_set_defaults(host)
693 #endif /* USE_NVRAM_DEFAULTS */
694 || isp1020_load_parameters(host)) {
695 goto fail_uninit;
696 }
697
698 host->this_id = hostdata->host_param.initiator_scsi_id;
699 host->max_sectors = 64;
700
701 if (request_irq(host->irq, do_isp1020_intr_handler, SA_INTERRUPT | SA_SHIRQ,
702 "qlogicisp", host))
703 {
704 printk("qlogicisp : interrupt %d already in use\n",
705 host->irq);
706 goto fail_uninit;
707 }
708
709 isp_outw(0x0, host, PCI_SEMAPHORE);
710 isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
711 isp1020_enable_irqs(host);
712
713 hosts++;
714 continue;
715
716 fail_uninit:
717 iounmap((void *)hostdata->memaddr);
718 release_region(host->io_port, 0xff);
719 fail_and_unregister:
720 if (hostdata->res_cpu)
721 pci_free_consistent(hostdata->pci_dev,
722 QSIZE(RES_QUEUE_LEN),
723 hostdata->res_cpu,
724 hostdata->res_dma);
725 if (hostdata->req_cpu)
726 pci_free_consistent(hostdata->pci_dev,
727 QSIZE(QLOGICISP_REQ_QUEUE_LEN),
728 hostdata->req_cpu,
729 hostdata->req_dma);
730 scsi_unregister(host);
731 }
732
733 LEAVE("isp1020_detect");
734
735 return hosts;
736 }
737
738
739 int isp1020_release(struct Scsi_Host *host)
740 {
741 struct isp1020_hostdata *hostdata;
742
743 ENTER("isp1020_release");
744
745 hostdata = (struct isp1020_hostdata *) host->hostdata;
746
747 isp_outw(0x0, host, PCI_INTF_CTL);
748 free_irq(host->irq, host);
749
750 iounmap((void *)hostdata->memaddr);
751
752 release_region(host->io_port, 0xff);
753
754 LEAVE("isp1020_release");
755
756 return 0;
757 }
758
759
760 const char *isp1020_info(struct Scsi_Host *host)
761 {
762 static char buf[80];
763 struct isp1020_hostdata *hostdata;
764
765 ENTER("isp1020_info");
766
767 hostdata = (struct isp1020_hostdata *) host->hostdata;
768 sprintf(buf,
769 "QLogic ISP1020 SCSI on PCI bus %02x device %02x irq %d %s base 0x%lx",
770 hostdata->pci_dev->bus->number, hostdata->pci_dev->devfn, host->irq,
771 (hostdata->memaddr ? "MEM" : "I/O"),
772 (hostdata->memaddr ? hostdata->memaddr : host->io_port));
773
774 LEAVE("isp1020_info");
775
776 return buf;
777 }
778
779
780 /*
781 * The middle SCSI layer ensures that queuecommand never gets invoked
782 * concurrently with itself or the interrupt handler (though the
783 * interrupt handler may call this routine as part of
784 * request-completion handling).
785 */
786 int isp1020_queuecommand(Scsi_Cmnd *Cmnd, void (*done)(Scsi_Cmnd *))
787 {
788 int i, n, num_free;
789 u_int in_ptr, out_ptr;
790 struct dataseg * ds;
791 struct scatterlist *sg;
792 struct Command_Entry *cmd;
793 struct Continuation_Entry *cont;
794 struct Scsi_Host *host;
795 struct isp1020_hostdata *hostdata;
796 dma_addr_t dma_addr;
797
798 ENTER("isp1020_queuecommand");
799
800 host = Cmnd->device->host;
801 hostdata = (struct isp1020_hostdata *) host->hostdata;
802 Cmnd->scsi_done = done;
803
804 DEBUG(isp1020_print_scsi_cmd(Cmnd));
805
806 out_ptr = isp_inw(host, + MBOX4);
807 in_ptr = hostdata->req_in_ptr;
808
809 DEBUG(printk("qlogicisp : request queue depth %d\n",
810 REQ_QUEUE_DEPTH(in_ptr, out_ptr)));
811
812 cmd = (struct Command_Entry *) &hostdata->req_cpu[in_ptr];
813 in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
814 if (in_ptr == out_ptr) {
815 printk("qlogicisp : request queue overflow\n");
816 return 1;
817 }
818
819 if (hostdata->send_marker) {
820 struct Marker_Entry *marker;
821
822 TRACE("queue marker", in_ptr, 0);
823
824 DEBUG(printk("qlogicisp : adding marker entry\n"));
825 marker = (struct Marker_Entry *) cmd;
826 memset(marker, 0, sizeof(struct Marker_Entry));
827
828 marker->hdr.entry_type = ENTRY_MARKER;
829 marker->hdr.entry_cnt = 1;
830 marker->modifier = SYNC_ALL;
831
832 hostdata->send_marker = 0;
833
834 if (((in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN) == out_ptr) {
835 isp_outw(in_ptr, host, MBOX4);
836 hostdata->req_in_ptr = in_ptr;
837 printk("qlogicisp : request queue overflow\n");
838 return 1;
839 }
840 cmd = (struct Command_Entry *) &hostdata->req_cpu[in_ptr];
841 in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
842 }
843
844 TRACE("queue command", in_ptr, Cmnd);
845
846 memset(cmd, 0, sizeof(struct Command_Entry));
847
848 cmd->hdr.entry_type = ENTRY_COMMAND;
849 cmd->hdr.entry_cnt = 1;
850
851 cmd->target_lun = Cmnd->device->lun;
852 cmd->target_id = Cmnd->device->id;
853 cmd->cdb_length = cpu_to_le16(Cmnd->cmd_len);
854 cmd->control_flags = cpu_to_le16(CFLAG_READ | CFLAG_WRITE);
855 cmd->time_out = cpu_to_le16(30);
856
857 memcpy(cmd->cdb, Cmnd->cmnd, Cmnd->cmd_len);
858
859 if (Cmnd->use_sg) {
860 int sg_count;
861
862 sg = (struct scatterlist *) Cmnd->request_buffer;
863 ds = cmd->dataseg;
864
865 sg_count = pci_map_sg(hostdata->pci_dev, sg, Cmnd->use_sg,
866 scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
867
868 cmd->segment_cnt = cpu_to_le16(sg_count);
869
870 /* fill in first four sg entries: */
871 n = sg_count;
872 if (n > IOCB_SEGS)
873 n = IOCB_SEGS;
874 for (i = 0; i < n; i++) {
875 dma_addr = sg_dma_address(sg);
876 ds[i].d_base = cpu_to_le32((u32) dma_addr);
877 #ifdef CONFIG_QL_ISP_A64
878 ds[i].d_base_hi = cpu_to_le32((u32) (dma_addr>>32));
879 #endif /* CONFIG_QL_ISP_A64 */
880 ds[i].d_count = cpu_to_le32(sg_dma_len(sg));
881 ++sg;
882 }
883 sg_count -= IOCB_SEGS;
884
885 while (sg_count > 0) {
886 ++cmd->hdr.entry_cnt;
887 cont = (struct Continuation_Entry *)
888 &hostdata->req_cpu[in_ptr];
889 in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
890 if (in_ptr == out_ptr) {
891 printk("isp1020: unexpected request queue "
892 "overflow\n");
893 return 1;
894 }
895 TRACE("queue continuation", in_ptr, 0);
896 cont->hdr.entry_type = ENTRY_CONTINUATION;
897 cont->hdr.entry_cnt = 0;
898 cont->hdr.sys_def_1 = 0;
899 cont->hdr.flags = 0;
900 #ifndef CONFIG_QL_ISP_A64
901 cont->reserved = 0;
902 #endif
903 ds = cont->dataseg;
904 n = sg_count;
905 if (n > CONTINUATION_SEGS)
906 n = CONTINUATION_SEGS;
907 for (i = 0; i < n; ++i) {
908 dma_addr = sg_dma_address(sg);
909 ds[i].d_base = cpu_to_le32((u32) dma_addr);
910 #ifdef CONFIG_QL_ISP_A64
911 ds[i].d_base_hi = cpu_to_le32((u32)(dma_addr>>32));
912 #endif /* CONFIG_QL_ISP_A64 */
913 ds[i].d_count = cpu_to_le32(sg_dma_len(sg));
914 ++sg;
915 }
916 sg_count -= n;
917 }
918 } else if (Cmnd->request_bufflen) {
919 /*Cmnd->SCp.ptr = (char *)(unsigned long)*/
920 dma_addr = pci_map_single(hostdata->pci_dev,
921 Cmnd->request_buffer,
922 Cmnd->request_bufflen,
923 scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
924 Cmnd->SCp.ptr = (char *)(unsigned long) dma_addr;
925
926 cmd->dataseg[0].d_base =
927 cpu_to_le32((u32) dma_addr);
928 #ifdef CONFIG_QL_ISP_A64
929 cmd->dataseg[0].d_base_hi =
930 cpu_to_le32((u32) (dma_addr>>32));
931 #endif /* CONFIG_QL_ISP_A64 */
932 cmd->dataseg[0].d_count =
933 cpu_to_le32((u32)Cmnd->request_bufflen);
934 cmd->segment_cnt = cpu_to_le16(1);
935 } else {
936 cmd->dataseg[0].d_base = 0;
937 #ifdef CONFIG_QL_ISP_A64
938 cmd->dataseg[0].d_base_hi = 0;
939 #endif /* CONFIG_QL_ISP_A64 */
940 cmd->dataseg[0].d_count = 0;
941 cmd->segment_cnt = cpu_to_le16(1); /* Shouldn't this be 0? */
942 }
943
944 /* Committed, record Scsi_Cmd so we can find it later. */
945 cmd->handle = in_ptr;
946 hostdata->cmd_slots[in_ptr] = Cmnd;
947
948 isp_outw(in_ptr, host, MBOX4);
949 hostdata->req_in_ptr = in_ptr;
950
951 num_free = QLOGICISP_REQ_QUEUE_LEN - REQ_QUEUE_DEPTH(in_ptr, out_ptr);
952 host->can_queue = host->host_busy + num_free;
953 host->sg_tablesize = QLOGICISP_MAX_SG(num_free);
954
955 LEAVE("isp1020_queuecommand");
956
957 return 0;
958 }
959
960
961 #define ASYNC_EVENT_INTERRUPT 0x01
962
963 irqreturn_t do_isp1020_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
964 {
965 struct Scsi_Host *host = dev_id;
966 unsigned long flags;
967
968 spin_lock_irqsave(host->host_lock, flags);
969 isp1020_intr_handler(irq, dev_id, regs);
970 spin_unlock_irqrestore(host->host_lock, flags);
971
972 return IRQ_HANDLED;
973 }
974
975 void isp1020_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
976 {
977 Scsi_Cmnd *Cmnd;
978 struct Status_Entry *sts;
979 struct Scsi_Host *host = dev_id;
980 struct isp1020_hostdata *hostdata;
981 u_int in_ptr, out_ptr;
982 u_short status;
983
984 ENTER_INTR("isp1020_intr_handler");
985
986 hostdata = (struct isp1020_hostdata *) host->hostdata;
987
988 DEBUG_INTR(printk("qlogicisp : interrupt on line %d\n", irq));
989
990 if (!(isp_inw(host, PCI_INTF_STS) & 0x04)) {
991 /* spurious interrupts can happen legally */
992 DEBUG_INTR(printk("qlogicisp: got spurious interrupt\n"));
993 return;
994 }
995 in_ptr = isp_inw(host, MBOX5);
996 isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
997
998 if ((isp_inw(host, PCI_SEMAPHORE) & ASYNC_EVENT_INTERRUPT)) {
999 status = isp_inw(host, MBOX0);
1000
1001 DEBUG_INTR(printk("qlogicisp : mbox completion status: %x\n",
1002 status));
1003
1004 switch (status) {
1005 case ASYNC_SCSI_BUS_RESET:
1006 case EXECUTION_TIMEOUT_RESET:
1007 hostdata->send_marker = 1;
1008 break;
1009 case INVALID_COMMAND:
1010 case HOST_INTERFACE_ERROR:
1011 case COMMAND_ERROR:
1012 case COMMAND_PARAM_ERROR:
1013 printk("qlogicisp : bad mailbox return status\n");
1014 break;
1015 }
1016 isp_outw(0x0, host, PCI_SEMAPHORE);
1017 }
1018 out_ptr = hostdata->res_out_ptr;
1019
1020 DEBUG_INTR(printk("qlogicisp : response queue update\n"));
1021 DEBUG_INTR(printk("qlogicisp : response queue depth %d\n",
1022 QUEUE_DEPTH(in_ptr, out_ptr, RES_QUEUE_LEN)));
1023
1024 while (out_ptr != in_ptr) {
1025 u_int cmd_slot;
1026
1027 sts = (struct Status_Entry *) &hostdata->res_cpu[out_ptr];
1028 out_ptr = (out_ptr + 1) & RES_QUEUE_LEN;
1029
1030 cmd_slot = sts->handle;
1031 Cmnd = hostdata->cmd_slots[cmd_slot];
1032 hostdata->cmd_slots[cmd_slot] = NULL;
1033
1034 TRACE("done", out_ptr, Cmnd);
1035
1036 if (le16_to_cpu(sts->completion_status) == CS_RESET_OCCURRED
1037 || le16_to_cpu(sts->completion_status) == CS_ABORTED
1038 || (le16_to_cpu(sts->status_flags) & STF_BUS_RESET))
1039 hostdata->send_marker = 1;
1040
1041 if (le16_to_cpu(sts->state_flags) & SF_GOT_SENSE)
1042 memcpy(Cmnd->sense_buffer, sts->req_sense_data,
1043 sizeof(Cmnd->sense_buffer));
1044
1045 DEBUG_INTR(isp1020_print_status_entry(sts));
1046
1047 if (sts->hdr.entry_type == ENTRY_STATUS)
1048 Cmnd->result = isp1020_return_status(sts);
1049 else
1050 Cmnd->result = DID_ERROR << 16;
1051
1052 if (Cmnd->use_sg)
1053 pci_unmap_sg(hostdata->pci_dev,
1054 (struct scatterlist *)Cmnd->buffer,
1055 Cmnd->use_sg,
1056 scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
1057 else if (Cmnd->request_bufflen)
1058 pci_unmap_single(hostdata->pci_dev,
1059 #ifdef CONFIG_QL_ISP_A64
1060 (dma_addr_t)((long)Cmnd->SCp.ptr),
1061 #else
1062 (u32)((long)Cmnd->SCp.ptr),
1063 #endif
1064 Cmnd->request_bufflen,
1065 scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
1066
1067 isp_outw(out_ptr, host, MBOX5);
1068 (*Cmnd->scsi_done)(Cmnd);
1069 }
1070 hostdata->res_out_ptr = out_ptr;
1071
1072 LEAVE_INTR("isp1020_intr_handler");
1073 }
1074
1075
1076 static int isp1020_return_status(struct Status_Entry *sts)
1077 {
1078 int host_status = DID_ERROR;
1079 #if DEBUG_ISP1020_INTR
1080 static char *reason[] = {
1081 "DID_OK",
1082 "DID_NO_CONNECT",
1083 "DID_BUS_BUSY",
1084 "DID_TIME_OUT",
1085 "DID_BAD_TARGET",
1086 "DID_ABORT",
1087 "DID_PARITY",
1088 "DID_ERROR",
1089 "DID_RESET",
1090 "DID_BAD_INTR"
1091 };
1092 #endif /* DEBUG_ISP1020_INTR */
1093
1094 ENTER("isp1020_return_status");
1095
1096 DEBUG(printk("qlogicisp : completion status = 0x%04x\n",
1097 le16_to_cpu(sts->completion_status)));
1098
1099 switch(le16_to_cpu(sts->completion_status)) {
1100 case CS_COMPLETE:
1101 host_status = DID_OK;
1102 break;
1103 case CS_INCOMPLETE:
1104 if (!(le16_to_cpu(sts->state_flags) & SF_GOT_BUS))
1105 host_status = DID_NO_CONNECT;
1106 else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_TARGET))
1107 host_status = DID_BAD_TARGET;
1108 else if (!(le16_to_cpu(sts->state_flags) & SF_SENT_CDB))
1109 host_status = DID_ERROR;
1110 else if (!(le16_to_cpu(sts->state_flags) & SF_TRANSFERRED_DATA))
1111 host_status = DID_ERROR;
1112 else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_STATUS))
1113 host_status = DID_ERROR;
1114 else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_SENSE))
1115 host_status = DID_ERROR;
1116 break;
1117 case CS_DMA_ERROR:
1118 case CS_TRANSPORT_ERROR:
1119 host_status = DID_ERROR;
1120 break;
1121 case CS_RESET_OCCURRED:
1122 host_status = DID_RESET;
1123 break;
1124 case CS_ABORTED:
1125 host_status = DID_ABORT;
1126 break;
1127 case CS_TIMEOUT:
1128 host_status = DID_TIME_OUT;
1129 break;
1130 case CS_DATA_OVERRUN:
1131 case CS_COMMAND_OVERRUN:
1132 case CS_STATUS_OVERRUN:
1133 case CS_BAD_MESSAGE:
1134 case CS_NO_MESSAGE_OUT:
1135 case CS_EXT_ID_FAILED:
1136 case CS_IDE_MSG_FAILED:
1137 case CS_ABORT_MSG_FAILED:
1138 case CS_NOP_MSG_FAILED:
1139 case CS_PARITY_ERROR_MSG_FAILED:
1140 case CS_DEVICE_RESET_MSG_FAILED:
1141 case CS_ID_MSG_FAILED:
1142 case CS_UNEXP_BUS_FREE:
1143 host_status = DID_ERROR;
1144 break;
1145 case CS_DATA_UNDERRUN:
1146 host_status = DID_OK;
1147 break;
1148 default:
1149 printk("qlogicisp : unknown completion status 0x%04x\n",
1150 le16_to_cpu(sts->completion_status));
1151 host_status = DID_ERROR;
1152 break;
1153 }
1154
1155 DEBUG_INTR(printk("qlogicisp : host status (%s) scsi status %x\n",
1156 reason[host_status], le16_to_cpu(sts->scsi_status)));
1157
1158 LEAVE("isp1020_return_status");
1159
1160 return (le16_to_cpu(sts->scsi_status) & STATUS_MASK) | (host_status << 16);
1161 }
1162
1163
1164 int isp1020_abort(Scsi_Cmnd *Cmnd)
1165 {
1166 u_short param[6];
1167 struct Scsi_Host *host;
1168 struct isp1020_hostdata *hostdata;
1169 int return_status = SCSI_ABORT_SUCCESS;
1170 u_int cmd_cookie;
1171 int i;
1172
1173 ENTER("isp1020_abort");
1174
1175 host = Cmnd->device->host;
1176 hostdata = (struct isp1020_hostdata *) host->hostdata;
1177
1178 for (i = 0; i < QLOGICISP_REQ_QUEUE_LEN + 1; i++)
1179 if (hostdata->cmd_slots[i] == Cmnd)
1180 break;
1181 cmd_cookie = i;
1182
1183 isp1020_disable_irqs(host);
1184
1185 param[0] = MBOX_ABORT;
1186 param[1] = (((u_short) Cmnd->device->id) << 8) | Cmnd->device->lun;
1187 param[2] = cmd_cookie >> 16;
1188 param[3] = cmd_cookie & 0xffff;
1189
1190 isp1020_mbox_command(host, param);
1191
1192 if (param[0] != MBOX_COMMAND_COMPLETE) {
1193 printk("qlogicisp : scsi abort failure: %x\n", param[0]);
1194 return_status = SCSI_ABORT_ERROR;
1195 }
1196
1197 isp1020_enable_irqs(host);
1198
1199 LEAVE("isp1020_abort");
1200
1201 return return_status;
1202 }
1203
1204
1205 int isp1020_reset(Scsi_Cmnd *Cmnd, unsigned int reset_flags)
1206 {
1207 u_short param[6];
1208 struct Scsi_Host *host;
1209 struct isp1020_hostdata *hostdata;
1210 int return_status = SCSI_RESET_SUCCESS;
1211
1212 ENTER("isp1020_reset");
1213
1214 host = Cmnd->device->host;
1215 hostdata = (struct isp1020_hostdata *) host->hostdata;
1216
1217 param[0] = MBOX_BUS_RESET;
1218 param[1] = hostdata->host_param.bus_reset_delay;
1219
1220 isp1020_disable_irqs(host);
1221
1222 isp1020_mbox_command(host, param);
1223
1224 if (param[0] != MBOX_COMMAND_COMPLETE) {
1225 printk("qlogicisp : scsi bus reset failure: %x\n", param[0]);
1226 return_status = SCSI_RESET_ERROR;
1227 }
1228
1229 isp1020_enable_irqs(host);
1230
1231 LEAVE("isp1020_reset");
1232
1233 return return_status;
1234 }
1235
1236
1237 int isp1020_biosparam(struct scsi_device *sdev, struct block_device *n,
1238 sector_t capacity, int ip[])
1239 {
1240 int size = capacity;
1241
1242 ENTER("isp1020_biosparam");
1243
1244 ip[0] = 64;
1245 ip[1] = 32;
1246 ip[2] = size >> 11;
1247 if (ip[2] > 1024) {
1248 ip[0] = 255;
1249 ip[1] = 63;
1250 ip[2] = size / (ip[0] * ip[1]);
1251 #if 0
1252 if (ip[2] > 1023)
1253 ip[2] = 1023;
1254 #endif
1255 }
1256
1257 LEAVE("isp1020_biosparam");
1258
1259 return 0;
1260 }
1261
1262
1263 static int isp1020_reset_hardware(struct Scsi_Host *host)
1264 {
1265 u_short param[6];
1266 int loop_count;
1267
1268 ENTER("isp1020_reset_hardware");
1269
1270 isp_outw(ISP_RESET, host, PCI_INTF_CTL);
1271 udelay(100);
1272 isp_outw(HCCR_RESET, host, HOST_HCCR);
1273 udelay(100);
1274 isp_outw(HCCR_RELEASE, host, HOST_HCCR);
1275 isp_outw(HCCR_BIOS_DISABLE, host, HOST_HCCR);
1276
1277 loop_count = DEFAULT_LOOP_COUNT;
1278 while (--loop_count && isp_inw(host, HOST_HCCR) == RISC_BUSY) {
1279 barrier();
1280 cpu_relax();
1281 }
1282 if (!loop_count)
1283 printk("qlogicisp: reset_hardware loop timeout\n");
1284
1285 isp_outw(0, host, ISP_CFG1);
1286
1287 #if DEBUG_ISP1020
1288 printk("qlogicisp : mbox 0 0x%04x \n", isp_inw(host, MBOX0));
1289 printk("qlogicisp : mbox 1 0x%04x \n", isp_inw(host, MBOX1));
1290 printk("qlogicisp : mbox 2 0x%04x \n", isp_inw(host, MBOX2));
1291 printk("qlogicisp : mbox 3 0x%04x \n", isp_inw(host, MBOX3));
1292 printk("qlogicisp : mbox 4 0x%04x \n", isp_inw(host, MBOX4));
1293 printk("qlogicisp : mbox 5 0x%04x \n", isp_inw(host, MBOX5));
1294 #endif /* DEBUG_ISP1020 */
1295
1296 param[0] = MBOX_NO_OP;
1297 isp1020_mbox_command(host, param);
1298 if (param[0] != MBOX_COMMAND_COMPLETE) {
1299 printk("qlogicisp : NOP test failed\n");
1300 return 1;
1301 }
1302
1303 DEBUG(printk("qlogicisp : loading risc ram\n"));
1304
1305 #if RELOAD_FIRMWARE
1306 for (loop_count = 0; loop_count < risc_code_length01; loop_count++) {
1307 param[0] = MBOX_WRITE_RAM_WORD;
1308 param[1] = risc_code_addr01 + loop_count;
1309 param[2] = risc_code01[loop_count];
1310 isp1020_mbox_command(host, param);
1311 if (param[0] != MBOX_COMMAND_COMPLETE) {
1312 printk("qlogicisp : firmware load failure at %d\n",
1313 loop_count);
1314 return 1;
1315 }
1316 }
1317 #endif /* RELOAD_FIRMWARE */
1318
1319 DEBUG(printk("qlogicisp : verifying checksum\n"));
1320
1321 param[0] = MBOX_VERIFY_CHECKSUM;
1322 param[1] = risc_code_addr01;
1323
1324 isp1020_mbox_command(host, param);
1325
1326 if (param[0] != MBOX_COMMAND_COMPLETE) {
1327 printk("qlogicisp : ram checksum failure\n");
1328 return 1;
1329 }
1330
1331 DEBUG(printk("qlogicisp : executing firmware\n"));
1332
1333 param[0] = MBOX_EXEC_FIRMWARE;
1334 param[1] = risc_code_addr01;
1335
1336 isp1020_mbox_command(host, param);
1337
1338 param[0] = MBOX_ABOUT_FIRMWARE;
1339
1340 isp1020_mbox_command(host, param);
1341
1342 if (param[0] != MBOX_COMMAND_COMPLETE) {
1343 printk("qlogicisp : about firmware failure\n");
1344 return 1;
1345 }
1346
1347 DEBUG(printk("qlogicisp : firmware major revision %d\n", param[1]));
1348 DEBUG(printk("qlogicisp : firmware minor revision %d\n", param[2]));
1349
1350 LEAVE("isp1020_reset_hardware");
1351
1352 return 0;
1353 }
1354
1355
1356 static int isp1020_init(struct Scsi_Host *sh)
1357 {
1358 u_long io_base, mem_base, io_flags, mem_flags;
1359 struct isp1020_hostdata *hostdata;
1360 u_char revision;
1361 u_int irq;
1362 u_short command;
1363 struct pci_dev *pdev;
1364
1365 ENTER("isp1020_init");
1366
1367 hostdata = (struct isp1020_hostdata *) sh->hostdata;
1368 pdev = hostdata->pci_dev;
1369
1370 if (pci_read_config_word(pdev, PCI_COMMAND, &command)
1371 || pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision))
1372 {
1373 printk("qlogicisp : error reading PCI configuration\n");
1374 return 1;
1375 }
1376
1377 io_base = pci_resource_start(pdev, 0);
1378 mem_base = pci_resource_start(pdev, 1);
1379 io_flags = pci_resource_flags(pdev, 0);
1380 mem_flags = pci_resource_flags(pdev, 1);
1381 irq = pdev->irq;
1382
1383 if (pdev->vendor != PCI_VENDOR_ID_QLOGIC) {
1384 printk("qlogicisp : 0x%04x is not QLogic vendor ID\n",
1385 pdev->vendor);
1386 return 1;
1387 }
1388
1389 if (pdev->device != PCI_DEVICE_ID_QLOGIC_ISP1020) {
1390 printk("qlogicisp : 0x%04x does not match ISP1020 device id\n",
1391 pdev->device);
1392 return 1;
1393 }
1394
1395 #ifdef __alpha__
1396 /* Force ALPHA to use bus I/O and not bus MEM.
1397 This is to avoid having to use HAE_MEM registers,
1398 which is broken on some platforms and with SMP. */
1399 command &= ~PCI_COMMAND_MEMORY;
1400 #endif
1401
1402 sh->io_port = io_base;
1403
1404 if (!request_region(sh->io_port, 0xff, "qlogicisp")) {
1405 printk("qlogicisp : i/o region 0x%lx-0x%lx already "
1406 "in use\n",
1407 sh->io_port, sh->io_port + 0xff);
1408 return 1;
1409 }
1410
1411 if ((command & PCI_COMMAND_MEMORY) &&
1412 ((mem_flags & 1) == 0)) {
1413 mem_base = (u_long) ioremap(mem_base, PAGE_SIZE);
1414 if (!mem_base) {
1415 printk("qlogicisp : i/o remapping failed.\n");
1416 goto out_release;
1417 }
1418 hostdata->memaddr = mem_base;
1419 } else {
1420 if (command & PCI_COMMAND_IO && (io_flags & 3) != 1) {
1421 printk("qlogicisp : i/o mapping is disabled\n");
1422 goto out_release;
1423 }
1424 hostdata->memaddr = 0; /* zero to signify no i/o mapping */
1425 mem_base = 0;
1426 }
1427
1428 if (revision != ISP1020_REV_ID)
1429 printk("qlogicisp : new isp1020 revision ID (%d)\n", revision);
1430
1431 if (isp_inw(sh, PCI_ID_LOW) != PCI_VENDOR_ID_QLOGIC
1432 || isp_inw(sh, PCI_ID_HIGH) != PCI_DEVICE_ID_QLOGIC_ISP1020)
1433 {
1434 printk("qlogicisp : can't decode %s address space 0x%lx\n",
1435 (io_base ? "I/O" : "MEM"),
1436 (io_base ? io_base : mem_base));
1437 goto out_unmap;
1438 }
1439
1440 hostdata->revision = revision;
1441
1442 sh->irq = irq;
1443 sh->max_id = MAX_TARGETS;
1444 sh->max_lun = MAX_LUNS;
1445
1446 hostdata->res_cpu = pci_alloc_consistent(hostdata->pci_dev,
1447 QSIZE(RES_QUEUE_LEN),
1448 &hostdata->res_dma);
1449 if (hostdata->res_cpu == NULL) {
1450 printk("qlogicisp : can't allocate response queue\n");
1451 goto out_unmap;
1452 }
1453
1454 hostdata->req_cpu = pci_alloc_consistent(hostdata->pci_dev,
1455 QSIZE(QLOGICISP_REQ_QUEUE_LEN),
1456 &hostdata->req_dma);
1457 if (hostdata->req_cpu == NULL) {
1458 pci_free_consistent(hostdata->pci_dev,
1459 QSIZE(RES_QUEUE_LEN),
1460 hostdata->res_cpu,
1461 hostdata->res_dma);
1462 printk("qlogicisp : can't allocate request queue\n");
1463 goto out_unmap;
1464 }
1465
1466 pci_set_master(pdev);
1467
1468 LEAVE("isp1020_init");
1469
1470 return 0;
1471
1472 out_unmap:
1473 iounmap((void *)hostdata->memaddr);
1474 out_release:
1475 release_region(sh->io_port, 0xff);
1476 return 1;
1477 }
1478
1479
1480 #if USE_NVRAM_DEFAULTS
1481
1482 static int isp1020_get_defaults(struct Scsi_Host *host)
1483 {
1484 int i;
1485 u_short value;
1486 struct isp1020_hostdata *hostdata =
1487 (struct isp1020_hostdata *) host->hostdata;
1488
1489 ENTER("isp1020_get_defaults");
1490
1491 if (!isp1020_verify_nvram(host)) {
1492 printk("qlogicisp : nvram checksum failure\n");
1493 printk("qlogicisp : attempting to use default parameters\n");
1494 return isp1020_set_defaults(host);
1495 }
1496
1497 value = isp1020_read_nvram_word(host, 2);
1498 hostdata->host_param.fifo_threshold = (value >> 8) & 0x03;
1499 hostdata->host_param.host_adapter_enable = (value >> 11) & 0x01;
1500 hostdata->host_param.initiator_scsi_id = (value >> 12) & 0x0f;
1501
1502 value = isp1020_read_nvram_word(host, 3);
1503 hostdata->host_param.bus_reset_delay = value & 0xff;
1504 hostdata->host_param.retry_count = value >> 8;
1505
1506 value = isp1020_read_nvram_word(host, 4);
1507 hostdata->host_param.retry_delay = value & 0xff;
1508 hostdata->host_param.async_data_setup_time = (value >> 8) & 0x0f;
1509 hostdata->host_param.req_ack_active_negation = (value >> 12) & 0x01;
1510 hostdata->host_param.data_line_active_negation = (value >> 13) & 0x01;
1511 hostdata->host_param.data_dma_burst_enable = (value >> 14) & 0x01;
1512 hostdata->host_param.command_dma_burst_enable = (value >> 15);
1513
1514 value = isp1020_read_nvram_word(host, 5);
1515 hostdata->host_param.tag_aging = value & 0xff;
1516
1517 value = isp1020_read_nvram_word(host, 6);
1518 hostdata->host_param.selection_timeout = value & 0xffff;
1519
1520 value = isp1020_read_nvram_word(host, 7);
1521 hostdata->host_param.max_queue_depth = value & 0xffff;
1522
1523 #if DEBUG_ISP1020_SETUP
1524 printk("qlogicisp : fifo threshold=%d\n",
1525 hostdata->host_param.fifo_threshold);
1526 printk("qlogicisp : initiator scsi id=%d\n",
1527 hostdata->host_param.initiator_scsi_id);
1528 printk("qlogicisp : bus reset delay=%d\n",
1529 hostdata->host_param.bus_reset_delay);
1530 printk("qlogicisp : retry count=%d\n",
1531 hostdata->host_param.retry_count);
1532 printk("qlogicisp : retry delay=%d\n",
1533 hostdata->host_param.retry_delay);
1534 printk("qlogicisp : async data setup time=%d\n",
1535 hostdata->host_param.async_data_setup_time);
1536 printk("qlogicisp : req/ack active negation=%d\n",
1537 hostdata->host_param.req_ack_active_negation);
1538 printk("qlogicisp : data line active negation=%d\n",
1539 hostdata->host_param.data_line_active_negation);
1540 printk("qlogicisp : data DMA burst enable=%d\n",
1541 hostdata->host_param.data_dma_burst_enable);
1542 printk("qlogicisp : command DMA burst enable=%d\n",
1543 hostdata->host_param.command_dma_burst_enable);
1544 printk("qlogicisp : tag age limit=%d\n",
1545 hostdata->host_param.tag_aging);
1546 printk("qlogicisp : selection timeout limit=%d\n",
1547 hostdata->host_param.selection_timeout);
1548 printk("qlogicisp : max queue depth=%d\n",
1549 hostdata->host_param.max_queue_depth);
1550 #endif /* DEBUG_ISP1020_SETUP */
1551
1552 for (i = 0; i < MAX_TARGETS; i++) {
1553
1554 value = isp1020_read_nvram_word(host, 14 + i * 3);
1555 hostdata->dev_param[i].device_flags = value & 0xff;
1556 hostdata->dev_param[i].execution_throttle = value >> 8;
1557
1558 value = isp1020_read_nvram_word(host, 15 + i * 3);
1559 hostdata->dev_param[i].synchronous_period = value & 0xff;
1560 hostdata->dev_param[i].synchronous_offset = (value >> 8) & 0x0f;
1561 hostdata->dev_param[i].device_enable = (value >> 12) & 0x01;
1562
1563 #if DEBUG_ISP1020_SETUP
1564 printk("qlogicisp : target 0x%02x\n", i);
1565 printk("qlogicisp : device flags=0x%02x\n",
1566 hostdata->dev_param[i].device_flags);
1567 printk("qlogicisp : execution throttle=%d\n",
1568 hostdata->dev_param[i].execution_throttle);
1569 printk("qlogicisp : synchronous period=%d\n",
1570 hostdata->dev_param[i].synchronous_period);
1571 printk("qlogicisp : synchronous offset=%d\n",
1572 hostdata->dev_param[i].synchronous_offset);
1573 printk("qlogicisp : device enable=%d\n",
1574 hostdata->dev_param[i].device_enable);
1575 #endif /* DEBUG_ISP1020_SETUP */
1576 }
1577
1578 LEAVE("isp1020_get_defaults");
1579
1580 return 0;
1581 }
1582
1583
1584 #define ISP1020_NVRAM_LEN 0x40
1585 #define ISP1020_NVRAM_SIG1 0x5349
1586 #define ISP1020_NVRAM_SIG2 0x2050
1587
1588 static int isp1020_verify_nvram(struct Scsi_Host *host)
1589 {
1590 int i;
1591 u_short value;
1592 u_char checksum = 0;
1593
1594 for (i = 0; i < ISP1020_NVRAM_LEN; i++) {
1595 value = isp1020_read_nvram_word(host, i);
1596
1597 switch (i) {
1598 case 0:
1599 if (value != ISP1020_NVRAM_SIG1) return 0;
1600 break;
1601 case 1:
1602 if (value != ISP1020_NVRAM_SIG2) return 0;
1603 break;
1604 case 2:
1605 if ((value & 0xff) != 0x02) return 0;
1606 break;
1607 }
1608 checksum += value & 0xff;
1609 checksum += value >> 8;
1610 }
1611
1612 return (checksum == 0);
1613 }
1614
1615 #define NVRAM_DELAY() udelay(2) /* 2 microsecond delay */
1616
1617
1618 u_short isp1020_read_nvram_word(struct Scsi_Host *host, u_short byte)
1619 {
1620 int i;
1621 u_short value, output, input;
1622
1623 byte &= 0x3f; byte |= 0x0180;
1624
1625 for (i = 8; i >= 0; i--) {
1626 output = ((byte >> i) & 0x1) ? 0x4 : 0x0;
1627 isp_outw(output | 0x2, host, PCI_NVRAM); NVRAM_DELAY();
1628 isp_outw(output | 0x3, host, PCI_NVRAM); NVRAM_DELAY();
1629 isp_outw(output | 0x2, host, PCI_NVRAM); NVRAM_DELAY();
1630 }
1631
1632 for (i = 0xf, value = 0; i >= 0; i--) {
1633 value <<= 1;
1634 isp_outw(0x3, host, PCI_NVRAM); NVRAM_DELAY();
1635 input = isp_inw(host, PCI_NVRAM); NVRAM_DELAY();
1636 isp_outw(0x2, host, PCI_NVRAM); NVRAM_DELAY();
1637 if (input & 0x8) value |= 1;
1638 }
1639
1640 isp_outw(0x0, host, PCI_NVRAM); NVRAM_DELAY();
1641
1642 return value;
1643 }
1644
1645 #endif /* USE_NVRAM_DEFAULTS */
1646
1647
1648 static int isp1020_set_defaults(struct Scsi_Host *host)
1649 {
1650 struct isp1020_hostdata *hostdata =
1651 (struct isp1020_hostdata *) host->hostdata;
1652 int i;
1653
1654 ENTER("isp1020_set_defaults");
1655
1656 hostdata->host_param.fifo_threshold = 2;
1657 hostdata->host_param.host_adapter_enable = 1;
1658 hostdata->host_param.initiator_scsi_id = 7;
1659 hostdata->host_param.bus_reset_delay = 3;
1660 hostdata->host_param.retry_count = 0;
1661 hostdata->host_param.retry_delay = 1;
1662 hostdata->host_param.async_data_setup_time = 6;
1663 hostdata->host_param.req_ack_active_negation = 1;
1664 hostdata->host_param.data_line_active_negation = 1;
1665 hostdata->host_param.data_dma_burst_enable = 1;
1666 hostdata->host_param.command_dma_burst_enable = 1;
1667 hostdata->host_param.tag_aging = 8;
1668 hostdata->host_param.selection_timeout = 250;
1669 hostdata->host_param.max_queue_depth = 256;
1670
1671 for (i = 0; i < MAX_TARGETS; i++) {
1672 hostdata->dev_param[i].device_flags = 0xfd;
1673 hostdata->dev_param[i].execution_throttle = 16;
1674 hostdata->dev_param[i].synchronous_period = 25;
1675 hostdata->dev_param[i].synchronous_offset = 12;
1676 hostdata->dev_param[i].device_enable = 1;
1677 }
1678
1679 LEAVE("isp1020_set_defaults");
1680
1681 return 0;
1682 }
1683
1684
1685 static int isp1020_load_parameters(struct Scsi_Host *host)
1686 {
1687 int i, k;
1688 #ifdef CONFIG_QL_ISP_A64
1689 u_long queue_addr;
1690 u_short param[8];
1691 #else
1692 u_int queue_addr;
1693 u_short param[6];
1694 #endif
1695 u_short isp_cfg1, hwrev;
1696 struct isp1020_hostdata *hostdata =
1697 (struct isp1020_hostdata *) host->hostdata;
1698
1699 ENTER("isp1020_load_parameters");
1700
1701 hwrev = isp_inw(host, ISP_CFG0) & ISP_CFG0_HWMSK;
1702 isp_cfg1 = ISP_CFG1_F64 | ISP_CFG1_BENAB;
1703 if (hwrev == ISP_CFG0_1040A) {
1704 /* Busted fifo, says mjacob. */
1705 isp_cfg1 &= ISP_CFG1_BENAB;
1706 }
1707
1708 isp_outw(isp_inw(host, ISP_CFG1) | isp_cfg1, host, ISP_CFG1);
1709 isp_outw(isp_inw(host, CDMA_CONF) | DMA_CONF_BENAB, host, CDMA_CONF);
1710 isp_outw(isp_inw(host, DDMA_CONF) | DMA_CONF_BENAB, host, DDMA_CONF);
1711
1712 param[0] = MBOX_SET_INIT_SCSI_ID;
1713 param[1] = hostdata->host_param.initiator_scsi_id;
1714
1715 isp1020_mbox_command(host, param);
1716
1717 if (param[0] != MBOX_COMMAND_COMPLETE) {
1718 printk("qlogicisp : set initiator id failure\n");
1719 return 1;
1720 }
1721
1722 param[0] = MBOX_SET_RETRY_COUNT;
1723 param[1] = hostdata->host_param.retry_count;
1724 param[2] = hostdata->host_param.retry_delay;
1725
1726 isp1020_mbox_command(host, param);
1727
1728 if (param[0] != MBOX_COMMAND_COMPLETE) {
1729 printk("qlogicisp : set retry count failure\n");
1730 return 1;
1731 }
1732
1733 param[0] = MBOX_SET_ASYNC_DATA_SETUP_TIME;
1734 param[1] = hostdata->host_param.async_data_setup_time;
1735
1736 isp1020_mbox_command(host, param);
1737
1738 if (param[0] != MBOX_COMMAND_COMPLETE) {
1739 printk("qlogicisp : async data setup time failure\n");
1740 return 1;
1741 }
1742
1743 param[0] = MBOX_SET_ACTIVE_NEG_STATE;
1744 param[1] = (hostdata->host_param.req_ack_active_negation << 4)
1745 | (hostdata->host_param.data_line_active_negation << 5);
1746
1747 isp1020_mbox_command(host, param);
1748
1749 if (param[0] != MBOX_COMMAND_COMPLETE) {
1750 printk("qlogicisp : set active negation state failure\n");
1751 return 1;
1752 }
1753
1754 param[0] = MBOX_SET_PCI_CONTROL_PARAMS;
1755 param[1] = hostdata->host_param.data_dma_burst_enable << 1;
1756 param[2] = hostdata->host_param.command_dma_burst_enable << 1;
1757
1758 isp1020_mbox_command(host, param);
1759
1760 if (param[0] != MBOX_COMMAND_COMPLETE) {
1761 printk("qlogicisp : set pci control parameter failure\n");
1762 return 1;
1763 }
1764
1765 param[0] = MBOX_SET_TAG_AGE_LIMIT;
1766 param[1] = hostdata->host_param.tag_aging;
1767
1768 isp1020_mbox_command(host, param);
1769
1770 if (param[0] != MBOX_COMMAND_COMPLETE) {
1771 printk("qlogicisp : set tag age limit failure\n");
1772 return 1;
1773 }
1774
1775 param[0] = MBOX_SET_SELECT_TIMEOUT;
1776 param[1] = hostdata->host_param.selection_timeout;
1777
1778 isp1020_mbox_command(host, param);
1779
1780 if (param[0] != MBOX_COMMAND_COMPLETE) {
1781 printk("qlogicisp : set selection timeout failure\n");
1782 return 1;
1783 }
1784
1785 for (i = 0; i < MAX_TARGETS; i++) {
1786
1787 if (!hostdata->dev_param[i].device_enable)
1788 continue;
1789
1790 param[0] = MBOX_SET_TARGET_PARAMS;
1791 param[1] = i << 8;
1792 param[2] = hostdata->dev_param[i].device_flags << 8;
1793 param[3] = (hostdata->dev_param[i].synchronous_offset << 8)
1794 | hostdata->dev_param[i].synchronous_period;
1795
1796 isp1020_mbox_command(host, param);
1797
1798 if (param[0] != MBOX_COMMAND_COMPLETE) {
1799 printk("qlogicisp : set target parameter failure\n");
1800 return 1;
1801 }
1802
1803 for (k = 0; k < MAX_LUNS; k++) {
1804
1805 param[0] = MBOX_SET_DEV_QUEUE_PARAMS;
1806 param[1] = (i << 8) | k;
1807 param[2] = hostdata->host_param.max_queue_depth;
1808 param[3] = hostdata->dev_param[i].execution_throttle;
1809
1810 isp1020_mbox_command(host, param);
1811
1812 if (param[0] != MBOX_COMMAND_COMPLETE) {
1813 printk("qlogicisp : set device queue "
1814 "parameter failure\n");
1815 return 1;
1816 }
1817 }
1818 }
1819
1820 queue_addr = hostdata->res_dma;
1821 #ifdef CONFIG_QL_ISP_A64
1822 param[0] = MBOX_CMD_INIT_RESPONSE_QUEUE_64;
1823 #else
1824 param[0] = MBOX_INIT_RES_QUEUE;
1825 #endif
1826 param[1] = RES_QUEUE_LEN + 1;
1827 param[2] = (u_short) (queue_addr >> 16);
1828 param[3] = (u_short) (queue_addr & 0xffff);
1829 param[4] = 0;
1830 param[5] = 0;
1831 #ifdef CONFIG_QL_ISP_A64
1832 param[6] = (u_short) (queue_addr >> 48);
1833 param[7] = (u_short) (queue_addr >> 32);
1834 #endif
1835
1836 isp1020_mbox_command(host, param);
1837
1838 if (param[0] != MBOX_COMMAND_COMPLETE) {
1839 printk("qlogicisp : set response queue failure\n");
1840 return 1;
1841 }
1842
1843 queue_addr = hostdata->req_dma;
1844 #ifdef CONFIG_QL_ISP_A64
1845 param[0] = MBOX_CMD_INIT_REQUEST_QUEUE_64;
1846 #else
1847 param[0] = MBOX_INIT_REQ_QUEUE;
1848 #endif
1849 param[1] = QLOGICISP_REQ_QUEUE_LEN + 1;
1850 param[2] = (u_short) (queue_addr >> 16);
1851 param[3] = (u_short) (queue_addr & 0xffff);
1852 param[4] = 0;
1853
1854 #ifdef CONFIG_QL_ISP_A64
1855 param[5] = 0;
1856 param[6] = (u_short) (queue_addr >> 48);
1857 param[7] = (u_short) (queue_addr >> 32);
1858 #endif
1859
1860 isp1020_mbox_command(host, param);
1861
1862 if (param[0] != MBOX_COMMAND_COMPLETE) {
1863 printk("qlogicisp : set request queue failure\n");
1864 return 1;
1865 }
1866
1867 LEAVE("isp1020_load_parameters");
1868
1869 return 0;
1870 }
1871
1872
1873 /*
1874 * currently, this is only called during initialization or abort/reset,
1875 * at which times interrupts are disabled, so polling is OK, I guess...
1876 */
1877 static int isp1020_mbox_command(struct Scsi_Host *host, u_short param[])
1878 {
1879 int loop_count;
1880
1881 if (mbox_param[param[0]] == 0)
1882 return 1;
1883
1884 loop_count = DEFAULT_LOOP_COUNT;
1885 while (--loop_count && isp_inw(host, HOST_HCCR) & 0x0080) {
1886 barrier();
1887 cpu_relax();
1888 }
1889 if (!loop_count)
1890 printk("qlogicisp: mbox_command loop timeout #1\n");
1891
1892 switch(mbox_param[param[0]] >> 4) {
1893 case 8: isp_outw(param[7], host, MBOX7);
1894 case 7: isp_outw(param[6], host, MBOX6);
1895 case 6: isp_outw(param[5], host, MBOX5);
1896 case 5: isp_outw(param[4], host, MBOX4);
1897 case 4: isp_outw(param[3], host, MBOX3);
1898 case 3: isp_outw(param[2], host, MBOX2);
1899 case 2: isp_outw(param[1], host, MBOX1);
1900 case 1: isp_outw(param[0], host, MBOX0);
1901 }
1902
1903 isp_outw(0x0, host, PCI_SEMAPHORE);
1904 isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
1905 isp_outw(HCCR_SET_HOST_INTR, host, HOST_HCCR);
1906
1907 loop_count = DEFAULT_LOOP_COUNT;
1908 while (--loop_count && !(isp_inw(host, PCI_INTF_STS) & 0x04)) {
1909 barrier();
1910 cpu_relax();
1911 }
1912 if (!loop_count)
1913 printk("qlogicisp: mbox_command loop timeout #2\n");
1914
1915 loop_count = DEFAULT_LOOP_COUNT;
1916 while (--loop_count && isp_inw(host, MBOX0) == 0x04) {
1917 barrier();
1918 cpu_relax();
1919 }
1920 if (!loop_count)
1921 printk("qlogicisp: mbox_command loop timeout #3\n");
1922
1923 switch(mbox_param[param[0]] & 0xf) {
1924 case 8: param[7] = isp_inw(host, MBOX7);
1925 case 7: param[6] = isp_inw(host, MBOX6);
1926 case 6: param[5] = isp_inw(host, MBOX5);
1927 case 5: param[4] = isp_inw(host, MBOX4);
1928 case 4: param[3] = isp_inw(host, MBOX3);
1929 case 3: param[2] = isp_inw(host, MBOX2);
1930 case 2: param[1] = isp_inw(host, MBOX1);
1931 case 1: param[0] = isp_inw(host, MBOX0);
1932 }
1933
1934 isp_outw(0x0, host, PCI_SEMAPHORE);
1935 isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
1936
1937 return 0;
1938 }
1939
1940
1941 #if DEBUG_ISP1020_INTR
1942
1943 void isp1020_print_status_entry(struct Status_Entry *status)
1944 {
1945 int i;
1946
1947 printk("qlogicisp : entry count = 0x%02x, type = 0x%02x, flags = 0x%02x\n",
1948 status->hdr.entry_cnt, status->hdr.entry_type, status->hdr.flags);
1949 printk("qlogicisp : scsi status = 0x%04x, completion status = 0x%04x\n",
1950 le16_to_cpu(status->scsi_status), le16_to_cpu(status->completion_status));
1951 printk("qlogicisp : state flags = 0x%04x, status flags = 0x%04x\n",
1952 le16_to_cpu(status->state_flags), le16_to_cpu(status->status_flags));
1953 printk("qlogicisp : time = 0x%04x, request sense length = 0x%04x\n",
1954 le16_to_cpu(status->time), le16_to_cpu(status->req_sense_len));
1955 printk("qlogicisp : residual transfer length = 0x%08x\n",
1956 le32_to_cpu(status->residual));
1957
1958 for (i = 0; i < le16_to_cpu(status->req_sense_len); i++)
1959 printk("qlogicisp : sense data = 0x%02x\n", status->req_sense_data[i]);
1960 }
1961
1962 #endif /* DEBUG_ISP1020_INTR */
1963
1964
1965 #if DEBUG_ISP1020
1966
1967 void isp1020_print_scsi_cmd(Scsi_Cmnd *cmd)
1968 {
1969 int i;
1970
1971 printk("qlogicisp : target = 0x%02x, lun = 0x%02x, cmd_len = 0x%02x\n",
1972 cmd->target, cmd->lun, cmd->cmd_len);
1973 printk("qlogicisp : command = ");
1974 for (i = 0; i < cmd->cmd_len; i++)
1975 printk("0x%02x ", cmd->cmnd[i]);
1976 printk("\n");
1977 }
1978
1979 #endif /* DEBUG_ISP1020 */
1980
1981 MODULE_LICENSE("GPL");
1982
1983 static Scsi_Host_Template driver_template = {
1984 .detect = isp1020_detect,
1985 .release = isp1020_release,
1986 .info = isp1020_info,
1987 .queuecommand = isp1020_queuecommand,
1988 .bios_param = isp1020_biosparam,
1989 .can_queue = QLOGICISP_REQ_QUEUE_LEN,
1990 .this_id = -1,
1991 .sg_tablesize = QLOGICISP_MAX_SG(QLOGICISP_REQ_QUEUE_LEN),
1992 .cmd_per_lun = 1,
1993 .use_clustering = DISABLE_CLUSTERING,
1994 };
1995 #include "scsi_module.c"
MOXA 2.6.9 from sdlinux-moxaart.tgz