drivers/scsi/i91uscsi.h

   1 /**************************************************************************
   2  * Initio 9100 device driver for Linux.
   3  *
   4  * Copyright (c) 1994-1998 Initio Corporation
   5  * All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2, or (at your option)
  10  * any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; see the file COPYING.  If not, write to
  19  * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  20  *
  21  * --------------------------------------------------------------------------
  22  *
  23  * Redistribution and use in source and binary forms, with or without
  24  * modification, are permitted provided that the following conditions
  25  * are met:
  26  * 1. Redistributions of source code must retain the above copyright
  27  *    notice, this list of conditions, and the following disclaimer,
  28  *    without modification, immediately at the beginning of the file.
  29  * 2. Redistributions in binary form must reproduce the above copyright
  30  *    notice, this list of conditions and the following disclaimer in the
  31  *    documentation and/or other materials provided with the distribution.
  32  * 3. The name of the author may not be used to endorse or promote products
  33  *    derived from this software without specific prior written permission.
  34  *
  35  * Where this Software is combined with software released under the terms of
  36  * the GNU General Public License ("GPL") and the terms of the GPL would require the
  37  * combined work to also be released under the terms of the GPL, the terms
  38  * and conditions of this License will apply in addition to those of the
  39  * GPL with the exception of any terms or conditions of this License that
  40  * conflict with, or are expressly prohibited by, the GPL.
  41  *
  42  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  43  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  44  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  45  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  46  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  47  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  48  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  49  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  50  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  51  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  52  * SUCH DAMAGE.
  53  *
  54  **************************************************************************/
  55
  56 #include <linux/config.h>
  57 #include <linux/types.h>
  58
  59 #define ULONG   unsigned long
  60 #define USHORT  unsigned short
  61 #define UCHAR   unsigned char
  62 #define BYTE    unsigned char
  63 #define WORD    unsigned short
  64 #define DWORD   unsigned long
  65 #define UBYTE   unsigned char
  66 #define UWORD   unsigned short
  67 #define UDWORD  unsigned long
  68 #define U32     u32
  69
  70 #ifndef FAILURE
  71 #define FAILURE  (-1)
  72 #endif
  73
  74 #define TOTAL_SG_ENTRY          32
  75 #define MAX_SUPPORTED_ADAPTERS  8
  76 #define MAX_OFFSET              15
  77 #define MAX_TARGETS             16
  78
  79 #define INI_VENDOR_ID   0x1101  /* Initio's PCI vendor ID       */
  80 #define I950_DEVICE_ID  0x9500  /* Initio's inic-950 product ID   */
  81 #define I940_DEVICE_ID  0x9400  /* Initio's inic-940 product ID   */
  82 #define I935_DEVICE_ID  0x9401  /* Initio's inic-935 product ID   */
  83
  84 #define _I91USCSI_H
  85
  86 typedef struct {
  87         unsigned short base;
  88         unsigned short vec;
  89 } i91u_config;
  90
  91 /***************************************/
  92 /*  Tulip Configuration Register Set */
  93 /***************************************/
  94 #define TUL_PVID        0x00    /* Vendor ID                    */
  95 #define TUL_PDID        0x02    /* Device ID                    */
  96 #define TUL_PCMD        0x04    /* Command                      */
  97 #define TUL_PSTUS       0x06    /* Status                       */
  98 #define TUL_PRID        0x08    /* Revision number              */
  99 #define TUL_PPI         0x09    /* Programming interface        */
 100 #define TUL_PSC         0x0A    /* Sub Class                    */
 101 #define TUL_PBC         0x0B    /* Base Class                   */
 102 #define TUL_PCLS        0x0C    /* Cache line size              */
 103 #define TUL_PLTR        0x0D    /* Latency timer                */
 104 #define TUL_PHDT        0x0E    /* Header type                  */
 105 #define TUL_PBIST       0x0F    /* BIST                         */
 106 #define TUL_PBAD        0x10    /* Base address                 */
 107 #define TUL_PBAD1       0x14    /* Base address                 */
 108 #define TUL_PBAD2       0x18    /* Base address                 */
 109 #define TUL_PBAD3       0x1C    /* Base address                 */
 110 #define TUL_PBAD4       0x20    /* Base address                 */
 111 #define TUL_PBAD5       0x24    /* Base address                 */
 112 #define TUL_PRSVD       0x28    /* Reserved                     */
 113 #define TUL_PRSVD1      0x2C    /* Reserved                     */
 114 #define TUL_PRAD        0x30    /* Expansion ROM base address   */
 115 #define TUL_PRSVD2      0x34    /* Reserved                     */
 116 #define TUL_PRSVD3      0x38    /* Reserved                     */
 117 #define TUL_PINTL       0x3C    /* Interrupt line               */
 118 #define TUL_PINTP       0x3D    /* Interrupt pin                */
 119 #define TUL_PIGNT       0x3E    /* MIN_GNT                      */
 120 #define TUL_PMGNT       0x3F    /* MAX_GNT                      */
 121
 122 /************************/
 123 /*  Jasmin Register Set */
 124 /************************/
 125 #define TUL_HACFG0      0x40    /* H/A Configuration Register 0         */
 126 #define TUL_HACFG1      0x41    /* H/A Configuration Register 1         */
 127 #define TUL_HACFG2      0x42    /* H/A Configuration Register 2         */
 128
 129 #define TUL_SDCFG0      0x44    /* SCSI Device Configuration 0          */
 130 #define TUL_SDCFG1      0x45    /* SCSI Device Configuration 1          */
 131 #define TUL_SDCFG2      0x46    /* SCSI Device Configuration 2          */
 132 #define TUL_SDCFG3      0x47    /* SCSI Device Configuration 3          */
 133
 134 #define TUL_GINTS       0x50    /* Global Interrupt Status Register     */
 135 #define TUL_GIMSK       0x52    /* Global Interrupt MASK Register       */
 136 #define TUL_GCTRL       0x54    /* Global Control Register              */
 137 #define TUL_GCTRL_EEPROM_BIT    0x04
 138 #define TUL_GCTRL1      0x55    /* Global Control Register              */
 139 #define TUL_DMACFG      0x5B    /* DMA configuration                    */
 140 #define TUL_NVRAM       0x5D    /* Non-volatile RAM port                */
 141
 142 #define TUL_SCnt0       0x80    /* 00 R/W Transfer Counter Low          */
 143 #define TUL_SCnt1       0x81    /* 01 R/W Transfer Counter Mid          */
 144 #define TUL_SCnt2       0x82    /* 02 R/W Transfer Count High           */
 145 #define TUL_SFifoCnt    0x83    /* 03 R   FIFO counter                  */
 146 #define TUL_SIntEnable  0x84    /* 03 W   Interrupt enble               */
 147 #define TUL_SInt        0x84    /* 04 R   Interrupt Register            */
 148 #define TUL_SCtrl0      0x85    /* 05 W   Control 0                     */
 149 #define TUL_SStatus0    0x85    /* 05 R   Status 0                      */
 150 #define TUL_SCtrl1      0x86    /* 06 W   Control 1                     */
 151 #define TUL_SStatus1    0x86    /* 06 R   Status 1                      */
 152 #define TUL_SConfig     0x87    /* 07 W   Configuration                 */
 153 #define TUL_SStatus2    0x87    /* 07 R   Status 2                      */
 154 #define TUL_SPeriod     0x88    /* 08 W   Sync. Transfer Period & Offset */
 155 #define TUL_SOffset     0x88    /* 08 R   Offset                        */
 156 #define TUL_SScsiId     0x89    /* 09 W   SCSI ID                       */
 157 #define TUL_SBusId      0x89    /* 09 R   SCSI BUS ID                   */
 158 #define TUL_STimeOut    0x8A    /* 0A W   Sel/Resel Time Out Register   */
 159 #define TUL_SIdent      0x8A    /* 0A R   Identify Message Register     */
 160 #define TUL_SAvail      0x8A    /* 0A R   Availiable Counter Register   */
 161 #define TUL_SData       0x8B    /* 0B R/W SCSI data in/out              */
 162 #define TUL_SFifo       0x8C    /* 0C R/W FIFO                          */
 163 #define TUL_SSignal     0x90    /* 10 R/W SCSI signal in/out            */
 164 #define TUL_SCmd        0x91    /* 11 R/W Command                       */
 165 #define TUL_STest0      0x92    /* 12 R/W Test0                         */
 166 #define TUL_STest1      0x93    /* 13 R/W Test1                         */
 167 #define TUL_SCFG1       0x94    /* 14 R/W Configuration                 */
 168
 169 #define TUL_XAddH       0xC0    /*DMA Transfer Physical Address         */
 170 #define TUL_XAddW       0xC8    /*DMA Current Transfer Physical Address */
 171 #define TUL_XCntH       0xD0    /*DMA Transfer Counter                  */
 172 #define TUL_XCntW       0xD4    /*DMA Current Transfer Counter          */
 173 #define TUL_XCmd        0xD8    /*DMA Command Register                  */
 174 #define TUL_Int         0xDC    /*Interrupt Register                    */
 175 #define TUL_XStatus     0xDD    /*DMA status Register                   */
 176 #define TUL_Mask        0xE0    /*Interrupt Mask Register               */
 177 #define TUL_XCtrl       0xE4    /*DMA Control Register                  */
 178 #define TUL_XCtrl1      0xE5    /*DMA Control Register 1                */
 179 #define TUL_XFifo       0xE8    /*DMA FIFO                              */
 180
 181 #define TUL_WCtrl       0xF7    /*Bus master wait state control         */
 182 #define TUL_DCtrl       0xFB    /*DMA delay control                     */
 183
 184 /*----------------------------------------------------------------------*/
 185 /*   bit definition for Command register of Configuration Space Header  */
 186 /*----------------------------------------------------------------------*/
 187 #define BUSMS           0x04    /* BUS MASTER Enable                    */
 188 #define IOSPA           0x01    /* IO Space Enable                      */
 189
 190 /*----------------------------------------------------------------------*/
 191 /* Command Codes of Tulip SCSI Command register                         */
 192 /*----------------------------------------------------------------------*/
 193 #define TSC_EN_RESEL    0x80    /* Enable Reselection                   */
 194 #define TSC_CMD_COMP    0x84    /* Command Complete Sequence            */
 195 #define TSC_SEL         0x01    /* Select Without ATN Sequence          */
 196 #define TSC_SEL_ATN     0x11    /* Select With ATN Sequence             */
 197 #define TSC_SEL_ATN_DMA 0x51    /* Select With ATN Sequence with DMA    */
 198 #define TSC_SEL_ATN3    0x31    /* Select With ATN3 Sequence            */
 199 #define TSC_SEL_ATNSTOP 0x12    /* Select With ATN and Stop Sequence    */
 200 #define TSC_SELATNSTOP  0x1E    /* Select With ATN and Stop Sequence    */
 201
 202 #define TSC_SEL_ATN_DIRECT_IN   0x95    /* Select With ATN Sequence     */
 203 #define TSC_SEL_ATN_DIRECT_OUT  0x15    /* Select With ATN Sequence     */
 204 #define TSC_SEL_ATN3_DIRECT_IN  0xB5    /* Select With ATN3 Sequence    */
 205 #define TSC_SEL_ATN3_DIRECT_OUT 0x35    /* Select With ATN3 Sequence    */
 206 #define TSC_XF_DMA_OUT_DIRECT   0x06    /* DMA Xfer Infomation out      */
 207 #define TSC_XF_DMA_IN_DIRECT    0x86    /* DMA Xfer Infomation in       */
 208
 209 #define TSC_XF_DMA_OUT  0x43    /* DMA Xfer Infomation out              */
 210 #define TSC_XF_DMA_IN   0xC3    /* DMA Xfer Infomation in               */
 211 #define TSC_XF_FIFO_OUT 0x03    /* FIFO Xfer Infomation out             */
 212 #define TSC_XF_FIFO_IN  0x83    /* FIFO Xfer Infomation in              */
 213
 214 #define TSC_MSG_ACCEPT  0x0F    /* Message Accept                       */
 215
 216 /*----------------------------------------------------------------------*/
 217 /* bit definition for Tulip SCSI Control 0 Register                     */
 218 /*----------------------------------------------------------------------*/
 219 #define TSC_RST_SEQ     0x20    /* Reset sequence counter               */
 220 #define TSC_FLUSH_FIFO  0x10    /* Flush FIFO                           */
 221 #define TSC_ABT_CMD     0x04    /* Abort command (sequence)             */
 222 #define TSC_RST_CHIP    0x02    /* Reset SCSI Chip                      */
 223 #define TSC_RST_BUS     0x01    /* Reset SCSI Bus                       */
 224
 225 /*----------------------------------------------------------------------*/
 226 /* bit definition for Tulip SCSI Control 1 Register                     */
 227 /*----------------------------------------------------------------------*/
 228 #define TSC_EN_SCAM     0x80    /* Enable SCAM                          */
 229 #define TSC_TIMER       0x40    /* Select timeout unit                  */
 230 #define TSC_EN_SCSI2    0x20    /* SCSI-2 mode                          */
 231 #define TSC_PWDN        0x10    /* Power down mode                      */
 232 #define TSC_WIDE_CPU    0x08    /* Wide CPU                             */
 233 #define TSC_HW_RESELECT 0x04    /* Enable HW reselect                   */
 234 #define TSC_EN_BUS_OUT  0x02    /* Enable SCSI data bus out latch       */
 235 #define TSC_EN_BUS_IN   0x01    /* Enable SCSI data bus in latch        */
 236
 237 /*----------------------------------------------------------------------*/
 238 /* bit definition for Tulip SCSI Configuration Register                 */
 239 /*----------------------------------------------------------------------*/
 240 #define TSC_EN_LATCH    0x80    /* Enable phase latch                   */
 241 #define TSC_INITIATOR   0x40    /* Initiator mode                       */
 242 #define TSC_EN_SCSI_PAR 0x20    /* Enable SCSI parity                   */
 243 #define TSC_DMA_8BIT    0x10    /* Alternate dma 8-bits mode            */
 244 #define TSC_DMA_16BIT   0x08    /* Alternate dma 16-bits mode           */
 245 #define TSC_EN_WDACK    0x04    /* Enable DACK while wide SCSI xfer     */
 246 #define TSC_ALT_PERIOD  0x02    /* Alternate sync period mode           */
 247 #define TSC_DIS_SCSIRST 0x01    /* Disable SCSI bus reset us            */
 248
 249 #define TSC_INITDEFAULT (TSC_INITIATOR | TSC_EN_LATCH | TSC_ALT_PERIOD | TSC_DIS_SCSIRST)
 250
 251 #define TSC_WIDE_SCSI   0x80    /* Enable Wide SCSI                     */
 252
 253 /*----------------------------------------------------------------------*/
 254 /* bit definition for Tulip SCSI signal Register                        */
 255 /*----------------------------------------------------------------------*/
 256 #define TSC_RST_ACK     0x00    /* Release ACK signal                   */
 257 #define TSC_RST_ATN     0x00    /* Release ATN signal                   */
 258 #define TSC_RST_BSY     0x00    /* Release BSY signal                   */
 259
 260 #define TSC_SET_ACK     0x40    /* ACK signal                           */
 261 #define TSC_SET_ATN     0x08    /* ATN signal                           */
 262
 263 #define TSC_REQI        0x80    /* REQ signal                           */
 264 #define TSC_ACKI        0x40    /* ACK signal                           */
 265 #define TSC_BSYI        0x20    /* BSY signal                           */
 266 #define TSC_SELI        0x10    /* SEL signal                           */
 267 #define TSC_ATNI        0x08    /* ATN signal                           */
 268 #define TSC_MSGI        0x04    /* MSG signal                           */
 269 #define TSC_CDI         0x02    /* C/D signal                           */
 270 #define TSC_IOI         0x01    /* I/O signal                           */
 271
 272
 273 /*----------------------------------------------------------------------*/
 274 /* bit definition for Tulip SCSI Status 0 Register                      */
 275 /*----------------------------------------------------------------------*/
 276 #define TSS_INT_PENDING 0x80    /* Interrupt pending            */
 277 #define TSS_SEQ_ACTIVE  0x40    /* Sequencer active             */
 278 #define TSS_XFER_CNT    0x20    /* Transfer counter zero        */
 279 #define TSS_FIFO_EMPTY  0x10    /* FIFO empty                   */
 280 #define TSS_PAR_ERROR   0x08    /* SCSI parity error            */
 281 #define TSS_PH_MASK     0x07    /* SCSI phase mask              */
 282
 283 /*----------------------------------------------------------------------*/
 284 /* bit definition for Tulip SCSI Status 1 Register                      */
 285 /*----------------------------------------------------------------------*/
 286 #define TSS_STATUS_RCV  0x08    /* Status received              */
 287 #define TSS_MSG_SEND    0x40    /* Message sent                 */
 288 #define TSS_CMD_PH_CMP  0x20    /* command phase done              */
 289 #define TSS_DATA_PH_CMP 0x10    /* Data phase done              */
 290 #define TSS_STATUS_SEND 0x08    /* Status sent                  */
 291 #define TSS_XFER_CMP    0x04    /* Transfer completed           */
 292 #define TSS_SEL_CMP     0x02    /* Selection completed          */
 293 #define TSS_ARB_CMP     0x01    /* Arbitration completed        */
 294
 295 /*----------------------------------------------------------------------*/
 296 /* bit definition for Tulip SCSI Status 2 Register                      */
 297 /*----------------------------------------------------------------------*/
 298 #define TSS_CMD_ABTED   0x80    /* Command aborted              */
 299 #define TSS_OFFSET_0    0x40    /* Offset counter zero          */
 300 #define TSS_FIFO_FULL   0x20    /* FIFO full                    */
 301 #define TSS_TIMEOUT_0   0x10    /* Timeout counter zero         */
 302 #define TSS_BUSY_RLS    0x08    /* Busy release                 */
 303 #define TSS_PH_MISMATCH 0x04    /* Phase mismatch               */
 304 #define TSS_SCSI_BUS_EN 0x02    /* SCSI data bus enable         */
 305 #define TSS_SCSIRST     0x01    /* SCSI bus reset in progress   */
 306
 307 /*----------------------------------------------------------------------*/
 308 /* bit definition for Tulip SCSI Interrupt Register                     */
 309 /*----------------------------------------------------------------------*/
 310 #define TSS_RESEL_INT   0x80    /* Reselected interrupt         */
 311 #define TSS_SEL_TIMEOUT 0x40    /* Selected/reselected timeout  */
 312 #define TSS_BUS_SERV    0x20
 313 #define TSS_SCSIRST_INT 0x10    /* SCSI bus reset detected      */
 314 #define TSS_DISC_INT    0x08    /* Disconnected interrupt       */
 315 #define TSS_SEL_INT     0x04    /* Select interrupt             */
 316 #define TSS_SCAM_SEL    0x02    /* SCAM selected                */
 317 #define TSS_FUNC_COMP   0x01
 318
 319 /*----------------------------------------------------------------------*/
 320 /* SCSI Phase Codes.                                                    */
 321 /*----------------------------------------------------------------------*/
 322 #define DATA_OUT        0
 323 #define DATA_IN         1       /* 4                            */
 324 #define CMD_OUT         2
 325 #define STATUS_IN       3       /* 6                            */
 326 #define MSG_OUT         6       /* 3                            */
 327 #define MSG_IN          7
 328
 329
 330
 331 /*----------------------------------------------------------------------*/
 332 /* Command Codes of Tulip xfer Command register                         */
 333 /*----------------------------------------------------------------------*/
 334 #define TAX_X_FORC      0x02
 335 #define TAX_X_ABT       0x04
 336 #define TAX_X_CLR_FIFO  0x08
 337
 338 #define TAX_X_IN        0x21
 339 #define TAX_X_OUT       0x01
 340 #define TAX_SG_IN       0xA1
 341 #define TAX_SG_OUT      0x81
 342
 343 /*----------------------------------------------------------------------*/
 344 /* Tulip Interrupt Register                                             */
 345 /*----------------------------------------------------------------------*/
 346 #define XCMP            0x01
 347 #define FCMP            0x02
 348 #define XABT            0x04
 349 #define XERR            0x08
 350 #define SCMP            0x10
 351 #define IPEND           0x80
 352
 353 /*----------------------------------------------------------------------*/
 354 /* Tulip DMA Status Register                                            */
 355 /*----------------------------------------------------------------------*/
 356 #define XPEND           0x01    /* Transfer pending             */
 357 #define FEMPTY          0x02    /* FIFO empty                   */
 358
 359
 360
 361 /*----------------------------------------------------------------------*/
 362 /* bit definition for TUL_GCTRL                                         */
 363 /*----------------------------------------------------------------------*/
 364 #define EXTSG           0x80
 365 #define EXTAD           0x60
 366 #define SEG4K           0x08
 367 #define EEPRG           0x04
 368 #define MRMUL           0x02
 369
 370 /*----------------------------------------------------------------------*/
 371 /* bit definition for TUL_NVRAM                                         */
 372 /*----------------------------------------------------------------------*/
 373 #define SE2CS           0x08
 374 #define SE2CLK          0x04
 375 #define SE2DO           0x02
 376 #define SE2DI           0x01
 377
 378
 379 /************************************************************************/
 380 /*              Scatter-Gather Element Structure                        */
 381 /************************************************************************/
 382 typedef struct SG_Struc {
 383         U32 SG_Ptr;             /* Data Pointer */
 384         U32 SG_Len;             /* Data Length */
 385 } SG;
 386
 387 /***********************************************************************
 388                 SCSI Control Block
 389 ************************************************************************/
 390 typedef struct Scsi_Ctrl_Blk {
 391         struct Scsi_Ctrl_Blk *SCB_NxtScb;
 392         UBYTE SCB_Status;       /*4 */
 393         UBYTE SCB_NxtStat;      /*5 */
 394         UBYTE SCB_Mode;         /*6 */
 395         UBYTE SCB_Msgin;        /*7 SCB_Res0 */
 396         UWORD SCB_SGIdx;        /*8 */
 397         UWORD SCB_SGMax;        /*A */
 398 #ifdef ALPHA
 399         U32 SCB_Reserved[2];    /*C */
 400 #else
 401         U32 SCB_Reserved[3];    /*C */
 402 #endif
 403
 404         U32 SCB_XferLen;        /*18 Current xfer len           */
 405         U32 SCB_TotXLen;        /*1C Total xfer len             */
 406         U32 SCB_PAddr;          /*20 SCB phy. Addr. */
 407
 408         UBYTE SCB_Opcode;       /*24 SCB command code */
 409         UBYTE SCB_Flags;        /*25 SCB Flags */
 410         UBYTE SCB_Target;       /*26 Target Id */
 411         UBYTE SCB_Lun;          /*27 Lun */
 412         U32 SCB_BufPtr;         /*28 Data Buffer Pointer */
 413         U32 SCB_BufLen;         /*2C Data Allocation Length */
 414         UBYTE SCB_SGLen;        /*30 SG list # */
 415         UBYTE SCB_SenseLen;     /*31 Sense Allocation Length */
 416         UBYTE SCB_HaStat;       /*32 */
 417         UBYTE SCB_TaStat;       /*33 */
 418         UBYTE SCB_CDBLen;       /*34 CDB Length */
 419         UBYTE SCB_Ident;        /*35 Identify */
 420         UBYTE SCB_TagMsg;       /*36 Tag Message */
 421         UBYTE SCB_TagId;        /*37 Queue Tag */
 422         UBYTE SCB_CDB[12];      /*38 */
 423         U32 SCB_SGPAddr;        /*44 SG List/Sense Buf phy. Addr. */
 424         U32 SCB_SensePtr;       /*48 Sense data pointer */
 425         void (*SCB_Post) (BYTE *, BYTE *);      /*4C POST routine */
 426         unsigned char *SCB_Srb; /*50 SRB Pointer */
 427         SG SCB_SGList[TOTAL_SG_ENTRY];  /*54 Start of SG list */
 428 } SCB;
 429
 430 /* Bit Definition for SCB_Status */
 431 #define SCB_RENT        0x01
 432 #define SCB_PEND        0x02
 433 #define SCB_CONTIG      0x04    /* Contigent Allegiance */
 434 #define SCB_SELECT      0x08
 435 #define SCB_BUSY        0x10
 436 #define SCB_DONE        0x20
 437
 438
 439 /* Opcodes of SCB_Opcode */
 440 #define ExecSCSI        0x1
 441 #define BusDevRst       0x2
 442 #define AbortCmd        0x3
 443
 444
 445 /* Bit Definition for SCB_Mode */
 446 #define SCM_RSENS       0x01    /* request sense mode */
 447
 448
 449 /* Bit Definition for SCB_Flags */
 450 #define SCF_DONE        0x01
 451 #define SCF_POST        0x02
 452 #define SCF_SENSE       0x04
 453 #define SCF_DIR         0x18
 454 #define SCF_NO_DCHK     0x00
 455 #define SCF_DIN         0x08
 456 #define SCF_DOUT        0x10
 457 #define SCF_NO_XF       0x18
 458 #define SCF_WR_VF       0x20    /* Write verify turn on         */
 459 #define SCF_POLL        0x40
 460 #define SCF_SG          0x80
 461
 462 /* Error Codes for SCB_HaStat */
 463 #define HOST_SEL_TOUT   0x11
 464 #define HOST_DO_DU      0x12
 465 #define HOST_BUS_FREE   0x13
 466 #define HOST_BAD_PHAS   0x14
 467 #define HOST_INV_CMD    0x16
 468 #define HOST_ABORTED    0x1A    /* 07/21/98 */
 469 #define HOST_SCSI_RST   0x1B
 470 #define HOST_DEV_RST    0x1C
 471
 472 /* Error Codes for SCB_TaStat */
 473 #define TARGET_CHKCOND  0x02
 474 #define TARGET_BUSY     0x08
 475 #define QUEUE_FULL      0x28
 476
 477 /* SCSI MESSAGE */
 478 #define MSG_COMP        0x00
 479 #define MSG_EXTEND      0x01
 480 #define MSG_SDP         0x02
 481 #define MSG_RESTORE     0x03
 482 #define MSG_DISC        0x04
 483 #define MSG_IDE         0x05
 484 #define MSG_ABORT       0x06
 485 #define MSG_REJ         0x07
 486 #define MSG_NOP         0x08
 487 #define MSG_PARITY      0x09
 488 #define MSG_LINK_COMP   0x0A
 489 #define MSG_LINK_FLAG   0x0B
 490 #define MSG_DEVRST      0x0C
 491 #define MSG_ABORT_TAG   0x0D
 492
 493 /* Queue tag msg: Simple_quque_tag, Head_of_queue_tag, Ordered_queue_tag */
 494 #define MSG_STAG        0x20
 495 #define MSG_HTAG        0x21
 496 #define MSG_OTAG        0x22
 497
 498 #define MSG_IGNOREWIDE  0x23
 499
 500 #define MSG_IDENT   0x80
 501
 502 /***********************************************************************
 503                 Target Device Control Structure
 504 **********************************************************************/
 505
 506 typedef struct Tar_Ctrl_Struc {
 507         UWORD TCS_Flags;        /* 0 */
 508         UBYTE TCS_JS_Period;    /* 2 */
 509         UBYTE TCS_SConfig0;     /* 3 */
 510
 511         UWORD TCS_DrvFlags;     /* 4 */
 512         UBYTE TCS_DrvHead;      /* 6 */
 513         UBYTE TCS_DrvSector;    /* 7 */
 514 } TCS;
 515
 516 /***********************************************************************
 517                 Target Device Control Structure
 518 **********************************************************************/
 519
 520 /* Bit Definition for TCF_Flags */
 521 #define TCF_SCSI_RATE           0x0007
 522 #define TCF_EN_DISC             0x0008
 523 #define TCF_NO_SYNC_NEGO        0x0010
 524 #define TCF_NO_WDTR             0x0020
 525 #define TCF_EN_255              0x0040
 526 #define TCF_EN_START            0x0080
 527 #define TCF_WDTR_DONE           0x0100
 528 #define TCF_SYNC_DONE           0x0200
 529 #define TCF_BUSY                0x0400
 530
 531
 532 /* Bit Definition for TCF_DrvFlags */
 533 #define TCF_DRV_BUSY            0x01    /* Indicate target busy(driver) */
 534 #define TCF_DRV_EN_TAG          0x0800
 535 #define TCF_DRV_255_63          0x0400
 536
 537 typedef struct I91u_Adpt_Struc {
 538         UWORD ADPT_BIOS;        /* 0 */
 539         UWORD ADPT_BASE;        /* 1 */
 540         UBYTE ADPT_Bus;         /* 2 */
 541         UBYTE ADPT_Device;      /* 3 */
 542         UBYTE ADPT_INTR;        /* 4 */
 543 } INI_ADPT_STRUCT;
 544
 545
 546 /***********************************************************************
 547               Host Adapter Control Structure
 548 ************************************************************************/
 549 typedef struct Ha_Ctrl_Struc {
 550         UWORD HCS_Base;         /* 00 */
 551         UWORD HCS_BIOS;         /* 02 */
 552         UBYTE HCS_Intr;         /* 04 */
 553         UBYTE HCS_SCSI_ID;      /* 05 */
 554         UBYTE HCS_MaxTar;       /* 06 */
 555         UBYTE HCS_NumScbs;      /* 07 */
 556
 557         UBYTE HCS_Flags;        /* 08 */
 558         UBYTE HCS_Index;        /* 09 */
 559         UBYTE HCS_HaId;         /* 0A */
 560         UBYTE HCS_Config;       /* 0B */
 561         UWORD HCS_IdMask;       /* 0C */
 562         UBYTE HCS_Semaph;       /* 0E */
 563         UBYTE HCS_Phase;        /* 0F */
 564         UBYTE HCS_JSStatus0;    /* 10 */
 565         UBYTE HCS_JSInt;        /* 11 */
 566         UBYTE HCS_JSStatus1;    /* 12 */
 567         UBYTE HCS_SConf1;       /* 13 */
 568
 569         UBYTE HCS_Msg[8];       /* 14 */
 570         SCB *HCS_NxtAvail;      /* 1C */
 571         SCB *HCS_Scb;           /* 20 */
 572         SCB *HCS_ScbEnd;        /* 24 */
 573         SCB *HCS_NxtPend;       /* 28 */
 574         SCB *HCS_NxtContig;     /* 2C */
 575         SCB *HCS_ActScb;        /* 30 */
 576         TCS *HCS_ActTcs;        /* 34 */
 577
 578         SCB *HCS_FirstAvail;    /* 38 */
 579         SCB *HCS_LastAvail;     /* 3C */
 580         SCB *HCS_FirstPend;     /* 40 */
 581         SCB *HCS_LastPend;      /* 44 */
 582         SCB *HCS_FirstBusy;     /* 48 */
 583         SCB *HCS_LastBusy;      /* 4C */
 584         SCB *HCS_FirstDone;     /* 50 */
 585         SCB *HCS_LastDone;      /* 54 */
 586         UBYTE HCS_MaxTags[16];  /* 58 */
 587         UBYTE HCS_ActTags[16];  /* 68 */
 588         TCS HCS_Tcs[MAX_TARGETS];       /* 78 */
 589         ULONG pSRB_head;        /* SRB save queue header     */
 590         ULONG pSRB_tail;        /* SRB save queue tail       */
 591         spinlock_t HCS_AvailLock;
 592         spinlock_t HCS_SemaphLock;
 593         spinlock_t pSRB_lock;   /* SRB queue lock            */
 594 } HCS;
 595
 596 /* Bit Definition for HCB_Config */
 597 #define HCC_SCSI_RESET          0x01
 598 #define HCC_EN_PAR              0x02
 599 #define HCC_ACT_TERM1           0x04
 600 #define HCC_ACT_TERM2           0x08
 601 #define HCC_AUTO_TERM           0x10
 602 #define HCC_EN_PWR              0x80
 603
 604 /* Bit Definition for HCB_Flags */
 605 #define HCF_EXPECT_DISC         0x01
 606 #define HCF_EXPECT_SELECT       0x02
 607 #define HCF_EXPECT_RESET        0x10
 608 #define HCF_EXPECT_DONE_DISC    0x20
 609
 610 /******************************************************************
 611         Serial EEProm
 612 *******************************************************************/
 613
 614 typedef struct _NVRAM_SCSI {    /* SCSI channel configuration   */
 615         UCHAR NVM_ChSCSIID;     /* 0Ch -> Channel SCSI ID       */
 616         UCHAR NVM_ChConfig1;    /* 0Dh -> Channel config 1      */
 617         UCHAR NVM_ChConfig2;    /* 0Eh -> Channel config 2      */
 618         UCHAR NVM_NumOfTarg;    /* 0Fh -> Number of SCSI target */
 619         /* SCSI target configuration    */
 620         UCHAR NVM_Targ0Config;  /* 10h -> Target 0 configuration */
 621         UCHAR NVM_Targ1Config;  /* 11h -> Target 1 configuration */
 622         UCHAR NVM_Targ2Config;  /* 12h -> Target 2 configuration */
 623         UCHAR NVM_Targ3Config;  /* 13h -> Target 3 configuration */
 624         UCHAR NVM_Targ4Config;  /* 14h -> Target 4 configuration */
 625         UCHAR NVM_Targ5Config;  /* 15h -> Target 5 configuration */
 626         UCHAR NVM_Targ6Config;  /* 16h -> Target 6 configuration */
 627         UCHAR NVM_Targ7Config;  /* 17h -> Target 7 configuration */
 628         UCHAR NVM_Targ8Config;  /* 18h -> Target 8 configuration */
 629         UCHAR NVM_Targ9Config;  /* 19h -> Target 9 configuration */
 630         UCHAR NVM_TargAConfig;  /* 1Ah -> Target A configuration */
 631         UCHAR NVM_TargBConfig;  /* 1Bh -> Target B configuration */
 632         UCHAR NVM_TargCConfig;  /* 1Ch -> Target C configuration */
 633         UCHAR NVM_TargDConfig;  /* 1Dh -> Target D configuration */
 634         UCHAR NVM_TargEConfig;  /* 1Eh -> Target E configuration */
 635         UCHAR NVM_TargFConfig;  /* 1Fh -> Target F configuration */
 636 } NVRAM_SCSI;
 637
 638 typedef struct _NVRAM {
 639 /*----------header ---------------*/
 640         USHORT NVM_Signature;   /* 0,1: Signature */
 641         UCHAR NVM_Size;         /* 2:   Size of data structure */
 642         UCHAR NVM_Revision;     /* 3:   Revision of data structure */
 643         /* ----Host Adapter Structure ---- */
 644         UCHAR NVM_ModelByte0;   /* 4:   Model number (byte 0) */
 645         UCHAR NVM_ModelByte1;   /* 5:   Model number (byte 1) */
 646         UCHAR NVM_ModelInfo;    /* 6:   Model information         */
 647         UCHAR NVM_NumOfCh;      /* 7:   Number of SCSI channel */
 648         UCHAR NVM_BIOSConfig1;  /* 8:   BIOS configuration 1  */
 649         UCHAR NVM_BIOSConfig2;  /* 9:   BIOS configuration 2  */
 650         UCHAR NVM_HAConfig1;    /* A:   Hoat adapter configuration 1 */
 651         UCHAR NVM_HAConfig2;    /* B:   Hoat adapter configuration 2 */
 652         NVRAM_SCSI NVM_SCSIInfo[2];
 653         UCHAR NVM_reserved[10];
 654         /* ---------- CheckSum ----------       */
 655         USHORT NVM_CheckSum;    /* 0x3E, 0x3F: Checksum of NVRam        */
 656 } NVRAM, *PNVRAM;
 657
 658 /* Bios Configuration for nvram->BIOSConfig1                            */
 659 #define NBC1_ENABLE             0x01    /* BIOS enable                  */
 660 #define NBC1_8DRIVE             0x02    /* Support more than 2 drives   */
 661 #define NBC1_REMOVABLE          0x04    /* Support removable drive      */
 662 #define NBC1_INT19              0x08    /* Intercept int 19h            */
 663 #define NBC1_BIOSSCAN           0x10    /* Dynamic BIOS scan            */
 664 #define NBC1_LUNSUPPORT         0x40    /* Support LUN                  */
 665
 666 /* HA Configuration Byte 1                                              */
 667 #define NHC1_BOOTIDMASK 0x0F    /* Boot ID number               */
 668 #define NHC1_LUNMASK    0x70    /* Boot LUN number              */
 669 #define NHC1_CHANMASK   0x80    /* Boot Channel number          */
 670
 671 /* Bit definition for nvram->SCSIconfig1                                */
 672 #define NCC1_BUSRESET           0x01    /* Reset SCSI bus at power up   */
 673 #define NCC1_PARITYCHK          0x02    /* SCSI parity enable           */
 674 #define NCC1_ACTTERM1           0x04    /* Enable active terminator 1   */
 675 #define NCC1_ACTTERM2           0x08    /* Enable active terminator 2   */
 676 #define NCC1_AUTOTERM           0x10    /* Enable auto terminator       */
 677 #define NCC1_PWRMGR             0x80    /* Enable power management      */
 678
 679 /* Bit definition for SCSI Target configuration byte                    */
 680 #define NTC_DISCONNECT          0x08    /* Enable SCSI disconnect       */
 681 #define NTC_SYNC                0x10    /* SYNC_NEGO                    */
 682 #define NTC_NO_WDTR             0x20    /* SYNC_NEGO                    */
 683 #define NTC_1GIGA               0x40    /* 255 head / 63 sectors (64/32) */
 684 #define NTC_SPINUP              0x80    /* Start disk drive             */
 685
 686 /*      Default NVRam values                                            */
 687 #define INI_SIGNATURE           0xC925
 688 #define NBC1_DEFAULT            (NBC1_ENABLE)
 689 #define NCC1_DEFAULT            (NCC1_BUSRESET | NCC1_AUTOTERM | NCC1_PARITYCHK)
 690 #define NTC_DEFAULT             (NTC_NO_WDTR | NTC_1GIGA | NTC_DISCONNECT)
 691
 692 /* SCSI related definition                                              */
 693 #define DISC_NOT_ALLOW          0x80    /* Disconnect is not allowed    */
 694 #define DISC_ALLOW              0xC0    /* Disconnect is allowed        */
 695 #define SCSICMD_RequestSense    0x03
 696
 697
 698 /*----------------------------------------------------------------------*/
 699 /*                              PCI                                     */
 700 /*----------------------------------------------------------------------*/
 701 #define PCI_FUNCTION_ID         0xB1
 702 #define PCI_BIOS_PRESENT        0x01
 703 #define FIND_PCI_DEVICE         0x02
 704 #define FIND_PCI_CLASS_CODE     0x03
 705 #define GENERATE_SPECIAL_CYCLE  0x06
 706 #define READ_CONFIG_BYTE        0x08
 707 #define READ_CONFIG_WORD        0x09
 708 #define READ_CONFIG_DWORD       0x0A
 709 #define WRITE_CONFIG_BYTE       0x0B
 710 #define WRITE_CONFIG_WORD       0x0C
 711 #define WRITE_CONFIG_DWORD      0x0D
 712
 713 #define SUCCESSFUL              0x00
 714 #define FUNC_NOT_SUPPORTED      0x81
 715 #define BAD_VENDOR_ID           0x83    /* Bad vendor ID                */
 716 #define DEVICE_NOT_FOUND        0x86    /* PCI device not found         */
 717 #define BAD_REGISTER_NUMBER     0x87
 718
 719 #define MAX_PCI_DEVICES         21      /* Maximum devices supportted   */
 720
 721 #define MAX_PCI_CHANL           4
 722
 723 typedef struct _BIOS32_ENTRY_STRUCTURE {
 724         DWORD Signatures;       /* Should be "_32_"             */
 725         DWORD BIOS32Entry;      /* 32-bit physical address      */
 726         BYTE Revision;          /* Revision level, should be 0  */
 727         BYTE Length;            /* Multiply of 16, should be 1  */
 728         BYTE CheckSum;          /* Checksum of whole structure  */
 729         BYTE Reserved[5];       /* Reserved                     */
 730 } BIOS32_ENTRY_STRUCTURE, *PBIOS32_ENTRY_STRUCTURE;
 731
 732 typedef struct {
 733         union {
 734                 unsigned int eax;
 735                 struct {
 736                         unsigned short ax;
 737                 } word;
 738                 struct {
 739                         unsigned char al;
 740                         unsigned char ah;
 741                 } byte;
 742         } eax;
 743         union {
 744                 unsigned int ebx;
 745                 struct {
 746                         unsigned short bx;
 747                 } word;
 748                 struct {
 749                         unsigned char bl;
 750                         unsigned char bh;
 751                 } byte;
 752         } ebx;
 753         union {
 754                 unsigned int ecx;
 755                 struct {
 756                         unsigned short cx;
 757                 } word;
 758                 struct {
 759                         unsigned char cl;
 760                         unsigned char ch;
 761                 } byte;
 762         } ecx;
 763         union {
 764                 unsigned int edx;
 765                 struct {
 766                         unsigned short dx;
 767                 } word;
 768                 struct {
 769                         unsigned char dl;
 770                         unsigned char dh;
 771                 } byte;
 772         } edx;
 773         union {
 774                 unsigned int edi;
 775                 struct {
 776                         unsigned short di;
 777                 } word;
 778         } edi;
 779         union {
 780                 unsigned int esi;
 781                 struct {
 782                         unsigned short si;
 783                 } word;
 784         } esi;
 785 } REGS;
 786
 787 typedef union {                 /* Union define for mechanism 1 */
 788         struct {
 789                 unsigned char RegNum;
 790                 unsigned char FcnNum:3;
 791                 unsigned char DeviceNum:5;
 792                 unsigned char BusNum;
 793                 unsigned char Reserved:7;
 794                 unsigned char Enable:1;
 795         } sConfigAdr;
 796         unsigned long lConfigAdr;
 797 } CONFIG_ADR;
 798
 799 typedef union {                 /* Union define for mechanism 2 */
 800         struct {
 801                 unsigned char RegNum;
 802                 unsigned char DeviceNum;
 803                 unsigned short Reserved;
 804         } sHostAdr;
 805         unsigned long lHostAdr;
 806 } HOST_ADR;
 807
 808 typedef struct _HCSinfo {
 809         ULONG base;
 810         UCHAR vec;
 811         UCHAR bios;             /* High byte of BIOS address */
 812         USHORT BaseAndBios;     /* high byte: pHcsInfo->bios,low byte:pHcsInfo->base */
 813 } HCSINFO;
 814
 815 #define TUL_RD(x,y)             (UCHAR)(inb(  (int)((ULONG)(x+y)) ))
 816 #define TUL_RDLONG(x,y)         (ULONG)(inl((int)((ULONG)(x+y)) ))
 817 #define TUL_WR(     adr,data)   outb( (UCHAR)(data), (int)(adr))
 818 #define TUL_WRSHORT(adr,data)   outw( (UWORD)(data), (int)(adr))
 819 #define TUL_WRLONG( adr,data)   outl( (ULONG)(data), (int)(adr))
 820
 821 #define SCSI_ABORT_SNOOZE 0
 822 #define SCSI_ABORT_SUCCESS 1
 823 #define SCSI_ABORT_PENDING 2
 824 #define SCSI_ABORT_BUSY 3
 825 #define SCSI_ABORT_NOT_RUNNING 4
 826 #define SCSI_ABORT_ERROR 5
 827
 828 #define SCSI_RESET_SNOOZE 0
 829 #define SCSI_RESET_PUNT 1
 830 #define SCSI_RESET_SUCCESS 2
 831 #define SCSI_RESET_PENDING 3
 832 #define SCSI_RESET_WAKEUP 4
 833 #define SCSI_RESET_NOT_RUNNING 5
 834 #define SCSI_RESET_ERROR 6
 835
 836 #define SCSI_RESET_SYNCHRONOUS          0x01
 837 #define SCSI_RESET_ASYNCHRONOUS         0x02
 838 #define SCSI_RESET_SUGGEST_BUS_RESET    0x04
 839 #define SCSI_RESET_SUGGEST_HOST_RESET   0x08
 840
 841 #define SCSI_RESET_BUS_RESET 0x100
 842 #define SCSI_RESET_HOST_RESET 0x200
 843 #define SCSI_RESET_ACTION   0xff