drivers/net/tulip/tulip.h

   1 /*
   2         drivers/net/tulip/tulip.h
   3
   4         Copyright 2000,2001  The Linux Kernel Team
   5         Written/copyright 1994-2001 by Donald Becker.
   6
   7         This software may be used and distributed according to the terms
   8         of the GNU General Public License, incorporated herein by reference.
   9
  10         Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
  11         for more information on this driver, or visit the project
  12         Web page at http://sourceforge.net/projects/tulip/
  13
  14 */
  15
  16 #ifndef __NET_TULIP_H__
  17 #define __NET_TULIP_H__
  18
  19 #include <linux/config.h>
  20 #include <linux/kernel.h>
  21 #include <linux/types.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/netdevice.h>
  24 #include <linux/timer.h>
  25 #include <linux/delay.h>
  26 #include <asm/io.h>
  27 #include <asm/irq.h>
  28
  29
  30
  31 /* undefine, or define to various debugging levels (>4 == obscene levels) */
  32 #define TULIP_DEBUG 1
  33
  34 /* undefine USE_IO_OPS for MMIO, define for PIO */
  35 #ifdef CONFIG_TULIP_MMIO
  36 # undef USE_IO_OPS
  37 #else
  38 # define USE_IO_OPS 1
  39 #endif
  40
  41
  42
  43 struct tulip_chip_table {
  44         char *chip_name;
  45         int io_size;
  46         int valid_intrs;        /* CSR7 interrupt enable settings */
  47         int flags;
  48         void (*media_timer) (unsigned long data);
  49 };
  50
  51
  52 enum tbl_flag {
  53         HAS_MII                 = 0x0001,
  54         HAS_MEDIA_TABLE         = 0x0002,
  55         CSR12_IN_SROM           = 0x0004,
  56         ALWAYS_CHECK_MII        = 0x0008,
  57         HAS_ACPI                = 0x0010,
  58         MC_HASH_ONLY            = 0x0020, /* Hash-only multicast filter. */
  59         HAS_PNICNWAY            = 0x0080,
  60         HAS_NWAY                = 0x0040, /* Uses internal NWay xcvr. */
  61         HAS_INTR_MITIGATION     = 0x0100,
  62         IS_ASIX                 = 0x0200,
  63         HAS_8023X               = 0x0400,
  64         COMET_MAC_ADDR          = 0x0800,
  65         HAS_PCI_MWI             = 0x1000,
  66         HAS_PHY_IRQ             = 0x2000,
  67         HAS_SWAPPED_SEEPROM     = 0x4000,
  68         NEEDS_FAKE_MEDIA_TABLE  = 0x8000,
  69 };
  70
  71
  72 /* chip types.  careful!  order is VERY IMPORTANT here, as these
  73  * are used throughout the driver as indices into arrays */
  74 /* Note 21142 == 21143. */
  75 enum chips {
  76         DC21040 = 0,
  77         DC21041 = 1,
  78         DC21140 = 2,
  79         DC21142 = 3, DC21143 = 3,
  80         LC82C168,
  81         MX98713,
  82         MX98715,
  83         MX98725,
  84         AX88140,
  85         PNIC2,
  86         COMET,
  87         COMPEX9881,
  88         I21145,
  89         DM910X,
  90         CONEXANT,
  91 };
  92
  93
  94 enum MediaIs {
  95         MediaIsFD = 1,
  96         MediaAlwaysFD = 2,
  97         MediaIsMII = 4,
  98         MediaIsFx = 8,
  99         MediaIs100 = 16
 100 };
 101
 102
 103 /* Offsets to the Command and Status Registers, "CSRs".  All accesses
 104    must be longword instructions and quadword aligned. */
 105 enum tulip_offsets {
 106         CSR0 = 0,
 107         CSR1 = 0x08,
 108         CSR2 = 0x10,
 109         CSR3 = 0x18,
 110         CSR4 = 0x20,
 111         CSR5 = 0x28,
 112         CSR6 = 0x30,
 113         CSR7 = 0x38,
 114         CSR8 = 0x40,
 115         CSR9 = 0x48,
 116         CSR10 = 0x50,
 117         CSR11 = 0x58,
 118         CSR12 = 0x60,
 119         CSR13 = 0x68,
 120         CSR14 = 0x70,
 121         CSR15 = 0x78,
 122 };
 123
 124 /* register offset and bits for CFDD PCI config reg */
 125 enum pci_cfg_driver_reg {
 126         CFDD = 0x40,
 127         CFDD_Sleep = (1 << 31),
 128         CFDD_Snooze = (1 << 30),
 129 };
 130
 131 #define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
 132
 133 /* The bits in the CSR5 status registers, mostly interrupt sources. */
 134 enum status_bits {
 135         TimerInt = 0x800,
 136         SytemError = 0x2000,
 137         TPLnkFail = 0x1000,
 138         TPLnkPass = 0x10,
 139         NormalIntr = 0x10000,
 140         AbnormalIntr = 0x8000,
 141         RxJabber = 0x200,
 142         RxDied = 0x100,
 143         RxNoBuf = 0x80,
 144         RxIntr = 0x40,
 145         TxFIFOUnderflow = 0x20,
 146         TxJabber = 0x08,
 147         TxNoBuf = 0x04,
 148         TxDied = 0x02,
 149         TxIntr = 0x01,
 150 };
 151
 152
 153 enum tulip_mode_bits {
 154         TxThreshold             = (1 << 22),
 155         FullDuplex              = (1 << 9),
 156         TxOn                    = 0x2000,
 157         AcceptBroadcast         = 0x0100,
 158         AcceptAllMulticast      = 0x0080,
 159         AcceptAllPhys           = 0x0040,
 160         AcceptRunt              = 0x0008,
 161         RxOn                    = 0x0002,
 162         RxTx                    = (TxOn | RxOn),
 163 };
 164
 165
 166 enum tulip_busconfig_bits {
 167         MWI                     = (1 << 24),
 168         MRL                     = (1 << 23),
 169         MRM                     = (1 << 21),
 170         CALShift                = 14,
 171         BurstLenShift           = 8,
 172 };
 173
 174
 175 /* The Tulip Rx and Tx buffer descriptors. */
 176 struct tulip_rx_desc {
 177         s32 status;
 178         s32 length;
 179         u32 buffer1;
 180         u32 buffer2;
 181 };
 182
 183
 184 struct tulip_tx_desc {
 185         s32 status;
 186         s32 length;
 187         u32 buffer1;
 188         u32 buffer2;            /* We use only buffer 1.  */
 189 };
 190
 191
 192 enum desc_status_bits {
 193         DescOwned = 0x80000000,
 194         RxDescFatalErr = 0x8000,
 195         RxWholePkt = 0x0300,
 196 };
 197
 198
 199 enum t21143_csr6_bits {
 200         csr6_sc = (1<<31),
 201         csr6_ra = (1<<30),
 202         csr6_ign_dest_msb = (1<<26),
 203         csr6_mbo = (1<<25),
 204         csr6_scr = (1<<24),  /* scramble mode flag: can't be set */
 205         csr6_pcs = (1<<23),  /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
 206         csr6_ttm = (1<<22),  /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
 207         csr6_sf = (1<<21),   /* Store and forward. If set ignores TR bits */
 208         csr6_hbd = (1<<19),  /* Heart beat disable. Disables SQE function in 10baseT */
 209         csr6_ps = (1<<18),   /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
 210         csr6_ca = (1<<17),   /* Collision Offset Enable. If set uses special algorithm in low collision situations */
 211         csr6_trh = (1<<15),  /* Transmit Threshold high bit */
 212         csr6_trl = (1<<14),  /* Transmit Threshold low bit */
 213
 214         /***************************************************************
 215          * This table shows transmit threshold values based on media   *
 216          * and these two registers (from PNIC1 & 2 docs) Note: this is *
 217          * all meaningless if sf is set.                               *
 218          ***************************************************************/
 219
 220         /***********************************
 221          * (trh,trl) * 100BaseTX * 10BaseT *
 222          ***********************************
 223          *   (0,0)   *     128   *    72   *
 224          *   (0,1)   *     256   *    96   *
 225          *   (1,0)   *     512   *   128   *
 226          *   (1,1)   *    1024   *   160   *
 227          ***********************************/
 228
 229         csr6_fc = (1<<12),   /* Forces a collision in next transmission (for testing in loopback mode) */
 230         csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
 231         csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
 232         /* set both and you get (PHY) loopback */
 233         csr6_fd = (1<<9),    /* Full duplex mode, disables hearbeat, no loopback */
 234         csr6_pm = (1<<7),    /* Pass All Multicast */
 235         csr6_pr = (1<<6),    /* Promiscuous mode */
 236         csr6_sb = (1<<5),    /* Start(1)/Stop(0) backoff counter */
 237         csr6_if = (1<<4),    /* Inverse Filtering, rejects only addresses in address table: can't be set */
 238         csr6_pb = (1<<3),    /* Pass Bad Frames, (1) causes even bad frames to be passed on */
 239         csr6_ho = (1<<2),    /* Hash-only filtering mode: can't be set */
 240         csr6_hp = (1<<0),    /* Hash/Perfect Receive Filtering Mode: can't be set */
 241
 242         csr6_mask_capture = (csr6_sc | csr6_ca),
 243         csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
 244         csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
 245         csr6_mask_hdcaptt = (csr6_mask_hdcap  | csr6_trh | csr6_trl),
 246         csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
 247         csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
 248         csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
 249         csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
 250 };
 251
 252
 253 /* Keep the ring sizes a power of two for efficiency.
 254    Making the Tx ring too large decreases the effectiveness of channel
 255    bonding and packet priority.
 256    There are no ill effects from too-large receive rings. */
 257
 258 #define TX_RING_SIZE    32
 259 #define RX_RING_SIZE    128
 260 #define MEDIA_MASK     31
 261
 262 #define PKT_BUF_SZ              1536    /* Size of each temporary Rx buffer. */
 263
 264 #define TULIP_MIN_CACHE_LINE    8       /* in units of 32-bit words */
 265
 266 #if defined(__sparc__) || defined(__hppa__)
 267 /* The UltraSparc PCI controllers will disconnect at every 64-byte
 268  * crossing anyways so it makes no sense to tell Tulip to burst
 269  * any more than that.
 270  */
 271 #define TULIP_MAX_CACHE_LINE    16      /* in units of 32-bit words */
 272 #else
 273 #define TULIP_MAX_CACHE_LINE    32      /* in units of 32-bit words */
 274 #endif
 275
 276
 277 /* Ring-wrap flag in length field, use for last ring entry.
 278         0x01000000 means chain on buffer2 address,
 279         0x02000000 means use the ring start address in CSR2/3.
 280    Note: Some work-alike chips do not function correctly in chained mode.
 281    The ASIX chip works only in chained mode.
 282    Thus we indicates ring mode, but always write the 'next' field for
 283    chained mode as well.
 284 */
 285 #define DESC_RING_WRAP 0x02000000
 286
 287
 288 #define EEPROM_SIZE 512         /* 2 << EEPROM_ADDRLEN */
 289
 290
 291 #define RUN_AT(x) (jiffies + (x))
 292
 293 #if defined(__i386__)                   /* AKA get_unaligned() */
 294 #define get_u16(ptr) (*(u16 *)(ptr))
 295 #else
 296 #define get_u16(ptr) (((u8*)(ptr))[0] + (((u8*)(ptr))[1]<<8))
 297 #endif
 298
 299 struct medialeaf {
 300         u8 type;
 301         u8 media;
 302         unsigned char *leafdata;
 303 };
 304
 305
 306 struct mediatable {
 307         u16 defaultmedia;
 308         u8 leafcount;
 309         u8 csr12dir;            /* General purpose pin directions. */
 310         unsigned has_mii:1;
 311         unsigned has_nonmii:1;
 312         unsigned has_reset:6;
 313         u32 csr15dir;
 314         u32 csr15val;           /* 21143 NWay setting. */
 315         struct medialeaf mleaf[0];
 316 };
 317
 318
 319 struct mediainfo {
 320         struct mediainfo *next;
 321         int info_type;
 322         int index;
 323         unsigned char *info;
 324 };
 325
 326 struct ring_info {
 327         struct sk_buff  *skb;
 328         dma_addr_t      mapping;
 329 };
 330
 331
 332 struct tulip_private {
 333         const char *product_name;
 334         struct net_device *next_module;
 335         struct tulip_rx_desc *rx_ring;
 336         struct tulip_tx_desc *tx_ring;
 337         dma_addr_t rx_ring_dma;
 338         dma_addr_t tx_ring_dma;
 339         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 340         struct ring_info tx_buffers[TX_RING_SIZE];
 341         /* The addresses of receive-in-place skbuffs. */
 342         struct ring_info rx_buffers[RX_RING_SIZE];
 343         u16 setup_frame[96];    /* Pseudo-Tx frame to init address table. */
 344         int chip_id;
 345         int revision;
 346         int flags;
 347         struct net_device_stats stats;
 348         struct timer_list timer;        /* Media selection timer. */
 349         struct timer_list oom_timer;    /* Out of memory timer. */
 350         u32 mc_filter[2];
 351         spinlock_t lock;
 352         spinlock_t mii_lock;
 353         unsigned int cur_rx, cur_tx;    /* The next free ring entry */
 354         unsigned int dirty_rx, dirty_tx;        /* The ring entries to be free()ed. */
 355
 356 #ifdef  CONFIG_TULIP_NAPI_HW_MITIGATION
 357         int mit_on;
 358 #endif
 359         unsigned int full_duplex:1;     /* Full-duplex operation requested. */
 360         unsigned int full_duplex_lock:1;
 361         unsigned int fake_addr:1;       /* Multiport board faked address. */
 362         unsigned int default_port:4;    /* Last dev->if_port value. */
 363         unsigned int media2:4;  /* Secondary monitored media port. */
 364         unsigned int medialock:1;       /* Don't sense media type. */
 365         unsigned int mediasense:1;      /* Media sensing in progress. */
 366         unsigned int nway:1, nwayset:1;         /* 21143 internal NWay. */
 367         unsigned int csr0;      /* CSR0 setting. */
 368         unsigned int csr6;      /* Current CSR6 control settings. */
 369         unsigned char eeprom[EEPROM_SIZE];      /* Serial EEPROM contents. */
 370         void (*link_change) (struct net_device * dev, int csr5);
 371         u16 sym_advertise, mii_advertise; /* NWay capabilities advertised.  */
 372         u16 lpar;               /* 21143 Link partner ability. */
 373         u16 advertising[4];
 374         signed char phys[4], mii_cnt;   /* MII device addresses. */
 375         struct mediatable *mtable;
 376         int cur_index;          /* Current media index. */
 377         int saved_if_port;
 378         struct pci_dev *pdev;
 379         int ttimer;
 380         int susp_rx;
 381         unsigned long nir;
 382         unsigned long base_addr;
 383         int csr12_shadow;
 384         int pad0;               /* Used for 8-byte alignment */
 385 };
 386
 387
 388 struct eeprom_fixup {
 389         char *name;
 390         unsigned char addr0;
 391         unsigned char addr1;
 392         unsigned char addr2;
 393         u16 newtable[32];       /* Max length below. */
 394 };
 395
 396
 397 /* 21142.c */
 398 extern u16 t21142_csr14[];
 399 void t21142_timer(unsigned long data);
 400 void t21142_start_nway(struct net_device *dev);
 401 void t21142_lnk_change(struct net_device *dev, int csr5);
 402
 403
 404 /* PNIC2.c */
 405 void pnic2_lnk_change(struct net_device *dev, int csr5);
 406 void pnic2_timer(unsigned long data);
 407 void pnic2_start_nway(struct net_device *dev);
 408 void pnic2_lnk_change(struct net_device *dev, int csr5);
 409
 410 /* eeprom.c */
 411 void tulip_parse_eeprom(struct net_device *dev);
 412 int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);
 413
 414 /* interrupt.c */
 415 extern unsigned int tulip_max_interrupt_work;
 416 extern int tulip_rx_copybreak;
 417 irqreturn_t tulip_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
 418 int tulip_refill_rx(struct net_device *dev);
 419 #ifdef CONFIG_TULIP_NAPI
 420 int tulip_poll(struct net_device *dev, int *budget);
 421 #endif
 422
 423
 424 /* media.c */
 425 int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
 426 void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
 427 void tulip_select_media(struct net_device *dev, int startup);
 428 int tulip_check_duplex(struct net_device *dev);
 429 void tulip_find_mii (struct net_device *dev, int board_idx);
 430
 431 /* pnic.c */
 432 void pnic_do_nway(struct net_device *dev);
 433 void pnic_lnk_change(struct net_device *dev, int csr5);
 434 void pnic_timer(unsigned long data);
 435
 436 /* timer.c */
 437 void tulip_timer(unsigned long data);
 438 void mxic_timer(unsigned long data);
 439 void comet_timer(unsigned long data);
 440
 441 /* tulip_core.c */
 442 extern int tulip_debug;
 443 extern const char * const medianame[];
 444 extern const char tulip_media_cap[];
 445 extern struct tulip_chip_table tulip_tbl[];
 446 void oom_timer(unsigned long data);
 447 extern u8 t21040_csr13[];
 448
 449 #ifndef USE_IO_OPS
 450 #undef inb
 451 #undef inw
 452 #undef inl
 453 #undef outb
 454 #undef outw
 455 #undef outl
 456 #define inb(addr) readb((void*)(addr))
 457 #define inw(addr) readw((void*)(addr))
 458 #define inl(addr) readl((void*)(addr))
 459 #define outb(val,addr) writeb((val), (void*)(addr))
 460 #define outw(val,addr) writew((val), (void*)(addr))
 461 #define outl(val,addr) writel((val), (void*)(addr))
 462 #endif /* !USE_IO_OPS */
 463
 464
 465
 466 static inline void tulip_start_rxtx(struct tulip_private *tp)
 467 {
 468         long ioaddr = tp->base_addr;
 469         outl(tp->csr6 | RxTx, ioaddr + CSR6);
 470         barrier();
 471         (void) inl(ioaddr + CSR6); /* mmio sync */
 472 }
 473
 474 static inline void tulip_stop_rxtx(struct tulip_private *tp)
 475 {
 476         long ioaddr = tp->base_addr;
 477         u32 csr6 = inl(ioaddr + CSR6);
 478
 479         if (csr6 & RxTx) {
 480                 outl(csr6 & ~RxTx, ioaddr + CSR6);
 481                 barrier();
 482                 (void) inl(ioaddr + CSR6); /* mmio sync */
 483         }
 484 }
 485
 486 static inline void tulip_restart_rxtx(struct tulip_private *tp)
 487 {
 488         tulip_stop_rxtx(tp);
 489         udelay(5);
 490         tulip_start_rxtx(tp);
 491 }
 492
 493 #endif /* __NET_TULIP_H__ */