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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / tulip / dmfe.c
blob7353f28ccc34b5c9f60ad7d9b86518abe9c8e681
1 /*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
26 Alan Cox <alan@redhat.com> :
27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
52 Alan Cox <alan@redhat.com>
53 Added new PCI identifiers provided by Clear Zhang at ALi
54 for their 1563 ethernet device.
55
56 TODO
57
58 Implement pci_driver::suspend() and pci_driver::resume()
59 power management methods.
60
61 Check on 64 bit boxes.
62 Check and fix on big endian boxes.
63
64 Test and make sure PCI latency is now correct for all cases.
65 */
66
67 #define DRV_NAME "dmfe"
68 #define DRV_VERSION "1.36.4"
69 #define DRV_RELDATE "2002-01-17"
70
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/string.h>
74 #include <linux/timer.h>
75 #include <linux/ptrace.h>
76 #include <linux/errno.h>
77 #include <linux/ioport.h>
78 #include <linux/slab.h>
79 #include <linux/interrupt.h>
80 #include <linux/pci.h>
81 #include <linux/init.h>
82 #include <linux/netdevice.h>
83 #include <linux/etherdevice.h>
84 #include <linux/ethtool.h>
85 #include <linux/skbuff.h>
86 #include <linux/delay.h>
87 #include <linux/spinlock.h>
88 #include <linux/crc32.h>
89
90 #include <asm/processor.h>
91 #include <asm/bitops.h>
92 #include <asm/io.h>
93 #include <asm/dma.h>
94 #include <asm/uaccess.h>
95
96
97 /* Board/System/Debug information/definition ---------------- */
98 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
99 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
100 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
101 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
102
103 #define DM9102_IO_SIZE 0x80
104 #define DM9102A_IO_SIZE 0x100
105 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
106 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
107 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
108 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
109 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
110 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
111 #define TX_BUF_ALLOC 0x600
112 #define RX_ALLOC_SIZE 0x620
113 #define DM910X_RESET 1
114 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
115 #define CR6_DEFAULT 0x00080000 /* HD */
116 #define CR7_DEFAULT 0x180c1
117 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
118 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
119 #define MAX_PACKET_SIZE 1514
120 #define DMFE_MAX_MULTICAST 14
121 #define RX_COPY_SIZE 100
122 #define MAX_CHECK_PACKET 0x8000
123 #define DM9801_NOISE_FLOOR 8
124 #define DM9802_NOISE_FLOOR 5
125
126 #define DMFE_10MHF 0
127 #define DMFE_100MHF 1
128 #define DMFE_10MFD 4
129 #define DMFE_100MFD 5
130 #define DMFE_AUTO 8
131 #define DMFE_1M_HPNA 0x10
132
133 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
134 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
135 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
136 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
137 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
138 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
139
140 #define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
141 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
142 #define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
143
144 #define DMFE_DBUG(dbug_now, msg, value) if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
145
146 #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
147
148
149 /* CR9 definition: SROM/MII */
150 #define CR9_SROM_READ 0x4800
151 #define CR9_SRCS 0x1
152 #define CR9_SRCLK 0x2
153 #define CR9_CRDOUT 0x8
154 #define SROM_DATA_0 0x0
155 #define SROM_DATA_1 0x4
156 #define PHY_DATA_1 0x20000
157 #define PHY_DATA_0 0x00000
158 #define MDCLKH 0x10000
159
160 #define PHY_POWER_DOWN 0x800
161
162 #define SROM_V41_CODE 0x14
163
164 #define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);
165
166 #define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
167 #define CHK_IO_SIZE(pci_dev, dev_rev) __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
168
169 /* Sten Check */
170 #define DEVICE net_device
171
172 /* Structure/enum declaration ------------------------------- */
173 struct tx_desc {
174 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
175 char *tx_buf_ptr; /* Data for us */
176 struct tx_desc *next_tx_desc;
177 } __attribute__(( aligned(32) ));
178
179 struct rx_desc {
180 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
181 struct sk_buff *rx_skb_ptr; /* Data for us */
182 struct rx_desc *next_rx_desc;
183 } __attribute__(( aligned(32) ));
184
185 struct dmfe_board_info {
186 u32 chip_id; /* Chip vendor/Device ID */
187 u32 chip_revision; /* Chip revision */
188 struct DEVICE *next_dev; /* next device */
189 struct pci_dev *pdev; /* PCI device */
190 spinlock_t lock;
191
192 long ioaddr; /* I/O base address */
193 u32 cr0_data;
194 u32 cr5_data;
195 u32 cr6_data;
196 u32 cr7_data;
197 u32 cr15_data;
198
199 /* pointer for memory physical address */
200 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
201 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
202 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
203 dma_addr_t first_tx_desc_dma;
204 dma_addr_t first_rx_desc_dma;
205
206 /* descriptor pointer */
207 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
208 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
209 unsigned char *desc_pool_ptr; /* descriptor pool memory */
210 struct tx_desc *first_tx_desc;
211 struct tx_desc *tx_insert_ptr;
212 struct tx_desc *tx_remove_ptr;
213 struct rx_desc *first_rx_desc;
214 struct rx_desc *rx_insert_ptr;
215 struct rx_desc *rx_ready_ptr; /* packet come pointer */
216 unsigned long tx_packet_cnt; /* transmitted packet count */
217 unsigned long tx_queue_cnt; /* wait to send packet count */
218 unsigned long rx_avail_cnt; /* available rx descriptor count */
219 unsigned long interval_rx_cnt; /* rx packet count a callback time */
220
221 u16 HPNA_command; /* For HPNA register 16 */
222 u16 HPNA_timer; /* For HPNA remote device check */
223 u16 dbug_cnt;
224 u16 NIC_capability; /* NIC media capability */
225 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
226
227 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
228 u8 chip_type; /* Keep DM9102A chip type */
229 u8 media_mode; /* user specify media mode */
230 u8 op_mode; /* real work media mode */
231 u8 phy_addr;
232 u8 link_failed; /* Ever link failed */
233 u8 wait_reset; /* Hardware failed, need to reset */
234 u8 dm910x_chk_mode; /* Operating mode check */
235 u8 first_in_callback; /* Flag to record state */
236 struct timer_list timer;
237
238 /* System defined statistic counter */
239 struct net_device_stats stats;
240
241 /* Driver defined statistic counter */
242 unsigned long tx_fifo_underrun;
243 unsigned long tx_loss_carrier;
244 unsigned long tx_no_carrier;
245 unsigned long tx_late_collision;
246 unsigned long tx_excessive_collision;
247 unsigned long tx_jabber_timeout;
248 unsigned long reset_count;
249 unsigned long reset_cr8;
250 unsigned long reset_fatal;
251 unsigned long reset_TXtimeout;
252
253 /* NIC SROM data */
254 unsigned char srom[128];
255 };
256
257 enum dmfe_offsets {
258 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
259 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
260 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
261 DCR15 = 0x78
262 };
263
264 enum dmfe_CR6_bits {
265 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
266 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
267 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
268 };
269
270 /* Global variable declaration ----------------------------- */
271 static int __devinitdata printed_version;
272 static char version[] __devinitdata =
273 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
274 DRV_VERSION " (" DRV_RELDATE ")\n";
275
276 static int dmfe_debug;
277 static unsigned char dmfe_media_mode = DMFE_AUTO;
278 static u32 dmfe_cr6_user_set;
279
280 /* For module input parameter */
281 static int debug;
282 static u32 cr6set;
283 static unsigned char mode = 8;
284 static u8 chkmode = 1;
285 static u8 HPNA_mode; /* Default: Low Power/High Speed */
286 static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
287 static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
288 static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
289 static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
290 4: TX pause packet */
291
292
293 /* function declaration ------------------------------------- */
294 static int dmfe_open(struct DEVICE *);
295 static int dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
296 static int dmfe_stop(struct DEVICE *);
297 static struct net_device_stats * dmfe_get_stats(struct DEVICE *);
298 static void dmfe_set_filter_mode(struct DEVICE *);
299 static struct ethtool_ops netdev_ethtool_ops;
300 static u16 read_srom_word(long ,int);
301 static irqreturn_t dmfe_interrupt(int , void *, struct pt_regs *);
302 #ifdef CONFIG_NET_POLL_CONTROLLER
303 static void poll_dmfe (struct net_device *dev);
304 #endif
305 static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
306 static void allocate_rx_buffer(struct dmfe_board_info *);
307 static void update_cr6(u32, unsigned long);
308 static void send_filter_frame(struct DEVICE * ,int);
309 static void dm9132_id_table(struct DEVICE * ,int);
310 static u16 phy_read(unsigned long, u8, u8, u32);
311 static void phy_write(unsigned long, u8, u8, u16, u32);
312 static void phy_write_1bit(unsigned long, u32);
313 static u16 phy_read_1bit(unsigned long);
314 static u8 dmfe_sense_speed(struct dmfe_board_info *);
315 static void dmfe_process_mode(struct dmfe_board_info *);
316 static void dmfe_timer(unsigned long);
317 static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
318 static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
319 static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
320 static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
321 static void dmfe_dynamic_reset(struct DEVICE *);
322 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
323 static void dmfe_init_dm910x(struct DEVICE *);
324 static void dmfe_parse_srom(struct dmfe_board_info *);
325 static void dmfe_program_DM9801(struct dmfe_board_info *, int);
326 static void dmfe_program_DM9802(struct dmfe_board_info *);
327 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
328 static void dmfe_set_phyxcer(struct dmfe_board_info *);
329
330 /* DM910X network baord routine ---------------------------- */
331
332 /*
333 * Search DM910X board ,allocate space and register it
334 */
335
336 static int __devinit dmfe_init_one (struct pci_dev *pdev,
337 const struct pci_device_id *ent)
338 {
339 struct dmfe_board_info *db; /* board information structure */
340 struct net_device *dev;
341 u32 dev_rev, pci_pmr;
342 int i, err;
343
344 DMFE_DBUG(0, "dmfe_init_one()", 0);
345
346 if (!printed_version++)
347 printk(version);
348
349 /* Init network device */
350 dev = alloc_etherdev(sizeof(*db));
351 if (dev == NULL)
352 return -ENOMEM;
353 SET_MODULE_OWNER(dev);
354 SET_NETDEV_DEV(dev, &pdev->dev);
355
356 if (pci_set_dma_mask(pdev, 0xffffffff)) {
357 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
358 err = -ENODEV;
359 goto err_out_free;
360 }
361
362 /* Enable Master/IO access, Disable memory access */
363 err = pci_enable_device(pdev);
364 if (err)
365 goto err_out_free;
366
367 if (!pci_resource_start(pdev, 0)) {
368 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
369 err = -ENODEV;
370 goto err_out_disable;
371 }
372
373 /* Read Chip revision */
374 pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
375
376 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev, dev_rev)) ) {
377 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
378 err = -ENODEV;
379 goto err_out_disable;
380 }
381
382 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
383
384 /* Set Latency Timer 80h */
385 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
386 Need a PCI quirk.. */
387
388 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
389 #endif
390
391 if (pci_request_regions(pdev, DRV_NAME)) {
392 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
393 err = -ENODEV;
394 goto err_out_disable;
395 }
396
397 /* Init system & device */
398 db = netdev_priv(dev);
399
400 /* Allocate Tx/Rx descriptor memory */
401 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
402 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
403
404 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
405 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
406 db->buf_pool_start = db->buf_pool_ptr;
407 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
408
409 db->chip_id = ent->driver_data;
410 db->ioaddr = pci_resource_start(pdev, 0);
411 db->chip_revision = dev_rev;
412
413 db->pdev = pdev;
414
415 dev->base_addr = db->ioaddr;
416 dev->irq = pdev->irq;
417 pci_set_drvdata(pdev, dev);
418 dev->open = &dmfe_open;
419 dev->hard_start_xmit = &dmfe_start_xmit;
420 dev->stop = &dmfe_stop;
421 dev->get_stats = &dmfe_get_stats;
422 dev->set_multicast_list = &dmfe_set_filter_mode;
423 #ifdef CONFIG_NET_POLL_CONTROLLER
424 dev->poll_controller = &poll_dmfe;
425 #endif
426 dev->ethtool_ops = &netdev_ethtool_ops;
427 spin_lock_init(&db->lock);
428
429 pci_read_config_dword(pdev, 0x50, &pci_pmr);
430 pci_pmr &= 0x70000;
431 if ( (pci_pmr == 0x10000) && (dev_rev == 0x02000031) )
432 db->chip_type = 1; /* DM9102A E3 */
433 else
434 db->chip_type = 0;
435
436 /* read 64 word srom data */
437 for (i = 0; i < 64; i++)
438 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
439
440 /* Set Node address */
441 for (i = 0; i < 6; i++)
442 dev->dev_addr[i] = db->srom[20 + i];
443
444 err = register_netdev (dev);
445 if (err)
446 goto err_out_res;
447
448 printk(KERN_INFO "%s: Davicom DM%04lx at pci%s,",
449 dev->name,
450 ent->driver_data >> 16,
451 pci_name(pdev));
452 for (i = 0; i < 6; i++)
453 printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]);
454 printk(", irq %d.\n", dev->irq);
455
456 pci_set_master(pdev);
457
458 return 0;
459
460 err_out_res:
461 pci_release_regions(pdev);
462 err_out_disable:
463 pci_disable_device(pdev);
464 err_out_free:
465 pci_set_drvdata(pdev, NULL);
466 free_netdev(dev);
467
468 return err;
469 }
470
471
472 static void __devexit dmfe_remove_one (struct pci_dev *pdev)
473 {
474 struct net_device *dev = pci_get_drvdata(pdev);
475 struct dmfe_board_info *db = netdev_priv(dev);
476
477 DMFE_DBUG(0, "dmfe_remove_one()", 0);
478
479 if (dev) {
480 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
481 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
482 db->desc_pool_dma_ptr);
483 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
484 db->buf_pool_ptr, db->buf_pool_dma_ptr);
485 unregister_netdev(dev);
486 pci_release_regions(pdev);
487 free_netdev(dev); /* free board information */
488 pci_set_drvdata(pdev, NULL);
489 }
490
491 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
492 }
493
494
495 /*
496 * Open the interface.
497 * The interface is opened whenever "ifconfig" actives it.
498 */
499
500 static int dmfe_open(struct DEVICE *dev)
501 {
502 int ret;
503 struct dmfe_board_info *db = netdev_priv(dev);
504
505 DMFE_DBUG(0, "dmfe_open", 0);
506
507 ret = request_irq(dev->irq, &dmfe_interrupt, SA_SHIRQ, dev->name, dev);
508 if (ret)
509 return ret;
510
511 /* system variable init */
512 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
513 db->tx_packet_cnt = 0;
514 db->tx_queue_cnt = 0;
515 db->rx_avail_cnt = 0;
516 db->link_failed = 1;
517 db->wait_reset = 0;
518
519 db->first_in_callback = 0;
520 db->NIC_capability = 0xf; /* All capability*/
521 db->PHY_reg4 = 0x1e0;
522
523 /* CR6 operation mode decision */
524 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
525 (db->chip_revision >= 0x02000030) ) {
526 db->cr6_data |= DMFE_TXTH_256;
527 db->cr0_data = CR0_DEFAULT;
528 db->dm910x_chk_mode=4; /* Enter the normal mode */
529 } else {
530 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
531 db->cr0_data = 0;
532 db->dm910x_chk_mode = 1; /* Enter the check mode */
533 }
534
535 /* Initilize DM910X board */
536 dmfe_init_dm910x(dev);
537
538 /* Active System Interface */
539 netif_wake_queue(dev);
540
541 /* set and active a timer process */
542 init_timer(&db->timer);
543 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
544 db->timer.data = (unsigned long)dev;
545 db->timer.function = &dmfe_timer;
546 add_timer(&db->timer);
547
548 return 0;
549 }
550
551
552 /* Initilize DM910X board
553 * Reset DM910X board
554 * Initilize TX/Rx descriptor chain structure
555 * Send the set-up frame
556 * Enable Tx/Rx machine
557 */
558
559 static void dmfe_init_dm910x(struct DEVICE *dev)
560 {
561 struct dmfe_board_info *db = netdev_priv(dev);
562 unsigned long ioaddr = db->ioaddr;
563
564 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
565
566 /* Reset DM910x MAC controller */
567 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
568 udelay(100);
569 outl(db->cr0_data, ioaddr + DCR0);
570 udelay(5);
571
572 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
573 db->phy_addr = 1;
574
575 /* Parser SROM and media mode */
576 dmfe_parse_srom(db);
577 db->media_mode = dmfe_media_mode;
578
579 /* RESET Phyxcer Chip by GPR port bit 7 */
580 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
581 if (db->chip_id == PCI_DM9009_ID) {
582 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
583 mdelay(300); /* Delay 300 ms */
584 }
585 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
586
587 /* Process Phyxcer Media Mode */
588 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
589 dmfe_set_phyxcer(db);
590
591 /* Media Mode Process */
592 if ( !(db->media_mode & DMFE_AUTO) )
593 db->op_mode = db->media_mode; /* Force Mode */
594
595 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
596 dmfe_descriptor_init(db, ioaddr);
597
598 /* Init CR6 to program DM910x operation */
599 update_cr6(db->cr6_data, ioaddr);
600
601 /* Send setup frame */
602 if (db->chip_id == PCI_DM9132_ID)
603 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
604 else
605 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
606
607 /* Init CR7, interrupt active bit */
608 db->cr7_data = CR7_DEFAULT;
609 outl(db->cr7_data, ioaddr + DCR7);
610
611 /* Init CR15, Tx jabber and Rx watchdog timer */
612 outl(db->cr15_data, ioaddr + DCR15);
613
614 /* Enable DM910X Tx/Rx function */
615 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
616 update_cr6(db->cr6_data, ioaddr);
617 }
618
619
620 /*
621 * Hardware start transmission.
622 * Send a packet to media from the upper layer.
623 */
624
625 static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
626 {
627 struct dmfe_board_info *db = netdev_priv(dev);
628 struct tx_desc *txptr;
629 unsigned long flags;
630
631 DMFE_DBUG(0, "dmfe_start_xmit", 0);
632
633 /* Resource flag check */
634 netif_stop_queue(dev);
635
636 /* Too large packet check */
637 if (skb->len > MAX_PACKET_SIZE) {
638 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
639 dev_kfree_skb(skb);
640 return 0;
641 }
642
643 spin_lock_irqsave(&db->lock, flags);
644
645 /* No Tx resource check, it never happen nromally */
646 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
647 spin_unlock_irqrestore(&db->lock, flags);
648 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_queue_cnt);
649 return 1;
650 }
651
652 /* Disable NIC interrupt */
653 outl(0, dev->base_addr + DCR7);
654
655 /* transmit this packet */
656 txptr = db->tx_insert_ptr;
657 memcpy(txptr->tx_buf_ptr, skb->data, skb->len);
658 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
659
660 /* Point to next transmit free descriptor */
661 db->tx_insert_ptr = txptr->next_tx_desc;
662
663 /* Transmit Packet Process */
664 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
665 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
666 db->tx_packet_cnt++; /* Ready to send */
667 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
668 dev->trans_start = jiffies; /* saved time stamp */
669 } else {
670 db->tx_queue_cnt++; /* queue TX packet */
671 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
672 }
673
674 /* Tx resource check */
675 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
676 netif_wake_queue(dev);
677
678 /* Restore CR7 to enable interrupt */
679 spin_unlock_irqrestore(&db->lock, flags);
680 outl(db->cr7_data, dev->base_addr + DCR7);
681
682 /* free this SKB */
683 dev_kfree_skb(skb);
684
685 return 0;
686 }
687
688
689 /*
690 * Stop the interface.
691 * The interface is stopped when it is brought.
692 */
693
694 static int dmfe_stop(struct DEVICE *dev)
695 {
696 struct dmfe_board_info *db = netdev_priv(dev);
697 unsigned long ioaddr = dev->base_addr;
698
699 DMFE_DBUG(0, "dmfe_stop", 0);
700
701 /* disable system */
702 netif_stop_queue(dev);
703
704 /* deleted timer */
705 del_timer_sync(&db->timer);
706
707 /* Reset & stop DM910X board */
708 outl(DM910X_RESET, ioaddr + DCR0);
709 udelay(5);
710 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
711
712 /* free interrupt */
713 free_irq(dev->irq, dev);
714
715 /* free allocated rx buffer */
716 dmfe_free_rxbuffer(db);
717
718 #if 0
719 /* show statistic counter */
720 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
721 db->tx_fifo_underrun, db->tx_excessive_collision,
722 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
723 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
724 db->reset_fatal, db->reset_TXtimeout);
725 #endif
726
727 return 0;
728 }
729
730
731 /*
732 * DM9102 insterrupt handler
733 * receive the packet to upper layer, free the transmitted packet
734 */
735
736 static irqreturn_t dmfe_interrupt(int irq, void *dev_id, struct pt_regs *regs)
737 {
738 struct DEVICE *dev = dev_id;
739 struct dmfe_board_info *db = netdev_priv(dev);
740 unsigned long ioaddr = dev->base_addr;
741 unsigned long flags;
742
743 DMFE_DBUG(0, "dmfe_interrupt()", 0);
744
745 if (!dev) {
746 DMFE_DBUG(1, "dmfe_interrupt() without DEVICE arg", 0);
747 return IRQ_NONE;
748 }
749
750 spin_lock_irqsave(&db->lock, flags);
751
752 /* Got DM910X status */
753 db->cr5_data = inl(ioaddr + DCR5);
754 outl(db->cr5_data, ioaddr + DCR5);
755 if ( !(db->cr5_data & 0xc1) ) {
756 spin_unlock_irqrestore(&db->lock, flags);
757 return IRQ_HANDLED;
758 }
759
760 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
761 outl(0, ioaddr + DCR7);
762
763 /* Check system status */
764 if (db->cr5_data & 0x2000) {
765 /* system bus error happen */
766 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
767 db->reset_fatal++;
768 db->wait_reset = 1; /* Need to RESET */
769 spin_unlock_irqrestore(&db->lock, flags);
770 return IRQ_HANDLED;
771 }
772
773 /* Received the coming packet */
774 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
775 dmfe_rx_packet(dev, db);
776
777 /* reallocate rx descriptor buffer */
778 if (db->rx_avail_cnt<RX_DESC_CNT)
779 allocate_rx_buffer(db);
780
781 /* Free the transmitted descriptor */
782 if ( db->cr5_data & 0x01)
783 dmfe_free_tx_pkt(dev, db);
784
785 /* Mode Check */
786 if (db->dm910x_chk_mode & 0x2) {
787 db->dm910x_chk_mode = 0x4;
788 db->cr6_data |= 0x100;
789 update_cr6(db->cr6_data, db->ioaddr);
790 }
791
792 /* Restore CR7 to enable interrupt mask */
793 outl(db->cr7_data, ioaddr + DCR7);
794
795 spin_unlock_irqrestore(&db->lock, flags);
796 return IRQ_HANDLED;
797 }
798
799
800 #ifdef CONFIG_NET_POLL_CONTROLLER
801 /*
802 * Polling 'interrupt' - used by things like netconsole to send skbs
803 * without having to re-enable interrupts. It's not called while
804 * the interrupt routine is executing.
805 */
806
807 static void poll_dmfe (struct net_device *dev)
808 {
809 /* disable_irq here is not very nice, but with the lockless
810 interrupt handler we have no other choice. */
811 disable_irq(dev->irq);
812 dmfe_interrupt (dev->irq, dev, NULL);
813 enable_irq(dev->irq);
814 }
815 #endif
816
817 /*
818 * Free TX resource after TX complete
819 */
820
821 static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
822 {
823 struct tx_desc *txptr;
824 unsigned long ioaddr = dev->base_addr;
825 u32 tdes0;
826
827 txptr = db->tx_remove_ptr;
828 while(db->tx_packet_cnt) {
829 tdes0 = le32_to_cpu(txptr->tdes0);
830 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
831 if (tdes0 & 0x80000000)
832 break;
833
834 /* A packet sent completed */
835 db->tx_packet_cnt--;
836 db->stats.tx_packets++;
837
838 /* Transmit statistic counter */
839 if ( tdes0 != 0x7fffffff ) {
840 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
841 db->stats.collisions += (tdes0 >> 3) & 0xf;
842 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
843 if (tdes0 & TDES0_ERR_MASK) {
844 db->stats.tx_errors++;
845
846 if (tdes0 & 0x0002) { /* UnderRun */
847 db->tx_fifo_underrun++;
848 if ( !(db->cr6_data & CR6_SFT) ) {
849 db->cr6_data = db->cr6_data | CR6_SFT;
850 update_cr6(db->cr6_data, db->ioaddr);
851 }
852 }
853 if (tdes0 & 0x0100)
854 db->tx_excessive_collision++;
855 if (tdes0 & 0x0200)
856 db->tx_late_collision++;
857 if (tdes0 & 0x0400)
858 db->tx_no_carrier++;
859 if (tdes0 & 0x0800)
860 db->tx_loss_carrier++;
861 if (tdes0 & 0x4000)
862 db->tx_jabber_timeout++;
863 }
864 }
865
866 txptr = txptr->next_tx_desc;
867 }/* End of while */
868
869 /* Update TX remove pointer to next */
870 db->tx_remove_ptr = txptr;
871
872 /* Send the Tx packet in queue */
873 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
874 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
875 db->tx_packet_cnt++; /* Ready to send */
876 db->tx_queue_cnt--;
877 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
878 dev->trans_start = jiffies; /* saved time stamp */
879 }
880
881 /* Resource available check */
882 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
883 netif_wake_queue(dev); /* Active upper layer, send again */
884 }
885
886
887 /*
888 * Calculate the CRC valude of the Rx packet
889 * flag = 1 : return the reverse CRC (for the received packet CRC)
890 * 0 : return the normal CRC (for Hash Table index)
891 */
892
893 static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
894 {
895 u32 crc = crc32(~0, Data, Len);
896 if (flag) crc = ~crc;
897 return crc;
898 }
899
900
901 /*
902 * Receive the come packet and pass to upper layer
903 */
904
905 static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
906 {
907 struct rx_desc *rxptr;
908 struct sk_buff *skb;
909 int rxlen;
910 u32 rdes0;
911
912 rxptr = db->rx_ready_ptr;
913
914 while(db->rx_avail_cnt) {
915 rdes0 = le32_to_cpu(rxptr->rdes0);
916 if (rdes0 & 0x80000000) /* packet owner check */
917 break;
918
919 db->rx_avail_cnt--;
920 db->interval_rx_cnt++;
921
922 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
923 if ( (rdes0 & 0x300) != 0x300) {
924 /* A packet without First/Last flag */
925 /* reuse this SKB */
926 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
927 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
928 } else {
929 /* A packet with First/Last flag */
930 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
931
932 /* error summary bit check */
933 if (rdes0 & 0x8000) {
934 /* This is a error packet */
935 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
936 db->stats.rx_errors++;
937 if (rdes0 & 1)
938 db->stats.rx_fifo_errors++;
939 if (rdes0 & 2)
940 db->stats.rx_crc_errors++;
941 if (rdes0 & 0x80)
942 db->stats.rx_length_errors++;
943 }
944
945 if ( !(rdes0 & 0x8000) ||
946 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
947 skb = rxptr->rx_skb_ptr;
948
949 /* Received Packet CRC check need or not */
950 if ( (db->dm910x_chk_mode & 1) &&
951 (cal_CRC(skb->tail, rxlen, 1) !=
952 (*(u32 *) (skb->tail+rxlen) ))) { /* FIXME (?) */
953 /* Found a error received packet */
954 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
955 db->dm910x_chk_mode = 3;
956 } else {
957 /* Good packet, send to upper layer */
958 /* Shorst packet used new SKB */
959 if ( (rxlen < RX_COPY_SIZE) &&
960 ( (skb = dev_alloc_skb(rxlen + 2) )
961 != NULL) ) {
962 /* size less than COPY_SIZE, allocate a rxlen SKB */
963 skb->dev = dev;
964 skb_reserve(skb, 2); /* 16byte align */
965 memcpy(skb_put(skb, rxlen), rxptr->rx_skb_ptr->tail, rxlen);
966 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
967 } else {
968 skb->dev = dev;
969 skb_put(skb, rxlen);
970 }
971 skb->protocol = eth_type_trans(skb, dev);
972 netif_rx(skb);
973 dev->last_rx = jiffies;
974 db->stats.rx_packets++;
975 db->stats.rx_bytes += rxlen;
976 }
977 } else {
978 /* Reuse SKB buffer when the packet is error */
979 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
980 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
981 }
982 }
983
984 rxptr = rxptr->next_rx_desc;
985 }
986
987 db->rx_ready_ptr = rxptr;
988 }
989
990
991 /*
992 * Get statistics from driver.
993 */
994
995 static struct net_device_stats * dmfe_get_stats(struct DEVICE *dev)
996 {
997 struct dmfe_board_info *db = netdev_priv(dev);
998
999 DMFE_DBUG(0, "dmfe_get_stats", 0);
1000 return &db->stats;
1001 }
1002
1003
1004 /*
1005 * Set DM910X multicast address
1006 */
1007
1008 static void dmfe_set_filter_mode(struct DEVICE * dev)
1009 {
1010 struct dmfe_board_info *db = netdev_priv(dev);
1011 unsigned long flags;
1012
1013 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1014 spin_lock_irqsave(&db->lock, flags);
1015
1016 if (dev->flags & IFF_PROMISC) {
1017 DMFE_DBUG(0, "Enable PROM Mode", 0);
1018 db->cr6_data |= CR6_PM | CR6_PBF;
1019 update_cr6(db->cr6_data, db->ioaddr);
1020 spin_unlock_irqrestore(&db->lock, flags);
1021 return;
1022 }
1023
1024 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
1025 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
1026 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1027 db->cr6_data |= CR6_PAM;
1028 spin_unlock_irqrestore(&db->lock, flags);
1029 return;
1030 }
1031
1032 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
1033 if (db->chip_id == PCI_DM9132_ID)
1034 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
1035 else
1036 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
1037 spin_unlock_irqrestore(&db->lock, flags);
1038 }
1039
1040 static void netdev_get_drvinfo(struct net_device *dev,
1041 struct ethtool_drvinfo *info)
1042 {
1043 struct dmfe_board_info *np = netdev_priv(dev);
1044
1045 strcpy(info->driver, DRV_NAME);
1046 strcpy(info->version, DRV_VERSION);
1047 if (np->pdev)
1048 strcpy(info->bus_info, pci_name(np->pdev));
1049 else
1050 sprintf(info->bus_info, "EISA 0x%lx %d",
1051 dev->base_addr, dev->irq);
1052 }
1053
1054 static struct ethtool_ops netdev_ethtool_ops = {
1055 .get_drvinfo = netdev_get_drvinfo,
1056 };
1057
1058 /*
1059 * A periodic timer routine
1060 * Dynamic media sense, allocate Rx buffer...
1061 */
1062
1063 static void dmfe_timer(unsigned long data)
1064 {
1065 u32 tmp_cr8;
1066 unsigned char tmp_cr12;
1067 struct DEVICE *dev = (struct DEVICE *) data;
1068 struct dmfe_board_info *db = netdev_priv(dev);
1069 unsigned long flags;
1070
1071 DMFE_DBUG(0, "dmfe_timer()", 0);
1072 spin_lock_irqsave(&db->lock, flags);
1073
1074 /* Media mode process when Link OK before enter this route */
1075 if (db->first_in_callback == 0) {
1076 db->first_in_callback = 1;
1077 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1078 db->cr6_data &= ~0x40000;
1079 update_cr6(db->cr6_data, db->ioaddr);
1080 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1081 db->cr6_data |= 0x40000;
1082 update_cr6(db->cr6_data, db->ioaddr);
1083 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1084 add_timer(&db->timer);
1085 spin_unlock_irqrestore(&db->lock, flags);
1086 return;
1087 }
1088 }
1089
1090
1091 /* Operating Mode Check */
1092 if ( (db->dm910x_chk_mode & 0x1) &&
1093 (db->stats.rx_packets > MAX_CHECK_PACKET) )
1094 db->dm910x_chk_mode = 0x4;
1095
1096 /* Dynamic reset DM910X : system error or transmit time-out */
1097 tmp_cr8 = inl(db->ioaddr + DCR8);
1098 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1099 db->reset_cr8++;
1100 db->wait_reset = 1;
1101 }
1102 db->interval_rx_cnt = 0;
1103
1104 /* TX polling kick monitor */
1105 if ( db->tx_packet_cnt &&
1106 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1107 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1108
1109 /* TX Timeout */
1110 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1111 db->reset_TXtimeout++;
1112 db->wait_reset = 1;
1113 printk(KERN_WARNING "%s: Tx timeout - resetting\n",
1114 dev->name);
1115 }
1116 }
1117
1118 if (db->wait_reset) {
1119 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1120 db->reset_count++;
1121 dmfe_dynamic_reset(dev);
1122 db->first_in_callback = 0;
1123 db->timer.expires = DMFE_TIMER_WUT;
1124 add_timer(&db->timer);
1125 spin_unlock_irqrestore(&db->lock, flags);
1126 return;
1127 }
1128
1129 /* Link status check, Dynamic media type change */
1130 if (db->chip_id == PCI_DM9132_ID)
1131 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1132 else
1133 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1134
1135 if ( ((db->chip_id == PCI_DM9102_ID) &&
1136 (db->chip_revision == 0x02000030)) ||
1137 ((db->chip_id == PCI_DM9132_ID) &&
1138 (db->chip_revision == 0x02000010)) ) {
1139 /* DM9102A Chip */
1140 if (tmp_cr12 & 2)
1141 tmp_cr12 = 0x0; /* Link failed */
1142 else
1143 tmp_cr12 = 0x3; /* Link OK */
1144 }
1145
1146 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1147 /* Link Failed */
1148 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1149 db->link_failed = 1;
1150
1151 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1152 /* AUTO or force 1M Homerun/Longrun don't need */
1153 if ( !(db->media_mode & 0x38) )
1154 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1155
1156 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1157 if (db->media_mode & DMFE_AUTO) {
1158 /* 10/100M link failed, used 1M Home-Net */
1159 db->cr6_data|=0x00040000; /* bit18=1, MII */
1160 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1161 update_cr6(db->cr6_data, db->ioaddr);
1162 }
1163 } else
1164 if ((tmp_cr12 & 0x3) && db->link_failed) {
1165 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1166 db->link_failed = 0;
1167
1168 /* Auto Sense Speed */
1169 if ( (db->media_mode & DMFE_AUTO) &&
1170 dmfe_sense_speed(db) )
1171 db->link_failed = 1;
1172 dmfe_process_mode(db);
1173 /* SHOW_MEDIA_TYPE(db->op_mode); */
1174 }
1175
1176 /* HPNA remote command check */
1177 if (db->HPNA_command & 0xf00) {
1178 db->HPNA_timer--;
1179 if (!db->HPNA_timer)
1180 dmfe_HPNA_remote_cmd_chk(db);
1181 }
1182
1183 /* Timer active again */
1184 db->timer.expires = DMFE_TIMER_WUT;
1185 add_timer(&db->timer);
1186 spin_unlock_irqrestore(&db->lock, flags);
1187 }
1188
1189
1190 /*
1191 * Dynamic reset the DM910X board
1192 * Stop DM910X board
1193 * Free Tx/Rx allocated memory
1194 * Reset DM910X board
1195 * Re-initilize DM910X board
1196 */
1197
1198 static void dmfe_dynamic_reset(struct DEVICE *dev)
1199 {
1200 struct dmfe_board_info *db = netdev_priv(dev);
1201
1202 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1203
1204 /* Sopt MAC controller */
1205 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1206 update_cr6(db->cr6_data, dev->base_addr);
1207 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1208 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1209
1210 /* Disable upper layer interface */
1211 netif_stop_queue(dev);
1212
1213 /* Free Rx Allocate buffer */
1214 dmfe_free_rxbuffer(db);
1215
1216 /* system variable init */
1217 db->tx_packet_cnt = 0;
1218 db->tx_queue_cnt = 0;
1219 db->rx_avail_cnt = 0;
1220 db->link_failed = 1;
1221 db->wait_reset = 0;
1222
1223 /* Re-initilize DM910X board */
1224 dmfe_init_dm910x(dev);
1225
1226 /* Restart upper layer interface */
1227 netif_wake_queue(dev);
1228 }
1229
1230
1231 /*
1232 * free all allocated rx buffer
1233 */
1234
1235 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1236 {
1237 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1238
1239 /* free allocated rx buffer */
1240 while (db->rx_avail_cnt) {
1241 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1242 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1243 db->rx_avail_cnt--;
1244 }
1245 }
1246
1247
1248 /*
1249 * Reuse the SK buffer
1250 */
1251
1252 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1253 {
1254 struct rx_desc *rxptr = db->rx_insert_ptr;
1255
1256 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1257 rxptr->rx_skb_ptr = skb;
1258 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1259 wmb();
1260 rxptr->rdes0 = cpu_to_le32(0x80000000);
1261 db->rx_avail_cnt++;
1262 db->rx_insert_ptr = rxptr->next_rx_desc;
1263 } else
1264 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1265 }
1266
1267
1268 /*
1269 * Initialize transmit/Receive descriptor
1270 * Using Chain structure, and allocate Tx/Rx buffer
1271 */
1272
1273 static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1274 {
1275 struct tx_desc *tmp_tx;
1276 struct rx_desc *tmp_rx;
1277 unsigned char *tmp_buf;
1278 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1279 dma_addr_t tmp_buf_dma;
1280 int i;
1281
1282 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1283
1284 /* tx descriptor start pointer */
1285 db->tx_insert_ptr = db->first_tx_desc;
1286 db->tx_remove_ptr = db->first_tx_desc;
1287 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1288
1289 /* rx descriptor start pointer */
1290 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1291 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1292 db->rx_insert_ptr = db->first_rx_desc;
1293 db->rx_ready_ptr = db->first_rx_desc;
1294 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1295
1296 /* Init Transmit chain */
1297 tmp_buf = db->buf_pool_start;
1298 tmp_buf_dma = db->buf_pool_dma_start;
1299 tmp_tx_dma = db->first_tx_desc_dma;
1300 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1301 tmp_tx->tx_buf_ptr = tmp_buf;
1302 tmp_tx->tdes0 = cpu_to_le32(0);
1303 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1304 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1305 tmp_tx_dma += sizeof(struct tx_desc);
1306 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1307 tmp_tx->next_tx_desc = tmp_tx + 1;
1308 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1309 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1310 }
1311 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1312 tmp_tx->next_tx_desc = db->first_tx_desc;
1313
1314 /* Init Receive descriptor chain */
1315 tmp_rx_dma=db->first_rx_desc_dma;
1316 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1317 tmp_rx->rdes0 = cpu_to_le32(0);
1318 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1319 tmp_rx_dma += sizeof(struct rx_desc);
1320 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1321 tmp_rx->next_rx_desc = tmp_rx + 1;
1322 }
1323 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1324 tmp_rx->next_rx_desc = db->first_rx_desc;
1325
1326 /* pre-allocate Rx buffer */
1327 allocate_rx_buffer(db);
1328 }
1329
1330
1331 /*
1332 * Update CR6 value
1333 * Firstly stop DM910X , then written value and start
1334 */
1335
1336 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1337 {
1338 u32 cr6_tmp;
1339
1340 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1341 outl(cr6_tmp, ioaddr + DCR6);
1342 udelay(5);
1343 outl(cr6_data, ioaddr + DCR6);
1344 udelay(5);
1345 }
1346
1347
1348 /*
1349 * Send a setup frame for DM9132
1350 * This setup frame initilize DM910X address filter mode
1351 */
1352
1353 static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
1354 {
1355 struct dev_mc_list *mcptr;
1356 u16 * addrptr;
1357 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1358 u32 hash_val;
1359 u16 i, hash_table[4];
1360
1361 DMFE_DBUG(0, "dm9132_id_table()", 0);
1362
1363 /* Node address */
1364 addrptr = (u16 *) dev->dev_addr;
1365 outw(addrptr[0], ioaddr);
1366 ioaddr += 4;
1367 outw(addrptr[1], ioaddr);
1368 ioaddr += 4;
1369 outw(addrptr[2], ioaddr);
1370 ioaddr += 4;
1371
1372 /* Clear Hash Table */
1373 for (i = 0; i < 4; i++)
1374 hash_table[i] = 0x0;
1375
1376 /* broadcast address */
1377 hash_table[3] = 0x8000;
1378
1379 /* the multicast address in Hash Table : 64 bits */
1380 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1381 hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1382 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1383 }
1384
1385 /* Write the hash table to MAC MD table */
1386 for (i = 0; i < 4; i++, ioaddr += 4)
1387 outw(hash_table[i], ioaddr);
1388 }
1389
1390
1391 /*
1392 * Send a setup frame for DM9102/DM9102A
1393 * This setup frame initilize DM910X address filter mode
1394 */
1395
1396 static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
1397 {
1398 struct dmfe_board_info *db = netdev_priv(dev);
1399 struct dev_mc_list *mcptr;
1400 struct tx_desc *txptr;
1401 u16 * addrptr;
1402 u32 * suptr;
1403 int i;
1404
1405 DMFE_DBUG(0, "send_filter_frame()", 0);
1406
1407 txptr = db->tx_insert_ptr;
1408 suptr = (u32 *) txptr->tx_buf_ptr;
1409
1410 /* Node address */
1411 addrptr = (u16 *) dev->dev_addr;
1412 *suptr++ = addrptr[0];
1413 *suptr++ = addrptr[1];
1414 *suptr++ = addrptr[2];
1415
1416 /* broadcast address */
1417 *suptr++ = 0xffff;
1418 *suptr++ = 0xffff;
1419 *suptr++ = 0xffff;
1420
1421 /* fit the multicast address */
1422 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1423 addrptr = (u16 *) mcptr->dmi_addr;
1424 *suptr++ = addrptr[0];
1425 *suptr++ = addrptr[1];
1426 *suptr++ = addrptr[2];
1427 }
1428
1429 for (; i<14; i++) {
1430 *suptr++ = 0xffff;
1431 *suptr++ = 0xffff;
1432 *suptr++ = 0xffff;
1433 }
1434
1435 /* prepare the setup frame */
1436 db->tx_insert_ptr = txptr->next_tx_desc;
1437 txptr->tdes1 = cpu_to_le32(0x890000c0);
1438
1439 /* Resource Check and Send the setup packet */
1440 if (!db->tx_packet_cnt) {
1441 /* Resource Empty */
1442 db->tx_packet_cnt++;
1443 txptr->tdes0 = cpu_to_le32(0x80000000);
1444 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1445 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1446 update_cr6(db->cr6_data, dev->base_addr);
1447 dev->trans_start = jiffies;
1448 } else
1449 db->tx_queue_cnt++; /* Put in TX queue */
1450 }
1451
1452
1453 /*
1454 * Allocate rx buffer,
1455 * As possible as allocate maxiumn Rx buffer
1456 */
1457
1458 static void allocate_rx_buffer(struct dmfe_board_info *db)
1459 {
1460 struct rx_desc *rxptr;
1461 struct sk_buff *skb;
1462
1463 rxptr = db->rx_insert_ptr;
1464
1465 while(db->rx_avail_cnt < RX_DESC_CNT) {
1466 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1467 break;
1468 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1469 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1470 wmb();
1471 rxptr->rdes0 = cpu_to_le32(0x80000000);
1472 rxptr = rxptr->next_rx_desc;
1473 db->rx_avail_cnt++;
1474 }
1475
1476 db->rx_insert_ptr = rxptr;
1477 }
1478
1479
1480 /*
1481 * Read one word data from the serial ROM
1482 */
1483
1484 static u16 read_srom_word(long ioaddr, int offset)
1485 {
1486 int i;
1487 u16 srom_data = 0;
1488 long cr9_ioaddr = ioaddr + DCR9;
1489
1490 outl(CR9_SROM_READ, cr9_ioaddr);
1491 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1492
1493 /* Send the Read Command 110b */
1494 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1495 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1496 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1497
1498 /* Send the offset */
1499 for (i = 5; i >= 0; i--) {
1500 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1501 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1502 }
1503
1504 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1505
1506 for (i = 16; i > 0; i--) {
1507 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1508 udelay(5);
1509 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1510 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1511 udelay(5);
1512 }
1513
1514 outl(CR9_SROM_READ, cr9_ioaddr);
1515 return srom_data;
1516 }
1517
1518
1519 /*
1520 * Auto sense the media mode
1521 */
1522
1523 static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1524 {
1525 u8 ErrFlag = 0;
1526 u16 phy_mode;
1527
1528 /* CR6 bit18=0, select 10/100M */
1529 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1530
1531 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1532 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1533
1534 if ( (phy_mode & 0x24) == 0x24 ) {
1535 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1536 phy_mode = phy_read(db->ioaddr, db->phy_addr, 7, db->chip_id) & 0xf000;
1537 else /* DM9102/DM9102A */
1538 phy_mode = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0xf000;
1539 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1540 switch (phy_mode) {
1541 case 0x1000: db->op_mode = DMFE_10MHF; break;
1542 case 0x2000: db->op_mode = DMFE_10MFD; break;
1543 case 0x4000: db->op_mode = DMFE_100MHF; break;
1544 case 0x8000: db->op_mode = DMFE_100MFD; break;
1545 default: db->op_mode = DMFE_10MHF;
1546 ErrFlag = 1;
1547 break;
1548 }
1549 } else {
1550 db->op_mode = DMFE_10MHF;
1551 DMFE_DBUG(0, "Link Failed :", phy_mode);
1552 ErrFlag = 1;
1553 }
1554
1555 return ErrFlag;
1556 }
1557
1558
1559 /*
1560 * Set 10/100 phyxcer capability
1561 * AUTO mode : phyxcer register4 is NIC capability
1562 * Force mode: phyxcer register4 is the force media
1563 */
1564
1565 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1566 {
1567 u16 phy_reg;
1568
1569 /* Select 10/100M phyxcer */
1570 db->cr6_data &= ~0x40000;
1571 update_cr6(db->cr6_data, db->ioaddr);
1572
1573 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1574 if (db->chip_id == PCI_DM9009_ID) {
1575 phy_reg = phy_read(db->ioaddr, db->phy_addr, 18, db->chip_id) & ~0x1000;
1576 phy_write(db->ioaddr, db->phy_addr, 18, phy_reg, db->chip_id);
1577 }
1578
1579 /* Phyxcer capability setting */
1580 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1581
1582 if (db->media_mode & DMFE_AUTO) {
1583 /* AUTO Mode */
1584 phy_reg |= db->PHY_reg4;
1585 } else {
1586 /* Force Mode */
1587 switch(db->media_mode) {
1588 case DMFE_10MHF: phy_reg |= 0x20; break;
1589 case DMFE_10MFD: phy_reg |= 0x40; break;
1590 case DMFE_100MHF: phy_reg |= 0x80; break;
1591 case DMFE_100MFD: phy_reg |= 0x100; break;
1592 }
1593 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1594 }
1595
1596 /* Write new capability to Phyxcer Reg4 */
1597 if ( !(phy_reg & 0x01e0)) {
1598 phy_reg|=db->PHY_reg4;
1599 db->media_mode|=DMFE_AUTO;
1600 }
1601 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1602
1603 /* Restart Auto-Negotiation */
1604 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1605 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1606 if ( !db->chip_type )
1607 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1608 }
1609
1610
1611 /*
1612 * Process op-mode
1613 * AUTO mode : PHY controller in Auto-negotiation Mode
1614 * Force mode: PHY controller in force mode with HUB
1615 * N-way force capability with SWITCH
1616 */
1617
1618 static void dmfe_process_mode(struct dmfe_board_info *db)
1619 {
1620 u16 phy_reg;
1621
1622 /* Full Duplex Mode Check */
1623 if (db->op_mode & 0x4)
1624 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1625 else
1626 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1627
1628 /* Transciver Selection */
1629 if (db->op_mode & 0x10) /* 1M HomePNA */
1630 db->cr6_data |= 0x40000;/* External MII select */
1631 else
1632 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1633
1634 update_cr6(db->cr6_data, db->ioaddr);
1635
1636 /* 10/100M phyxcer force mode need */
1637 if ( !(db->media_mode & 0x18)) {
1638 /* Forece Mode */
1639 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1640 if ( !(phy_reg & 0x1) ) {
1641 /* parter without N-Way capability */
1642 phy_reg = 0x0;
1643 switch(db->op_mode) {
1644 case DMFE_10MHF: phy_reg = 0x0; break;
1645 case DMFE_10MFD: phy_reg = 0x100; break;
1646 case DMFE_100MHF: phy_reg = 0x2000; break;
1647 case DMFE_100MFD: phy_reg = 0x2100; break;
1648 }
1649 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1650 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1651 mdelay(20);
1652 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1653 }
1654 }
1655 }
1656
1657
1658 /*
1659 * Write a word to Phy register
1660 */
1661
1662 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1663 {
1664 u16 i;
1665 unsigned long ioaddr;
1666
1667 if (chip_id == PCI_DM9132_ID) {
1668 ioaddr = iobase + 0x80 + offset * 4;
1669 outw(phy_data, ioaddr);
1670 } else {
1671 /* DM9102/DM9102A Chip */
1672 ioaddr = iobase + DCR9;
1673
1674 /* Send 33 synchronization clock to Phy controller */
1675 for (i = 0; i < 35; i++)
1676 phy_write_1bit(ioaddr, PHY_DATA_1);
1677
1678 /* Send start command(01) to Phy */
1679 phy_write_1bit(ioaddr, PHY_DATA_0);
1680 phy_write_1bit(ioaddr, PHY_DATA_1);
1681
1682 /* Send write command(01) to Phy */
1683 phy_write_1bit(ioaddr, PHY_DATA_0);
1684 phy_write_1bit(ioaddr, PHY_DATA_1);
1685
1686 /* Send Phy address */
1687 for (i = 0x10; i > 0; i = i >> 1)
1688 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1689
1690 /* Send register address */
1691 for (i = 0x10; i > 0; i = i >> 1)
1692 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1693
1694 /* written trasnition */
1695 phy_write_1bit(ioaddr, PHY_DATA_1);
1696 phy_write_1bit(ioaddr, PHY_DATA_0);
1697
1698 /* Write a word data to PHY controller */
1699 for ( i = 0x8000; i > 0; i >>= 1)
1700 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1701 }
1702 }
1703
1704
1705 /*
1706 * Read a word data from phy register
1707 */
1708
1709 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1710 {
1711 int i;
1712 u16 phy_data;
1713 unsigned long ioaddr;
1714
1715 if (chip_id == PCI_DM9132_ID) {
1716 /* DM9132 Chip */
1717 ioaddr = iobase + 0x80 + offset * 4;
1718 phy_data = inw(ioaddr);
1719 } else {
1720 /* DM9102/DM9102A Chip */
1721 ioaddr = iobase + DCR9;
1722
1723 /* Send 33 synchronization clock to Phy controller */
1724 for (i = 0; i < 35; i++)
1725 phy_write_1bit(ioaddr, PHY_DATA_1);
1726
1727 /* Send start command(01) to Phy */
1728 phy_write_1bit(ioaddr, PHY_DATA_0);
1729 phy_write_1bit(ioaddr, PHY_DATA_1);
1730
1731 /* Send read command(10) to Phy */
1732 phy_write_1bit(ioaddr, PHY_DATA_1);
1733 phy_write_1bit(ioaddr, PHY_DATA_0);
1734
1735 /* Send Phy address */
1736 for (i = 0x10; i > 0; i = i >> 1)
1737 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1738
1739 /* Send register address */
1740 for (i = 0x10; i > 0; i = i >> 1)
1741 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1742
1743 /* Skip transition state */
1744 phy_read_1bit(ioaddr);
1745
1746 /* read 16bit data */
1747 for (phy_data = 0, i = 0; i < 16; i++) {
1748 phy_data <<= 1;
1749 phy_data |= phy_read_1bit(ioaddr);
1750 }
1751 }
1752
1753 return phy_data;
1754 }
1755
1756
1757 /*
1758 * Write one bit data to Phy Controller
1759 */
1760
1761 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1762 {
1763 outl(phy_data, ioaddr); /* MII Clock Low */
1764 udelay(1);
1765 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1766 udelay(1);
1767 outl(phy_data, ioaddr); /* MII Clock Low */
1768 udelay(1);
1769 }
1770
1771
1772 /*
1773 * Read one bit phy data from PHY controller
1774 */
1775
1776 static u16 phy_read_1bit(unsigned long ioaddr)
1777 {
1778 u16 phy_data;
1779
1780 outl(0x50000, ioaddr);
1781 udelay(1);
1782 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1783 outl(0x40000, ioaddr);
1784 udelay(1);
1785
1786 return phy_data;
1787 }
1788
1789
1790 /*
1791 * Parser SROM and media mode
1792 */
1793
1794 static void dmfe_parse_srom(struct dmfe_board_info * db)
1795 {
1796 char * srom = db->srom;
1797 int dmfe_mode, tmp_reg;
1798
1799 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1800
1801 /* Init CR15 */
1802 db->cr15_data = CR15_DEFAULT;
1803
1804 /* Check SROM Version */
1805 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1806 /* SROM V4.01 */
1807 /* Get NIC support media mode */
1808 db->NIC_capability = le16_to_cpup(srom + 34);
1809 db->PHY_reg4 = 0;
1810 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1811 switch( db->NIC_capability & tmp_reg ) {
1812 case 0x1: db->PHY_reg4 |= 0x0020; break;
1813 case 0x2: db->PHY_reg4 |= 0x0040; break;
1814 case 0x4: db->PHY_reg4 |= 0x0080; break;
1815 case 0x8: db->PHY_reg4 |= 0x0100; break;
1816 }
1817 }
1818
1819 /* Media Mode Force or not check */
1820 dmfe_mode = le32_to_cpup(srom + 34) & le32_to_cpup(srom + 36);
1821 switch(dmfe_mode) {
1822 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1823 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1824 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1825 case 0x100:
1826 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1827 }
1828
1829 /* Special Function setting */
1830 /* VLAN function */
1831 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1832 db->cr15_data |= 0x40;
1833
1834 /* Flow Control */
1835 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1836 db->cr15_data |= 0x400;
1837
1838 /* TX pause packet */
1839 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1840 db->cr15_data |= 0x9800;
1841 }
1842
1843 /* Parse HPNA parameter */
1844 db->HPNA_command = 1;
1845
1846 /* Accept remote command or not */
1847 if (HPNA_rx_cmd == 0)
1848 db->HPNA_command |= 0x8000;
1849
1850 /* Issue remote command & operation mode */
1851 if (HPNA_tx_cmd == 1)
1852 switch(HPNA_mode) { /* Issue Remote Command */
1853 case 0: db->HPNA_command |= 0x0904; break;
1854 case 1: db->HPNA_command |= 0x0a00; break;
1855 case 2: db->HPNA_command |= 0x0506; break;
1856 case 3: db->HPNA_command |= 0x0602; break;
1857 }
1858 else
1859 switch(HPNA_mode) { /* Don't Issue */
1860 case 0: db->HPNA_command |= 0x0004; break;
1861 case 1: db->HPNA_command |= 0x0000; break;
1862 case 2: db->HPNA_command |= 0x0006; break;
1863 case 3: db->HPNA_command |= 0x0002; break;
1864 }
1865
1866 /* Check DM9801 or DM9802 present or not */
1867 db->HPNA_present = 0;
1868 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1869 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1870 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1871 /* DM9801 or DM9802 present */
1872 db->HPNA_timer = 8;
1873 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1874 /* DM9801 HomeRun */
1875 db->HPNA_present = 1;
1876 dmfe_program_DM9801(db, tmp_reg);
1877 } else {
1878 /* DM9802 LongRun */
1879 db->HPNA_present = 2;
1880 dmfe_program_DM9802(db);
1881 }
1882 }
1883
1884 }
1885
1886
1887 /*
1888 * Init HomeRun DM9801
1889 */
1890
1891 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
1892 {
1893 uint reg17, reg25;
1894
1895 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
1896 switch(HPNA_rev) {
1897 case 0xb900: /* DM9801 E3 */
1898 db->HPNA_command |= 0x1000;
1899 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
1900 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
1901 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1902 break;
1903 case 0xb901: /* DM9801 E4 */
1904 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1905 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
1906 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1907 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
1908 break;
1909 case 0xb902: /* DM9801 E5 */
1910 case 0xb903: /* DM9801 E6 */
1911 default:
1912 db->HPNA_command |= 0x1000;
1913 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1914 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
1915 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1916 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
1917 break;
1918 }
1919 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1920 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
1921 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
1922 }
1923
1924
1925 /*
1926 * Init HomeRun DM9802
1927 */
1928
1929 static void dmfe_program_DM9802(struct dmfe_board_info * db)
1930 {
1931 uint phy_reg;
1932
1933 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
1934 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1935 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1936 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
1937 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
1938 }
1939
1940
1941 /*
1942 * Check remote HPNA power and speed status. If not correct,
1943 * issue command again.
1944 */
1945
1946 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
1947 {
1948 uint phy_reg;
1949
1950 /* Got remote device status */
1951 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
1952 switch(phy_reg) {
1953 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
1954 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
1955 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
1956 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
1957 }
1958
1959 /* Check remote device status match our setting ot not */
1960 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
1961 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1962 db->HPNA_timer=8;
1963 } else
1964 db->HPNA_timer=600; /* Match, every 10 minutes, check */
1965 }
1966
1967
1968
1969 static struct pci_device_id dmfe_pci_tbl[] = {
1970 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
1971 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
1972 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
1973 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
1974 { 0, }
1975 };
1976 MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
1977
1978
1979 static struct pci_driver dmfe_driver = {
1980 .name = "dmfe",
1981 .id_table = dmfe_pci_tbl,
1982 .probe = dmfe_init_one,
1983 .remove = __devexit_p(dmfe_remove_one),
1984 };
1985
1986 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
1987 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
1988 MODULE_LICENSE("GPL");
1989
1990 MODULE_PARM(debug, "i");
1991 MODULE_PARM(mode, "i");
1992 MODULE_PARM(cr6set, "i");
1993 MODULE_PARM(chkmode, "i");
1994 MODULE_PARM(HPNA_mode, "i");
1995 MODULE_PARM(HPNA_rx_cmd, "i");
1996 MODULE_PARM(HPNA_tx_cmd, "i");
1997 MODULE_PARM(HPNA_NoiseFloor, "i");
1998 MODULE_PARM(SF_mode, "i");
1999 MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
2000 MODULE_PARM_DESC(mode, "Davicom DM9xxx: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2001 MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function (bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2002
2003 /* Description:
2004 * when user used insmod to add module, system invoked init_module()
2005 * to initilize and register.
2006 */
2007
2008 static int __init dmfe_init_module(void)
2009 {
2010 int rc;
2011
2012 printk(version);
2013 printed_version = 1;
2014
2015 DMFE_DBUG(0, "init_module() ", debug);
2016
2017 if (debug)
2018 dmfe_debug = debug; /* set debug flag */
2019 if (cr6set)
2020 dmfe_cr6_user_set = cr6set;
2021
2022 switch(mode) {
2023 case DMFE_10MHF:
2024 case DMFE_100MHF:
2025 case DMFE_10MFD:
2026 case DMFE_100MFD:
2027 case DMFE_1M_HPNA:
2028 dmfe_media_mode = mode;
2029 break;
2030 default:dmfe_media_mode = DMFE_AUTO;
2031 break;
2032 }
2033
2034 if (HPNA_mode > 4)
2035 HPNA_mode = 0; /* Default: LP/HS */
2036 if (HPNA_rx_cmd > 1)
2037 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2038 if (HPNA_tx_cmd > 1)
2039 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2040 if (HPNA_NoiseFloor > 15)
2041 HPNA_NoiseFloor = 0;
2042
2043 rc = pci_module_init(&dmfe_driver);
2044 if (rc < 0)
2045 return rc;
2046
2047 return 0;
2048 }
2049
2050
2051 /*
2052 * Description:
2053 * when user used rmmod to delete module, system invoked clean_module()
2054 * to un-register all registered services.
2055 */
2056
2057 static void __exit dmfe_cleanup_module(void)
2058 {
2059 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2060 pci_unregister_driver(&dmfe_driver);
2061 }
2062
2063 module_init(dmfe_init_module);
2064 module_exit(dmfe_cleanup_module);
MOXA 2.6.9 from sdlinux-moxaart.tgz