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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / smc91x.h
blobcf74b74c30018cc04b5b684a5f6c3a9e8a6f68ea
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37
38 /*
39 * Define your architecture specific bus configuration parameters here.
40 */
41
42 #if defined(CONFIG_SA1100_GRAPHICSCLIENT) || \
43 defined(CONFIG_SA1100_PFS168) || \
44 defined(CONFIG_SA1100_FLEXANET) || \
45 defined(CONFIG_SA1100_GRAPHICSMASTER) || \
46 defined(CONFIG_ARCH_LUBBOCK)
47
48 /* We can only do 16-bit reads and writes in the static memory space. */
49 #define SMC_CAN_USE_8BIT 0
50 #define SMC_CAN_USE_16BIT 1
51 #define SMC_CAN_USE_32BIT 0
52 #define SMC_NOWAIT 1
53
54 /* The first two address lines aren't connected... */
55 #define SMC_IO_SHIFT 2
56
57 #define SMC_inw(a, r) readw((a) + (r))
58 #define SMC_outw(v, a, r) writew(v, (a) + (r))
59 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
60 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
61
62 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
63
64 /* We can only do 16-bit reads and writes in the static memory space. */
65 #define SMC_CAN_USE_8BIT 0
66 #define SMC_CAN_USE_16BIT 1
67 #define SMC_CAN_USE_32BIT 0
68 #define SMC_NOWAIT 1
69
70 #define SMC_IO_SHIFT 0
71
72 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
73 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
74 #define SMC_insw(a, r, p, l) \
75 do { \
76 unsigned long __port = (a) + (r); \
77 u16 *__p = (u16 *)(p); \
78 int __l = (l); \
79 insw(__port, __p, __l); \
80 while (__l > 0) { \
81 *__p = swab16(*__p); \
82 __p++; \
83 __l--; \
84 } \
85 } while (0)
86 #define SMC_outsw(a, r, p, l) \
87 do { \
88 unsigned long __port = (a) + (r); \
89 u16 *__p = (u16 *)(p); \
90 int __l = (l); \
91 while (__l > 0) { \
92 /* Believe it or not, the swab isn't needed. */ \
93 outw( /* swab16 */ (*__p++), __port); \
94 __l--; \
95 } \
96 } while (0)
97 #define set_irq_type(irq, type)
98
99 #elif defined(CONFIG_SA1100_ASSABET)
100
101 #include <asm/arch/neponset.h>
102
103 /* We can only do 8-bit reads and writes in the static memory space. */
104 #define SMC_CAN_USE_8BIT 1
105 #define SMC_CAN_USE_16BIT 0
106 #define SMC_CAN_USE_32BIT 0
107 #define SMC_NOWAIT 1
108
109 /* The first two address lines aren't connected... */
110 #define SMC_IO_SHIFT 2
111
112 #define SMC_inb(a, r) readb((a) + (r))
113 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
114 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
115 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
116
117 #elif defined(CONFIG_ARCH_INNOKOM) || \
118 defined(CONFIG_MACH_MAINSTONE) || \
119 defined(CONFIG_ARCH_PXA_IDP) || \
120 defined(CONFIG_ARCH_RAMSES)
121
122 #define SMC_CAN_USE_8BIT 1
123 #define SMC_CAN_USE_16BIT 1
124 #define SMC_CAN_USE_32BIT 1
125 #define SMC_IO_SHIFT 0
126 #define SMC_NOWAIT 1
127 #define SMC_USE_PXA_DMA 1
128
129 #define SMC_inb(a, r) readb((a) + (r))
130 #define SMC_inw(a, r) readw((a) + (r))
131 #define SMC_inl(a, r) readl((a) + (r))
132 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
133 #define SMC_outl(v, a, r) writel(v, (a) + (r))
134 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
135 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
136
137 /* We actually can't write halfwords properly if not word aligned */
138 static inline void
139 SMC_outw(u16 val, unsigned long ioaddr, int reg)
140 {
141 if (reg & 2) {
142 unsigned int v = val << 16;
143 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
144 writel(v, ioaddr + (reg & ~2));
145 } else {
146 writew(val, ioaddr + reg);
147 }
148 }
149
150 #elif defined(CONFIG_ISA)
151
152 #define SMC_CAN_USE_8BIT 1
153 #define SMC_CAN_USE_16BIT 1
154 #define SMC_CAN_USE_32BIT 0
155
156 #define SMC_inb(a, r) inb((a) + (r))
157 #define SMC_inw(a, r) inw((a) + (r))
158 #define SMC_outb(v, a, r) outb(v, (a) + (r))
159 #define SMC_outw(v, a, r) outw(v, (a) + (r))
160 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
161 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
162
163 #elif defined(CONFIG_M32R)
164
165 #define SMC_CAN_USE_8BIT 0
166 #define SMC_CAN_USE_16BIT 1
167 #define SMC_CAN_USE_32BIT 0
168
169 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
170 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
171 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
172 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
173 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
174 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
175
176 #else
177
178 #define SMC_CAN_USE_8BIT 1
179 #define SMC_CAN_USE_16BIT 1
180 #define SMC_CAN_USE_32BIT 1
181 #define SMC_NOWAIT 1
182
183 #define SMC_inb(a, r) readb((a) + (r))
184 #define SMC_inw(a, r) readw((a) + (r))
185 #define SMC_inl(a, r) readl((a) + (r))
186 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
187 #define SMC_outw(v, a, r) writew(v, (a) + (r))
188 #define SMC_outl(v, a, r) writel(v, (a) + (r))
189 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
190 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
191
192 #define RPC_LSA_DEFAULT RPC_LED_100_10
193 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
194
195 #endif
196
197
198 #ifdef SMC_USE_PXA_DMA
199 /*
200 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
201 * always happening in irq context so no need to worry about races. TX is
202 * different and probably not worth it for that reason, and not as critical
203 * as RX which can overrun memory and lose packets.
204 */
205 #include <linux/pci.h>
206 #include <asm/dma.h>
207
208 #ifdef SMC_insl
209 #undef SMC_insl
210 #define SMC_insl(a, r, p, l) \
211 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
212 static inline void
213 smc_pxa_dma_insl(u_long ioaddr, u_long physaddr, int reg, int dma,
214 u_char *buf, int len)
215 {
216 dma_addr_t dmabuf;
217
218 /* fallback if no DMA available */
219 if (dma == (unsigned char)-1) {
220 readsl(ioaddr + reg, buf, len);
221 return;
222 }
223
224 /* 64 bit alignment is required for memory to memory DMA */
225 if ((long)buf & 4) {
226 *((u32 *)buf)++ = SMC_inl(ioaddr, reg);
227 len--;
228 }
229
230 len *= 4;
231 dmabuf = dma_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE);
232 DCSR(dma) = DCSR_NODESC;
233 DTADR(dma) = dmabuf;
234 DSADR(dma) = physaddr + reg;
235 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
236 DCMD_WIDTH4 | (DCMD_LENGTH & len));
237 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
238 while (!(DCSR(dma) & DCSR_STOPSTATE));
239 DCSR(dma) = 0;
240 dma_unmap_single(NULL, dmabuf, len, PCI_DMA_FROMDEVICE);
241 }
242 #endif
243
244 #ifdef SMC_insw
245 #undef SMC_insw
246 #define SMC_insw(a, r, p, l) \
247 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
248 static inline void
249 smc_pxa_dma_insw(u_long ioaddr, u_long physaddr, int reg, int dma,
250 u_char *buf, int len)
251 {
252 dma_addr_t dmabuf;
253
254 /* fallback if no DMA available */
255 if (dma == (unsigned char)-1) {
256 readsw(ioaddr + reg, buf, len);
257 return;
258 }
259
260 /* 64 bit alignment is required for memory to memory DMA */
261 while ((long)buf & 6) {
262 *((u16 *)buf)++ = SMC_inw(ioaddr, reg);
263 len--;
264 }
265
266 len *= 2;
267 dmabuf = dma_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE);
268 DCSR(dma) = DCSR_NODESC;
269 DTADR(dma) = dmabuf;
270 DSADR(dma) = physaddr + reg;
271 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
272 DCMD_WIDTH2 | (DCMD_LENGTH & len));
273 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
274 while (!(DCSR(dma) & DCSR_STOPSTATE));
275 DCSR(dma) = 0;
276 dma_unmap_single(NULL, dmabuf, len, PCI_DMA_FROMDEVICE);
277 }
278 #endif
279
280 static void
281 smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs)
282 {
283 DCSR(dma) = 0;
284 }
285 #endif /* SMC_USE_PXA_DMA */
286
287
288 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
289 #ifndef SMC_IO_SHIFT
290 #define SMC_IO_SHIFT 0
291 #endif
292 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
293
294
295 /*
296 . Bank Select Register:
297 .
298 . yyyy yyyy 0000 00xx
299 . xx = bank number
300 . yyyy yyyy = 0x33, for identification purposes.
301 */
302 #define BANK_SELECT (14 << SMC_IO_SHIFT)
303
304
305 // Transmit Control Register
306 /* BANK 0 */
307 #define TCR_REG SMC_REG(0x0000, 0)
308 #define TCR_ENABLE 0x0001 // When 1 we can transmit
309 #define TCR_LOOP 0x0002 // Controls output pin LBK
310 #define TCR_FORCOL 0x0004 // When 1 will force a collision
311 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
312 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
313 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
314 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
315 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
316 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
317 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
318
319 #define TCR_CLEAR 0 /* do NOTHING */
320 /* the default settings for the TCR register : */
321 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
322
323
324 // EPH Status Register
325 /* BANK 0 */
326 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
327 #define ES_TX_SUC 0x0001 // Last TX was successful
328 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
329 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
330 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
331 #define ES_16COL 0x0010 // 16 Collisions Reached
332 #define ES_SQET 0x0020 // Signal Quality Error Test
333 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
334 #define ES_TXDEFR 0x0080 // Transmit Deferred
335 #define ES_LATCOL 0x0200 // Late collision detected on last tx
336 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
337 #define ES_EXC_DEF 0x0800 // Excessive Deferral
338 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
339 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
340 #define ES_TXUNRN 0x8000 // Tx Underrun
341
342
343 // Receive Control Register
344 /* BANK 0 */
345 #define RCR_REG SMC_REG(0x0004, 0)
346 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
347 #define RCR_PRMS 0x0002 // Enable promiscuous mode
348 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
349 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
350 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
351 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
352 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
353 #define RCR_SOFTRST 0x8000 // resets the chip
354
355 /* the normal settings for the RCR register : */
356 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
357 #define RCR_CLEAR 0x0 // set it to a base state
358
359
360 // Counter Register
361 /* BANK 0 */
362 #define COUNTER_REG SMC_REG(0x0006, 0)
363
364
365 // Memory Information Register
366 /* BANK 0 */
367 #define MIR_REG SMC_REG(0x0008, 0)
368
369
370 // Receive/Phy Control Register
371 /* BANK 0 */
372 #define RPC_REG SMC_REG(0x000A, 0)
373 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
374 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
375 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
376 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
377 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
378 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
379 #define RPC_LED_RES (0x01) // LED = Reserved
380 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
381 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
382 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
383 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
384 #define RPC_LED_TX (0x06) // LED = TX packet occurred
385 #define RPC_LED_RX (0x07) // LED = RX packet occurred
386
387 #ifndef RPC_LSA_DEFAULT
388 #define RPC_LSA_DEFAULT RPC_LED_100
389 #endif
390 #ifndef RPC_LSB_DEFAULT
391 #define RPC_LSB_DEFAULT RPC_LED_FD
392 #endif
393
394 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
395
396
397 /* Bank 0 0x0C is reserved */
398
399 // Bank Select Register
400 /* All Banks */
401 #define BSR_REG 0x000E
402
403
404 // Configuration Reg
405 /* BANK 1 */
406 #define CONFIG_REG SMC_REG(0x0000, 1)
407 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
408 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
409 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
410 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
411
412 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
413 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
414
415
416 // Base Address Register
417 /* BANK 1 */
418 #define BASE_REG SMC_REG(0x0002, 1)
419
420
421 // Individual Address Registers
422 /* BANK 1 */
423 #define ADDR0_REG SMC_REG(0x0004, 1)
424 #define ADDR1_REG SMC_REG(0x0006, 1)
425 #define ADDR2_REG SMC_REG(0x0008, 1)
426
427
428 // General Purpose Register
429 /* BANK 1 */
430 #define GP_REG SMC_REG(0x000A, 1)
431
432
433 // Control Register
434 /* BANK 1 */
435 #define CTL_REG SMC_REG(0x000C, 1)
436 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
437 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
438 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
439 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
440 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
441 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
442 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
443 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
444
445
446 // MMU Command Register
447 /* BANK 2 */
448 #define MMU_CMD_REG SMC_REG(0x0000, 2)
449 #define MC_BUSY 1 // When 1 the last release has not completed
450 #define MC_NOP (0<<5) // No Op
451 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
452 #define MC_RESET (2<<5) // Reset MMU to initial state
453 #define MC_REMOVE (3<<5) // Remove the current rx packet
454 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
455 #define MC_FREEPKT (5<<5) // Release packet in PNR register
456 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
457 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
458
459
460 // Packet Number Register
461 /* BANK 2 */
462 #define PN_REG SMC_REG(0x0002, 2)
463
464
465 // Allocation Result Register
466 /* BANK 2 */
467 #define AR_REG SMC_REG(0x0003, 2)
468 #define AR_FAILED 0x80 // Alocation Failed
469
470
471 // TX FIFO Ports Register
472 /* BANK 2 */
473 #define TXFIFO_REG SMC_REG(0x0004, 2)
474 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
475
476 // RX FIFO Ports Register
477 /* BANK 2 */
478 #define RXFIFO_REG SMC_REG(0x0005, 2)
479 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
480
481 #define FIFO_REG SMC_REG(0x0004, 2)
482
483 // Pointer Register
484 /* BANK 2 */
485 #define PTR_REG SMC_REG(0x0006, 2)
486 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
487 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
488 #define PTR_READ 0x2000 // When 1 the operation is a read
489
490
491 // Data Register
492 /* BANK 2 */
493 #define DATA_REG SMC_REG(0x0008, 2)
494
495
496 // Interrupt Status/Acknowledge Register
497 /* BANK 2 */
498 #define INT_REG SMC_REG(0x000C, 2)
499
500
501 // Interrupt Mask Register
502 /* BANK 2 */
503 #define IM_REG SMC_REG(0x000D, 2)
504 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
505 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
506 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
507 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
508 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
509 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
510 #define IM_TX_INT 0x02 // Transmit Interrupt
511 #define IM_RCV_INT 0x01 // Receive Interrupt
512
513
514 // Multicast Table Registers
515 /* BANK 3 */
516 #define MCAST_REG1 SMC_REG(0x0000, 3)
517 #define MCAST_REG2 SMC_REG(0x0002, 3)
518 #define MCAST_REG3 SMC_REG(0x0004, 3)
519 #define MCAST_REG4 SMC_REG(0x0006, 3)
520
521
522 // Management Interface Register (MII)
523 /* BANK 3 */
524 #define MII_REG SMC_REG(0x0008, 3)
525 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
526 #define MII_MDOE 0x0008 // MII Output Enable
527 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
528 #define MII_MDI 0x0002 // MII Input, pin MDI
529 #define MII_MDO 0x0001 // MII Output, pin MDO
530
531
532 // Revision Register
533 /* BANK 3 */
534 /* ( hi: chip id low: rev # ) */
535 #define REV_REG SMC_REG(0x000A, 3)
536
537
538 // Early RCV Register
539 /* BANK 3 */
540 /* this is NOT on SMC9192 */
541 #define ERCV_REG SMC_REG(0x000C, 3)
542 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
543 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
544
545
546 // External Register
547 /* BANK 7 */
548 #define EXT_REG SMC_REG(0x0000, 7)
549
550
551 #define CHIP_9192 3
552 #define CHIP_9194 4
553 #define CHIP_9195 5
554 #define CHIP_9196 6
555 #define CHIP_91100 7
556 #define CHIP_91100FD 8
557 #define CHIP_91111FD 9
558
559 static const char * chip_ids[ 16 ] = {
560 NULL, NULL, NULL,
561 /* 3 */ "SMC91C90/91C92",
562 /* 4 */ "SMC91C94",
563 /* 5 */ "SMC91C95",
564 /* 6 */ "SMC91C96",
565 /* 7 */ "SMC91C100",
566 /* 8 */ "SMC91C100FD",
567 /* 9 */ "SMC91C11xFD",
568 NULL, NULL, NULL,
569 NULL, NULL, NULL};
570
571
572 /*
573 . Transmit status bits
574 */
575 #define TS_SUCCESS 0x0001
576 #define TS_LOSTCAR 0x0400
577 #define TS_LATCOL 0x0200
578 #define TS_16COL 0x0010
579
580 /*
581 . Receive status bits
582 */
583 #define RS_ALGNERR 0x8000
584 #define RS_BRODCAST 0x4000
585 #define RS_BADCRC 0x2000
586 #define RS_ODDFRAME 0x1000
587 #define RS_TOOLONG 0x0800
588 #define RS_TOOSHORT 0x0400
589 #define RS_MULTICAST 0x0001
590 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
591
592
593 /*
594 * PHY IDs
595 * LAN83C183 == LAN91C111 Internal PHY
596 */
597 #define PHY_LAN83C183 0x0016f840
598 #define PHY_LAN83C180 0x02821c50
599
600 /*
601 * PHY Register Addresses (LAN91C111 Internal PHY)
602 *
603 * Generic PHY registers can be found in <linux/mii.h>
604 *
605 * These phy registers are specific to our on-board phy.
606 */
607
608 // PHY Configuration Register 1
609 #define PHY_CFG1_REG 0x10
610 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
611 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
612 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
613 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
614 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
615 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
616 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
617 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
618 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
619 #define PHY_CFG1_TLVL_MASK 0x003C
620 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
621
622
623 // PHY Configuration Register 2
624 #define PHY_CFG2_REG 0x11
625 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
626 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
627 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
628 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
629
630 // PHY Status Output (and Interrupt status) Register
631 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
632 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
633 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
634 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
635 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
636 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
637 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
638 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
639 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
640 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
641 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
642
643 // PHY Interrupt/Status Mask Register
644 #define PHY_MASK_REG 0x13 // Interrupt Mask
645 // Uses the same bit definitions as PHY_INT_REG
646
647
648 /*
649 * SMC91C96 ethernet config and status registers.
650 * These are in the "attribute" space.
651 */
652 #define ECOR 0x8000
653 #define ECOR_RESET 0x80
654 #define ECOR_LEVEL_IRQ 0x40
655 #define ECOR_WR_ATTRIB 0x04
656 #define ECOR_ENABLE 0x01
657
658 #define ECSR 0x8002
659 #define ECSR_IOIS8 0x20
660 #define ECSR_PWRDWN 0x04
661 #define ECSR_INT 0x02
662
663 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
664
665
666 /*
667 * Macros to abstract register access according to the data bus
668 * capabilities. Please use those and not the in/out primitives.
669 * Note: the following macros do *not* select the bank -- this must
670 * be done separately as needed in the main code. The SMC_REG() macro
671 * only uses the bank argument for debugging purposes (when enabled).
672 */
673
674 #if SMC_DEBUG > 0
675 #define SMC_REG(reg, bank) \
676 ({ \
677 int __b = SMC_CURRENT_BANK(); \
678 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
679 printk( "%s: bank reg screwed (0x%04x)\n", \
680 CARDNAME, __b ); \
681 BUG(); \
682 } \
683 reg<<SMC_IO_SHIFT; \
684 })
685 #else
686 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
687 #endif
688
689 #if SMC_CAN_USE_8BIT
690 #define SMC_GET_PN() SMC_inb( ioaddr, PN_REG )
691 #define SMC_SET_PN(x) SMC_outb( x, ioaddr, PN_REG )
692 #define SMC_GET_AR() SMC_inb( ioaddr, AR_REG )
693 #define SMC_GET_TXFIFO() SMC_inb( ioaddr, TXFIFO_REG )
694 #define SMC_GET_RXFIFO() SMC_inb( ioaddr, RXFIFO_REG )
695 #define SMC_GET_INT() SMC_inb( ioaddr, INT_REG )
696 #define SMC_ACK_INT(x) SMC_outb( x, ioaddr, INT_REG )
697 #define SMC_GET_INT_MASK() SMC_inb( ioaddr, IM_REG )
698 #define SMC_SET_INT_MASK(x) SMC_outb( x, ioaddr, IM_REG )
699 #else
700 #define SMC_GET_PN() (SMC_inw( ioaddr, PN_REG ) & 0xFF)
701 #define SMC_SET_PN(x) SMC_outw( x, ioaddr, PN_REG )
702 #define SMC_GET_AR() (SMC_inw( ioaddr, PN_REG ) >> 8)
703 #define SMC_GET_TXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) & 0xFF)
704 #define SMC_GET_RXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) >> 8)
705 #define SMC_GET_INT() (SMC_inw( ioaddr, INT_REG ) & 0xFF)
706 #define SMC_ACK_INT(x) \
707 do { \
708 unsigned long __flags; \
709 int __mask; \
710 local_irq_save(__flags); \
711 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
712 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
713 local_irq_restore(__flags); \
714 } while (0)
715 #define SMC_GET_INT_MASK() (SMC_inw( ioaddr, INT_REG ) >> 8)
716 #define SMC_SET_INT_MASK(x) SMC_outw( (x) << 8, ioaddr, INT_REG )
717 #endif
718
719 #define SMC_CURRENT_BANK() SMC_inw( ioaddr, BANK_SELECT )
720 #define SMC_SELECT_BANK(x) SMC_outw( x, ioaddr, BANK_SELECT )
721 #define SMC_GET_BASE() SMC_inw( ioaddr, BASE_REG )
722 #define SMC_SET_BASE(x) SMC_outw( x, ioaddr, BASE_REG )
723 #define SMC_GET_CONFIG() SMC_inw( ioaddr, CONFIG_REG )
724 #define SMC_SET_CONFIG(x) SMC_outw( x, ioaddr, CONFIG_REG )
725 #define SMC_GET_COUNTER() SMC_inw( ioaddr, COUNTER_REG )
726 #define SMC_GET_CTL() SMC_inw( ioaddr, CTL_REG )
727 #define SMC_SET_CTL(x) SMC_outw( x, ioaddr, CTL_REG )
728 #define SMC_GET_MII() SMC_inw( ioaddr, MII_REG )
729 #define SMC_SET_MII(x) SMC_outw( x, ioaddr, MII_REG )
730 #define SMC_GET_MIR() SMC_inw( ioaddr, MIR_REG )
731 #define SMC_SET_MIR(x) SMC_outw( x, ioaddr, MIR_REG )
732 #define SMC_GET_MMU_CMD() SMC_inw( ioaddr, MMU_CMD_REG )
733 #define SMC_SET_MMU_CMD(x) SMC_outw( x, ioaddr, MMU_CMD_REG )
734 #define SMC_GET_FIFO() SMC_inw( ioaddr, FIFO_REG )
735 #define SMC_GET_PTR() SMC_inw( ioaddr, PTR_REG )
736 #define SMC_SET_PTR(x) SMC_outw( x, ioaddr, PTR_REG )
737 #define SMC_GET_RCR() SMC_inw( ioaddr, RCR_REG )
738 #define SMC_SET_RCR(x) SMC_outw( x, ioaddr, RCR_REG )
739 #define SMC_GET_REV() SMC_inw( ioaddr, REV_REG )
740 #define SMC_GET_RPC() SMC_inw( ioaddr, RPC_REG )
741 #define SMC_SET_RPC(x) SMC_outw( x, ioaddr, RPC_REG )
742 #define SMC_GET_TCR() SMC_inw( ioaddr, TCR_REG )
743 #define SMC_SET_TCR(x) SMC_outw( x, ioaddr, TCR_REG )
744
745 #ifndef SMC_GET_MAC_ADDR
746 #define SMC_GET_MAC_ADDR(addr) \
747 do { \
748 unsigned int __v; \
749 __v = SMC_inw( ioaddr, ADDR0_REG ); \
750 addr[0] = __v; addr[1] = __v >> 8; \
751 __v = SMC_inw( ioaddr, ADDR1_REG ); \
752 addr[2] = __v; addr[3] = __v >> 8; \
753 __v = SMC_inw( ioaddr, ADDR2_REG ); \
754 addr[4] = __v; addr[5] = __v >> 8; \
755 } while (0)
756 #endif
757
758 #define SMC_SET_MAC_ADDR(addr) \
759 do { \
760 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
761 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
762 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
763 } while (0)
764
765 #define SMC_CLEAR_MCAST() \
766 do { \
767 SMC_outw( 0, ioaddr, MCAST_REG1 ); \
768 SMC_outw( 0, ioaddr, MCAST_REG2 ); \
769 SMC_outw( 0, ioaddr, MCAST_REG3 ); \
770 SMC_outw( 0, ioaddr, MCAST_REG4 ); \
771 } while (0)
772 #define SMC_SET_MCAST(x) \
773 do { \
774 unsigned char *mt = (x); \
775 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
776 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
777 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
778 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
779 } while (0)
780
781 #if SMC_CAN_USE_32BIT
782 /*
783 * Some setups just can't write 8 or 16 bits reliably when not aligned
784 * to a 32 bit boundary. I tell you that exists!
785 * We re-do the ones here that can be easily worked around if they can have
786 * their low parts written to 0 without adverse effects.
787 */
788 #undef SMC_SELECT_BANK
789 #define SMC_SELECT_BANK(x) SMC_outl( (x)<<16, ioaddr, 12<<SMC_IO_SHIFT )
790 #undef SMC_SET_RPC
791 #define SMC_SET_RPC(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(8, 0) )
792 #undef SMC_SET_PN
793 #define SMC_SET_PN(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(0, 2) )
794 #undef SMC_SET_PTR
795 #define SMC_SET_PTR(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(4, 2) )
796 #endif
797
798 #if SMC_CAN_USE_32BIT
799 #define SMC_PUT_PKT_HDR(status, length) \
800 SMC_outl( (status) | (length) << 16, ioaddr, DATA_REG )
801 #define SMC_GET_PKT_HDR(status, length) \
802 do { \
803 unsigned int __val = SMC_inl( ioaddr, DATA_REG ); \
804 (status) = __val & 0xffff; \
805 (length) = __val >> 16; \
806 } while (0)
807 #else
808 #define SMC_PUT_PKT_HDR(status, length) \
809 do { \
810 SMC_outw( status, ioaddr, DATA_REG ); \
811 SMC_outw( length, ioaddr, DATA_REG ); \
812 } while (0)
813 #define SMC_GET_PKT_HDR(status, length) \
814 do { \
815 (status) = SMC_inw( ioaddr, DATA_REG ); \
816 (length) = SMC_inw( ioaddr, DATA_REG ); \
817 } while (0)
818 #endif
819
820 #if SMC_CAN_USE_32BIT
821 #define SMC_PUSH_DATA(p, l) \
822 do { \
823 char *__ptr = (p); \
824 int __len = (l); \
825 if (__len >= 2 && (unsigned long)__ptr & 2) { \
826 __len -= 2; \
827 SMC_outw( *(u16 *)__ptr, ioaddr, DATA_REG ); \
828 __ptr += 2; \
829 } \
830 SMC_outsl( ioaddr, DATA_REG, __ptr, __len >> 2); \
831 if (__len & 2) { \
832 __ptr += (__len & ~3); \
833 SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \
834 } \
835 } while (0)
836 #define SMC_PULL_DATA(p, l) \
837 do { \
838 char *__ptr = (p); \
839 int __len = (l); \
840 if ((unsigned long)__ptr & 2) { \
841 /* \
842 * We want 32bit alignment here. \
843 * Since some buses perform a full 32bit \
844 * fetch even for 16bit data we can't use \
845 * SMC_inw() here. Back both source (on chip \
846 * and destination) pointers of 2 bytes. \
847 */ \
848 __ptr -= 2; \
849 __len += 2; \
850 SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \
851 } \
852 __len += 2; \
853 SMC_insl( ioaddr, DATA_REG, __ptr, __len >> 2); \
854 } while (0)
855 #elif SMC_CAN_USE_16BIT
856 #define SMC_PUSH_DATA(p, l) SMC_outsw( ioaddr, DATA_REG, p, (l) >> 1 )
857 #define SMC_PULL_DATA(p, l) SMC_insw ( ioaddr, DATA_REG, p, (l) >> 1 )
858 #elif SMC_CAN_USE_8BIT
859 #define SMC_PUSH_DATA(p, l) SMC_outsb( ioaddr, DATA_REG, p, l )
860 #define SMC_PULL_DATA(p, l) SMC_insb ( ioaddr, DATA_REG, p, l )
861 #endif
862
863 #if ! SMC_CAN_USE_16BIT
864 #define SMC_outw(x, ioaddr, reg) \
865 do { \
866 unsigned int __val16 = (x); \
867 SMC_outb( __val16, ioaddr, reg ); \
868 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
869 } while (0)
870 #define SMC_inw(ioaddr, reg) \
871 ({ \
872 unsigned int __val16; \
873 __val16 = SMC_inb( ioaddr, reg ); \
874 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
875 __val16; \
876 })
877 #endif
878
879
880 #endif /* _SMC91X_H_ */
MOXA 2.6.9 from sdlinux-moxaart.tgz