?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / dl2k.c
blob53f01d51c338da97ced39d43485add1410106cac
1 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
2 /*
3 Copyright (c) 2001, 2002 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11 */
12 /*
13 Rev Date Description
14 ==========================================================================
15 0.01 2001/05/03 Created DL2000-based linux driver
16 0.02 2001/05/21 Added VLAN and hardware checksum support.
17 1.00 2001/06/26 Added jumbo frame support.
18 1.01 2001/08/21 Added two parameters, rx_coalesce and rx_timeout.
19 1.02 2001/10/08 Supported fiber media.
20 Added flow control parameters.
21 1.03 2001/10/12 Changed the default media to 1000mbps_fd for
22 the fiber devices.
23 1.04 2001/11/08 Fixed Tx stopped when tx very busy.
24 1.05 2001/11/22 Fixed Tx stopped when unidirectional tx busy.
25 1.06 2001/12/13 Fixed disconnect bug at 10Mbps mode.
26 Fixed tx_full flag incorrect.
27 Added tx_coalesce paramter.
28 1.07 2002/01/03 Fixed miscount of RX frame error.
29 1.08 2002/01/17 Fixed the multicast bug.
30 1.09 2002/03/07 Move rx-poll-now to re-fill loop.
31 Added rio_timer() to watch rx buffers.
32 1.10 2002/04/16 Fixed miscount of carrier error.
33 1.11 2002/05/23 Added ISR schedule scheme
34 Fixed miscount of rx frame error for DGE-550SX.
35 Fixed VLAN bug.
36 1.12 2002/06/13 Lock tx_coalesce=1 on 10/100Mbps mode.
37 1.13 2002/08/13 1. Fix disconnection (many tx:carrier/rx:frame
38 errs) with some mainboards.
39 2. Use definition "DRV_NAME" "DRV_VERSION"
40 "DRV_RELDATE" for flexibility.
41 1.14 2002/08/14 Support ethtool.
42 1.15 2002/08/27 Changed the default media to Auto-Negotiation
43 for the fiber devices.
44 1.16 2002/09/04 More power down time for fiber devices auto-
45 negotiation.
46 Fix disconnect bug after ifup and ifdown.
47 1.17 2002/10/03 Fix RMON statistics overflow.
48 Always use I/O mapping to access eeprom,
49 avoid system freezing with some chipsets.
50
51 */
52 #define DRV_NAME "D-Link DL2000-based linux driver"
53 #define DRV_VERSION "v1.17a"
54 #define DRV_RELDATE "2002/10/04"
55 #include "dl2k.h"
56
57 static char version[] __devinitdata =
58 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
59 #define MAX_UNITS 8
60 static int mtu[MAX_UNITS];
61 static int vlan[MAX_UNITS];
62 static int jumbo[MAX_UNITS];
63 static char *media[MAX_UNITS];
64 static int tx_flow=-1;
65 static int rx_flow=-1;
66 static int copy_thresh;
67 static int rx_coalesce=10; /* Rx frame count each interrupt */
68 static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
69 static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
70
71
72 MODULE_AUTHOR ("Edward Peng");
73 MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
74 MODULE_LICENSE("GPL");
75 MODULE_PARM (mtu, "1-" __MODULE_STRING (MAX_UNITS) "i");
76 MODULE_PARM (media, "1-" __MODULE_STRING (MAX_UNITS) "s");
77 MODULE_PARM (vlan, "1-" __MODULE_STRING (MAX_UNITS) "i");
78 MODULE_PARM (jumbo, "1-" __MODULE_STRING (MAX_UNITS) "i");
79 MODULE_PARM (tx_flow, "i");
80 MODULE_PARM (rx_flow, "i");
81 MODULE_PARM (copy_thresh, "i");
82 MODULE_PARM (rx_coalesce, "i"); /* Rx frame count each interrupt */
83 MODULE_PARM (rx_timeout, "i"); /* Rx DMA wait time in 64ns increments */
84 MODULE_PARM (tx_coalesce, "i"); /* HW xmit count each TxDMAComplete */
85
86
87 /* Enable the default interrupts */
88 #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
89 UpdateStats | LinkEvent)
90 #define EnableInt() \
91 writew(DEFAULT_INTR, ioaddr + IntEnable)
92
93 static int max_intrloop = 50;
94 static int multicast_filter_limit = 0x40;
95
96 static int rio_open (struct net_device *dev);
97 static void rio_timer (unsigned long data);
98 static void rio_tx_timeout (struct net_device *dev);
99 static void alloc_list (struct net_device *dev);
100 static int start_xmit (struct sk_buff *skb, struct net_device *dev);
101 static irqreturn_t rio_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
102 static void rio_free_tx (struct net_device *dev, int irq);
103 static void tx_error (struct net_device *dev, int tx_status);
104 static int receive_packet (struct net_device *dev);
105 static void rio_error (struct net_device *dev, int int_status);
106 static int change_mtu (struct net_device *dev, int new_mtu);
107 static void set_multicast (struct net_device *dev);
108 static struct net_device_stats *get_stats (struct net_device *dev);
109 static int clear_stats (struct net_device *dev);
110 static int rio_ethtool_ioctl (struct net_device *dev, void __user *useraddr);
111 static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
112 static int rio_close (struct net_device *dev);
113 static int find_miiphy (struct net_device *dev);
114 static int parse_eeprom (struct net_device *dev);
115 static int read_eeprom (long ioaddr, int eep_addr);
116 static int mii_wait_link (struct net_device *dev, int wait);
117 static int mii_set_media (struct net_device *dev);
118 static int mii_get_media (struct net_device *dev);
119 static int mii_set_media_pcs (struct net_device *dev);
120 static int mii_get_media_pcs (struct net_device *dev);
121 static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
122 static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
123 u16 data);
124
125 static int __devinit
126 rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
127 {
128 struct net_device *dev;
129 struct netdev_private *np;
130 static int card_idx;
131 int chip_idx = ent->driver_data;
132 int err, irq;
133 long ioaddr;
134 static int version_printed;
135 void *ring_space;
136 dma_addr_t ring_dma;
137
138 if (!version_printed++)
139 printk ("%s", version);
140
141 err = pci_enable_device (pdev);
142 if (err)
143 return err;
144
145 irq = pdev->irq;
146 err = pci_request_regions (pdev, "dl2k");
147 if (err)
148 goto err_out_disable;
149
150 pci_set_master (pdev);
151 dev = alloc_etherdev (sizeof (*np));
152 if (!dev) {
153 err = -ENOMEM;
154 goto err_out_res;
155 }
156 SET_MODULE_OWNER (dev);
157 SET_NETDEV_DEV(dev, &pdev->dev);
158
159 #ifdef MEM_MAPPING
160 ioaddr = pci_resource_start (pdev, 1);
161 ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
162 if (!ioaddr) {
163 err = -ENOMEM;
164 goto err_out_dev;
165 }
166 #else
167 ioaddr = pci_resource_start (pdev, 0);
168 #endif
169 dev->base_addr = ioaddr;
170 dev->irq = irq;
171 np = dev->priv;
172 np->chip_id = chip_idx;
173 np->pdev = pdev;
174 spin_lock_init (&np->tx_lock);
175 spin_lock_init (&np->rx_lock);
176
177 /* Parse manual configuration */
178 np->an_enable = 1;
179 np->tx_coalesce = 1;
180 if (card_idx < MAX_UNITS) {
181 if (media[card_idx] != NULL) {
182 np->an_enable = 0;
183 if (strcmp (media[card_idx], "auto") == 0 ||
184 strcmp (media[card_idx], "autosense") == 0 ||
185 strcmp (media[card_idx], "0") == 0 ) {
186 np->an_enable = 2;
187 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
188 strcmp (media[card_idx], "4") == 0) {
189 np->speed = 100;
190 np->full_duplex = 1;
191 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
192 || strcmp (media[card_idx], "3") == 0) {
193 np->speed = 100;
194 np->full_duplex = 0;
195 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
196 strcmp (media[card_idx], "2") == 0) {
197 np->speed = 10;
198 np->full_duplex = 1;
199 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
200 strcmp (media[card_idx], "1") == 0) {
201 np->speed = 10;
202 np->full_duplex = 0;
203 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
204 strcmp (media[card_idx], "6") == 0) {
205 np->speed=1000;
206 np->full_duplex=1;
207 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
208 strcmp (media[card_idx], "5") == 0) {
209 np->speed = 1000;
210 np->full_duplex = 0;
211 } else {
212 np->an_enable = 1;
213 }
214 }
215 if (jumbo[card_idx] != 0) {
216 np->jumbo = 1;
217 dev->mtu = MAX_JUMBO;
218 } else {
219 np->jumbo = 0;
220 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
221 dev->mtu = mtu[card_idx];
222 }
223 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
224 vlan[card_idx] : 0;
225 if (rx_coalesce > 0 && rx_timeout > 0) {
226 np->rx_coalesce = rx_coalesce;
227 np->rx_timeout = rx_timeout;
228 np->coalesce = 1;
229 }
230 np->tx_flow = (tx_flow == 0) ? 0 : 1;
231 np->rx_flow = (rx_flow == 0) ? 0 : 1;
232
233 if (tx_coalesce < 1)
234 tx_coalesce = 1;
235 else if (tx_coalesce > TX_RING_SIZE-1)
236 tx_coalesce = TX_RING_SIZE - 1;
237 }
238 dev->open = &rio_open;
239 dev->hard_start_xmit = &start_xmit;
240 dev->stop = &rio_close;
241 dev->get_stats = &get_stats;
242 dev->set_multicast_list = &set_multicast;
243 dev->do_ioctl = &rio_ioctl;
244 dev->tx_timeout = &rio_tx_timeout;
245 dev->watchdog_timeo = TX_TIMEOUT;
246 dev->change_mtu = &change_mtu;
247 #if 0
248 dev->features = NETIF_F_IP_CSUM;
249 #endif
250 pci_set_drvdata (pdev, dev);
251
252 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
253 if (!ring_space)
254 goto err_out_iounmap;
255 np->tx_ring = (struct netdev_desc *) ring_space;
256 np->tx_ring_dma = ring_dma;
257
258 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
259 if (!ring_space)
260 goto err_out_unmap_tx;
261 np->rx_ring = (struct netdev_desc *) ring_space;
262 np->rx_ring_dma = ring_dma;
263
264 /* Parse eeprom data */
265 parse_eeprom (dev);
266
267 /* Find PHY address */
268 err = find_miiphy (dev);
269 if (err)
270 goto err_out_unmap_rx;
271
272 /* Fiber device? */
273 np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
274 np->link_status = 0;
275 /* Set media and reset PHY */
276 if (np->phy_media) {
277 /* default Auto-Negotiation for fiber deivices */
278 if (np->an_enable == 2) {
279 np->an_enable = 1;
280 }
281 mii_set_media_pcs (dev);
282 } else {
283 /* Auto-Negotiation is mandatory for 1000BASE-T,
284 IEEE 802.3ab Annex 28D page 14 */
285 if (np->speed == 1000)
286 np->an_enable = 1;
287 mii_set_media (dev);
288 }
289 pci_read_config_byte(pdev, PCI_REVISION_ID, &np->pci_rev_id);
290
291 err = register_netdev (dev);
292 if (err)
293 goto err_out_unmap_rx;
294
295 card_idx++;
296
297 printk (KERN_INFO "%s: %s, %02x:%02x:%02x:%02x:%02x:%02x, IRQ %d\n",
298 dev->name, np->name,
299 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
300 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], irq);
301 if (tx_coalesce > 1)
302 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
303 tx_coalesce);
304 if (np->coalesce)
305 printk(KERN_INFO "rx_coalesce:\t%d packets\n"
306 KERN_INFO "rx_timeout: \t%d ns\n",
307 np->rx_coalesce, np->rx_timeout*640);
308 if (np->vlan)
309 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
310 return 0;
311
312 err_out_unmap_rx:
313 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
314 err_out_unmap_tx:
315 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
316 err_out_iounmap:
317 #ifdef MEM_MAPPING
318 iounmap ((void *) ioaddr);
319
320 err_out_dev:
321 #endif
322 free_netdev (dev);
323
324 err_out_res:
325 pci_release_regions (pdev);
326
327 err_out_disable:
328 pci_disable_device (pdev);
329 return err;
330 }
331
332 int
333 find_miiphy (struct net_device *dev)
334 {
335 int i, phy_found = 0;
336 struct netdev_private *np;
337 long ioaddr;
338 np = dev->priv;
339 ioaddr = dev->base_addr;
340 np->phy_addr = 1;
341
342 for (i = 31; i >= 0; i--) {
343 int mii_status = mii_read (dev, i, 1);
344 if (mii_status != 0xffff && mii_status != 0x0000) {
345 np->phy_addr = i;
346 phy_found++;
347 }
348 }
349 if (!phy_found) {
350 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
351 return -ENODEV;
352 }
353 return 0;
354 }
355
356 int
357 parse_eeprom (struct net_device *dev)
358 {
359 int i, j;
360 long ioaddr = dev->base_addr;
361 u8 sromdata[256];
362 u8 *psib;
363 u32 crc;
364 PSROM_t psrom = (PSROM_t) sromdata;
365 struct netdev_private *np = dev->priv;
366
367 int cid, next;
368
369 #ifdef MEM_MAPPING
370 ioaddr = pci_resource_start (np->pdev, 0);
371 #endif
372 /* Read eeprom */
373 for (i = 0; i < 128; i++) {
374 ((u16 *) sromdata)[i] = le16_to_cpu (read_eeprom (ioaddr, i));
375 }
376 #ifdef MEM_MAPPING
377 ioaddr = dev->base_addr;
378 #endif
379 /* Check CRC */
380 crc = ~ether_crc_le (256 - 4, sromdata);
381 if (psrom->crc != crc) {
382 printk (KERN_ERR "%s: EEPROM data CRC error.\n", dev->name);
383 return -1;
384 }
385
386 /* Set MAC address */
387 for (i = 0; i < 6; i++)
388 dev->dev_addr[i] = psrom->mac_addr[i];
389
390 /* Parse Software Infomation Block */
391 i = 0x30;
392 psib = (u8 *) sromdata;
393 do {
394 cid = psib[i++];
395 next = psib[i++];
396 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
397 printk (KERN_ERR "Cell data error\n");
398 return -1;
399 }
400 switch (cid) {
401 case 0: /* Format version */
402 break;
403 case 1: /* End of cell */
404 return 0;
405 case 2: /* Duplex Polarity */
406 np->duplex_polarity = psib[i];
407 writeb (readb (ioaddr + PhyCtrl) | psib[i],
408 ioaddr + PhyCtrl);
409 break;
410 case 3: /* Wake Polarity */
411 np->wake_polarity = psib[i];
412 break;
413 case 9: /* Adapter description */
414 j = (next - i > 255) ? 255 : next - i;
415 memcpy (np->name, &(psib[i]), j);
416 break;
417 case 4:
418 case 5:
419 case 6:
420 case 7:
421 case 8: /* Reversed */
422 break;
423 default: /* Unknown cell */
424 return -1;
425 }
426 i = next;
427 } while (1);
428
429 return 0;
430 }
431
432 static int
433 rio_open (struct net_device *dev)
434 {
435 struct netdev_private *np = dev->priv;
436 long ioaddr = dev->base_addr;
437 int i;
438 u16 macctrl;
439
440 i = request_irq (dev->irq, &rio_interrupt, SA_SHIRQ, dev->name, dev);
441 if (i)
442 return i;
443
444 /* Reset all logic functions */
445 writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
446 ioaddr + ASICCtrl + 2);
447 mdelay(10);
448
449 /* DebugCtrl bit 4, 5, 9 must set */
450 writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
451
452 /* Jumbo frame */
453 if (np->jumbo != 0)
454 writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
455
456 alloc_list (dev);
457
458 /* Get station address */
459 for (i = 0; i < 6; i++)
460 writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
461
462 set_multicast (dev);
463 if (np->coalesce) {
464 writel (np->rx_coalesce | np->rx_timeout << 16,
465 ioaddr + RxDMAIntCtrl);
466 }
467 /* Set RIO to poll every N*320nsec. */
468 writeb (0x20, ioaddr + RxDMAPollPeriod);
469 writeb (0xff, ioaddr + TxDMAPollPeriod);
470 writeb (0x30, ioaddr + RxDMABurstThresh);
471 writeb (0x30, ioaddr + RxDMAUrgentThresh);
472 writel (0x0007ffff, ioaddr + RmonStatMask);
473 /* clear statistics */
474 clear_stats (dev);
475
476 /* VLAN supported */
477 if (np->vlan) {
478 /* priority field in RxDMAIntCtrl */
479 writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
480 ioaddr + RxDMAIntCtrl);
481 /* VLANId */
482 writew (np->vlan, ioaddr + VLANId);
483 /* Length/Type should be 0x8100 */
484 writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
485 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
486 VLAN information tagged by TFC' VID, CFI fields. */
487 writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
488 ioaddr + MACCtrl);
489 }
490
491 init_timer (&np->timer);
492 np->timer.expires = jiffies + 1*HZ;
493 np->timer.data = (unsigned long) dev;
494 np->timer.function = &rio_timer;
495 add_timer (&np->timer);
496
497 /* Start Tx/Rx */
498 writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
499 ioaddr + MACCtrl);
500
501 macctrl = 0;
502 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
503 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
504 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
505 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
506 writew(macctrl, ioaddr + MACCtrl);
507
508 netif_start_queue (dev);
509
510 /* Enable default interrupts */
511 EnableInt ();
512 return 0;
513 }
514
515 static void
516 rio_timer (unsigned long data)
517 {
518 struct net_device *dev = (struct net_device *)data;
519 struct netdev_private *np = dev->priv;
520 unsigned int entry;
521 int next_tick = 1*HZ;
522 unsigned long flags;
523
524 spin_lock_irqsave(&np->rx_lock, flags);
525 /* Recover rx ring exhausted error */
526 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
527 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
528 /* Re-allocate skbuffs to fill the descriptor ring */
529 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
530 struct sk_buff *skb;
531 entry = np->old_rx % RX_RING_SIZE;
532 /* Dropped packets don't need to re-allocate */
533 if (np->rx_skbuff[entry] == NULL) {
534 skb = dev_alloc_skb (np->rx_buf_sz);
535 if (skb == NULL) {
536 np->rx_ring[entry].fraginfo = 0;
537 printk (KERN_INFO
538 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
539 dev->name, entry);
540 break;
541 }
542 np->rx_skbuff[entry] = skb;
543 skb->dev = dev;
544 /* 16 byte align the IP header */
545 skb_reserve (skb, 2);
546 np->rx_ring[entry].fraginfo =
547 cpu_to_le64 (pci_map_single
548 (np->pdev, skb->tail, np->rx_buf_sz,
549 PCI_DMA_FROMDEVICE));
550 }
551 np->rx_ring[entry].fraginfo |=
552 cpu_to_le64 (np->rx_buf_sz) << 48;
553 np->rx_ring[entry].status = 0;
554 } /* end for */
555 } /* end if */
556 spin_unlock_irqrestore (&np->rx_lock, flags);
557 np->timer.expires = jiffies + next_tick;
558 add_timer(&np->timer);
559 }
560
561 static void
562 rio_tx_timeout (struct net_device *dev)
563 {
564 long ioaddr = dev->base_addr;
565
566 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
567 dev->name, readl (ioaddr + TxStatus));
568 rio_free_tx(dev, 0);
569 dev->if_port = 0;
570 dev->trans_start = jiffies;
571 }
572
573 /* allocate and initialize Tx and Rx descriptors */
574 static void
575 alloc_list (struct net_device *dev)
576 {
577 struct netdev_private *np = dev->priv;
578 int i;
579
580 np->cur_rx = np->cur_tx = 0;
581 np->old_rx = np->old_tx = 0;
582 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
583
584 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
585 for (i = 0; i < TX_RING_SIZE; i++) {
586 np->tx_skbuff[i] = NULL;
587 np->tx_ring[i].status = cpu_to_le64 (TFDDone);
588 np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
589 ((i+1)%TX_RING_SIZE) *
590 sizeof (struct netdev_desc));
591 }
592
593 /* Initialize Rx descriptors */
594 for (i = 0; i < RX_RING_SIZE; i++) {
595 np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
596 ((i + 1) % RX_RING_SIZE) *
597 sizeof (struct netdev_desc));
598 np->rx_ring[i].status = 0;
599 np->rx_ring[i].fraginfo = 0;
600 np->rx_skbuff[i] = NULL;
601 }
602
603 /* Allocate the rx buffers */
604 for (i = 0; i < RX_RING_SIZE; i++) {
605 /* Allocated fixed size of skbuff */
606 struct sk_buff *skb = dev_alloc_skb (np->rx_buf_sz);
607 np->rx_skbuff[i] = skb;
608 if (skb == NULL) {
609 printk (KERN_ERR
610 "%s: alloc_list: allocate Rx buffer error! ",
611 dev->name);
612 break;
613 }
614 skb->dev = dev; /* Mark as being used by this device. */
615 skb_reserve (skb, 2); /* 16 byte align the IP header. */
616 /* Rubicon now supports 40 bits of addressing space. */
617 np->rx_ring[i].fraginfo =
618 cpu_to_le64 ( pci_map_single (
619 np->pdev, skb->tail, np->rx_buf_sz,
620 PCI_DMA_FROMDEVICE));
621 np->rx_ring[i].fraginfo |= cpu_to_le64 (np->rx_buf_sz) << 48;
622 }
623
624 /* Set RFDListPtr */
625 writel (cpu_to_le32 (np->rx_ring_dma), dev->base_addr + RFDListPtr0);
626 writel (0, dev->base_addr + RFDListPtr1);
627
628 return;
629 }
630
631 static int
632 start_xmit (struct sk_buff *skb, struct net_device *dev)
633 {
634 struct netdev_private *np = dev->priv;
635 struct netdev_desc *txdesc;
636 unsigned entry;
637 u32 ioaddr;
638 u64 tfc_vlan_tag = 0;
639
640 if (np->link_status == 0) { /* Link Down */
641 dev_kfree_skb(skb);
642 return 0;
643 }
644 ioaddr = dev->base_addr;
645 entry = np->cur_tx % TX_RING_SIZE;
646 np->tx_skbuff[entry] = skb;
647 txdesc = &np->tx_ring[entry];
648
649 #if 0
650 if (skb->ip_summed == CHECKSUM_HW) {
651 txdesc->status |=
652 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
653 IPChecksumEnable);
654 }
655 #endif
656 if (np->vlan) {
657 tfc_vlan_tag =
658 cpu_to_le64 (VLANTagInsert) |
659 (cpu_to_le64 (np->vlan) << 32) |
660 (cpu_to_le64 (skb->priority) << 45);
661 }
662 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
663 skb->len,
664 PCI_DMA_TODEVICE));
665 txdesc->fraginfo |= cpu_to_le64 (skb->len) << 48;
666
667 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
668 * Work around: Always use 1 descriptor in 10Mbps mode */
669 if (entry % np->tx_coalesce == 0 || np->speed == 10)
670 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
671 WordAlignDisable |
672 TxDMAIndicate |
673 (1 << FragCountShift));
674 else
675 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
676 WordAlignDisable |
677 (1 << FragCountShift));
678
679 /* TxDMAPollNow */
680 writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
681 /* Schedule ISR */
682 writel(10000, ioaddr + CountDown);
683 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
684 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
685 < TX_QUEUE_LEN - 1 && np->speed != 10) {
686 /* do nothing */
687 } else if (!netif_queue_stopped(dev)) {
688 netif_stop_queue (dev);
689 }
690
691 /* The first TFDListPtr */
692 if (readl (dev->base_addr + TFDListPtr0) == 0) {
693 writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
694 dev->base_addr + TFDListPtr0);
695 writel (0, dev->base_addr + TFDListPtr1);
696 }
697
698 /* NETDEV WATCHDOG timer */
699 dev->trans_start = jiffies;
700 return 0;
701 }
702
703 static irqreturn_t
704 rio_interrupt (int irq, void *dev_instance, struct pt_regs *rgs)
705 {
706 struct net_device *dev = dev_instance;
707 struct netdev_private *np;
708 unsigned int_status;
709 long ioaddr;
710 int cnt = max_intrloop;
711 int handled = 0;
712
713 ioaddr = dev->base_addr;
714 np = dev->priv;
715 while (1) {
716 int_status = readw (ioaddr + IntStatus);
717 writew (int_status, ioaddr + IntStatus);
718 int_status &= DEFAULT_INTR;
719 if (int_status == 0 || --cnt < 0)
720 break;
721 handled = 1;
722 /* Processing received packets */
723 if (int_status & RxDMAComplete)
724 receive_packet (dev);
725 /* TxDMAComplete interrupt */
726 if ((int_status & (TxDMAComplete|IntRequested))) {
727 int tx_status;
728 tx_status = readl (ioaddr + TxStatus);
729 if (tx_status & 0x01)
730 tx_error (dev, tx_status);
731 /* Free used tx skbuffs */
732 rio_free_tx (dev, 1);
733 }
734
735 /* Handle uncommon events */
736 if (int_status &
737 (HostError | LinkEvent | UpdateStats))
738 rio_error (dev, int_status);
739 }
740 if (np->cur_tx != np->old_tx)
741 writel (100, ioaddr + CountDown);
742 return IRQ_RETVAL(handled);
743 }
744
745 static void
746 rio_free_tx (struct net_device *dev, int irq)
747 {
748 struct netdev_private *np = dev->priv;
749 int entry = np->old_tx % TX_RING_SIZE;
750 int tx_use = 0;
751 unsigned long flag = 0;
752
753 if (irq)
754 spin_lock(&np->tx_lock);
755 else
756 spin_lock_irqsave(&np->tx_lock, flag);
757
758 /* Free used tx skbuffs */
759 while (entry != np->cur_tx) {
760 struct sk_buff *skb;
761
762 if (!(np->tx_ring[entry].status & TFDDone))
763 break;
764 skb = np->tx_skbuff[entry];
765 pci_unmap_single (np->pdev,
766 np->tx_ring[entry].fraginfo,
767 skb->len, PCI_DMA_TODEVICE);
768 if (irq)
769 dev_kfree_skb_irq (skb);
770 else
771 dev_kfree_skb (skb);
772
773 np->tx_skbuff[entry] = NULL;
774 entry = (entry + 1) % TX_RING_SIZE;
775 tx_use++;
776 }
777 if (irq)
778 spin_unlock(&np->tx_lock);
779 else
780 spin_unlock_irqrestore(&np->tx_lock, flag);
781 np->old_tx = entry;
782
783 /* If the ring is no longer full, clear tx_full and
784 call netif_wake_queue() */
785
786 if (netif_queue_stopped(dev) &&
787 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
788 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
789 netif_wake_queue (dev);
790 }
791 }
792
793 static void
794 tx_error (struct net_device *dev, int tx_status)
795 {
796 struct netdev_private *np;
797 long ioaddr = dev->base_addr;
798 int frame_id;
799 int i;
800
801 np = dev->priv;
802
803 frame_id = (tx_status & 0xffff0000);
804 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
805 dev->name, tx_status, frame_id);
806 np->stats.tx_errors++;
807 /* Ttransmit Underrun */
808 if (tx_status & 0x10) {
809 np->stats.tx_fifo_errors++;
810 writew (readw (ioaddr + TxStartThresh) + 0x10,
811 ioaddr + TxStartThresh);
812 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
813 writew (TxReset | DMAReset | FIFOReset | NetworkReset,
814 ioaddr + ASICCtrl + 2);
815 /* Wait for ResetBusy bit clear */
816 for (i = 50; i > 0; i--) {
817 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
818 break;
819 mdelay (1);
820 }
821 rio_free_tx (dev, 1);
822 /* Reset TFDListPtr */
823 writel (np->tx_ring_dma +
824 np->old_tx * sizeof (struct netdev_desc),
825 dev->base_addr + TFDListPtr0);
826 writel (0, dev->base_addr + TFDListPtr1);
827
828 /* Let TxStartThresh stay default value */
829 }
830 /* Late Collision */
831 if (tx_status & 0x04) {
832 np->stats.tx_fifo_errors++;
833 /* TxReset and clear FIFO */
834 writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
835 /* Wait reset done */
836 for (i = 50; i > 0; i--) {
837 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
838 break;
839 mdelay (1);
840 }
841 /* Let TxStartThresh stay default value */
842 }
843 /* Maximum Collisions */
844 #ifdef ETHER_STATS
845 if (tx_status & 0x08)
846 np->stats.collisions16++;
847 #else
848 if (tx_status & 0x08)
849 np->stats.collisions++;
850 #endif
851 /* Restart the Tx */
852 writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
853 }
854
855 static int
856 receive_packet (struct net_device *dev)
857 {
858 struct netdev_private *np = dev->priv;
859 int entry = np->cur_rx % RX_RING_SIZE;
860 int cnt = 30;
861
862 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
863 while (1) {
864 struct netdev_desc *desc = &np->rx_ring[entry];
865 int pkt_len;
866 u64 frame_status;
867
868 if (!(desc->status & RFDDone) ||
869 !(desc->status & FrameStart) || !(desc->status & FrameEnd))
870 break;
871
872 /* Chip omits the CRC. */
873 pkt_len = le64_to_cpu (desc->status & 0xffff);
874 frame_status = le64_to_cpu (desc->status);
875 if (--cnt < 0)
876 break;
877 /* Update rx error statistics, drop packet. */
878 if (frame_status & RFS_Errors) {
879 np->stats.rx_errors++;
880 if (frame_status & (RxRuntFrame | RxLengthError))
881 np->stats.rx_length_errors++;
882 if (frame_status & RxFCSError)
883 np->stats.rx_crc_errors++;
884 if (frame_status & RxAlignmentError && np->speed != 1000)
885 np->stats.rx_frame_errors++;
886 if (frame_status & RxFIFOOverrun)
887 np->stats.rx_fifo_errors++;
888 } else {
889 struct sk_buff *skb;
890
891 /* Small skbuffs for short packets */
892 if (pkt_len > copy_thresh) {
893 pci_unmap_single (np->pdev, desc->fraginfo,
894 np->rx_buf_sz,
895 PCI_DMA_FROMDEVICE);
896 skb_put (skb = np->rx_skbuff[entry], pkt_len);
897 np->rx_skbuff[entry] = NULL;
898 } else if ((skb = dev_alloc_skb (pkt_len + 2)) != NULL) {
899 pci_dma_sync_single_for_cpu(np->pdev,
900 desc->fraginfo,
901 np->rx_buf_sz,
902 PCI_DMA_FROMDEVICE);
903 skb->dev = dev;
904 /* 16 byte align the IP header */
905 skb_reserve (skb, 2);
906 eth_copy_and_sum (skb,
907 np->rx_skbuff[entry]->tail,
908 pkt_len, 0);
909 skb_put (skb, pkt_len);
910 pci_dma_sync_single_for_device(np->pdev,
911 desc->fraginfo,
912 np->rx_buf_sz,
913 PCI_DMA_FROMDEVICE);
914 }
915 skb->protocol = eth_type_trans (skb, dev);
916 #if 0
917 /* Checksum done by hw, but csum value unavailable. */
918 if (np->pci_rev_id >= 0x0c &&
919 !(frame_status & (TCPError | UDPError | IPError))) {
920 skb->ip_summed = CHECKSUM_UNNECESSARY;
921 }
922 #endif
923 netif_rx (skb);
924 dev->last_rx = jiffies;
925 }
926 entry = (entry + 1) % RX_RING_SIZE;
927 }
928 spin_lock(&np->rx_lock);
929 np->cur_rx = entry;
930 /* Re-allocate skbuffs to fill the descriptor ring */
931 entry = np->old_rx;
932 while (entry != np->cur_rx) {
933 struct sk_buff *skb;
934 /* Dropped packets don't need to re-allocate */
935 if (np->rx_skbuff[entry] == NULL) {
936 skb = dev_alloc_skb (np->rx_buf_sz);
937 if (skb == NULL) {
938 np->rx_ring[entry].fraginfo = 0;
939 printk (KERN_INFO
940 "%s: receive_packet: "
941 "Unable to re-allocate Rx skbuff.#%d\n",
942 dev->name, entry);
943 break;
944 }
945 np->rx_skbuff[entry] = skb;
946 skb->dev = dev;
947 /* 16 byte align the IP header */
948 skb_reserve (skb, 2);
949 np->rx_ring[entry].fraginfo =
950 cpu_to_le64 (pci_map_single
951 (np->pdev, skb->tail, np->rx_buf_sz,
952 PCI_DMA_FROMDEVICE));
953 }
954 np->rx_ring[entry].fraginfo |=
955 cpu_to_le64 (np->rx_buf_sz) << 48;
956 np->rx_ring[entry].status = 0;
957 entry = (entry + 1) % RX_RING_SIZE;
958 }
959 np->old_rx = entry;
960 spin_unlock(&np->rx_lock);
961 return 0;
962 }
963
964 static void
965 rio_error (struct net_device *dev, int int_status)
966 {
967 long ioaddr = dev->base_addr;
968 struct netdev_private *np = dev->priv;
969 u16 macctrl;
970
971 /* Link change event */
972 if (int_status & LinkEvent) {
973 if (mii_wait_link (dev, 10) == 0) {
974 printk (KERN_INFO "%s: Link up\n", dev->name);
975 if (np->phy_media)
976 mii_get_media_pcs (dev);
977 else
978 mii_get_media (dev);
979 if (np->speed == 1000)
980 np->tx_coalesce = tx_coalesce;
981 else
982 np->tx_coalesce = 1;
983 macctrl = 0;
984 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
985 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
986 macctrl |= (np->tx_flow) ?
987 TxFlowControlEnable : 0;
988 macctrl |= (np->rx_flow) ?
989 RxFlowControlEnable : 0;
990 writew(macctrl, ioaddr + MACCtrl);
991 np->link_status = 1;
992 netif_carrier_on(dev);
993 } else {
994 printk (KERN_INFO "%s: Link off\n", dev->name);
995 np->link_status = 0;
996 netif_carrier_off(dev);
997 }
998 }
999
1000 /* UpdateStats statistics registers */
1001 if (int_status & UpdateStats) {
1002 get_stats (dev);
1003 }
1004
1005 /* PCI Error, a catastronphic error related to the bus interface
1006 occurs, set GlobalReset and HostReset to reset. */
1007 if (int_status & HostError) {
1008 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
1009 dev->name, int_status);
1010 writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
1011 mdelay (500);
1012 }
1013 }
1014
1015 static struct net_device_stats *
1016 get_stats (struct net_device *dev)
1017 {
1018 long ioaddr = dev->base_addr;
1019 struct netdev_private *np = dev->priv;
1020 #ifdef MEM_MAPPING
1021 int i;
1022 #endif
1023 unsigned int stat_reg;
1024
1025 /* All statistics registers need to be acknowledged,
1026 else statistic overflow could cause problems */
1027
1028 np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
1029 np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
1030 np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
1031 np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
1032
1033 np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
1034 np->stats.collisions += readl (ioaddr + SingleColFrames)
1035 + readl (ioaddr + MultiColFrames);
1036
1037 /* detailed tx errors */
1038 stat_reg = readw (ioaddr + FramesAbortXSColls);
1039 np->stats.tx_aborted_errors += stat_reg;
1040 np->stats.tx_errors += stat_reg;
1041
1042 stat_reg = readw (ioaddr + CarrierSenseErrors);
1043 np->stats.tx_carrier_errors += stat_reg;
1044 np->stats.tx_errors += stat_reg;
1045
1046 /* Clear all other statistic register. */
1047 readl (ioaddr + McstOctetXmtOk);
1048 readw (ioaddr + BcstFramesXmtdOk);
1049 readl (ioaddr + McstFramesXmtdOk);
1050 readw (ioaddr + BcstFramesRcvdOk);
1051 readw (ioaddr + MacControlFramesRcvd);
1052 readw (ioaddr + FrameTooLongErrors);
1053 readw (ioaddr + InRangeLengthErrors);
1054 readw (ioaddr + FramesCheckSeqErrors);
1055 readw (ioaddr + FramesLostRxErrors);
1056 readl (ioaddr + McstOctetXmtOk);
1057 readl (ioaddr + BcstOctetXmtOk);
1058 readl (ioaddr + McstFramesXmtdOk);
1059 readl (ioaddr + FramesWDeferredXmt);
1060 readl (ioaddr + LateCollisions);
1061 readw (ioaddr + BcstFramesXmtdOk);
1062 readw (ioaddr + MacControlFramesXmtd);
1063 readw (ioaddr + FramesWEXDeferal);
1064
1065 #ifdef MEM_MAPPING
1066 for (i = 0x100; i <= 0x150; i += 4)
1067 readl (ioaddr + i);
1068 #endif
1069 readw (ioaddr + TxJumboFrames);
1070 readw (ioaddr + RxJumboFrames);
1071 readw (ioaddr + TCPCheckSumErrors);
1072 readw (ioaddr + UDPCheckSumErrors);
1073 readw (ioaddr + IPCheckSumErrors);
1074 return &np->stats;
1075 }
1076
1077 static int
1078 clear_stats (struct net_device *dev)
1079 {
1080 long ioaddr = dev->base_addr;
1081 #ifdef MEM_MAPPING
1082 int i;
1083 #endif
1084
1085 /* All statistics registers need to be acknowledged,
1086 else statistic overflow could cause problems */
1087 readl (ioaddr + FramesRcvOk);
1088 readl (ioaddr + FramesXmtOk);
1089 readl (ioaddr + OctetRcvOk);
1090 readl (ioaddr + OctetXmtOk);
1091
1092 readl (ioaddr + McstFramesRcvdOk);
1093 readl (ioaddr + SingleColFrames);
1094 readl (ioaddr + MultiColFrames);
1095 readl (ioaddr + LateCollisions);
1096 /* detailed rx errors */
1097 readw (ioaddr + FrameTooLongErrors);
1098 readw (ioaddr + InRangeLengthErrors);
1099 readw (ioaddr + FramesCheckSeqErrors);
1100 readw (ioaddr + FramesLostRxErrors);
1101
1102 /* detailed tx errors */
1103 readw (ioaddr + FramesAbortXSColls);
1104 readw (ioaddr + CarrierSenseErrors);
1105
1106 /* Clear all other statistic register. */
1107 readl (ioaddr + McstOctetXmtOk);
1108 readw (ioaddr + BcstFramesXmtdOk);
1109 readl (ioaddr + McstFramesXmtdOk);
1110 readw (ioaddr + BcstFramesRcvdOk);
1111 readw (ioaddr + MacControlFramesRcvd);
1112 readl (ioaddr + McstOctetXmtOk);
1113 readl (ioaddr + BcstOctetXmtOk);
1114 readl (ioaddr + McstFramesXmtdOk);
1115 readl (ioaddr + FramesWDeferredXmt);
1116 readw (ioaddr + BcstFramesXmtdOk);
1117 readw (ioaddr + MacControlFramesXmtd);
1118 readw (ioaddr + FramesWEXDeferal);
1119 #ifdef MEM_MAPPING
1120 for (i = 0x100; i <= 0x150; i += 4)
1121 readl (ioaddr + i);
1122 #endif
1123 readw (ioaddr + TxJumboFrames);
1124 readw (ioaddr + RxJumboFrames);
1125 readw (ioaddr + TCPCheckSumErrors);
1126 readw (ioaddr + UDPCheckSumErrors);
1127 readw (ioaddr + IPCheckSumErrors);
1128 return 0;
1129 }
1130
1131
1132 int
1133 change_mtu (struct net_device *dev, int new_mtu)
1134 {
1135 struct netdev_private *np = dev->priv;
1136 int max = (np->jumbo) ? MAX_JUMBO : 1536;
1137
1138 if ((new_mtu < 68) || (new_mtu > max)) {
1139 return -EINVAL;
1140 }
1141
1142 dev->mtu = new_mtu;
1143
1144 return 0;
1145 }
1146
1147 static void
1148 set_multicast (struct net_device *dev)
1149 {
1150 long ioaddr = dev->base_addr;
1151 u32 hash_table[2];
1152 u16 rx_mode = 0;
1153 struct netdev_private *np = dev->priv;
1154
1155 hash_table[0] = hash_table[1] = 0;
1156 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1157 hash_table[1] |= cpu_to_le32(0x02000000);
1158 if (dev->flags & IFF_PROMISC) {
1159 /* Receive all frames promiscuously. */
1160 rx_mode = ReceiveAllFrames;
1161 } else if ((dev->flags & IFF_ALLMULTI) ||
1162 (dev->mc_count > multicast_filter_limit)) {
1163 /* Receive broadcast and multicast frames */
1164 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1165 } else if (dev->mc_count > 0) {
1166 int i;
1167 struct dev_mc_list *mclist;
1168 /* Receive broadcast frames and multicast frames filtering
1169 by Hashtable */
1170 rx_mode =
1171 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1172 for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1173 i++, mclist=mclist->next)
1174 {
1175 int bit, index = 0;
1176 int crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1177 /* The inverted high significant 6 bits of CRC are
1178 used as an index to hashtable */
1179 for (bit = 0; bit < 6; bit++)
1180 if (crc & (1 << (31 - bit)))
1181 index |= (1 << bit);
1182 hash_table[index / 32] |= (1 << (index % 32));
1183 }
1184 } else {
1185 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1186 }
1187 if (np->vlan) {
1188 /* ReceiveVLANMatch field in ReceiveMode */
1189 rx_mode |= ReceiveVLANMatch;
1190 }
1191
1192 writel (hash_table[0], ioaddr + HashTable0);
1193 writel (hash_table[1], ioaddr + HashTable1);
1194 writew (rx_mode, ioaddr + ReceiveMode);
1195 }
1196
1197 static int
1198 rio_ethtool_ioctl (struct net_device *dev, void __user *useraddr)
1199 {
1200 struct netdev_private *np = dev->priv;
1201 u32 ethcmd;
1202
1203 if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
1204 return -EFAULT;
1205 switch (ethcmd) {
1206 case ETHTOOL_GDRVINFO: {
1207 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
1208 strcpy(info.driver, "DL2K");
1209 strcpy(info.version, DRV_VERSION);
1210 strcpy(info.bus_info, pci_name(np->pdev));
1211 memset(&info.fw_version, 0, sizeof(info.fw_version));
1212 if (copy_to_user(useraddr, &info, sizeof(info)))
1213 return -EFAULT;
1214 return 0;
1215 }
1216
1217 case ETHTOOL_GSET: {
1218 struct ethtool_cmd cmd = { ETHTOOL_GSET };
1219 if (np->phy_media) {
1220 /* fiber device */
1221 cmd.supported = SUPPORTED_Autoneg |
1222 SUPPORTED_FIBRE;
1223 cmd.advertising= ADVERTISED_Autoneg |
1224 ADVERTISED_FIBRE;
1225 cmd.port = PORT_FIBRE;
1226 cmd.transceiver = XCVR_INTERNAL;
1227 } else {
1228 /* copper device */
1229 cmd.supported = SUPPORTED_10baseT_Half |
1230 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1231 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1232 SUPPORTED_Autoneg | SUPPORTED_MII;
1233 cmd.advertising = ADVERTISED_10baseT_Half |
1234 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1235 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
1236 ADVERTISED_Autoneg | ADVERTISED_MII;
1237 cmd.port = PORT_MII;
1238 cmd.transceiver = XCVR_INTERNAL;
1239 }
1240 if ( np->link_status ) {
1241 cmd.speed = np->speed;
1242 cmd.duplex = np->full_duplex ?
1243 DUPLEX_FULL : DUPLEX_HALF;
1244 } else {
1245 cmd.speed = -1;
1246 cmd.duplex = -1;
1247 }
1248 if ( np->an_enable)
1249 cmd.autoneg = AUTONEG_ENABLE;
1250 else
1251 cmd.autoneg = AUTONEG_DISABLE;
1252
1253 cmd.phy_address = np->phy_addr;
1254
1255 if (copy_to_user(useraddr, &cmd,
1256 sizeof(cmd)))
1257 return -EFAULT;
1258 return 0;
1259 }
1260 case ETHTOOL_SSET: {
1261 struct ethtool_cmd cmd;
1262 if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
1263 return -EFAULT;
1264 netif_carrier_off(dev);
1265 if (cmd.autoneg == AUTONEG_ENABLE) {
1266 if (np->an_enable)
1267 return 0;
1268 else {
1269 np->an_enable = 1;
1270 mii_set_media(dev);
1271 return 0;
1272 }
1273 } else {
1274 np->an_enable = 0;
1275 if (np->speed == 1000){
1276 cmd.speed = SPEED_100;
1277 cmd.duplex = DUPLEX_FULL;
1278 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manul 100Mbps, Full duplex.\n");
1279 }
1280 switch(cmd.speed + cmd.duplex){
1281
1282 case SPEED_10 + DUPLEX_HALF:
1283 np->speed = 10;
1284 np->full_duplex = 0;
1285 break;
1286
1287 case SPEED_10 + DUPLEX_FULL:
1288 np->speed = 10;
1289 np->full_duplex = 1;
1290 break;
1291 case SPEED_100 + DUPLEX_HALF:
1292 np->speed = 100;
1293 np->full_duplex = 0;
1294 break;
1295 case SPEED_100 + DUPLEX_FULL:
1296 np->speed = 100;
1297 np->full_duplex = 1;
1298 break;
1299 case SPEED_1000 + DUPLEX_HALF:/* not supported */
1300 case SPEED_1000 + DUPLEX_FULL:/* not supported */
1301 default:
1302 return -EINVAL;
1303 }
1304 mii_set_media(dev);
1305 }
1306 return 0;
1307 }
1308 #ifdef ETHTOOL_GLINK
1309 case ETHTOOL_GLINK:{
1310 struct ethtool_value link = { ETHTOOL_GLINK };
1311 link.data = np->link_status;
1312 if (copy_to_user(useraddr, &link, sizeof(link)))
1313 return -EFAULT;
1314 return 0;
1315 }
1316 #endif
1317 default:
1318 return -EOPNOTSUPP;
1319 }
1320 }
1321
1322
1323 static int
1324 rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1325 {
1326 int phy_addr;
1327 struct netdev_private *np = dev->priv;
1328 struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru;
1329
1330 struct netdev_desc *desc;
1331 int i;
1332
1333 phy_addr = np->phy_addr;
1334 switch (cmd) {
1335 case SIOCETHTOOL:
1336 return rio_ethtool_ioctl(dev, rq->ifr_data);
1337 case SIOCDEVPRIVATE:
1338 break;
1339
1340 case SIOCDEVPRIVATE + 1:
1341 miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
1342 break;
1343 case SIOCDEVPRIVATE + 2:
1344 mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
1345 break;
1346 case SIOCDEVPRIVATE + 3:
1347 break;
1348 case SIOCDEVPRIVATE + 4:
1349 break;
1350 case SIOCDEVPRIVATE + 5:
1351 netif_stop_queue (dev);
1352 break;
1353 case SIOCDEVPRIVATE + 6:
1354 netif_wake_queue (dev);
1355 break;
1356 case SIOCDEVPRIVATE + 7:
1357 printk
1358 ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
1359 netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
1360 np->old_rx);
1361 break;
1362 case SIOCDEVPRIVATE + 8:
1363 printk("TX ring:\n");
1364 for (i = 0; i < TX_RING_SIZE; i++) {
1365 desc = &np->tx_ring[i];
1366 printk
1367 ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
1368 i,
1369 (u32) (np->tx_ring_dma + i * sizeof (*desc)),
1370 (u32) desc->next_desc,
1371 (u32) desc->status, (u32) (desc->fraginfo >> 32),
1372 (u32) desc->fraginfo);
1373 printk ("\n");
1374 }
1375 printk ("\n");
1376 break;
1377
1378 default:
1379 return -EOPNOTSUPP;
1380 }
1381 return 0;
1382 }
1383
1384 #define EEP_READ 0x0200
1385 #define EEP_BUSY 0x8000
1386 /* Read the EEPROM word */
1387 /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
1388 int
1389 read_eeprom (long ioaddr, int eep_addr)
1390 {
1391 int i = 1000;
1392 outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
1393 while (i-- > 0) {
1394 if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
1395 return inw (ioaddr + EepromData);
1396 }
1397 }
1398 return 0;
1399 }
1400
1401 enum phy_ctrl_bits {
1402 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1403 MII_DUPLEX = 0x08,
1404 };
1405
1406 #define mii_delay() readb(ioaddr)
1407 static void
1408 mii_sendbit (struct net_device *dev, u32 data)
1409 {
1410 long ioaddr = dev->base_addr + PhyCtrl;
1411 data = (data) ? MII_DATA1 : 0;
1412 data |= MII_WRITE;
1413 data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
1414 writeb (data, ioaddr);
1415 mii_delay ();
1416 writeb (data | MII_CLK, ioaddr);
1417 mii_delay ();
1418 }
1419
1420 static int
1421 mii_getbit (struct net_device *dev)
1422 {
1423 long ioaddr = dev->base_addr + PhyCtrl;
1424 u8 data;
1425
1426 data = (readb (ioaddr) & 0xf8) | MII_READ;
1427 writeb (data, ioaddr);
1428 mii_delay ();
1429 writeb (data | MII_CLK, ioaddr);
1430 mii_delay ();
1431 return ((readb (ioaddr) >> 1) & 1);
1432 }
1433
1434 static void
1435 mii_send_bits (struct net_device *dev, u32 data, int len)
1436 {
1437 int i;
1438 for (i = len - 1; i >= 0; i--) {
1439 mii_sendbit (dev, data & (1 << i));
1440 }
1441 }
1442
1443 static int
1444 mii_read (struct net_device *dev, int phy_addr, int reg_num)
1445 {
1446 u32 cmd;
1447 int i;
1448 u32 retval = 0;
1449
1450 /* Preamble */
1451 mii_send_bits (dev, 0xffffffff, 32);
1452 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1453 /* ST,OP = 0110'b for read operation */
1454 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1455 mii_send_bits (dev, cmd, 14);
1456 /* Turnaround */
1457 if (mii_getbit (dev))
1458 goto err_out;
1459 /* Read data */
1460 for (i = 0; i < 16; i++) {
1461 retval |= mii_getbit (dev);
1462 retval <<= 1;
1463 }
1464 /* End cycle */
1465 mii_getbit (dev);
1466 return (retval >> 1) & 0xffff;
1467
1468 err_out:
1469 return 0;
1470 }
1471 static int
1472 mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1473 {
1474 u32 cmd;
1475
1476 /* Preamble */
1477 mii_send_bits (dev, 0xffffffff, 32);
1478 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1479 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1480 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1481 mii_send_bits (dev, cmd, 32);
1482 /* End cycle */
1483 mii_getbit (dev);
1484 return 0;
1485 }
1486 static int
1487 mii_wait_link (struct net_device *dev, int wait)
1488 {
1489 BMSR_t bmsr;
1490 int phy_addr;
1491 struct netdev_private *np;
1492
1493 np = dev->priv;
1494 phy_addr = np->phy_addr;
1495
1496 do {
1497 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1498 if (bmsr.bits.link_status)
1499 return 0;
1500 mdelay (1);
1501 } while (--wait > 0);
1502 return -1;
1503 }
1504 static int
1505 mii_get_media (struct net_device *dev)
1506 {
1507 ANAR_t negotiate;
1508 BMSR_t bmsr;
1509 BMCR_t bmcr;
1510 MSCR_t mscr;
1511 MSSR_t mssr;
1512 int phy_addr;
1513 struct netdev_private *np;
1514
1515 np = dev->priv;
1516 phy_addr = np->phy_addr;
1517
1518 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1519 if (np->an_enable) {
1520 if (!bmsr.bits.an_complete) {
1521 /* Auto-Negotiation not completed */
1522 return -1;
1523 }
1524 negotiate.image = mii_read (dev, phy_addr, MII_ANAR) &
1525 mii_read (dev, phy_addr, MII_ANLPAR);
1526 mscr.image = mii_read (dev, phy_addr, MII_MSCR);
1527 mssr.image = mii_read (dev, phy_addr, MII_MSSR);
1528 if (mscr.bits.media_1000BT_FD & mssr.bits.lp_1000BT_FD) {
1529 np->speed = 1000;
1530 np->full_duplex = 1;
1531 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1532 } else if (mscr.bits.media_1000BT_HD & mssr.bits.lp_1000BT_HD) {
1533 np->speed = 1000;
1534 np->full_duplex = 0;
1535 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1536 } else if (negotiate.bits.media_100BX_FD) {
1537 np->speed = 100;
1538 np->full_duplex = 1;
1539 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1540 } else if (negotiate.bits.media_100BX_HD) {
1541 np->speed = 100;
1542 np->full_duplex = 0;
1543 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1544 } else if (negotiate.bits.media_10BT_FD) {
1545 np->speed = 10;
1546 np->full_duplex = 1;
1547 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1548 } else if (negotiate.bits.media_10BT_HD) {
1549 np->speed = 10;
1550 np->full_duplex = 0;
1551 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1552 }
1553 if (negotiate.bits.pause) {
1554 np->tx_flow &= 1;
1555 np->rx_flow &= 1;
1556 } else if (negotiate.bits.asymmetric) {
1557 np->tx_flow = 0;
1558 np->rx_flow &= 1;
1559 }
1560 /* else tx_flow, rx_flow = user select */
1561 } else {
1562 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1563 if (bmcr.bits.speed100 == 1 && bmcr.bits.speed1000 == 0) {
1564 printk (KERN_INFO "Operating at 100 Mbps, ");
1565 } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 0) {
1566 printk (KERN_INFO "Operating at 10 Mbps, ");
1567 } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 1) {
1568 printk (KERN_INFO "Operating at 1000 Mbps, ");
1569 }
1570 if (bmcr.bits.duplex_mode) {
1571 printk ("Full duplex\n");
1572 } else {
1573 printk ("Half duplex\n");
1574 }
1575 }
1576 if (np->tx_flow)
1577 printk(KERN_INFO "Enable Tx Flow Control\n");
1578 else
1579 printk(KERN_INFO "Disable Tx Flow Control\n");
1580 if (np->rx_flow)
1581 printk(KERN_INFO "Enable Rx Flow Control\n");
1582 else
1583 printk(KERN_INFO "Disable Rx Flow Control\n");
1584
1585 return 0;
1586 }
1587
1588 static int
1589 mii_set_media (struct net_device *dev)
1590 {
1591 PHY_SCR_t pscr;
1592 BMCR_t bmcr;
1593 BMSR_t bmsr;
1594 ANAR_t anar;
1595 int phy_addr;
1596 struct netdev_private *np;
1597 np = dev->priv;
1598 phy_addr = np->phy_addr;
1599
1600 /* Does user set speed? */
1601 if (np->an_enable) {
1602 /* Advertise capabilities */
1603 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1604 anar.image = mii_read (dev, phy_addr, MII_ANAR);
1605 anar.bits.media_100BX_FD = bmsr.bits.media_100BX_FD;
1606 anar.bits.media_100BX_HD = bmsr.bits.media_100BX_HD;
1607 anar.bits.media_100BT4 = bmsr.bits.media_100BT4;
1608 anar.bits.media_10BT_FD = bmsr.bits.media_10BT_FD;
1609 anar.bits.media_10BT_HD = bmsr.bits.media_10BT_HD;
1610 anar.bits.pause = 1;
1611 anar.bits.asymmetric = 1;
1612 mii_write (dev, phy_addr, MII_ANAR, anar.image);
1613
1614 /* Enable Auto crossover */
1615 pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
1616 pscr.bits.mdi_crossover_mode = 3; /* 11'b */
1617 mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
1618
1619 /* Soft reset PHY */
1620 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1621 bmcr.image = 0;
1622 bmcr.bits.an_enable = 1;
1623 bmcr.bits.restart_an = 1;
1624 bmcr.bits.reset = 1;
1625 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1626 mdelay(1);
1627 } else {
1628 /* Force speed setting */
1629 /* 1) Disable Auto crossover */
1630 pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
1631 pscr.bits.mdi_crossover_mode = 0;
1632 mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
1633
1634 /* 2) PHY Reset */
1635 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1636 bmcr.bits.reset = 1;
1637 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1638
1639 /* 3) Power Down */
1640 bmcr.image = 0x1940; /* must be 0x1940 */
1641 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1642 mdelay (100); /* wait a certain time */
1643
1644 /* 4) Advertise nothing */
1645 mii_write (dev, phy_addr, MII_ANAR, 0);
1646
1647 /* 5) Set media and Power Up */
1648 bmcr.image = 0;
1649 bmcr.bits.power_down = 1;
1650 if (np->speed == 100) {
1651 bmcr.bits.speed100 = 1;
1652 bmcr.bits.speed1000 = 0;
1653 printk (KERN_INFO "Manual 100 Mbps, ");
1654 } else if (np->speed == 10) {
1655 bmcr.bits.speed100 = 0;
1656 bmcr.bits.speed1000 = 0;
1657 printk (KERN_INFO "Manual 10 Mbps, ");
1658 }
1659 if (np->full_duplex) {
1660 bmcr.bits.duplex_mode = 1;
1661 printk ("Full duplex\n");
1662 } else {
1663 bmcr.bits.duplex_mode = 0;
1664 printk ("Half duplex\n");
1665 }
1666 #if 0
1667 /* Set 1000BaseT Master/Slave setting */
1668 mscr.image = mii_read (dev, phy_addr, MII_MSCR);
1669 mscr.bits.cfg_enable = 1;
1670 mscr.bits.cfg_value = 0;
1671 #endif
1672 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1673 mdelay(10);
1674 }
1675 return 0;
1676 }
1677
1678 static int
1679 mii_get_media_pcs (struct net_device *dev)
1680 {
1681 ANAR_PCS_t negotiate;
1682 BMSR_t bmsr;
1683 BMCR_t bmcr;
1684 int phy_addr;
1685 struct netdev_private *np;
1686
1687 np = dev->priv;
1688 phy_addr = np->phy_addr;
1689
1690 bmsr.image = mii_read (dev, phy_addr, PCS_BMSR);
1691 if (np->an_enable) {
1692 if (!bmsr.bits.an_complete) {
1693 /* Auto-Negotiation not completed */
1694 return -1;
1695 }
1696 negotiate.image = mii_read (dev, phy_addr, PCS_ANAR) &
1697 mii_read (dev, phy_addr, PCS_ANLPAR);
1698 np->speed = 1000;
1699 if (negotiate.bits.full_duplex) {
1700 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1701 np->full_duplex = 1;
1702 } else {
1703 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1704 np->full_duplex = 0;
1705 }
1706 if (negotiate.bits.pause) {
1707 np->tx_flow &= 1;
1708 np->rx_flow &= 1;
1709 } else if (negotiate.bits.asymmetric) {
1710 np->tx_flow = 0;
1711 np->rx_flow &= 1;
1712 }
1713 /* else tx_flow, rx_flow = user select */
1714 } else {
1715 bmcr.image = mii_read (dev, phy_addr, PCS_BMCR);
1716 printk (KERN_INFO "Operating at 1000 Mbps, ");
1717 if (bmcr.bits.duplex_mode) {
1718 printk ("Full duplex\n");
1719 } else {
1720 printk ("Half duplex\n");
1721 }
1722 }
1723 if (np->tx_flow)
1724 printk(KERN_INFO "Enable Tx Flow Control\n");
1725 else
1726 printk(KERN_INFO "Disable Tx Flow Control\n");
1727 if (np->rx_flow)
1728 printk(KERN_INFO "Enable Rx Flow Control\n");
1729 else
1730 printk(KERN_INFO "Disable Rx Flow Control\n");
1731
1732 return 0;
1733 }
1734
1735 static int
1736 mii_set_media_pcs (struct net_device *dev)
1737 {
1738 BMCR_t bmcr;
1739 ESR_t esr;
1740 ANAR_PCS_t anar;
1741 int phy_addr;
1742 struct netdev_private *np;
1743 np = dev->priv;
1744 phy_addr = np->phy_addr;
1745
1746 /* Auto-Negotiation? */
1747 if (np->an_enable) {
1748 /* Advertise capabilities */
1749 esr.image = mii_read (dev, phy_addr, PCS_ESR);
1750 anar.image = mii_read (dev, phy_addr, MII_ANAR);
1751 anar.bits.half_duplex =
1752 esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD;
1753 anar.bits.full_duplex =
1754 esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD;
1755 anar.bits.pause = 1;
1756 anar.bits.asymmetric = 1;
1757 mii_write (dev, phy_addr, MII_ANAR, anar.image);
1758
1759 /* Soft reset PHY */
1760 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1761 bmcr.image = 0;
1762 bmcr.bits.an_enable = 1;
1763 bmcr.bits.restart_an = 1;
1764 bmcr.bits.reset = 1;
1765 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1766 mdelay(1);
1767 } else {
1768 /* Force speed setting */
1769 /* PHY Reset */
1770 bmcr.image = 0;
1771 bmcr.bits.reset = 1;
1772 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1773 mdelay(10);
1774 bmcr.image = 0;
1775 bmcr.bits.an_enable = 0;
1776 if (np->full_duplex) {
1777 bmcr.bits.duplex_mode = 1;
1778 printk (KERN_INFO "Manual full duplex\n");
1779 } else {
1780 bmcr.bits.duplex_mode = 0;
1781 printk (KERN_INFO "Manual half duplex\n");
1782 }
1783 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1784 mdelay(10);
1785
1786 /* Advertise nothing */
1787 mii_write (dev, phy_addr, MII_ANAR, 0);
1788 }
1789 return 0;
1790 }
1791
1792
1793 static int
1794 rio_close (struct net_device *dev)
1795 {
1796 long ioaddr = dev->base_addr;
1797 struct netdev_private *np = dev->priv;
1798 struct sk_buff *skb;
1799 int i;
1800
1801 netif_stop_queue (dev);
1802
1803 /* Disable interrupts */
1804 writew (0, ioaddr + IntEnable);
1805
1806 /* Stop Tx and Rx logics */
1807 writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
1808 synchronize_irq (dev->irq);
1809 free_irq (dev->irq, dev);
1810 del_timer_sync (&np->timer);
1811
1812 /* Free all the skbuffs in the queue. */
1813 for (i = 0; i < RX_RING_SIZE; i++) {
1814 np->rx_ring[i].status = 0;
1815 np->rx_ring[i].fraginfo = 0;
1816 skb = np->rx_skbuff[i];
1817 if (skb) {
1818 pci_unmap_single (np->pdev, np->rx_ring[i].fraginfo,
1819 skb->len, PCI_DMA_FROMDEVICE);
1820 dev_kfree_skb (skb);
1821 np->rx_skbuff[i] = NULL;
1822 }
1823 }
1824 for (i = 0; i < TX_RING_SIZE; i++) {
1825 skb = np->tx_skbuff[i];
1826 if (skb) {
1827 pci_unmap_single (np->pdev, np->tx_ring[i].fraginfo,
1828 skb->len, PCI_DMA_TODEVICE);
1829 dev_kfree_skb (skb);
1830 np->tx_skbuff[i] = NULL;
1831 }
1832 }
1833
1834 return 0;
1835 }
1836
1837 static void __devexit
1838 rio_remove1 (struct pci_dev *pdev)
1839 {
1840 struct net_device *dev = pci_get_drvdata (pdev);
1841
1842 if (dev) {
1843 struct netdev_private *np = dev->priv;
1844
1845 unregister_netdev (dev);
1846 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
1847 np->rx_ring_dma);
1848 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
1849 np->tx_ring_dma);
1850 #ifdef MEM_MAPPING
1851 iounmap ((char *) (dev->base_addr));
1852 #endif
1853 free_netdev (dev);
1854 pci_release_regions (pdev);
1855 pci_disable_device (pdev);
1856 }
1857 pci_set_drvdata (pdev, NULL);
1858 }
1859
1860 static struct pci_driver rio_driver = {
1861 .name = "dl2k",
1862 .id_table = rio_pci_tbl,
1863 .probe = rio_probe1,
1864 .remove = __devexit_p(rio_remove1),
1865 };
1866
1867 static int __init
1868 rio_init (void)
1869 {
1870 return pci_module_init (&rio_driver);
1871 }
1872
1873 static void __exit
1874 rio_exit (void)
1875 {
1876 pci_unregister_driver (&rio_driver);
1877 }
1878
1879 module_init (rio_init);
1880 module_exit (rio_exit);
1881
1882 /*
1883
1884 Compile command:
1885
1886 gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
1887
1888 Read Documentation/networking/dl2k.txt for details.
1889
1890 */
1891
MOXA 2.6.9 from sdlinux-moxaart.tgz