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[linux-2.6.9-moxart.git] / drivers / net / arm / eth_s3c4510b.h
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1 #ifndef __ETH_S3C4510B_H
2 #define __ETH_S3C4510B_H
4 /*
5 * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
6 * Curt Brune <curt@cucy.com>
8 * See file CREDITS for list of people who contributed to this
9 * project.
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
26 * Description: Ethernet interface
27 * Runtime Env: ARM7TDMI
28 * Change History:
29 * 03-02-04 Create (Curt Brune) curt@cucy.com
33 #define __packed __attribute__ ((packed))
35 #define ETH_NTxFrames (16) /* Max number of Tx Frames */
36 #define ETH_NRxFrames (16) /* Max number of Rx Frames */
38 /* Buffered DMA Receiver Control Register */
39 #define ETH_BRxBRST 0x0000F /* BDMA Rx Burst Size * BRxBRST */
40 /* = Burst Data Size 16 */
41 #define ETH_BRxSTSKO 0x00020 /* BDMA Rx Stop/Skip Frame or Interrupt(=1) */
42 /* case of not OWNER the current Frame */
43 #define ETH_BRxMAINC 0x00040 /* BDMA Rx Memory Address Inc/Dec */
44 #define ETH_BRxDIE 0x00080 /* BDMA Rx Every Received Frame Interrupt Enable */
45 #define ETH_BRxNLIE 0x00100 /* BDMA Rx NULL List Interrupt Enable */
46 #define ETH_BRxNOIE 0x00200 /* BDMA Rx Not Owner Interrupt Enable */
47 #define ETH_BRxMSOIE 0x00400 /* BDMA Rx Maximum Size over Interrupr Enable */
48 #define ETH_BRxLittle 0x00800 /* BDMA Rx Big/Little Endian */
49 #define ETH_BRxBig 0x00000 /* BDMA Rx Big/Little Endian */
50 #define ETH_BRxWA01 0x01000 /* BDMA Rx Word Alignment- one invalid byte */
51 #define ETH_BRxWA10 0x02000 /* BDMA Rx Word Alignment- two invalid bytes */
52 #define ETH_BRxWA11 0x03000 /* BDMA Rx Word Alignment- three invalid bytes */
53 #define ETH_BRxEn 0x04000 /* BDMA Rx Enable */
54 #define ETH_BRxRS 0x08000 /* BDMA Rx Reset */
55 #define ETH_RxEmpty 0x10000 /* BDMA Rx Buffer empty interrupt */
56 #define ETH_BRxEarly 0x20000 /* BDMA Rx Early notify Interrupt */
58 /* Buffered DMA Trasmit Control Register(BDMATXCON) */
59 #define ETH_BTxBRST 0x0000F /* BDMA Tx Burst Size = 16 */
60 #define ETH_BTxSTSKO 0x00020 /* BDMA Tx Stop/Skip Frame or Interrupt in case */
61 /* of not Owner the current frame */
62 #define ETH_BTxCPIE 0x00080 /* BDMA Tx Complete to send control */
63 /* packet Enable */
64 #define ETH_BTxNOIE 0x00200 /* BDMA Tx Buffer Not Owner */
65 #define ETH_BTxEmpty 0x00400 /* BDMA Tx Buffer Empty Interrupt */
67 /* BDMA Tx buffer can be moved to the MAC Tx IO when the new frame comes in. */
68 #define ETH_BTxMSL000 0x00000 /* No wait to fill the BDMA */
69 #define ETH_BTxMSL001 0x00800 /* wait to fill 1/8 of the BDMA */
70 #define ETH_BTxMSL010 0x01000 /* wait to fill 2/8 of the BDMA */
71 #define ETH_BTxMSL011 0x01800 /* wait to fill 3/8 of the BDMA */
72 #define ETH_BTxMSL100 0x02000 /* wait to fill 4/8 of the BDMA */
73 #define ETH_BTxMSL101 0x02800 /* wait to fill 5/8 of the BDMA */
74 #define ETH_BTxMSL110 0x03000 /* wait to fill 6/8 of the BDMA */
75 #define ETH_BTxMSL111 0x03800 /* wait to fill 7/8 of the BDMA */
76 #define ETH_BTxEn 0x04000 /* BDMA Tx Enable */
77 #define ETH_BTxRS 0x08000 /* BDMA Tx Reset */
79 /* BDMA Status Register */
80 #define ETH_S_BRxRDF 0x00001 /* BDMA Rx Done Every Received Frame */
81 #define ETH_S_BRxNL 0x00002 /* BDMA Rx NULL List */
82 #define ETH_S_BRxNO 0x00004 /* BDMA Rx Not Owner */
83 #define ETH_S_BRxMSO 0x00008 /* BDMA Rx Maximum Size Over */
84 #define ETH_S_BRxEmpty 0x00010 /* BDMA Rx Buffer Empty */
85 #define ETH_S_BRxSEarly 0x00020 /* Early Notify */
86 #define ETH_S_BRxFRF 0x00080 /* One more frame data in BDMA receive buffer */
87 #define ETH_S_BTxCCP 0x10000 /* BDMA Tx Complete to send Control Packet */
88 #define ETH_S_BTxNL 0x20000 /* BDMA Tx Null List */
89 #define ETH_S_BTxNO 0x40000 /* BDMA Tx Not Owner */
90 #define ETH_S_BTxEmpty 0x100000 /* BDMA Tx Buffer Empty */
92 /* MAC Control Register */
93 #define ETH_HaltReg 0x0001 /* stop transmission and reception */
94 /* after completion of any current packets */
95 #define ETH_HaltImm 0x0002 /* Stop transmission and reception immediately */
96 #define ETH_SwReset 0x0004 /* reset all Ethernet controller state machines */
97 /* and FIFOs */
98 #define ETH_FullDup 0x0008 /* allow transmission to begin while reception */
99 /* is occurring */
100 #define ETH_MACLoop 0x0010 /* MAC loopback */
101 #define ETH_ConnM00 0x0000 /* Automatic-default */
102 #define ETH_ConnM01 0x0020 /* Force 10Mbits endec */
103 #define ETH_ConnM10 0x0040 /* Force MII (rate determined by MII clock */
104 #define ETH_MIIOFF 0x0040 /* Force MII (rate determined by MII clock */
105 #define ETH_Loop10 0x0080 /* Loop 10Mbps */
106 #define ETH_MissRoll 0x0400 /* Missed error counter rolled over */
107 #define ETH_MDCOFF 0x1000 /* MII Station Management Clock Off */
108 #define ETH_EnMissRoll 0x2000 /* Interrupt when missed error counter rolls */
109 /* over */
110 #define ETH_Link10 0x8000 /* Link status 10Mbps */
112 /* CAM control register(CAMCON) */
113 #define ETH_StationAcc 0x0001 /* Accept any packet with a unicast station */
114 /* address */
115 #define ETH_GroupAcc 0x0002 /* Accept any packet with multicast-group */
116 /* station address */
117 #define ETH_BroadAcc 0x0004 /* Accept any packet with a broadcast station */
118 /* address */
119 #define ETH_NegCAM 0x0008 /* 0: Accept packets CAM recognizes, */
120 /* reject others */
121 /* 1: reject packets CAM recognizes, */
122 /* accept others */
123 #define ETH_CompEn 0x0010 /* Compare Enable mode */
125 /* Transmit Control Register(MACTXCON) */
126 #define ETH_TxEn 0x0001 /* transmit Enable */
127 #define ETH_TxHalt 0x0002 /* Transmit Halt Request */
128 #define ETH_NoPad 0x0004 /* suppress Padding */
129 #define ETH_NoCRC 0x0008 /* Suppress CRC */
130 #define ETH_FBack 0x0010 /* Fast Back-off */
131 #define ETH_NoDef 0x0020 /* Disable the defer counter */
132 #define ETH_SdPause 0x0040 /* Send Pause */
133 #define ETH_MII10En 0x0080 /* MII 10Mbps mode enable */
134 #define ETH_EnUnder 0x0100 /* Enable Underrun */
135 #define ETH_EnDefer 0x0200 /* Enable Deferral */
136 #define ETH_EnNCarr 0x0400 /* Enable No Carrier */
137 #define ETH_EnExColl 0x0800 /* interrupt if 16 collision occur */
138 /* in the same packet */
139 #define ETH_EnLateColl 0x1000 /* interrupt if collision occurs after */
140 /* 512 bit times(64 bytes times) */
141 #define ETH_EnTxPar 0x2000 /* interrupt if the MAC transmit FIFO */
142 /* has a parity error */
143 #define ETH_EnComp 0x4000 /* interrupt when the MAC transmits or */
144 /* discards one packet */
146 /* Transmit Status Register(MACTXSTAT) */
147 #define ETH_ExColl 0x0010 /* Excessive collision */
148 #define ETH_TxDeffered 0x0020 /* set if 16 collisions occur for same packet */
149 #define ETH_Paused 0x0040 /* packet waited because of pause during */
150 /* transmission */
151 #define ETH_IntTx 0x0080 /* set if transmission of packet causes an */
152 /* interrupt condiftion */
153 #define ETH_Under 0x0100 /* MAC transmit FIFO becomes empty during */
154 /* transmission */
155 #define ETH_Defer 0x0200 /* MAC defers for MAC deferral */
156 #define ETH_NCarr 0x0400 /* No carrier sense detected during the */
157 /* transmission of a packet */
158 #define ETH_SQE 0x0800 /* Signal Quality Error */
159 #define ETH_LateColl 0x1000 /* a collision occures after 512 bit times */
160 #define ETH_TxPar 0x2000 /* MAC transmit FIFO has detected a parity error */
161 #define ETH_Comp 0x4000 /* MAC transmit or discards one packet */
162 #define ETH_TxHalted 0x8000 /* Transmission was halted by clearing */
163 /* TxEn or Halt immedite */
165 /* Receive Control Register (MACRXCON) */
166 #define ETH_RxEn 0x0001
167 #define ETH_RxHalt 0x0002
168 #define ETH_LongEn 0x0004
169 #define ETH_ShortEn 0x0008
170 #define ETH_StripCRC 0x0010
171 #define ETH_PassCtl 0x0020
172 #define ETH_IgnoreCRC 0x0040
173 #define ETH_EnAlign 0x0100
174 #define ETH_EnCRCErr 0x0200
175 #define ETH_EnOver 0x0400
176 #define ETH_EnLongErr 0x0800
177 #define ETH_EnRxPar 0x2000
178 #define ETH_EnGood 0x4000
180 /* Receive Status Register(MACRXSTAT) */
181 #define ETH_MCtlRecd 0x0020
182 #define ETH_MIntRx 0x0040
183 #define ETH_MRx10Stat 0x0080
184 #define ETH_MAllignErr 0x0100
185 #define ETH_MCRCErr 0x0200
186 #define ETH_MOverflow 0x0400
187 #define ETH_MLongErr 0x0800
188 #define ETH_MRxPar 0x2000
189 #define ETH_MRxGood 0x4000
190 #define ETH_MRxHalted 0x8000
192 /* Tx Frame Descriptor Options */
193 #define TX_OptNoPadding (0x01)
194 #define TX_OptNoCRCMode (0x02)
195 #define TX_OptMACTxIntEn (0x04)
196 #define TX_OptLittleEndian (0x08)
197 #define TX_OptFrameDataPtrInc (0x10)
198 #define TX_OptWA01 (0x20)
199 #define TX_OptWA10 (0x40)
200 #define TX_OptWA11 (0x60)
202 /* bit field for frame data pointer word */
203 typedef struct __BF_FrameDataPtr {
204 u32 dataPtr:31;
205 u32 owner: 1;
206 } BF_FrameDataPtr;
208 typedef union _FrameDataPtr {
209 u32 ui;
210 BF_FrameDataPtr bf;
211 } FrameDataPtr;
213 typedef struct __BF_TX_Options {
214 u32 no_padding: 1;
215 u32 no_crc: 1;
216 u32 macTxIrqEnbl: 1;
217 u32 littleEndian: 1;
218 u32 frameDataDir: 1;
219 u32 widgetAlign: 2;
220 u32 reserved:25;
221 } BF_TX_Options;
223 typedef union _TX_Options {
224 u32 ui;
225 BF_TX_Options bf;
226 } TX_Options;
228 typedef struct __BF_RX_Status {
229 u32 len:16; /* frame length */
230 u32 reserved1: 3;
231 u32 overMax: 1;
232 u32 reserved2: 1;
233 u32 ctrlRcv: 1;
234 u32 intRx: 1;
235 u32 rx10stat: 1;
236 u32 alignErr: 1;
237 u32 crcErr: 1;
238 u32 overFlow: 1;
239 u32 longErr: 1;
240 u32 reserved3: 1;
241 u32 parityErr: 1;
242 u32 good: 1;
243 u32 halted: 1;
244 } BF_RX_Status;
246 typedef union _RX_Status {
247 u32 ui;
248 BF_RX_Status bf;
249 } RX_Status;
251 typedef struct __BF_TX_Status {
252 u32 len:16; /* frame length */
253 u32 txCollCnt: 4;
254 u32 exColl: 1;
255 u32 txDefer: 1;
256 u32 paused: 1;
257 u32 intTx: 1;
258 u32 underRun: 1;
259 u32 defer: 1;
260 u32 noCarrier: 1;
261 u32 SQErr: 1;
262 u32 lateColl: 1;
263 u32 parityErr: 1;
264 u32 complete: 1;
265 u32 halted: 1;
266 } BF_TX_Status;
268 typedef union _TX_Status {
269 u32 ui;
270 BF_TX_Status bf;
271 } TX_Status;
273 /* TX descriptor structure */
274 typedef struct __TX_FrameDescriptor {
275 volatile FrameDataPtr m_frameDataPtr;
276 volatile TX_Options m_opt;
277 volatile TX_Status m_status;
278 volatile struct __TX_FrameDescriptor *m_nextFD;
279 /* We can add our own "per frame" data here */
280 struct sk_buff *skb;
281 } TX_FrameDesc;
283 /* RX descriptor structure */
284 typedef struct __RX_FrameDescriptor {
285 volatile FrameDataPtr m_frameDataPtr;
286 volatile u32 m_reserved;
287 volatile RX_Status m_status;
288 volatile struct __RX_FrameDescriptor *m_nextFD;
289 /* We can add our own "per frame" data here */
290 struct sk_buff *skb;
291 } RX_FrameDesc;
293 /* ETH Frame Structure */
294 typedef struct __ETHFrame {
295 u8 m_dstAddr[ETH_ALEN] __packed;
296 u8 m_srcAddr[ETH_ALEN] __packed;
297 u16 m_proto __packed;
298 u8 m_payload[ETH_DATA_LEN] __packed;
299 } ETHFrame;
301 #endif