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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / 8139too.c
blobd1b96cd2348afd8a5f29c76145ee7c0b9d457c35
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.27"
94
95
96 #include <linux/config.h>
97 #include <linux/module.h>
98 #include <linux/kernel.h>
99 #include <linux/compiler.h>
100 #include <linux/pci.h>
101 #include <linux/init.h>
102 #include <linux/ioport.h>
103 #include <linux/netdevice.h>
104 #include <linux/etherdevice.h>
105 #include <linux/rtnetlink.h>
106 #include <linux/delay.h>
107 #include <linux/ethtool.h>
108 #include <linux/mii.h>
109 #include <linux/completion.h>
110 #include <linux/crc32.h>
111 #include <linux/suspend.h>
112 #include <asm/io.h>
113 #include <asm/uaccess.h>
114 #include <asm/irq.h>
115
116 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
117 #define PFX DRV_NAME ": "
118
119 /* Default Message level */
120 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
121 NETIF_MSG_PROBE | \
122 NETIF_MSG_LINK)
123
124
125 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
126 #ifdef CONFIG_8139TOO_PIO
127 #define USE_IO_OPS 1
128 #endif
129
130 /* define to 1 to enable copious debugging info */
131 #undef RTL8139_DEBUG
132
133 /* define to 1 to disable lightweight runtime debugging checks */
134 #undef RTL8139_NDEBUG
135
136
137 #ifdef RTL8139_DEBUG
138 /* note: prints function name for you */
139 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
140 #else
141 # define DPRINTK(fmt, args...)
142 #endif
143
144 #ifdef RTL8139_NDEBUG
145 # define assert(expr) do {} while (0)
146 #else
147 # define assert(expr) \
148 if(unlikely(!(expr))) { \
149 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
150 #expr,__FILE__,__FUNCTION__,__LINE__); \
151 }
152 #endif
153
154
155 /* A few user-configurable values. */
156 /* media options */
157 #define MAX_UNITS 8
158 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
159 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
160
161 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
162 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
163 static int multicast_filter_limit = 32;
164
165 /* bitmapped message enable number */
166 static int debug = -1;
167
168 /*
169 * Receive ring size
170 * Warning: 64K ring has hardware issues and may lock up.
171 */
172 #if defined(CONFIG_SH_DREAMCAST)
173 #define RX_BUF_IDX 1 /* 16K ring */
174 #else
175 #define RX_BUF_IDX 2 /* 32K ring */
176 #endif
177 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
178 #define RX_BUF_PAD 16
179 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
180
181 #if RX_BUF_LEN == 65536
182 #define RX_BUF_TOT_LEN RX_BUF_LEN
183 #else
184 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
185 #endif
186
187 /* Number of Tx descriptor registers. */
188 #define NUM_TX_DESC 4
189
190 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
191 #define MAX_ETH_FRAME_SIZE 1536
192
193 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
194 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
195 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
196
197 /* PCI Tuning Parameters
198 Threshold is bytes transferred to chip before transmission starts. */
199 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
200
201 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
202 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
203 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
205 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
206
207 /* Operational parameters that usually are not changed. */
208 /* Time in jiffies before concluding the transmitter is hung. */
209 #define TX_TIMEOUT (6*HZ)
210
211
212 enum {
213 HAS_MII_XCVR = 0x010000,
214 HAS_CHIP_XCVR = 0x020000,
215 HAS_LNK_CHNG = 0x040000,
216 };
217
218 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
219 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
220 #define RTL_MIN_IO_SIZE 0x80
221 #define RTL8139B_IO_SIZE 256
222
223 #define RTL8129_CAPS HAS_MII_XCVR
224 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
225
226 typedef enum {
227 RTL8139 = 0,
228 RTL8129,
229 } board_t;
230
231
232 /* indexed by board_t, above */
233 static struct {
234 const char *name;
235 u32 hw_flags;
236 } board_info[] __devinitdata = {
237 { "RealTek RTL8139", RTL8139_CAPS },
238 { "RealTek RTL8129", RTL8129_CAPS },
239 };
240
241
242 static struct pci_device_id rtl8139_pci_tbl[] = {
243 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
262
263 #ifdef CONFIG_SH_SECUREEDGE5410
264 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
265 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
266 #endif
267 #ifdef CONFIG_8139TOO_8129
268 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
269 #endif
270
271 /* some crazy cards report invalid vendor ids like
272 * 0x0001 here. The other ids are valid and constant,
273 * so we simply don't match on the main vendor id.
274 */
275 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
277 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
278
279 {0,}
280 };
281 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
282
283 static struct {
284 const char str[ETH_GSTRING_LEN];
285 } ethtool_stats_keys[] = {
286 { "early_rx" },
287 { "tx_buf_mapped" },
288 { "tx_timeouts" },
289 { "rx_lost_in_ring" },
290 };
291
292 /* The rest of these values should never change. */
293
294 /* Symbolic offsets to registers. */
295 enum RTL8139_registers {
296 MAC0 = 0, /* Ethernet hardware address. */
297 MAR0 = 8, /* Multicast filter. */
298 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
299 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
300 RxBuf = 0x30,
301 ChipCmd = 0x37,
302 RxBufPtr = 0x38,
303 RxBufAddr = 0x3A,
304 IntrMask = 0x3C,
305 IntrStatus = 0x3E,
306 TxConfig = 0x40,
307 RxConfig = 0x44,
308 Timer = 0x48, /* A general-purpose counter. */
309 RxMissed = 0x4C, /* 24 bits valid, write clears. */
310 Cfg9346 = 0x50,
311 Config0 = 0x51,
312 Config1 = 0x52,
313 FlashReg = 0x54,
314 MediaStatus = 0x58,
315 Config3 = 0x59,
316 Config4 = 0x5A, /* absent on RTL-8139A */
317 HltClk = 0x5B,
318 MultiIntr = 0x5C,
319 TxSummary = 0x60,
320 BasicModeCtrl = 0x62,
321 BasicModeStatus = 0x64,
322 NWayAdvert = 0x66,
323 NWayLPAR = 0x68,
324 NWayExpansion = 0x6A,
325 /* Undocumented registers, but required for proper operation. */
326 FIFOTMS = 0x70, /* FIFO Control and test. */
327 CSCR = 0x74, /* Chip Status and Configuration Register. */
328 PARA78 = 0x78,
329 PARA7c = 0x7c, /* Magic transceiver parameter register. */
330 Config5 = 0xD8, /* absent on RTL-8139A */
331 };
332
333 enum ClearBitMasks {
334 MultiIntrClear = 0xF000,
335 ChipCmdClear = 0xE2,
336 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
337 };
338
339 enum ChipCmdBits {
340 CmdReset = 0x10,
341 CmdRxEnb = 0x08,
342 CmdTxEnb = 0x04,
343 RxBufEmpty = 0x01,
344 };
345
346 /* Interrupt register bits, using my own meaningful names. */
347 enum IntrStatusBits {
348 PCIErr = 0x8000,
349 PCSTimeout = 0x4000,
350 RxFIFOOver = 0x40,
351 RxUnderrun = 0x20,
352 RxOverflow = 0x10,
353 TxErr = 0x08,
354 TxOK = 0x04,
355 RxErr = 0x02,
356 RxOK = 0x01,
357
358 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
359 };
360
361 enum TxStatusBits {
362 TxHostOwns = 0x2000,
363 TxUnderrun = 0x4000,
364 TxStatOK = 0x8000,
365 TxOutOfWindow = 0x20000000,
366 TxAborted = 0x40000000,
367 TxCarrierLost = 0x80000000,
368 };
369 enum RxStatusBits {
370 RxMulticast = 0x8000,
371 RxPhysical = 0x4000,
372 RxBroadcast = 0x2000,
373 RxBadSymbol = 0x0020,
374 RxRunt = 0x0010,
375 RxTooLong = 0x0008,
376 RxCRCErr = 0x0004,
377 RxBadAlign = 0x0002,
378 RxStatusOK = 0x0001,
379 };
380
381 /* Bits in RxConfig. */
382 enum rx_mode_bits {
383 AcceptErr = 0x20,
384 AcceptRunt = 0x10,
385 AcceptBroadcast = 0x08,
386 AcceptMulticast = 0x04,
387 AcceptMyPhys = 0x02,
388 AcceptAllPhys = 0x01,
389 };
390
391 /* Bits in TxConfig. */
392 enum tx_config_bits {
393 TxIFG1 = (1 << 25), /* Interframe Gap Time */
394 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
395 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
396 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
397 TxClearAbt = (1 << 0), /* Clear abort (WO) */
398 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
399 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
400
401 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
402 };
403
404 /* Bits in Config1 */
405 enum Config1Bits {
406 Cfg1_PM_Enable = 0x01,
407 Cfg1_VPD_Enable = 0x02,
408 Cfg1_PIO = 0x04,
409 Cfg1_MMIO = 0x08,
410 LWAKE = 0x10, /* not on 8139, 8139A */
411 Cfg1_Driver_Load = 0x20,
412 Cfg1_LED0 = 0x40,
413 Cfg1_LED1 = 0x80,
414 SLEEP = (1 << 1), /* only on 8139, 8139A */
415 PWRDN = (1 << 0), /* only on 8139, 8139A */
416 };
417
418 /* Bits in Config3 */
419 enum Config3Bits {
420 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
421 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
422 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
423 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
424 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
425 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
426 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
427 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
428 };
429
430 /* Bits in Config4 */
431 enum Config4Bits {
432 LWPTN = (1 << 2), /* not on 8139, 8139A */
433 };
434
435 /* Bits in Config5 */
436 enum Config5Bits {
437 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
438 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
439 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
440 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
441 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
442 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
443 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
444 };
445
446 enum RxConfigBits {
447 /* rx fifo threshold */
448 RxCfgFIFOShift = 13,
449 RxCfgFIFONone = (7 << RxCfgFIFOShift),
450
451 /* Max DMA burst */
452 RxCfgDMAShift = 8,
453 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
454
455 /* rx ring buffer length */
456 RxCfgRcv8K = 0,
457 RxCfgRcv16K = (1 << 11),
458 RxCfgRcv32K = (1 << 12),
459 RxCfgRcv64K = (1 << 11) | (1 << 12),
460
461 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
462 RxNoWrap = (1 << 7),
463 };
464
465 /* Twister tuning parameters from RealTek.
466 Completely undocumented, but required to tune bad links on some boards. */
467 enum CSCRBits {
468 CSCR_LinkOKBit = 0x0400,
469 CSCR_LinkChangeBit = 0x0800,
470 CSCR_LinkStatusBits = 0x0f000,
471 CSCR_LinkDownOffCmd = 0x003c0,
472 CSCR_LinkDownCmd = 0x0f3c0,
473 };
474
475 enum Cfg9346Bits {
476 Cfg9346_Lock = 0x00,
477 Cfg9346_Unlock = 0xC0,
478 };
479
480 typedef enum {
481 CH_8139 = 0,
482 CH_8139_K,
483 CH_8139A,
484 CH_8139A_G,
485 CH_8139B,
486 CH_8130,
487 CH_8139C,
488 CH_8100,
489 CH_8100B_8139D,
490 CH_8101,
491 } chip_t;
492
493 enum chip_flags {
494 HasHltClk = (1 << 0),
495 HasLWake = (1 << 1),
496 };
497
498 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
499 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
500 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
501
502 /* directly indexed by chip_t, above */
503 const static struct {
504 const char *name;
505 u32 version; /* from RTL8139C/RTL8139D docs */
506 u32 flags;
507 } rtl_chip_info[] = {
508 { "RTL-8139",
509 HW_REVID(1, 0, 0, 0, 0, 0, 0),
510 HasHltClk,
511 },
512
513 { "RTL-8139 rev K",
514 HW_REVID(1, 1, 0, 0, 0, 0, 0),
515 HasHltClk,
516 },
517
518 { "RTL-8139A",
519 HW_REVID(1, 1, 1, 0, 0, 0, 0),
520 HasHltClk, /* XXX undocumented? */
521 },
522
523 { "RTL-8139A rev G",
524 HW_REVID(1, 1, 1, 0, 0, 1, 0),
525 HasHltClk, /* XXX undocumented? */
526 },
527
528 { "RTL-8139B",
529 HW_REVID(1, 1, 1, 1, 0, 0, 0),
530 HasLWake,
531 },
532
533 { "RTL-8130",
534 HW_REVID(1, 1, 1, 1, 1, 0, 0),
535 HasLWake,
536 },
537
538 { "RTL-8139C",
539 HW_REVID(1, 1, 1, 0, 1, 0, 0),
540 HasLWake,
541 },
542
543 { "RTL-8100",
544 HW_REVID(1, 1, 1, 1, 0, 1, 0),
545 HasLWake,
546 },
547
548 { "RTL-8100B/8139D",
549 HW_REVID(1, 1, 1, 0, 1, 0, 1),
550 HasLWake,
551 },
552
553 { "RTL-8101",
554 HW_REVID(1, 1, 1, 0, 1, 1, 1),
555 HasLWake,
556 },
557 };
558
559 struct rtl_extra_stats {
560 unsigned long early_rx;
561 unsigned long tx_buf_mapped;
562 unsigned long tx_timeouts;
563 unsigned long rx_lost_in_ring;
564 };
565
566 struct rtl8139_private {
567 void *mmio_addr;
568 int drv_flags;
569 struct pci_dev *pci_dev;
570 u32 pci_state[16];
571 u32 msg_enable;
572 struct net_device_stats stats;
573 unsigned char *rx_ring;
574 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
575 unsigned int tx_flag;
576 unsigned long cur_tx;
577 unsigned long dirty_tx;
578 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
579 unsigned char *tx_bufs; /* Tx bounce buffer region. */
580 dma_addr_t rx_ring_dma;
581 dma_addr_t tx_bufs_dma;
582 signed char phys[4]; /* MII device addresses. */
583 char twistie, twist_row, twist_col; /* Twister tune state. */
584 unsigned int default_port:4; /* Last dev->if_port value. */
585 spinlock_t lock;
586 spinlock_t rx_lock;
587 chip_t chipset;
588 pid_t thr_pid;
589 wait_queue_head_t thr_wait;
590 struct completion thr_exited;
591 u32 rx_config;
592 struct rtl_extra_stats xstats;
593 int time_to_die;
594 struct mii_if_info mii;
595 unsigned int regs_len;
596 unsigned long fifo_copy_timeout;
597 };
598
599 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
600 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
601 MODULE_LICENSE("GPL");
602
603 MODULE_PARM (multicast_filter_limit, "i");
604 MODULE_PARM (media, "1-" __MODULE_STRING(MAX_UNITS) "i");
605 MODULE_PARM (full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
606 MODULE_PARM (debug, "i");
607 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
608 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
609 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
610 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
611
612 static int read_eeprom (void *ioaddr, int location, int addr_len);
613 static int rtl8139_open (struct net_device *dev);
614 static int mdio_read (struct net_device *dev, int phy_id, int location);
615 static void mdio_write (struct net_device *dev, int phy_id, int location,
616 int val);
617 static void rtl8139_start_thread(struct net_device *dev);
618 static void rtl8139_tx_timeout (struct net_device *dev);
619 static void rtl8139_init_ring (struct net_device *dev);
620 static int rtl8139_start_xmit (struct sk_buff *skb,
621 struct net_device *dev);
622 static int rtl8139_poll(struct net_device *dev, int *budget);
623 #ifdef CONFIG_NET_POLL_CONTROLLER
624 static void rtl8139_poll_controller(struct net_device *dev);
625 #endif
626 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
627 struct pt_regs *regs);
628 static int rtl8139_close (struct net_device *dev);
629 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
630 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
631 static void rtl8139_set_rx_mode (struct net_device *dev);
632 static void __set_rx_mode (struct net_device *dev);
633 static void rtl8139_hw_start (struct net_device *dev);
634 static struct ethtool_ops rtl8139_ethtool_ops;
635
636 #ifdef USE_IO_OPS
637
638 #define RTL_R8(reg) inb (((unsigned long)ioaddr) + (reg))
639 #define RTL_R16(reg) inw (((unsigned long)ioaddr) + (reg))
640 #define RTL_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
641 #define RTL_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
642 #define RTL_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
643 #define RTL_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
644 #define RTL_W8_F RTL_W8
645 #define RTL_W16_F RTL_W16
646 #define RTL_W32_F RTL_W32
647 #undef readb
648 #undef readw
649 #undef readl
650 #undef writeb
651 #undef writew
652 #undef writel
653 #define readb(addr) inb((unsigned long)(addr))
654 #define readw(addr) inw((unsigned long)(addr))
655 #define readl(addr) inl((unsigned long)(addr))
656 #define writeb(val,addr) outb((val),(unsigned long)(addr))
657 #define writew(val,addr) outw((val),(unsigned long)(addr))
658 #define writel(val,addr) outl((val),(unsigned long)(addr))
659
660 #else
661
662 /* write MMIO register, with flush */
663 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
664 #define RTL_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
665 #define RTL_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
666 #define RTL_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
667
668
669 #define MMIO_FLUSH_AUDIT_COMPLETE 1
670 #if MMIO_FLUSH_AUDIT_COMPLETE
671
672 /* write MMIO register */
673 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
674 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
675 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
676
677 #else
678
679 /* write MMIO register, then flush */
680 #define RTL_W8 RTL_W8_F
681 #define RTL_W16 RTL_W16_F
682 #define RTL_W32 RTL_W32_F
683
684 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
685
686 /* read MMIO register */
687 #define RTL_R8(reg) readb (ioaddr + (reg))
688 #define RTL_R16(reg) readw (ioaddr + (reg))
689 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
690
691 #endif /* USE_IO_OPS */
692
693
694 static const u16 rtl8139_intr_mask =
695 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
696 TxErr | TxOK | RxErr | RxOK;
697
698 static const u16 rtl8139_norx_intr_mask =
699 PCIErr | PCSTimeout | RxUnderrun |
700 TxErr | TxOK | RxErr ;
701
702 #if RX_BUF_IDX == 0
703 static const unsigned int rtl8139_rx_config =
704 RxCfgRcv8K | RxNoWrap |
705 (RX_FIFO_THRESH << RxCfgFIFOShift) |
706 (RX_DMA_BURST << RxCfgDMAShift);
707 #elif RX_BUF_IDX == 1
708 static const unsigned int rtl8139_rx_config =
709 RxCfgRcv16K | RxNoWrap |
710 (RX_FIFO_THRESH << RxCfgFIFOShift) |
711 (RX_DMA_BURST << RxCfgDMAShift);
712 #elif RX_BUF_IDX == 2
713 static const unsigned int rtl8139_rx_config =
714 RxCfgRcv32K | RxNoWrap |
715 (RX_FIFO_THRESH << RxCfgFIFOShift) |
716 (RX_DMA_BURST << RxCfgDMAShift);
717 #elif RX_BUF_IDX == 3
718 static const unsigned int rtl8139_rx_config =
719 RxCfgRcv64K |
720 (RX_FIFO_THRESH << RxCfgFIFOShift) |
721 (RX_DMA_BURST << RxCfgDMAShift);
722 #else
723 #error "Invalid configuration for 8139_RXBUF_IDX"
724 #endif
725
726 static const unsigned int rtl8139_tx_config =
727 (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
728
729 static void __rtl8139_cleanup_dev (struct net_device *dev)
730 {
731 struct rtl8139_private *tp;
732 struct pci_dev *pdev;
733
734 assert (dev != NULL);
735 assert (dev->priv != NULL);
736
737 tp = dev->priv;
738 assert (tp->pci_dev != NULL);
739 pdev = tp->pci_dev;
740
741 #ifndef USE_IO_OPS
742 if (tp->mmio_addr)
743 iounmap (tp->mmio_addr);
744 #endif /* !USE_IO_OPS */
745
746 /* it's ok to call this even if we have no regions to free */
747 pci_release_regions (pdev);
748
749 free_netdev(dev);
750
751 pci_set_drvdata (pdev, NULL);
752 }
753
754
755 static void rtl8139_chip_reset (void *ioaddr)
756 {
757 int i;
758
759 /* Soft reset the chip. */
760 RTL_W8 (ChipCmd, CmdReset);
761
762 /* Check that the chip has finished the reset. */
763 for (i = 1000; i > 0; i--) {
764 barrier();
765 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
766 break;
767 udelay (10);
768 }
769 }
770
771
772 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
773 struct net_device **dev_out)
774 {
775 void *ioaddr;
776 struct net_device *dev;
777 struct rtl8139_private *tp;
778 u8 tmp8;
779 int rc;
780 unsigned int i;
781 unsigned long pio_start, pio_end, pio_flags, pio_len;
782 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
783 u32 version;
784
785 assert (pdev != NULL);
786
787 *dev_out = NULL;
788
789 /* dev and dev->priv zeroed in alloc_etherdev */
790 dev = alloc_etherdev (sizeof (*tp));
791 if (dev == NULL) {
792 printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pci_name(pdev));
793 return -ENOMEM;
794 }
795 SET_MODULE_OWNER(dev);
796 SET_NETDEV_DEV(dev, &pdev->dev);
797
798 tp = dev->priv;
799 tp->pci_dev = pdev;
800
801 /* enable device (incl. PCI PM wakeup and hotplug setup) */
802 rc = pci_enable_device (pdev);
803 if (rc)
804 goto err_out;
805
806 pio_start = pci_resource_start (pdev, 0);
807 pio_end = pci_resource_end (pdev, 0);
808 pio_flags = pci_resource_flags (pdev, 0);
809 pio_len = pci_resource_len (pdev, 0);
810
811 mmio_start = pci_resource_start (pdev, 1);
812 mmio_end = pci_resource_end (pdev, 1);
813 mmio_flags = pci_resource_flags (pdev, 1);
814 mmio_len = pci_resource_len (pdev, 1);
815
816 /* set this immediately, we need to know before
817 * we talk to the chip directly */
818 DPRINTK("PIO region size == 0x%02X\n", pio_len);
819 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
820
821 #ifdef USE_IO_OPS
822 /* make sure PCI base addr 0 is PIO */
823 if (!(pio_flags & IORESOURCE_IO)) {
824 printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pci_name(pdev));
825 rc = -ENODEV;
826 goto err_out;
827 }
828 /* check for weird/broken PCI region reporting */
829 if (pio_len < RTL_MIN_IO_SIZE) {
830 printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pci_name(pdev));
831 rc = -ENODEV;
832 goto err_out;
833 }
834 #else
835 /* make sure PCI base addr 1 is MMIO */
836 if (!(mmio_flags & IORESOURCE_MEM)) {
837 printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pci_name(pdev));
838 rc = -ENODEV;
839 goto err_out;
840 }
841 if (mmio_len < RTL_MIN_IO_SIZE) {
842 printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pci_name(pdev));
843 rc = -ENODEV;
844 goto err_out;
845 }
846 #endif
847
848 rc = pci_request_regions (pdev, "8139too");
849 if (rc)
850 goto err_out;
851
852 /* enable PCI bus-mastering */
853 pci_set_master (pdev);
854
855 #ifdef USE_IO_OPS
856 ioaddr = (void *) pio_start;
857 dev->base_addr = pio_start;
858 tp->mmio_addr = ioaddr;
859 tp->regs_len = pio_len;
860 #else
861 /* ioremap MMIO region */
862 ioaddr = ioremap (mmio_start, mmio_len);
863 if (ioaddr == NULL) {
864 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pci_name(pdev));
865 rc = -EIO;
866 goto err_out;
867 }
868 dev->base_addr = (long) ioaddr;
869 tp->mmio_addr = ioaddr;
870 tp->regs_len = mmio_len;
871 #endif /* USE_IO_OPS */
872
873 /* Bring old chips out of low-power mode. */
874 RTL_W8 (HltClk, 'R');
875
876 /* check for missing/broken hardware */
877 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
878 printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",
879 pci_name(pdev));
880 rc = -EIO;
881 goto err_out;
882 }
883
884 /* identify chip attached to board */
885 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
886 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
887 if (version == rtl_chip_info[i].version) {
888 tp->chipset = i;
889 goto match;
890 }
891
892 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
893 printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",
894 pci_name(pdev));
895 printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pci_name(pdev), RTL_R32 (TxConfig));
896 tp->chipset = 0;
897
898 match:
899 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
900 version, i, rtl_chip_info[i].name);
901
902 if (tp->chipset >= CH_8139B) {
903 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
904 DPRINTK("PCI PM wakeup\n");
905 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
906 (tmp8 & LWAKE))
907 new_tmp8 &= ~LWAKE;
908 new_tmp8 |= Cfg1_PM_Enable;
909 if (new_tmp8 != tmp8) {
910 RTL_W8 (Cfg9346, Cfg9346_Unlock);
911 RTL_W8 (Config1, tmp8);
912 RTL_W8 (Cfg9346, Cfg9346_Lock);
913 }
914 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
915 tmp8 = RTL_R8 (Config4);
916 if (tmp8 & LWPTN) {
917 RTL_W8 (Cfg9346, Cfg9346_Unlock);
918 RTL_W8 (Config4, tmp8 & ~LWPTN);
919 RTL_W8 (Cfg9346, Cfg9346_Lock);
920 }
921 }
922 } else {
923 DPRINTK("Old chip wakeup\n");
924 tmp8 = RTL_R8 (Config1);
925 tmp8 &= ~(SLEEP | PWRDN);
926 RTL_W8 (Config1, tmp8);
927 }
928
929 rtl8139_chip_reset (ioaddr);
930
931 *dev_out = dev;
932 return 0;
933
934 err_out:
935 __rtl8139_cleanup_dev (dev);
936 return rc;
937 }
938
939
940 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
941 const struct pci_device_id *ent)
942 {
943 struct net_device *dev = NULL;
944 struct rtl8139_private *tp;
945 int i, addr_len, option;
946 void *ioaddr;
947 static int board_idx = -1;
948 u8 pci_rev;
949
950 assert (pdev != NULL);
951 assert (ent != NULL);
952
953 board_idx++;
954
955 /* when we're built into the kernel, the driver version message
956 * is only printed if at least one 8139 board has been found
957 */
958 #ifndef MODULE
959 {
960 static int printed_version;
961 if (!printed_version++)
962 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
963 }
964 #endif
965
966 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
967
968 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
969 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
970 printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
971 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
972 printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");
973 }
974
975 i = rtl8139_init_board (pdev, &dev);
976 if (i < 0)
977 return i;
978
979 assert (dev != NULL);
980 tp = dev->priv;
981 assert (tp != NULL);
982 ioaddr = tp->mmio_addr;
983 assert (ioaddr != NULL);
984
985 #ifdef CONFIG_SH_SECUREEDGE5410
986 /* Don't rely on the eeprom, get MAC from chip. */
987 for (i = 0; i < 6; i++)
988 dev->dev_addr[i] = readb(ioaddr + MAC0 + i);
989 #else
990 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
991 for (i = 0; i < 3; i++)
992 ((u16 *) (dev->dev_addr))[i] =
993 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
994 #endif
995
996 /* The Rtl8139-specific entries in the device structure. */
997 dev->open = rtl8139_open;
998 dev->hard_start_xmit = rtl8139_start_xmit;
999 dev->poll = rtl8139_poll;
1000 dev->weight = 64;
1001 dev->stop = rtl8139_close;
1002 dev->get_stats = rtl8139_get_stats;
1003 dev->set_multicast_list = rtl8139_set_rx_mode;
1004 dev->do_ioctl = netdev_ioctl;
1005 dev->ethtool_ops = &rtl8139_ethtool_ops;
1006 dev->tx_timeout = rtl8139_tx_timeout;
1007 dev->watchdog_timeo = TX_TIMEOUT;
1008 #ifdef CONFIG_NET_POLL_CONTROLLER
1009 dev->poll_controller = rtl8139_poll_controller;
1010 #endif
1011
1012 /* note: the hardware is not capable of sg/csum/highdma, however
1013 * through the use of skb_copy_and_csum_dev we enable these
1014 * features
1015 */
1016 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1017
1018 dev->irq = pdev->irq;
1019
1020 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
1021 tp = dev->priv;
1022
1023 /* note: tp->chipset set in rtl8139_init_board */
1024 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1025 tp->mmio_addr = ioaddr;
1026 tp->msg_enable =
1027 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1028 spin_lock_init (&tp->lock);
1029 spin_lock_init (&tp->rx_lock);
1030 init_waitqueue_head (&tp->thr_wait);
1031 init_completion (&tp->thr_exited);
1032 tp->mii.dev = dev;
1033 tp->mii.mdio_read = mdio_read;
1034 tp->mii.mdio_write = mdio_write;
1035 tp->mii.phy_id_mask = 0x3f;
1036 tp->mii.reg_num_mask = 0x1f;
1037
1038 /* dev is fully set up and ready to use now */
1039 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1040 i = register_netdev (dev);
1041 if (i) goto err_out;
1042
1043 pci_set_drvdata (pdev, dev);
1044
1045 printk (KERN_INFO "%s: %s at 0x%lx, "
1046 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1047 "IRQ %d\n",
1048 dev->name,
1049 board_info[ent->driver_data].name,
1050 dev->base_addr,
1051 dev->dev_addr[0], dev->dev_addr[1],
1052 dev->dev_addr[2], dev->dev_addr[3],
1053 dev->dev_addr[4], dev->dev_addr[5],
1054 dev->irq);
1055
1056 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1057 dev->name, rtl_chip_info[tp->chipset].name);
1058
1059 /* Find the connected MII xcvrs.
1060 Doing this in open() would allow detecting external xcvrs later, but
1061 takes too much time. */
1062 #ifdef CONFIG_8139TOO_8129
1063 if (tp->drv_flags & HAS_MII_XCVR) {
1064 int phy, phy_idx = 0;
1065 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1066 int mii_status = mdio_read(dev, phy, 1);
1067 if (mii_status != 0xffff && mii_status != 0x0000) {
1068 u16 advertising = mdio_read(dev, phy, 4);
1069 tp->phys[phy_idx++] = phy;
1070 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1071 "advertising %4.4x.\n",
1072 dev->name, phy, mii_status, advertising);
1073 }
1074 }
1075 if (phy_idx == 0) {
1076 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1077 "transceiver.\n",
1078 dev->name);
1079 tp->phys[0] = 32;
1080 }
1081 } else
1082 #endif
1083 tp->phys[0] = 32;
1084 tp->mii.phy_id = tp->phys[0];
1085
1086 /* The lower four bits are the media type. */
1087 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1088 if (option > 0) {
1089 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1090 tp->default_port = option & 0xFF;
1091 if (tp->default_port)
1092 tp->mii.force_media = 1;
1093 }
1094 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1095 tp->mii.full_duplex = full_duplex[board_idx];
1096 if (tp->mii.full_duplex) {
1097 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1098 /* Changing the MII-advertised media because might prevent
1099 re-connection. */
1100 tp->mii.force_media = 1;
1101 }
1102 if (tp->default_port) {
1103 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1104 (option & 0x20 ? 100 : 10),
1105 (option & 0x10 ? "full" : "half"));
1106 mdio_write(dev, tp->phys[0], 0,
1107 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1108 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1109 }
1110
1111 /* Put the chip into low-power mode. */
1112 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1113 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1114
1115 return 0;
1116
1117 err_out:
1118 __rtl8139_cleanup_dev (dev);
1119 return i;
1120 }
1121
1122
1123 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1124 {
1125 struct net_device *dev = pci_get_drvdata (pdev);
1126 struct rtl8139_private *np;
1127
1128 assert (dev != NULL);
1129 np = dev->priv;
1130 assert (np != NULL);
1131
1132 unregister_netdev (dev);
1133
1134 __rtl8139_cleanup_dev (dev);
1135 }
1136
1137
1138 /* Serial EEPROM section. */
1139
1140 /* EEPROM_Ctrl bits. */
1141 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1142 #define EE_CS 0x08 /* EEPROM chip select. */
1143 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1144 #define EE_WRITE_0 0x00
1145 #define EE_WRITE_1 0x02
1146 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1147 #define EE_ENB (0x80 | EE_CS)
1148
1149 /* Delay between EEPROM clock transitions.
1150 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1151 */
1152
1153 #define eeprom_delay() readl(ee_addr)
1154
1155 /* The EEPROM commands include the alway-set leading bit. */
1156 #define EE_WRITE_CMD (5)
1157 #define EE_READ_CMD (6)
1158 #define EE_ERASE_CMD (7)
1159
1160 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
1161 {
1162 int i;
1163 unsigned retval = 0;
1164 void *ee_addr = ioaddr + Cfg9346;
1165 int read_cmd = location | (EE_READ_CMD << addr_len);
1166
1167 writeb (EE_ENB & ~EE_CS, ee_addr);
1168 writeb (EE_ENB, ee_addr);
1169 eeprom_delay ();
1170
1171 /* Shift the read command bits out. */
1172 for (i = 4 + addr_len; i >= 0; i--) {
1173 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1174 writeb (EE_ENB | dataval, ee_addr);
1175 eeprom_delay ();
1176 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1177 eeprom_delay ();
1178 }
1179 writeb (EE_ENB, ee_addr);
1180 eeprom_delay ();
1181
1182 for (i = 16; i > 0; i--) {
1183 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1184 eeprom_delay ();
1185 retval =
1186 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1187 0);
1188 writeb (EE_ENB, ee_addr);
1189 eeprom_delay ();
1190 }
1191
1192 /* Terminate the EEPROM access. */
1193 writeb (~EE_CS, ee_addr);
1194 eeprom_delay ();
1195
1196 return retval;
1197 }
1198
1199 /* MII serial management: mostly bogus for now. */
1200 /* Read and write the MII management registers using software-generated
1201 serial MDIO protocol.
1202 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1203 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1204 "overclocking" issues. */
1205 #define MDIO_DIR 0x80
1206 #define MDIO_DATA_OUT 0x04
1207 #define MDIO_DATA_IN 0x02
1208 #define MDIO_CLK 0x01
1209 #define MDIO_WRITE0 (MDIO_DIR)
1210 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1211
1212 #define mdio_delay(mdio_addr) readb(mdio_addr)
1213
1214
1215 static char mii_2_8139_map[8] = {
1216 BasicModeCtrl,
1217 BasicModeStatus,
1218 0,
1219 0,
1220 NWayAdvert,
1221 NWayLPAR,
1222 NWayExpansion,
1223 0
1224 };
1225
1226
1227 #ifdef CONFIG_8139TOO_8129
1228 /* Syncronize the MII management interface by shifting 32 one bits out. */
1229 static void mdio_sync (void *mdio_addr)
1230 {
1231 int i;
1232
1233 for (i = 32; i >= 0; i--) {
1234 writeb (MDIO_WRITE1, mdio_addr);
1235 mdio_delay (mdio_addr);
1236 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
1237 mdio_delay (mdio_addr);
1238 }
1239 }
1240 #endif
1241
1242 static int mdio_read (struct net_device *dev, int phy_id, int location)
1243 {
1244 struct rtl8139_private *tp = dev->priv;
1245 int retval = 0;
1246 #ifdef CONFIG_8139TOO_8129
1247 void *mdio_addr = tp->mmio_addr + Config4;
1248 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1249 int i;
1250 #endif
1251
1252 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1253 return location < 8 && mii_2_8139_map[location] ?
1254 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
1255 }
1256
1257 #ifdef CONFIG_8139TOO_8129
1258 mdio_sync (mdio_addr);
1259 /* Shift the read command bits out. */
1260 for (i = 15; i >= 0; i--) {
1261 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1262
1263 writeb (MDIO_DIR | dataval, mdio_addr);
1264 mdio_delay (mdio_addr);
1265 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1266 mdio_delay (mdio_addr);
1267 }
1268
1269 /* Read the two transition, 16 data, and wire-idle bits. */
1270 for (i = 19; i > 0; i--) {
1271 writeb (0, mdio_addr);
1272 mdio_delay (mdio_addr);
1273 retval = (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1 : 0);
1274 writeb (MDIO_CLK, mdio_addr);
1275 mdio_delay (mdio_addr);
1276 }
1277 #endif
1278
1279 return (retval >> 1) & 0xffff;
1280 }
1281
1282
1283 static void mdio_write (struct net_device *dev, int phy_id, int location,
1284 int value)
1285 {
1286 struct rtl8139_private *tp = dev->priv;
1287 #ifdef CONFIG_8139TOO_8129
1288 void *mdio_addr = tp->mmio_addr + Config4;
1289 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1290 int i;
1291 #endif
1292
1293 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1294 void *ioaddr = tp->mmio_addr;
1295 if (location == 0) {
1296 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1297 RTL_W16 (BasicModeCtrl, value);
1298 RTL_W8 (Cfg9346, Cfg9346_Lock);
1299 } else if (location < 8 && mii_2_8139_map[location])
1300 RTL_W16 (mii_2_8139_map[location], value);
1301 return;
1302 }
1303
1304 #ifdef CONFIG_8139TOO_8129
1305 mdio_sync (mdio_addr);
1306
1307 /* Shift the command bits out. */
1308 for (i = 31; i >= 0; i--) {
1309 int dataval =
1310 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1311 writeb (dataval, mdio_addr);
1312 mdio_delay (mdio_addr);
1313 writeb (dataval | MDIO_CLK, mdio_addr);
1314 mdio_delay (mdio_addr);
1315 }
1316 /* Clear out extra bits. */
1317 for (i = 2; i > 0; i--) {
1318 writeb (0, mdio_addr);
1319 mdio_delay (mdio_addr);
1320 writeb (MDIO_CLK, mdio_addr);
1321 mdio_delay (mdio_addr);
1322 }
1323 #endif
1324 }
1325
1326
1327 static int rtl8139_open (struct net_device *dev)
1328 {
1329 struct rtl8139_private *tp = dev->priv;
1330 int retval;
1331 void *ioaddr = tp->mmio_addr;
1332
1333 retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
1334 if (retval)
1335 return retval;
1336
1337 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1338 &tp->tx_bufs_dma);
1339 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1340 &tp->rx_ring_dma);
1341 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1342 free_irq(dev->irq, dev);
1343
1344 if (tp->tx_bufs)
1345 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1346 tp->tx_bufs, tp->tx_bufs_dma);
1347 if (tp->rx_ring)
1348 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1349 tp->rx_ring, tp->rx_ring_dma);
1350
1351 return -ENOMEM;
1352
1353 }
1354
1355 tp->mii.full_duplex = tp->mii.force_media;
1356 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1357
1358 rtl8139_init_ring (dev);
1359 rtl8139_hw_start (dev);
1360 netif_start_queue (dev);
1361
1362 if (netif_msg_ifup(tp))
1363 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#lx IRQ %d"
1364 " GP Pins %2.2x %s-duplex.\n",
1365 dev->name, pci_resource_start (tp->pci_dev, 1),
1366 dev->irq, RTL_R8 (MediaStatus),
1367 tp->mii.full_duplex ? "full" : "half");
1368
1369 rtl8139_start_thread(dev);
1370
1371 return 0;
1372 }
1373
1374
1375 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1376 {
1377 struct rtl8139_private *tp = dev->priv;
1378
1379 if (tp->phys[0] >= 0) {
1380 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1381 }
1382 }
1383
1384 /* Start the hardware at open or resume. */
1385 static void rtl8139_hw_start (struct net_device *dev)
1386 {
1387 struct rtl8139_private *tp = dev->priv;
1388 void *ioaddr = tp->mmio_addr;
1389 u32 i;
1390 u8 tmp;
1391
1392 /* Bring old chips out of low-power mode. */
1393 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1394 RTL_W8 (HltClk, 'R');
1395
1396 rtl8139_chip_reset (ioaddr);
1397
1398 /* unlock Config[01234] and BMCR register writes */
1399 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1400 /* Restore our idea of the MAC address. */
1401 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1402 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1403
1404 /* Must enable Tx/Rx before setting transfer thresholds! */
1405 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1406
1407 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1408 RTL_W32 (RxConfig, tp->rx_config);
1409
1410 /* Check this value: the documentation for IFG contradicts ifself. */
1411 RTL_W32 (TxConfig, rtl8139_tx_config);
1412
1413 tp->cur_rx = 0;
1414
1415 rtl_check_media (dev, 1);
1416
1417 if (tp->chipset >= CH_8139B) {
1418 /* Disable magic packet scanning, which is enabled
1419 * when PM is enabled in Config1. It can be reenabled
1420 * via ETHTOOL_SWOL if desired. */
1421 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1422 }
1423
1424 DPRINTK("init buffer addresses\n");
1425
1426 /* Lock Config[01234] and BMCR register writes */
1427 RTL_W8 (Cfg9346, Cfg9346_Lock);
1428
1429 /* init Rx ring buffer DMA address */
1430 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1431
1432 /* init Tx buffer DMA addresses */
1433 for (i = 0; i < NUM_TX_DESC; i++)
1434 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1435
1436 RTL_W32 (RxMissed, 0);
1437
1438 rtl8139_set_rx_mode (dev);
1439
1440 /* no early-rx interrupts */
1441 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1442
1443 /* make sure RxTx has started */
1444 tmp = RTL_R8 (ChipCmd);
1445 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1446 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1447
1448 /* Enable all known interrupts by setting the interrupt mask. */
1449 RTL_W16 (IntrMask, rtl8139_intr_mask);
1450 }
1451
1452
1453 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1454 static void rtl8139_init_ring (struct net_device *dev)
1455 {
1456 struct rtl8139_private *tp = dev->priv;
1457 int i;
1458
1459 tp->cur_rx = 0;
1460 tp->cur_tx = 0;
1461 tp->dirty_tx = 0;
1462
1463 for (i = 0; i < NUM_TX_DESC; i++)
1464 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1465 }
1466
1467
1468 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1469 static int next_tick = 3 * HZ;
1470
1471 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1472 static inline void rtl8139_tune_twister (struct net_device *dev,
1473 struct rtl8139_private *tp) {}
1474 #else
1475 enum TwisterParamVals {
1476 PARA78_default = 0x78fa8388,
1477 PARA7c_default = 0xcb38de43, /* param[0][3] */
1478 PARA7c_xxx = 0xcb38de43,
1479 };
1480
1481 static const unsigned long param[4][4] = {
1482 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1483 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1484 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1485 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1486 };
1487
1488 static void rtl8139_tune_twister (struct net_device *dev,
1489 struct rtl8139_private *tp)
1490 {
1491 int linkcase;
1492 void *ioaddr = tp->mmio_addr;
1493
1494 /* This is a complicated state machine to configure the "twister" for
1495 impedance/echos based on the cable length.
1496 All of this is magic and undocumented.
1497 */
1498 switch (tp->twistie) {
1499 case 1:
1500 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1501 /* We have link beat, let us tune the twister. */
1502 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1503 tp->twistie = 2; /* Change to state 2. */
1504 next_tick = HZ / 10;
1505 } else {
1506 /* Just put in some reasonable defaults for when beat returns. */
1507 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1508 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1509 RTL_W32 (PARA78, PARA78_default);
1510 RTL_W32 (PARA7c, PARA7c_default);
1511 tp->twistie = 0; /* Bail from future actions. */
1512 }
1513 break;
1514 case 2:
1515 /* Read how long it took to hear the echo. */
1516 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1517 if (linkcase == 0x7000)
1518 tp->twist_row = 3;
1519 else if (linkcase == 0x3000)
1520 tp->twist_row = 2;
1521 else if (linkcase == 0x1000)
1522 tp->twist_row = 1;
1523 else
1524 tp->twist_row = 0;
1525 tp->twist_col = 0;
1526 tp->twistie = 3; /* Change to state 2. */
1527 next_tick = HZ / 10;
1528 break;
1529 case 3:
1530 /* Put out four tuning parameters, one per 100msec. */
1531 if (tp->twist_col == 0)
1532 RTL_W16 (FIFOTMS, 0);
1533 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1534 [(int) tp->twist_col]);
1535 next_tick = HZ / 10;
1536 if (++tp->twist_col >= 4) {
1537 /* For short cables we are done.
1538 For long cables (row == 3) check for mistune. */
1539 tp->twistie =
1540 (tp->twist_row == 3) ? 4 : 0;
1541 }
1542 break;
1543 case 4:
1544 /* Special case for long cables: check for mistune. */
1545 if ((RTL_R16 (CSCR) &
1546 CSCR_LinkStatusBits) == 0x7000) {
1547 tp->twistie = 0;
1548 break;
1549 } else {
1550 RTL_W32 (PARA7c, 0xfb38de03);
1551 tp->twistie = 5;
1552 next_tick = HZ / 10;
1553 }
1554 break;
1555 case 5:
1556 /* Retune for shorter cable (column 2). */
1557 RTL_W32 (FIFOTMS, 0x20);
1558 RTL_W32 (PARA78, PARA78_default);
1559 RTL_W32 (PARA7c, PARA7c_default);
1560 RTL_W32 (FIFOTMS, 0x00);
1561 tp->twist_row = 2;
1562 tp->twist_col = 0;
1563 tp->twistie = 3;
1564 next_tick = HZ / 10;
1565 break;
1566
1567 default:
1568 /* do nothing */
1569 break;
1570 }
1571 }
1572 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1573
1574 static inline void rtl8139_thread_iter (struct net_device *dev,
1575 struct rtl8139_private *tp,
1576 void *ioaddr)
1577 {
1578 int mii_lpa;
1579
1580 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1581
1582 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1583 int duplex = (mii_lpa & LPA_100FULL)
1584 || (mii_lpa & 0x01C0) == 0x0040;
1585 if (tp->mii.full_duplex != duplex) {
1586 tp->mii.full_duplex = duplex;
1587
1588 if (mii_lpa) {
1589 printk (KERN_INFO
1590 "%s: Setting %s-duplex based on MII #%d link"
1591 " partner ability of %4.4x.\n",
1592 dev->name,
1593 tp->mii.full_duplex ? "full" : "half",
1594 tp->phys[0], mii_lpa);
1595 } else {
1596 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1597 dev->name);
1598 }
1599 #if 0
1600 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1601 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1602 RTL_W8 (Cfg9346, Cfg9346_Lock);
1603 #endif
1604 }
1605 }
1606
1607 next_tick = HZ * 60;
1608
1609 rtl8139_tune_twister (dev, tp);
1610
1611 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1612 dev->name, RTL_R16 (NWayLPAR));
1613 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1614 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1615 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1616 dev->name, RTL_R8 (Config0),
1617 RTL_R8 (Config1));
1618 }
1619
1620 static int rtl8139_thread (void *data)
1621 {
1622 struct net_device *dev = data;
1623 struct rtl8139_private *tp = dev->priv;
1624 unsigned long timeout;
1625
1626 daemonize("%s", dev->name);
1627 allow_signal(SIGTERM);
1628
1629 while (1) {
1630 timeout = next_tick;
1631 do {
1632 timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
1633 /* make swsusp happy with our thread */
1634 if (current->flags & PF_FREEZE)
1635 refrigerator(PF_FREEZE);
1636 } while (!signal_pending (current) && (timeout > 0));
1637
1638 if (signal_pending (current)) {
1639 flush_signals(current);
1640 }
1641
1642 if (tp->time_to_die)
1643 break;
1644
1645 rtnl_lock ();
1646 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1647 rtnl_unlock ();
1648 }
1649
1650 complete_and_exit (&tp->thr_exited, 0);
1651 }
1652
1653 static void rtl8139_start_thread(struct net_device *dev)
1654 {
1655 struct rtl8139_private *tp = dev->priv;
1656
1657 tp->thr_pid = -1;
1658 tp->twistie = 0;
1659 tp->time_to_die = 0;
1660 if (tp->chipset == CH_8139_K)
1661 tp->twistie = 1;
1662 else if (tp->drv_flags & HAS_LNK_CHNG)
1663 return;
1664
1665 tp->thr_pid = kernel_thread(rtl8139_thread, dev, CLONE_FS|CLONE_FILES);
1666 if (tp->thr_pid < 0) {
1667 printk (KERN_WARNING "%s: unable to start kernel thread\n",
1668 dev->name);
1669 }
1670 }
1671
1672 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1673 {
1674 tp->cur_tx = 0;
1675 tp->dirty_tx = 0;
1676
1677 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1678 }
1679
1680
1681 static void rtl8139_tx_timeout (struct net_device *dev)
1682 {
1683 struct rtl8139_private *tp = dev->priv;
1684 void *ioaddr = tp->mmio_addr;
1685 int i;
1686 u8 tmp8;
1687 unsigned long flags;
1688
1689 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1690 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1691 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1692 /* Emit info to figure out what went wrong. */
1693 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1694 dev->name, tp->cur_tx, tp->dirty_tx);
1695 for (i = 0; i < NUM_TX_DESC; i++)
1696 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1697 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1698 i == tp->dirty_tx % NUM_TX_DESC ?
1699 " (queue head)" : "");
1700
1701 tp->xstats.tx_timeouts++;
1702
1703 /* disable Tx ASAP, if not already */
1704 tmp8 = RTL_R8 (ChipCmd);
1705 if (tmp8 & CmdTxEnb)
1706 RTL_W8 (ChipCmd, CmdRxEnb);
1707
1708 spin_lock(&tp->rx_lock);
1709 /* Disable interrupts by clearing the interrupt mask. */
1710 RTL_W16 (IntrMask, 0x0000);
1711
1712 /* Stop a shared interrupt from scavenging while we are. */
1713 spin_lock_irqsave (&tp->lock, flags);
1714 rtl8139_tx_clear (tp);
1715 spin_unlock_irqrestore (&tp->lock, flags);
1716
1717 /* ...and finally, reset everything */
1718 if (netif_running(dev)) {
1719 rtl8139_hw_start (dev);
1720 netif_wake_queue (dev);
1721 }
1722 spin_unlock(&tp->rx_lock);
1723 }
1724
1725
1726 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1727 {
1728 struct rtl8139_private *tp = dev->priv;
1729 void *ioaddr = tp->mmio_addr;
1730 unsigned int entry;
1731 unsigned int len = skb->len;
1732
1733 /* Calculate the next Tx descriptor entry. */
1734 entry = tp->cur_tx % NUM_TX_DESC;
1735
1736 /* Note: the chip doesn't have auto-pad! */
1737 if (likely(len < TX_BUF_SIZE)) {
1738 if (len < ETH_ZLEN)
1739 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1740 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1741 dev_kfree_skb(skb);
1742 } else {
1743 dev_kfree_skb(skb);
1744 tp->stats.tx_dropped++;
1745 return 0;
1746 }
1747
1748 spin_lock_irq(&tp->lock);
1749 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1750 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1751
1752 dev->trans_start = jiffies;
1753
1754 tp->cur_tx++;
1755 wmb();
1756
1757 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1758 netif_stop_queue (dev);
1759 spin_unlock_irq(&tp->lock);
1760
1761 if (netif_msg_tx_queued(tp))
1762 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1763 dev->name, len, entry);
1764
1765 return 0;
1766 }
1767
1768
1769 static void rtl8139_tx_interrupt (struct net_device *dev,
1770 struct rtl8139_private *tp,
1771 void *ioaddr)
1772 {
1773 unsigned long dirty_tx, tx_left;
1774
1775 assert (dev != NULL);
1776 assert (tp != NULL);
1777 assert (ioaddr != NULL);
1778
1779 dirty_tx = tp->dirty_tx;
1780 tx_left = tp->cur_tx - dirty_tx;
1781 while (tx_left > 0) {
1782 int entry = dirty_tx % NUM_TX_DESC;
1783 int txstatus;
1784
1785 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1786
1787 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1788 break; /* It still hasn't been Txed */
1789
1790 /* Note: TxCarrierLost is always asserted at 100mbps. */
1791 if (txstatus & (TxOutOfWindow | TxAborted)) {
1792 /* There was an major error, log it. */
1793 if (netif_msg_tx_err(tp))
1794 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1795 dev->name, txstatus);
1796 tp->stats.tx_errors++;
1797 if (txstatus & TxAborted) {
1798 tp->stats.tx_aborted_errors++;
1799 RTL_W32 (TxConfig, TxClearAbt);
1800 RTL_W16 (IntrStatus, TxErr);
1801 wmb();
1802 }
1803 if (txstatus & TxCarrierLost)
1804 tp->stats.tx_carrier_errors++;
1805 if (txstatus & TxOutOfWindow)
1806 tp->stats.tx_window_errors++;
1807 } else {
1808 if (txstatus & TxUnderrun) {
1809 /* Add 64 to the Tx FIFO threshold. */
1810 if (tp->tx_flag < 0x00300000)
1811 tp->tx_flag += 0x00020000;
1812 tp->stats.tx_fifo_errors++;
1813 }
1814 tp->stats.collisions += (txstatus >> 24) & 15;
1815 tp->stats.tx_bytes += txstatus & 0x7ff;
1816 tp->stats.tx_packets++;
1817 }
1818
1819 dirty_tx++;
1820 tx_left--;
1821 }
1822
1823 #ifndef RTL8139_NDEBUG
1824 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1825 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1826 dev->name, dirty_tx, tp->cur_tx);
1827 dirty_tx += NUM_TX_DESC;
1828 }
1829 #endif /* RTL8139_NDEBUG */
1830
1831 /* only wake the queue if we did work, and the queue is stopped */
1832 if (tp->dirty_tx != dirty_tx) {
1833 tp->dirty_tx = dirty_tx;
1834 mb();
1835 netif_wake_queue (dev);
1836 }
1837 }
1838
1839
1840 /* TODO: clean this up! Rx reset need not be this intensive */
1841 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1842 struct rtl8139_private *tp, void *ioaddr)
1843 {
1844 u8 tmp8;
1845 #ifdef CONFIG_8139_OLD_RX_RESET
1846 int tmp_work;
1847 #endif
1848
1849 if (netif_msg_rx_err (tp))
1850 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1851 dev->name, rx_status);
1852 tp->stats.rx_errors++;
1853 if (!(rx_status & RxStatusOK)) {
1854 if (rx_status & RxTooLong) {
1855 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1856 dev->name, rx_status);
1857 /* A.C.: The chip hangs here. */
1858 }
1859 if (rx_status & (RxBadSymbol | RxBadAlign))
1860 tp->stats.rx_frame_errors++;
1861 if (rx_status & (RxRunt | RxTooLong))
1862 tp->stats.rx_length_errors++;
1863 if (rx_status & RxCRCErr)
1864 tp->stats.rx_crc_errors++;
1865 } else {
1866 tp->xstats.rx_lost_in_ring++;
1867 }
1868
1869 #ifndef CONFIG_8139_OLD_RX_RESET
1870 tmp8 = RTL_R8 (ChipCmd);
1871 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1872 RTL_W8 (ChipCmd, tmp8);
1873 RTL_W32 (RxConfig, tp->rx_config);
1874 tp->cur_rx = 0;
1875 #else
1876 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1877
1878 /* disable receive */
1879 RTL_W8_F (ChipCmd, CmdTxEnb);
1880 tmp_work = 200;
1881 while (--tmp_work > 0) {
1882 udelay(1);
1883 tmp8 = RTL_R8 (ChipCmd);
1884 if (!(tmp8 & CmdRxEnb))
1885 break;
1886 }
1887 if (tmp_work <= 0)
1888 printk (KERN_WARNING PFX "rx stop wait too long\n");
1889 /* restart receive */
1890 tmp_work = 200;
1891 while (--tmp_work > 0) {
1892 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1893 udelay(1);
1894 tmp8 = RTL_R8 (ChipCmd);
1895 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1896 break;
1897 }
1898 if (tmp_work <= 0)
1899 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1900
1901 /* and reinitialize all rx related registers */
1902 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1903 /* Must enable Tx/Rx before setting transfer thresholds! */
1904 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1905
1906 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1907 RTL_W32 (RxConfig, tp->rx_config);
1908 tp->cur_rx = 0;
1909
1910 DPRINTK("init buffer addresses\n");
1911
1912 /* Lock Config[01234] and BMCR register writes */
1913 RTL_W8 (Cfg9346, Cfg9346_Lock);
1914
1915 /* init Rx ring buffer DMA address */
1916 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1917
1918 /* A.C.: Reset the multicast list. */
1919 __set_rx_mode (dev);
1920 #endif
1921 }
1922
1923 #if RX_BUF_IDX == 3
1924 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1925 u32 offset, unsigned int size)
1926 {
1927 u32 left = RX_BUF_LEN - offset;
1928
1929 if (size > left) {
1930 memcpy(skb->data, ring + offset, left);
1931 memcpy(skb->data+left, ring, size - left);
1932 } else
1933 memcpy(skb->data, ring + offset, size);
1934 }
1935 #endif
1936
1937 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1938 {
1939 void *ioaddr = tp->mmio_addr;
1940 u16 status;
1941
1942 status = RTL_R16 (IntrStatus) & RxAckBits;
1943
1944 /* Clear out errors and receive interrupts */
1945 if (likely(status != 0)) {
1946 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1947 tp->stats.rx_errors++;
1948 if (status & RxFIFOOver)
1949 tp->stats.rx_fifo_errors++;
1950 }
1951 RTL_W16_F (IntrStatus, RxAckBits);
1952 }
1953 }
1954
1955 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1956 int budget)
1957 {
1958 void *ioaddr = tp->mmio_addr;
1959 int received = 0;
1960 unsigned char *rx_ring = tp->rx_ring;
1961 unsigned int cur_rx = tp->cur_rx;
1962 unsigned int rx_size = 0;
1963
1964 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1965 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1966 RTL_R16 (RxBufAddr),
1967 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1968
1969 while (netif_running(dev) && received < budget
1970 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1971 u32 ring_offset = cur_rx % RX_BUF_LEN;
1972 u32 rx_status;
1973 unsigned int pkt_size;
1974 struct sk_buff *skb;
1975
1976 rmb();
1977
1978 /* read size+status of next frame from DMA ring buffer */
1979 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1980 rx_size = rx_status >> 16;
1981 pkt_size = rx_size - 4;
1982
1983 if (netif_msg_rx_status(tp))
1984 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1985 " cur %4.4x.\n", dev->name, rx_status,
1986 rx_size, cur_rx);
1987 #if RTL8139_DEBUG > 2
1988 {
1989 int i;
1990 DPRINTK ("%s: Frame contents ", dev->name);
1991 for (i = 0; i < 70; i++)
1992 printk (" %2.2x",
1993 rx_ring[ring_offset + i]);
1994 printk (".\n");
1995 }
1996 #endif
1997
1998 /* Packet copy from FIFO still in progress.
1999 * Theoretically, this should never happen
2000 * since EarlyRx is disabled.
2001 */
2002 if (unlikely(rx_size == 0xfff0)) {
2003 if (!tp->fifo_copy_timeout)
2004 tp->fifo_copy_timeout = jiffies + 2;
2005 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
2006 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
2007 rx_size = 0;
2008 goto no_early_rx;
2009 }
2010 if (netif_msg_intr(tp)) {
2011 printk(KERN_DEBUG "%s: fifo copy in progress.",
2012 dev->name);
2013 }
2014 tp->xstats.early_rx++;
2015 break;
2016 }
2017
2018 no_early_rx:
2019 tp->fifo_copy_timeout = 0;
2020
2021 /* If Rx err or invalid rx_size/rx_status received
2022 * (which happens if we get lost in the ring),
2023 * Rx process gets reset, so we abort any further
2024 * Rx processing.
2025 */
2026 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2027 (rx_size < 8) ||
2028 (!(rx_status & RxStatusOK)))) {
2029 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2030 received = -1;
2031 goto out;
2032 }
2033
2034 /* Malloc up new buffer, compatible with net-2e. */
2035 /* Omit the four octet CRC from the length. */
2036
2037 skb = dev_alloc_skb (pkt_size + 2);
2038 if (likely(skb)) {
2039 skb->dev = dev;
2040 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2041 #if RX_BUF_IDX == 3
2042 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2043 #else
2044 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
2045 #endif
2046 skb_put (skb, pkt_size);
2047
2048 skb->protocol = eth_type_trans (skb, dev);
2049
2050 dev->last_rx = jiffies;
2051 tp->stats.rx_bytes += pkt_size;
2052 tp->stats.rx_packets++;
2053
2054 netif_receive_skb (skb);
2055 } else {
2056 if (net_ratelimit())
2057 printk (KERN_WARNING
2058 "%s: Memory squeeze, dropping packet.\n",
2059 dev->name);
2060 tp->stats.rx_dropped++;
2061 }
2062 received++;
2063
2064 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2065 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2066
2067 rtl8139_isr_ack(tp);
2068 }
2069
2070 if (unlikely(!received || rx_size == 0xfff0))
2071 rtl8139_isr_ack(tp);
2072
2073 #if RTL8139_DEBUG > 1
2074 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2075 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2076 RTL_R16 (RxBufAddr),
2077 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2078 #endif
2079
2080 tp->cur_rx = cur_rx;
2081
2082 /*
2083 * The receive buffer should be mostly empty.
2084 * Tell NAPI to reenable the Rx irq.
2085 */
2086 if (tp->fifo_copy_timeout)
2087 received = budget;
2088
2089 out:
2090 return received;
2091 }
2092
2093
2094 static void rtl8139_weird_interrupt (struct net_device *dev,
2095 struct rtl8139_private *tp,
2096 void *ioaddr,
2097 int status, int link_changed)
2098 {
2099 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2100 dev->name, status);
2101
2102 assert (dev != NULL);
2103 assert (tp != NULL);
2104 assert (ioaddr != NULL);
2105
2106 /* Update the error count. */
2107 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2108 RTL_W32 (RxMissed, 0);
2109
2110 if ((status & RxUnderrun) && link_changed &&
2111 (tp->drv_flags & HAS_LNK_CHNG)) {
2112 rtl_check_media(dev, 0);
2113 status &= ~RxUnderrun;
2114 }
2115
2116 if (status & (RxUnderrun | RxErr))
2117 tp->stats.rx_errors++;
2118
2119 if (status & PCSTimeout)
2120 tp->stats.rx_length_errors++;
2121 if (status & RxUnderrun)
2122 tp->stats.rx_fifo_errors++;
2123 if (status & PCIErr) {
2124 u16 pci_cmd_status;
2125 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2126 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2127
2128 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2129 dev->name, pci_cmd_status);
2130 }
2131 }
2132
2133 static int rtl8139_poll(struct net_device *dev, int *budget)
2134 {
2135 struct rtl8139_private *tp = dev->priv;
2136 void *ioaddr = tp->mmio_addr;
2137 int orig_budget = min(*budget, dev->quota);
2138 int done = 1;
2139
2140 spin_lock(&tp->rx_lock);
2141 if (likely(RTL_R16(IntrStatus) & RxAckBits)) {
2142 int work_done;
2143
2144 work_done = rtl8139_rx(dev, tp, orig_budget);
2145 if (likely(work_done > 0)) {
2146 *budget -= work_done;
2147 dev->quota -= work_done;
2148 done = (work_done < orig_budget);
2149 }
2150 }
2151
2152 if (done) {
2153 /*
2154 * Order is important since data can get interrupted
2155 * again when we think we are done.
2156 */
2157 local_irq_disable();
2158 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2159 __netif_rx_complete(dev);
2160 local_irq_enable();
2161 }
2162 spin_unlock(&tp->rx_lock);
2163
2164 return !done;
2165 }
2166
2167 /* The interrupt handler does all of the Rx thread work and cleans up
2168 after the Tx thread. */
2169 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
2170 struct pt_regs *regs)
2171 {
2172 struct net_device *dev = (struct net_device *) dev_instance;
2173 struct rtl8139_private *tp = dev->priv;
2174 void *ioaddr = tp->mmio_addr;
2175 u16 status, ackstat;
2176 int link_changed = 0; /* avoid bogus "uninit" warning */
2177 int handled = 0;
2178
2179 spin_lock (&tp->lock);
2180 status = RTL_R16 (IntrStatus);
2181
2182 /* shared irq? */
2183 if (unlikely((status & rtl8139_intr_mask) == 0))
2184 goto out;
2185
2186 handled = 1;
2187
2188 /* h/w no longer present (hotplug?) or major error, bail */
2189 if (unlikely(status == 0xFFFF))
2190 goto out;
2191
2192 /* close possible race's with dev_close */
2193 if (unlikely(!netif_running(dev))) {
2194 RTL_W16 (IntrMask, 0);
2195 goto out;
2196 }
2197
2198 /* Acknowledge all of the current interrupt sources ASAP, but
2199 an first get an additional status bit from CSCR. */
2200 if (unlikely(status & RxUnderrun))
2201 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2202
2203 ackstat = status & ~(RxAckBits | TxErr);
2204 if (ackstat)
2205 RTL_W16 (IntrStatus, ackstat);
2206
2207 /* Receive packets are processed by poll routine.
2208 If not running start it now. */
2209 if (status & RxAckBits){
2210 if (netif_rx_schedule_prep(dev)) {
2211 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2212 __netif_rx_schedule (dev);
2213 }
2214 }
2215
2216 /* Check uncommon events with one test. */
2217 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2218 rtl8139_weird_interrupt (dev, tp, ioaddr,
2219 status, link_changed);
2220
2221 if (status & (TxOK | TxErr)) {
2222 rtl8139_tx_interrupt (dev, tp, ioaddr);
2223 if (status & TxErr)
2224 RTL_W16 (IntrStatus, TxErr);
2225 }
2226 out:
2227 spin_unlock (&tp->lock);
2228
2229 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2230 dev->name, RTL_R16 (IntrStatus));
2231 return IRQ_RETVAL(handled);
2232 }
2233
2234 #ifdef CONFIG_NET_POLL_CONTROLLER
2235 /*
2236 * Polling receive - used by netconsole and other diagnostic tools
2237 * to allow network i/o with interrupts disabled.
2238 */
2239 static void rtl8139_poll_controller(struct net_device *dev)
2240 {
2241 disable_irq(dev->irq);
2242 rtl8139_interrupt(dev->irq, dev, NULL);
2243 enable_irq(dev->irq);
2244 }
2245 #endif
2246
2247 static int rtl8139_close (struct net_device *dev)
2248 {
2249 struct rtl8139_private *tp = dev->priv;
2250 void *ioaddr = tp->mmio_addr;
2251 int ret = 0;
2252 unsigned long flags;
2253
2254 netif_stop_queue (dev);
2255
2256 if (tp->thr_pid >= 0) {
2257 tp->time_to_die = 1;
2258 wmb();
2259 ret = kill_proc (tp->thr_pid, SIGTERM, 1);
2260 if (ret) {
2261 printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
2262 return ret;
2263 }
2264 wait_for_completion (&tp->thr_exited);
2265 }
2266
2267 if (netif_msg_ifdown(tp))
2268 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2269 dev->name, RTL_R16 (IntrStatus));
2270
2271 spin_lock_irqsave (&tp->lock, flags);
2272
2273 /* Stop the chip's Tx and Rx DMA processes. */
2274 RTL_W8 (ChipCmd, 0);
2275
2276 /* Disable interrupts by clearing the interrupt mask. */
2277 RTL_W16 (IntrMask, 0);
2278
2279 /* Update the error counts. */
2280 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2281 RTL_W32 (RxMissed, 0);
2282
2283 spin_unlock_irqrestore (&tp->lock, flags);
2284
2285 synchronize_irq (dev->irq); /* racy, but that's ok here */
2286 free_irq (dev->irq, dev);
2287
2288 rtl8139_tx_clear (tp);
2289
2290 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2291 tp->rx_ring, tp->rx_ring_dma);
2292 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2293 tp->tx_bufs, tp->tx_bufs_dma);
2294 tp->rx_ring = NULL;
2295 tp->tx_bufs = NULL;
2296
2297 /* Green! Put the chip in low-power mode. */
2298 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2299
2300 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2301 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2302
2303 return 0;
2304 }
2305
2306
2307 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2308 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2309 other threads or interrupts aren't messing with the 8139. */
2310 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2311 {
2312 struct rtl8139_private *np = dev->priv;
2313 void *ioaddr = np->mmio_addr;
2314
2315 spin_lock_irq(&np->lock);
2316 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2317 u8 cfg3 = RTL_R8 (Config3);
2318 u8 cfg5 = RTL_R8 (Config5);
2319
2320 wol->supported = WAKE_PHY | WAKE_MAGIC
2321 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2322
2323 wol->wolopts = 0;
2324 if (cfg3 & Cfg3_LinkUp)
2325 wol->wolopts |= WAKE_PHY;
2326 if (cfg3 & Cfg3_Magic)
2327 wol->wolopts |= WAKE_MAGIC;
2328 /* (KON)FIXME: See how netdev_set_wol() handles the
2329 following constants. */
2330 if (cfg5 & Cfg5_UWF)
2331 wol->wolopts |= WAKE_UCAST;
2332 if (cfg5 & Cfg5_MWF)
2333 wol->wolopts |= WAKE_MCAST;
2334 if (cfg5 & Cfg5_BWF)
2335 wol->wolopts |= WAKE_BCAST;
2336 }
2337 spin_unlock_irq(&np->lock);
2338 }
2339
2340
2341 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2342 that wol points to kernel memory and other threads or interrupts
2343 aren't messing with the 8139. */
2344 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2345 {
2346 struct rtl8139_private *np = dev->priv;
2347 void *ioaddr = np->mmio_addr;
2348 u32 support;
2349 u8 cfg3, cfg5;
2350
2351 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2352 ? (WAKE_PHY | WAKE_MAGIC
2353 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2354 : 0);
2355 if (wol->wolopts & ~support)
2356 return -EINVAL;
2357
2358 spin_lock_irq(&np->lock);
2359 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2360 if (wol->wolopts & WAKE_PHY)
2361 cfg3 |= Cfg3_LinkUp;
2362 if (wol->wolopts & WAKE_MAGIC)
2363 cfg3 |= Cfg3_Magic;
2364 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2365 RTL_W8 (Config3, cfg3);
2366 RTL_W8 (Cfg9346, Cfg9346_Lock);
2367
2368 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2369 /* (KON)FIXME: These are untested. We may have to set the
2370 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2371 documentation. */
2372 if (wol->wolopts & WAKE_UCAST)
2373 cfg5 |= Cfg5_UWF;
2374 if (wol->wolopts & WAKE_MCAST)
2375 cfg5 |= Cfg5_MWF;
2376 if (wol->wolopts & WAKE_BCAST)
2377 cfg5 |= Cfg5_BWF;
2378 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2379 spin_unlock_irq(&np->lock);
2380
2381 return 0;
2382 }
2383
2384 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2385 {
2386 struct rtl8139_private *np = dev->priv;
2387 strcpy(info->driver, DRV_NAME);
2388 strcpy(info->version, DRV_VERSION);
2389 strcpy(info->bus_info, pci_name(np->pci_dev));
2390 info->regdump_len = np->regs_len;
2391 }
2392
2393 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2394 {
2395 struct rtl8139_private *np = dev->priv;
2396 spin_lock_irq(&np->lock);
2397 mii_ethtool_gset(&np->mii, cmd);
2398 spin_unlock_irq(&np->lock);
2399 return 0;
2400 }
2401
2402 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2403 {
2404 struct rtl8139_private *np = dev->priv;
2405 int rc;
2406 spin_lock_irq(&np->lock);
2407 rc = mii_ethtool_sset(&np->mii, cmd);
2408 spin_unlock_irq(&np->lock);
2409 return rc;
2410 }
2411
2412 static int rtl8139_nway_reset(struct net_device *dev)
2413 {
2414 struct rtl8139_private *np = dev->priv;
2415 return mii_nway_restart(&np->mii);
2416 }
2417
2418 static u32 rtl8139_get_link(struct net_device *dev)
2419 {
2420 struct rtl8139_private *np = dev->priv;
2421 return mii_link_ok(&np->mii);
2422 }
2423
2424 static u32 rtl8139_get_msglevel(struct net_device *dev)
2425 {
2426 struct rtl8139_private *np = dev->priv;
2427 return np->msg_enable;
2428 }
2429
2430 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2431 {
2432 struct rtl8139_private *np = dev->priv;
2433 np->msg_enable = datum;
2434 }
2435
2436 /* TODO: we are too slack to do reg dumping for pio, for now */
2437 #ifdef CONFIG_8139TOO_PIO
2438 #define rtl8139_get_regs_len NULL
2439 #define rtl8139_get_regs NULL
2440 #else
2441 static int rtl8139_get_regs_len(struct net_device *dev)
2442 {
2443 struct rtl8139_private *np = dev->priv;
2444 return np->regs_len;
2445 }
2446
2447 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2448 {
2449 struct rtl8139_private *np = dev->priv;
2450
2451 regs->version = RTL_REGS_VER;
2452
2453 spin_lock_irq(&np->lock);
2454 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2455 spin_unlock_irq(&np->lock);
2456 }
2457 #endif /* CONFIG_8139TOO_MMIO */
2458
2459 static int rtl8139_get_stats_count(struct net_device *dev)
2460 {
2461 return RTL_NUM_STATS;
2462 }
2463
2464 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2465 {
2466 struct rtl8139_private *np = dev->priv;
2467
2468 data[0] = np->xstats.early_rx;
2469 data[1] = np->xstats.tx_buf_mapped;
2470 data[2] = np->xstats.tx_timeouts;
2471 data[3] = np->xstats.rx_lost_in_ring;
2472 }
2473
2474 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2475 {
2476 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2477 }
2478
2479 static struct ethtool_ops rtl8139_ethtool_ops = {
2480 .get_drvinfo = rtl8139_get_drvinfo,
2481 .get_settings = rtl8139_get_settings,
2482 .set_settings = rtl8139_set_settings,
2483 .get_regs_len = rtl8139_get_regs_len,
2484 .get_regs = rtl8139_get_regs,
2485 .nway_reset = rtl8139_nway_reset,
2486 .get_link = rtl8139_get_link,
2487 .get_msglevel = rtl8139_get_msglevel,
2488 .set_msglevel = rtl8139_set_msglevel,
2489 .get_wol = rtl8139_get_wol,
2490 .set_wol = rtl8139_set_wol,
2491 .get_strings = rtl8139_get_strings,
2492 .get_stats_count = rtl8139_get_stats_count,
2493 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2494 };
2495
2496 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2497 {
2498 struct rtl8139_private *np = dev->priv;
2499 int rc;
2500
2501 if (!netif_running(dev))
2502 return -EINVAL;
2503
2504 spin_lock_irq(&np->lock);
2505 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2506 spin_unlock_irq(&np->lock);
2507
2508 return rc;
2509 }
2510
2511
2512 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2513 {
2514 struct rtl8139_private *tp = dev->priv;
2515 void *ioaddr = tp->mmio_addr;
2516 unsigned long flags;
2517
2518 if (netif_running(dev)) {
2519 spin_lock_irqsave (&tp->lock, flags);
2520 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2521 RTL_W32 (RxMissed, 0);
2522 spin_unlock_irqrestore (&tp->lock, flags);
2523 }
2524
2525 return &tp->stats;
2526 }
2527
2528 /* Set or clear the multicast filter for this adaptor.
2529 This routine is not state sensitive and need not be SMP locked. */
2530
2531 static void __set_rx_mode (struct net_device *dev)
2532 {
2533 struct rtl8139_private *tp = dev->priv;
2534 void *ioaddr = tp->mmio_addr;
2535 u32 mc_filter[2]; /* Multicast hash filter */
2536 int i, rx_mode;
2537 u32 tmp;
2538
2539 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2540 dev->name, dev->flags, RTL_R32 (RxConfig));
2541
2542 /* Note: do not reorder, GCC is clever about common statements. */
2543 if (dev->flags & IFF_PROMISC) {
2544 /* Unconditionally log net taps. */
2545 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2546 dev->name);
2547 rx_mode =
2548 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2549 AcceptAllPhys;
2550 mc_filter[1] = mc_filter[0] = 0xffffffff;
2551 } else if ((dev->mc_count > multicast_filter_limit)
2552 || (dev->flags & IFF_ALLMULTI)) {
2553 /* Too many to filter perfectly -- accept all multicasts. */
2554 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2555 mc_filter[1] = mc_filter[0] = 0xffffffff;
2556 } else {
2557 struct dev_mc_list *mclist;
2558 rx_mode = AcceptBroadcast | AcceptMyPhys;
2559 mc_filter[1] = mc_filter[0] = 0;
2560 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2561 i++, mclist = mclist->next) {
2562 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2563
2564 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2565 rx_mode |= AcceptMulticast;
2566 }
2567 }
2568
2569 /* We can safely update without stopping the chip. */
2570 tmp = rtl8139_rx_config | rx_mode;
2571 if (tp->rx_config != tmp) {
2572 RTL_W32_F (RxConfig, tmp);
2573 tp->rx_config = tmp;
2574 }
2575 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2576 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2577 }
2578
2579 static void rtl8139_set_rx_mode (struct net_device *dev)
2580 {
2581 unsigned long flags;
2582 struct rtl8139_private *tp = dev->priv;
2583
2584 spin_lock_irqsave (&tp->lock, flags);
2585 __set_rx_mode(dev);
2586 spin_unlock_irqrestore (&tp->lock, flags);
2587 }
2588
2589 #ifdef CONFIG_PM
2590
2591 static int rtl8139_suspend (struct pci_dev *pdev, u32 state)
2592 {
2593 struct net_device *dev = pci_get_drvdata (pdev);
2594 struct rtl8139_private *tp = dev->priv;
2595 void *ioaddr = tp->mmio_addr;
2596 unsigned long flags;
2597
2598 pci_save_state (pdev, tp->pci_state);
2599
2600 if (!netif_running (dev))
2601 return 0;
2602
2603 netif_device_detach (dev);
2604
2605 spin_lock_irqsave (&tp->lock, flags);
2606
2607 /* Disable interrupts, stop Tx and Rx. */
2608 RTL_W16 (IntrMask, 0);
2609 RTL_W8 (ChipCmd, 0);
2610
2611 /* Update the error counts. */
2612 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2613 RTL_W32 (RxMissed, 0);
2614
2615 spin_unlock_irqrestore (&tp->lock, flags);
2616
2617 pci_set_power_state (pdev, 3);
2618
2619 return 0;
2620 }
2621
2622
2623 static int rtl8139_resume (struct pci_dev *pdev)
2624 {
2625 struct net_device *dev = pci_get_drvdata (pdev);
2626 struct rtl8139_private *tp = dev->priv;
2627
2628 pci_restore_state (pdev, tp->pci_state);
2629 if (!netif_running (dev))
2630 return 0;
2631 pci_set_power_state (pdev, 0);
2632 rtl8139_init_ring (dev);
2633 rtl8139_hw_start (dev);
2634 netif_device_attach (dev);
2635 return 0;
2636 }
2637
2638 #endif /* CONFIG_PM */
2639
2640
2641 static struct pci_driver rtl8139_pci_driver = {
2642 .name = DRV_NAME,
2643 .id_table = rtl8139_pci_tbl,
2644 .probe = rtl8139_init_one,
2645 .remove = __devexit_p(rtl8139_remove_one),
2646 #ifdef CONFIG_PM
2647 .suspend = rtl8139_suspend,
2648 .resume = rtl8139_resume,
2649 #endif /* CONFIG_PM */
2650 };
2651
2652
2653 static int __init rtl8139_init_module (void)
2654 {
2655 /* when we're a module, we always print a version message,
2656 * even if no 8139 board is found.
2657 */
2658 #ifdef MODULE
2659 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2660 #endif
2661
2662 return pci_module_init (&rtl8139_pci_driver);
2663 }
2664
2665
2666 static void __exit rtl8139_cleanup_module (void)
2667 {
2668 pci_unregister_driver (&rtl8139_pci_driver);
2669 }
2670
2671
2672 module_init(rtl8139_init_module);
2673 module_exit(rtl8139_cleanup_module);
MOXA 2.6.9 from sdlinux-moxaart.tgz