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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / mtd / chips / jedec_probe.c
blobbf9091277aecfd4fee426ca30f299852c7026a25
1 /*
2 Common Flash Interface probe code.
3 (C) 2000 Red Hat. GPL'd.
4 $Id: jedec_probe.c,v 1.51 2004/07/14 14:44:30 thayne Exp $
5 See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5)
6 for the standard this probe goes back to.
7
8 Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
9 */
10
11 #include <linux/config.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <asm/io.h>
18 #include <asm/byteorder.h>
19 #include <linux/errno.h>
20 #include <linux/slab.h>
21 #include <linux/interrupt.h>
22 #include <linux/init.h>
23
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/map.h>
26 #include <linux/mtd/cfi.h>
27 #include <linux/mtd/gen_probe.h>
28
29 /* Manufacturers */
30 #define MANUFACTURER_AMD 0x0001
31 #define MANUFACTURER_ATMEL 0x001f
32 #define MANUFACTURER_FUJITSU 0x0004
33 #define MANUFACTURER_HYUNDAI 0x00AD
34 #define MANUFACTURER_INTEL 0x0089
35 #define MANUFACTURER_MACRONIX 0x00C2
36 #define MANUFACTURER_PMC 0x009D
37 #define MANUFACTURER_SST 0x00BF
38 #define MANUFACTURER_ST 0x0020
39 #define MANUFACTURER_TOSHIBA 0x0098
40 #define MANUFACTURER_WINBOND 0x00da
41
42
43 /* AMD */
44 #define AM29DL800BB 0x22C8
45 #define AM29DL800BT 0x224A
46
47 #define AM29F800BB 0x2258
48 #define AM29F800BT 0x22D6
49 #define AM29LV400BB 0x22BA
50 #define AM29LV400BT 0x22B9
51 #define AM29LV800BB 0x225B
52 #define AM29LV800BT 0x22DA
53 #define AM29LV160DT 0x22C4
54 #define AM29LV160DB 0x2249
55 #define AM29F017D 0x003D
56 #define AM29F016D 0x00AD
57 #define AM29F080 0x00D5
58 #define AM29F040 0x00A4
59 #define AM29LV040B 0x004F
60 #define AM29F032B 0x0041
61 #define AM29F002T 0x00B0
62
63 /* Atmel */
64 #define AT49BV512 0x0003
65 #define AT29LV512 0x003d
66 #define AT49BV16X 0x00C0
67 #define AT49BV16XT 0x00C2
68 #define AT49BV32X 0x00C8
69 #define AT49BV32XT 0x00C9
70
71 /* Fujitsu */
72 #define MBM29F040C 0x00A4
73 #define MBM29LV650UE 0x22D7
74 #define MBM29LV320TE 0x22F6
75 #define MBM29LV320BE 0x22F9
76 #define MBM29LV160TE 0x22C4
77 #define MBM29LV160BE 0x2249
78 #define MBM29LV800BA 0x225B
79 #define MBM29LV800TA 0x22DA
80 #define MBM29LV400TC 0x22B9
81 #define MBM29LV400BC 0x22BA
82
83 /* Hyundai */
84 #define HY29F002T 0x00B0
85
86 /* Intel */
87 #define I28F004B3T 0x00d4
88 #define I28F004B3B 0x00d5
89 #define I28F400B3T 0x8894
90 #define I28F400B3B 0x8895
91 #define I28F008S5 0x00a6
92 #define I28F016S5 0x00a0
93 #define I28F008SA 0x00a2
94 #define I28F008B3T 0x00d2
95 #define I28F008B3B 0x00d3
96 #define I28F800B3T 0x8892
97 #define I28F800B3B 0x8893
98 #define I28F016S3 0x00aa
99 #define I28F016B3T 0x00d0
100 #define I28F016B3B 0x00d1
101 #define I28F160B3T 0x8890
102 #define I28F160B3B 0x8891
103 #define I28F320B3T 0x8896
104 #define I28F320B3B 0x8897
105 #define I28F640B3T 0x8898
106 #define I28F640B3B 0x8899
107 #define I82802AB 0x00ad
108 #define I82802AC 0x00ac
109
110 /* Macronix */
111 #define MX29LV160T 0x22C4
112 #define MX29LV160B 0x2249
113 #define MX29F016 0x00AD
114 #define MX29F002T 0x00B0
115 #define MX29F004T 0x0045
116 #define MX29F004B 0x0046
117
118 /* PMC */
119 #define PM49FL002 0x006D
120 #define PM49FL004 0x006E
121 #define PM49FL008 0x006A
122
123 /* ST - www.st.com */
124 #define M29W800DT 0x00D7
125 #define M29W800DB 0x005B
126 #define M29W160DT 0x22C4
127 #define M29W160DB 0x2249
128 #define M29W040B 0x00E3
129 #define M50FW040 0x002C
130 #define M50FW080 0x002D
131 #define M50FW016 0x002E
132
133 /* SST */
134 #define SST29EE020 0x0010
135 #define SST29LE020 0x0012
136 #define SST29EE512 0x005d
137 #define SST29LE512 0x003d
138 #define SST39LF800 0x2781
139 #define SST39LF160 0x2782
140 #define SST39LF512 0x00D4
141 #define SST39LF010 0x00D5
142 #define SST39LF020 0x00D6
143 #define SST39LF040 0x00D7
144 #define SST39SF010A 0x00B5
145 #define SST39SF020A 0x00B6
146 #define SST49LF004B 0x0060
147 #define SST49LF008A 0x005a
148 #define SST49LF030A 0x001C
149 #define SST49LF040A 0x0051
150 #define SST49LF080A 0x005B
151
152 /* Toshiba */
153 #define TC58FVT160 0x00C2
154 #define TC58FVB160 0x0043
155 #define TC58FVT321 0x009A
156 #define TC58FVB321 0x009C
157 #define TC58FVT641 0x0093
158 #define TC58FVB641 0x0095
159
160 /* Winbond */
161 #define W49V002A 0x00b0
162
163
164 /*
165 * Unlock address sets for AMD command sets.
166 * Intel command sets use the MTD_UADDR_UNNECESSARY.
167 * Each identifier, except MTD_UADDR_UNNECESSARY, and
168 * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
169 * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
170 * initialization need not require initializing all of the
171 * unlock addresses for all bit widths.
172 */
173 enum uaddr {
174 MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
175 MTD_UADDR_0x0555_0x02AA,
176 MTD_UADDR_0x0555_0x0AAA,
177 MTD_UADDR_0x5555_0x2AAA,
178 MTD_UADDR_0x0AAA_0x0555,
179 MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
180 MTD_UADDR_UNNECESSARY, /* Does not require any address */
181 };
182
183
184 struct unlock_addr {
185 int addr1;
186 int addr2;
187 };
188
189
190 /*
191 * I don't like the fact that the first entry in unlock_addrs[]
192 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
193 * should not be used. The problem is that structures with
194 * initializers have extra fields initialized to 0. It is _very_
195 * desireable to have the unlock address entries for unsupported
196 * data widths automatically initialized - that means that
197 * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
198 * must go unused.
199 */
200 static const struct unlock_addr unlock_addrs[] = {
201 [MTD_UADDR_NOT_SUPPORTED] = {
202 .addr1 = 0xffff,
203 .addr2 = 0xffff
204 },
205
206 [MTD_UADDR_0x0555_0x02AA] = {
207 .addr1 = 0x0555,
208 .addr2 = 0x02aa
209 },
210
211 [MTD_UADDR_0x0555_0x0AAA] = {
212 .addr1 = 0x0555,
213 .addr2 = 0x0aaa
214 },
215
216 [MTD_UADDR_0x5555_0x2AAA] = {
217 .addr1 = 0x5555,
218 .addr2 = 0x2aaa
219 },
220
221 [MTD_UADDR_0x0AAA_0x0555] = {
222 .addr1 = 0x0AAA,
223 .addr2 = 0x0555
224 },
225
226 [MTD_UADDR_DONT_CARE] = {
227 .addr1 = 0x0000, /* Doesn't matter which address */
228 .addr2 = 0x0000 /* is used - must be last entry */
229 }
230 };
231
232
233 struct amd_flash_info {
234 const __u16 mfr_id;
235 const __u16 dev_id;
236 const char *name;
237 const int DevSize;
238 const int NumEraseRegions;
239 const int CmdSet;
240 const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */
241 const ulong regions[6];
242 };
243
244 #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
245
246 #define SIZE_64KiB 16
247 #define SIZE_128KiB 17
248 #define SIZE_256KiB 18
249 #define SIZE_512KiB 19
250 #define SIZE_1MiB 20
251 #define SIZE_2MiB 21
252 #define SIZE_4MiB 22
253 #define SIZE_8MiB 23
254
255
256 /*
257 * Please keep this list ordered by manufacturer!
258 * Fortunately, the list isn't searched often and so a
259 * slow, linear search isn't so bad.
260 */
261 static const struct amd_flash_info jedec_table[] = {
262 {
263 .mfr_id = MANUFACTURER_AMD,
264 .dev_id = AM29LV004T,
265 .name = "AMD AM29LV004T",
266 .uaddr = {
267 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
268 },
269 .DevSize = SIZE_512KiB,
270 .CmdSet = P_ID_AMD_STD,
271 .NumEraseRegions= 4,
272 .regions = {
273 ERASEINFO(0x10000,7),
274 ERASEINFO(0x08000,1),
275 ERASEINFO(0x02000,2),
276 ERASEINFO(0x04000,1)
277 }
278 }, {
279 .mfr_id = MANUFACTURER_AMD,
280 .dev_id = AM29LV004B,
281 .name = "AMD AM29LV004B",
282 .uaddr = {
283 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
284 },
285 .DevSize = SIZE_512KiB,
286 .CmdSet = P_ID_AMD_STD,
287 .NumEraseRegions= 4,
288 .regions = {
289 ERASEINFO(0x04000,1),
290 ERASEINFO(0x02000,2),
291 ERASEINFO(0x08000,1),
292 ERASEINFO(0x10000,7)
293 }
294 }, {
295 .mfr_id = MANUFACTURER_AMD,
296 .dev_id = AM29F032B,
297 .name = "AMD AM29F032B",
298 .uaddr = {
299 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
300 },
301 .DevSize = SIZE_4MiB,
302 .CmdSet = P_ID_AMD_STD,
303 .NumEraseRegions= 1,
304 .regions = {
305 ERASEINFO(0x10000,64)
306 }
307 }, {
308 .mfr_id = MANUFACTURER_AMD,
309 .dev_id = AM29LV160DT,
310 .name = "AMD AM29LV160DT",
311 .uaddr = {
312 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
313 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
314 },
315 .DevSize = SIZE_2MiB,
316 .CmdSet = P_ID_AMD_STD,
317 .NumEraseRegions= 4,
318 .regions = {
319 ERASEINFO(0x10000,31),
320 ERASEINFO(0x08000,1),
321 ERASEINFO(0x02000,2),
322 ERASEINFO(0x04000,1)
323 }
324 }, {
325 .mfr_id = MANUFACTURER_AMD,
326 .dev_id = AM29LV160DB,
327 .name = "AMD AM29LV160DB",
328 .uaddr = {
329 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
330 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
331 },
332 .DevSize = SIZE_2MiB,
333 .CmdSet = P_ID_AMD_STD,
334 .NumEraseRegions= 4,
335 .regions = {
336 ERASEINFO(0x04000,1),
337 ERASEINFO(0x02000,2),
338 ERASEINFO(0x08000,1),
339 ERASEINFO(0x10000,31)
340 }
341 }, {
342 .mfr_id = MANUFACTURER_AMD,
343 .dev_id = AM29LV400BB,
344 .name = "AMD AM29LV400BB",
345 .uaddr = {
346 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
347 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
348 },
349 .DevSize = SIZE_512KiB,
350 .CmdSet = P_ID_AMD_STD,
351 .NumEraseRegions= 4,
352 .regions = {
353 ERASEINFO(0x04000,1),
354 ERASEINFO(0x02000,2),
355 ERASEINFO(0x08000,1),
356 ERASEINFO(0x10000,7)
357 }
358 }, {
359 .mfr_id = MANUFACTURER_AMD,
360 .dev_id = AM29LV400BT,
361 .name = "AMD AM29LV400BT",
362 .uaddr = {
363 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
364 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
365 },
366 .DevSize = SIZE_512KiB,
367 .CmdSet = P_ID_AMD_STD,
368 .NumEraseRegions= 4,
369 .regions = {
370 ERASEINFO(0x10000,7),
371 ERASEINFO(0x08000,1),
372 ERASEINFO(0x02000,2),
373 ERASEINFO(0x04000,1)
374 }
375 }, {
376 .mfr_id = MANUFACTURER_AMD,
377 .dev_id = AM29LV800BB,
378 .name = "AMD AM29LV800BB",
379 .uaddr = {
380 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
381 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
382 },
383 .DevSize = SIZE_1MiB,
384 .CmdSet = P_ID_AMD_STD,
385 .NumEraseRegions= 4,
386 .regions = {
387 ERASEINFO(0x04000,1),
388 ERASEINFO(0x02000,2),
389 ERASEINFO(0x08000,1),
390 ERASEINFO(0x10000,15),
391 }
392 }, {
393 /* add DL */
394 .mfr_id = MANUFACTURER_AMD,
395 .dev_id = AM29DL800BB,
396 .name = "AMD AM29DL800BB",
397 .uaddr = {
398 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
399 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
400 },
401 .DevSize = SIZE_1MiB,
402 .CmdSet = P_ID_AMD_STD,
403 .NumEraseRegions= 6,
404 .regions = {
405 ERASEINFO(0x04000,1),
406 ERASEINFO(0x08000,1),
407 ERASEINFO(0x02000,4),
408 ERASEINFO(0x08000,1),
409 ERASEINFO(0x04000,1),
410 ERASEINFO(0x10000,14)
411 }
412 }, {
413 .mfr_id = MANUFACTURER_AMD,
414 .dev_id = AM29DL800BT,
415 .name = "AMD AM29DL800BT",
416 .uaddr = {
417 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
418 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
419 },
420 .DevSize = SIZE_1MiB,
421 .CmdSet = P_ID_AMD_STD,
422 .NumEraseRegions= 6,
423 .regions = {
424 ERASEINFO(0x10000,14),
425 ERASEINFO(0x04000,1),
426 ERASEINFO(0x08000,1),
427 ERASEINFO(0x02000,4),
428 ERASEINFO(0x08000,1),
429 ERASEINFO(0x04000,1)
430 }
431 }, {
432 .mfr_id = MANUFACTURER_AMD,
433 .dev_id = AM29F800BB,
434 .name = "AMD AM29F800BB",
435 .uaddr = {
436 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
437 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
438 },
439 .DevSize = SIZE_1MiB,
440 .CmdSet = P_ID_AMD_STD,
441 .NumEraseRegions= 4,
442 .regions = {
443 ERASEINFO(0x04000,1),
444 ERASEINFO(0x02000,2),
445 ERASEINFO(0x08000,1),
446 ERASEINFO(0x10000,15),
447 }
448 }, {
449 .mfr_id = MANUFACTURER_AMD,
450 .dev_id = AM29LV800BT,
451 .name = "AMD AM29LV800BT",
452 .uaddr = {
453 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
454 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
455 },
456 .DevSize = SIZE_1MiB,
457 .CmdSet = P_ID_AMD_STD,
458 .NumEraseRegions= 4,
459 .regions = {
460 ERASEINFO(0x10000,15),
461 ERASEINFO(0x08000,1),
462 ERASEINFO(0x02000,2),
463 ERASEINFO(0x04000,1)
464 }
465 }, {
466 .mfr_id = MANUFACTURER_AMD,
467 .dev_id = AM29F800BT,
468 .name = "AMD AM29F800BT",
469 .uaddr = {
470 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
471 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
472 },
473 .DevSize = SIZE_1MiB,
474 .CmdSet = P_ID_AMD_STD,
475 .NumEraseRegions= 4,
476 .regions = {
477 ERASEINFO(0x10000,15),
478 ERASEINFO(0x08000,1),
479 ERASEINFO(0x02000,2),
480 ERASEINFO(0x04000,1)
481 }
482 }, {
483 .mfr_id = MANUFACTURER_AMD,
484 .dev_id = AM29F017D,
485 .name = "AMD AM29F017D",
486 .uaddr = {
487 [0] = MTD_UADDR_DONT_CARE /* x8 */
488 },
489 .DevSize = SIZE_2MiB,
490 .CmdSet = P_ID_AMD_STD,
491 .NumEraseRegions= 1,
492 .regions = {
493 ERASEINFO(0x10000,32),
494 }
495 }, {
496 .mfr_id = MANUFACTURER_AMD,
497 .dev_id = AM29F016D,
498 .name = "AMD AM29F016D",
499 .uaddr = {
500 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
501 },
502 .DevSize = SIZE_2MiB,
503 .CmdSet = P_ID_AMD_STD,
504 .NumEraseRegions= 1,
505 .regions = {
506 ERASEINFO(0x10000,32),
507 }
508 }, {
509 .mfr_id = MANUFACTURER_AMD,
510 .dev_id = AM29F080,
511 .name = "AMD AM29F080",
512 .uaddr = {
513 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
514 },
515 .DevSize = SIZE_1MiB,
516 .CmdSet = P_ID_AMD_STD,
517 .NumEraseRegions= 1,
518 .regions = {
519 ERASEINFO(0x10000,16),
520 }
521 }, {
522 .mfr_id = MANUFACTURER_AMD,
523 .dev_id = AM29F040,
524 .name = "AMD AM29F040",
525 .uaddr = {
526 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
527 },
528 .DevSize = SIZE_512KiB,
529 .CmdSet = P_ID_AMD_STD,
530 .NumEraseRegions= 1,
531 .regions = {
532 ERASEINFO(0x10000,8),
533 }
534 }, {
535 .mfr_id = MANUFACTURER_AMD,
536 .dev_id = AM29LV040B,
537 .name = "AMD AM29LV040B",
538 .uaddr = {
539 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
540 },
541 .DevSize = SIZE_512KiB,
542 .CmdSet = P_ID_AMD_STD,
543 .NumEraseRegions= 1,
544 .regions = {
545 ERASEINFO(0x10000,8),
546 }
547 }, {
548 .mfr_id = MANUFACTURER_AMD,
549 .dev_id = AM29F002T,
550 .name = "AMD AM29F002T",
551 .DevSize = SIZE_256KiB,
552 .NumEraseRegions = 4,
553 .regions = {ERASEINFO(0x10000,3),
554 ERASEINFO(0x08000,1),
555 ERASEINFO(0x02000,2),
556 ERASEINFO(0x04000,1)
557 }
558 }, {
559 .mfr_id = MANUFACTURER_ATMEL,
560 .dev_id = AT49BV512,
561 .name = "Atmel AT49BV512",
562 .uaddr = {
563 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
564 },
565 .DevSize = SIZE_64KiB,
566 .CmdSet = P_ID_AMD_STD,
567 .NumEraseRegions= 1,
568 .regions = {
569 ERASEINFO(0x10000,1)
570 }
571 }, {
572 .mfr_id = MANUFACTURER_ATMEL,
573 .dev_id = AT29LV512,
574 .name = "Atmel AT29LV512",
575 .uaddr = {
576 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
577 },
578 .DevSize = SIZE_64KiB,
579 .CmdSet = P_ID_AMD_STD,
580 .NumEraseRegions= 1,
581 .regions = {
582 ERASEINFO(0x80,256),
583 ERASEINFO(0x80,256)
584 }
585 }, {
586 .mfr_id = MANUFACTURER_ATMEL,
587 .dev_id = AT49BV16X,
588 .name = "Atmel AT49BV16X",
589 .uaddr = {
590 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
591 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
592 },
593 .DevSize = SIZE_2MiB,
594 .CmdSet = P_ID_AMD_STD,
595 .NumEraseRegions= 2,
596 .regions = {
597 ERASEINFO(0x02000,8),
598 ERASEINFO(0x10000,31)
599 }
600 }, {
601 .mfr_id = MANUFACTURER_ATMEL,
602 .dev_id = AT49BV16XT,
603 .name = "Atmel AT49BV16XT",
604 .uaddr = {
605 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
606 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
607 },
608 .DevSize = SIZE_2MiB,
609 .CmdSet = P_ID_AMD_STD,
610 .NumEraseRegions= 2,
611 .regions = {
612 ERASEINFO(0x10000,31),
613 ERASEINFO(0x02000,8)
614 }
615 }, {
616 .mfr_id = MANUFACTURER_ATMEL,
617 .dev_id = AT49BV32X,
618 .name = "Atmel AT49BV32X",
619 .uaddr = {
620 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
621 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
622 },
623 .DevSize = SIZE_4MiB,
624 .CmdSet = P_ID_AMD_STD,
625 .NumEraseRegions= 2,
626 .regions = {
627 ERASEINFO(0x02000,8),
628 ERASEINFO(0x10000,63)
629 }
630 }, {
631 .mfr_id = MANUFACTURER_ATMEL,
632 .dev_id = AT49BV32XT,
633 .name = "Atmel AT49BV32XT",
634 .uaddr = {
635 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
636 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
637 },
638 .DevSize = SIZE_4MiB,
639 .CmdSet = P_ID_AMD_STD,
640 .NumEraseRegions= 2,
641 .regions = {
642 ERASEINFO(0x10000,63),
643 ERASEINFO(0x02000,8)
644 }
645 }, {
646 .mfr_id = MANUFACTURER_FUJITSU,
647 .dev_id = MBM29F040C,
648 .name = "Fujitsu MBM29F040C",
649 .uaddr = {
650 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
651 },
652 .DevSize = SIZE_512KiB,
653 .CmdSet = P_ID_AMD_STD,
654 .NumEraseRegions= 1,
655 .regions = {
656 ERASEINFO(0x10000,8)
657 }
658 }, {
659 .mfr_id = MANUFACTURER_FUJITSU,
660 .dev_id = MBM29LV650UE,
661 .name = "Fujitsu MBM29LV650UE",
662 .uaddr = {
663 [0] = MTD_UADDR_DONT_CARE /* x16 */
664 },
665 .DevSize = SIZE_8MiB,
666 .CmdSet = P_ID_AMD_STD,
667 .NumEraseRegions= 1,
668 .regions = {
669 ERASEINFO(0x10000,128)
670 }
671 }, {
672 .mfr_id = MANUFACTURER_FUJITSU,
673 .dev_id = MBM29LV320TE,
674 .name = "Fujitsu MBM29LV320TE",
675 .uaddr = {
676 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
677 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
678 },
679 .DevSize = SIZE_4MiB,
680 .CmdSet = P_ID_AMD_STD,
681 .NumEraseRegions= 2,
682 .regions = {
683 ERASEINFO(0x10000,63),
684 ERASEINFO(0x02000,8)
685 }
686 }, {
687 .mfr_id = MANUFACTURER_FUJITSU,
688 .dev_id = MBM29LV320BE,
689 .name = "Fujitsu MBM29LV320BE",
690 .uaddr = {
691 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
692 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
693 },
694 .DevSize = SIZE_4MiB,
695 .CmdSet = P_ID_AMD_STD,
696 .NumEraseRegions= 2,
697 .regions = {
698 ERASEINFO(0x02000,8),
699 ERASEINFO(0x10000,63)
700 }
701 }, {
702 .mfr_id = MANUFACTURER_FUJITSU,
703 .dev_id = MBM29LV160TE,
704 .name = "Fujitsu MBM29LV160TE",
705 .uaddr = {
706 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
707 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
708 },
709 .DevSize = SIZE_2MiB,
710 .CmdSet = P_ID_AMD_STD,
711 .NumEraseRegions= 4,
712 .regions = {
713 ERASEINFO(0x10000,31),
714 ERASEINFO(0x08000,1),
715 ERASEINFO(0x02000,2),
716 ERASEINFO(0x04000,1)
717 }
718 }, {
719 .mfr_id = MANUFACTURER_FUJITSU,
720 .dev_id = MBM29LV160BE,
721 .name = "Fujitsu MBM29LV160BE",
722 .uaddr = {
723 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
724 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
725 },
726 .DevSize = SIZE_2MiB,
727 .CmdSet = P_ID_AMD_STD,
728 .NumEraseRegions= 4,
729 .regions = {
730 ERASEINFO(0x04000,1),
731 ERASEINFO(0x02000,2),
732 ERASEINFO(0x08000,1),
733 ERASEINFO(0x10000,31)
734 }
735 }, {
736 .mfr_id = MANUFACTURER_FUJITSU,
737 .dev_id = MBM29LV800BA,
738 .name = "Fujitsu MBM29LV800BA",
739 .uaddr = {
740 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
741 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
742 },
743 .DevSize = SIZE_1MiB,
744 .CmdSet = P_ID_AMD_STD,
745 .NumEraseRegions= 4,
746 .regions = {
747 ERASEINFO(0x04000,1),
748 ERASEINFO(0x02000,2),
749 ERASEINFO(0x08000,1),
750 ERASEINFO(0x10000,15)
751 }
752 }, {
753 .mfr_id = MANUFACTURER_FUJITSU,
754 .dev_id = MBM29LV800TA,
755 .name = "Fujitsu MBM29LV800TA",
756 .uaddr = {
757 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
758 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
759 },
760 .DevSize = SIZE_1MiB,
761 .CmdSet = P_ID_AMD_STD,
762 .NumEraseRegions= 4,
763 .regions = {
764 ERASEINFO(0x10000,15),
765 ERASEINFO(0x08000,1),
766 ERASEINFO(0x02000,2),
767 ERASEINFO(0x04000,1)
768 }
769 }, {
770 .mfr_id = MANUFACTURER_FUJITSU,
771 .dev_id = MBM29LV400BC,
772 .name = "Fujitsu MBM29LV400BC",
773 .uaddr = {
774 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
775 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
776 },
777 .DevSize = SIZE_512KiB,
778 .CmdSet = P_ID_AMD_STD,
779 .NumEraseRegions= 4,
780 .regions = {
781 ERASEINFO(0x04000,1),
782 ERASEINFO(0x02000,2),
783 ERASEINFO(0x08000,1),
784 ERASEINFO(0x10000,7)
785 }
786 }, {
787 .mfr_id = MANUFACTURER_FUJITSU,
788 .dev_id = MBM29LV400TC,
789 .name = "Fujitsu MBM29LV400TC",
790 .uaddr = {
791 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
792 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
793 },
794 .DevSize = SIZE_512KiB,
795 .CmdSet = P_ID_AMD_STD,
796 .NumEraseRegions= 4,
797 .regions = {
798 ERASEINFO(0x10000,7),
799 ERASEINFO(0x08000,1),
800 ERASEINFO(0x02000,2),
801 ERASEINFO(0x04000,1)
802 }
803 }, {
804 .mfr_id = MANUFACTURER_HYUNDAI,
805 .dev_id = HY29F002T,
806 .name = "Hyundai HY29F002T",
807 .DevSize = SIZE_256KiB,
808 .NumEraseRegions = 4,
809 .regions = {ERASEINFO(0x10000,3),
810 ERASEINFO(0x08000,1),
811 ERASEINFO(0x02000,2),
812 ERASEINFO(0x04000,1)
813 }
814 }, {
815 .mfr_id = MANUFACTURER_INTEL,
816 .dev_id = I28F004B3B,
817 .name = "Intel 28F004B3B",
818 .uaddr = {
819 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
820 },
821 .DevSize = SIZE_512KiB,
822 .CmdSet = P_ID_INTEL_STD,
823 .NumEraseRegions= 2,
824 .regions = {
825 ERASEINFO(0x02000, 8),
826 ERASEINFO(0x10000, 7),
827 }
828 }, {
829 .mfr_id = MANUFACTURER_INTEL,
830 .dev_id = I28F004B3T,
831 .name = "Intel 28F004B3T",
832 .uaddr = {
833 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
834 },
835 .DevSize = SIZE_512KiB,
836 .CmdSet = P_ID_INTEL_STD,
837 .NumEraseRegions= 2,
838 .regions = {
839 ERASEINFO(0x10000, 7),
840 ERASEINFO(0x02000, 8),
841 }
842 }, {
843 .mfr_id = MANUFACTURER_INTEL,
844 .dev_id = I28F400B3B,
845 .name = "Intel 28F400B3B",
846 .uaddr = {
847 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
848 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
849 },
850 .DevSize = SIZE_512KiB,
851 .CmdSet = P_ID_INTEL_STD,
852 .NumEraseRegions= 2,
853 .regions = {
854 ERASEINFO(0x02000, 8),
855 ERASEINFO(0x10000, 7),
856 }
857 }, {
858 .mfr_id = MANUFACTURER_INTEL,
859 .dev_id = I28F400B3T,
860 .name = "Intel 28F400B3T",
861 .uaddr = {
862 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
863 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
864 },
865 .DevSize = SIZE_512KiB,
866 .CmdSet = P_ID_INTEL_STD,
867 .NumEraseRegions= 2,
868 .regions = {
869 ERASEINFO(0x10000, 7),
870 ERASEINFO(0x02000, 8),
871 }
872 }, {
873 .mfr_id = MANUFACTURER_INTEL,
874 .dev_id = I28F008B3B,
875 .name = "Intel 28F008B3B",
876 .uaddr = {
877 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
878 },
879 .DevSize = SIZE_1MiB,
880 .CmdSet = P_ID_INTEL_STD,
881 .NumEraseRegions= 2,
882 .regions = {
883 ERASEINFO(0x02000, 8),
884 ERASEINFO(0x10000, 15),
885 }
886 }, {
887 .mfr_id = MANUFACTURER_INTEL,
888 .dev_id = I28F008B3T,
889 .name = "Intel 28F008B3T",
890 .uaddr = {
891 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
892 },
893 .DevSize = SIZE_1MiB,
894 .CmdSet = P_ID_INTEL_STD,
895 .NumEraseRegions= 2,
896 .regions = {
897 ERASEINFO(0x10000, 15),
898 ERASEINFO(0x02000, 8),
899 }
900 }, {
901 .mfr_id = MANUFACTURER_INTEL,
902 .dev_id = I28F008S5,
903 .name = "Intel 28F008S5",
904 .uaddr = {
905 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
906 },
907 .DevSize = SIZE_1MiB,
908 .CmdSet = P_ID_INTEL_EXT,
909 .NumEraseRegions= 1,
910 .regions = {
911 ERASEINFO(0x10000,16),
912 }
913 }, {
914 .mfr_id = MANUFACTURER_INTEL,
915 .dev_id = I28F016S5,
916 .name = "Intel 28F016S5",
917 .uaddr = {
918 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
919 },
920 .DevSize = SIZE_2MiB,
921 .CmdSet = P_ID_INTEL_EXT,
922 .NumEraseRegions= 1,
923 .regions = {
924 ERASEINFO(0x10000,32),
925 }
926 }, {
927 .mfr_id = MANUFACTURER_INTEL,
928 .dev_id = I28F008SA,
929 .name = "Intel 28F008SA",
930 .uaddr = {
931 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
932 },
933 .DevSize = SIZE_1MiB,
934 .CmdSet = P_ID_INTEL_STD,
935 .NumEraseRegions= 1,
936 .regions = {
937 ERASEINFO(0x10000, 16),
938 }
939 }, {
940 .mfr_id = MANUFACTURER_INTEL,
941 .dev_id = I28F800B3B,
942 .name = "Intel 28F800B3B",
943 .uaddr = {
944 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
945 },
946 .DevSize = SIZE_1MiB,
947 .CmdSet = P_ID_INTEL_STD,
948 .NumEraseRegions= 2,
949 .regions = {
950 ERASEINFO(0x02000, 8),
951 ERASEINFO(0x10000, 15),
952 }
953 }, {
954 .mfr_id = MANUFACTURER_INTEL,
955 .dev_id = I28F800B3T,
956 .name = "Intel 28F800B3T",
957 .uaddr = {
958 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
959 },
960 .DevSize = SIZE_1MiB,
961 .CmdSet = P_ID_INTEL_STD,
962 .NumEraseRegions= 2,
963 .regions = {
964 ERASEINFO(0x10000, 15),
965 ERASEINFO(0x02000, 8),
966 }
967 }, {
968 .mfr_id = MANUFACTURER_INTEL,
969 .dev_id = I28F016B3B,
970 .name = "Intel 28F016B3B",
971 .uaddr = {
972 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
973 },
974 .DevSize = SIZE_2MiB,
975 .CmdSet = P_ID_INTEL_STD,
976 .NumEraseRegions= 2,
977 .regions = {
978 ERASEINFO(0x02000, 8),
979 ERASEINFO(0x10000, 31),
980 }
981 }, {
982 .mfr_id = MANUFACTURER_INTEL,
983 .dev_id = I28F016S3,
984 .name = "Intel I28F016S3",
985 .uaddr = {
986 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
987 },
988 .DevSize = SIZE_2MiB,
989 .CmdSet = P_ID_INTEL_STD,
990 .NumEraseRegions= 1,
991 .regions = {
992 ERASEINFO(0x10000, 32),
993 }
994 }, {
995 .mfr_id = MANUFACTURER_INTEL,
996 .dev_id = I28F016B3T,
997 .name = "Intel 28F016B3T",
998 .uaddr = {
999 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1000 },
1001 .DevSize = SIZE_2MiB,
1002 .CmdSet = P_ID_INTEL_STD,
1003 .NumEraseRegions= 2,
1004 .regions = {
1005 ERASEINFO(0x10000, 31),
1006 ERASEINFO(0x02000, 8),
1007 }
1008 }, {
1009 .mfr_id = MANUFACTURER_INTEL,
1010 .dev_id = I28F160B3B,
1011 .name = "Intel 28F160B3B",
1012 .uaddr = {
1013 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1014 },
1015 .DevSize = SIZE_2MiB,
1016 .CmdSet = P_ID_INTEL_STD,
1017 .NumEraseRegions= 2,
1018 .regions = {
1019 ERASEINFO(0x02000, 8),
1020 ERASEINFO(0x10000, 31),
1021 }
1022 }, {
1023 .mfr_id = MANUFACTURER_INTEL,
1024 .dev_id = I28F160B3T,
1025 .name = "Intel 28F160B3T",
1026 .uaddr = {
1027 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1028 },
1029 .DevSize = SIZE_2MiB,
1030 .CmdSet = P_ID_INTEL_STD,
1031 .NumEraseRegions= 2,
1032 .regions = {
1033 ERASEINFO(0x10000, 31),
1034 ERASEINFO(0x02000, 8),
1035 }
1036 }, {
1037 .mfr_id = MANUFACTURER_INTEL,
1038 .dev_id = I28F320B3B,
1039 .name = "Intel 28F320B3B",
1040 .uaddr = {
1041 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1042 },
1043 .DevSize = SIZE_4MiB,
1044 .CmdSet = P_ID_INTEL_STD,
1045 .NumEraseRegions= 2,
1046 .regions = {
1047 ERASEINFO(0x02000, 8),
1048 ERASEINFO(0x10000, 63),
1049 }
1050 }, {
1051 .mfr_id = MANUFACTURER_INTEL,
1052 .dev_id = I28F320B3T,
1053 .name = "Intel 28F320B3T",
1054 .uaddr = {
1055 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1056 },
1057 .DevSize = SIZE_4MiB,
1058 .CmdSet = P_ID_INTEL_STD,
1059 .NumEraseRegions= 2,
1060 .regions = {
1061 ERASEINFO(0x10000, 63),
1062 ERASEINFO(0x02000, 8),
1063 }
1064 }, {
1065 .mfr_id = MANUFACTURER_INTEL,
1066 .dev_id = I28F640B3B,
1067 .name = "Intel 28F640B3B",
1068 .uaddr = {
1069 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1070 },
1071 .DevSize = SIZE_8MiB,
1072 .CmdSet = P_ID_INTEL_STD,
1073 .NumEraseRegions= 2,
1074 .regions = {
1075 ERASEINFO(0x02000, 8),
1076 ERASEINFO(0x10000, 127),
1077 }
1078 }, {
1079 .mfr_id = MANUFACTURER_INTEL,
1080 .dev_id = I28F640B3T,
1081 .name = "Intel 28F640B3T",
1082 .uaddr = {
1083 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1084 },
1085 .DevSize = SIZE_8MiB,
1086 .CmdSet = P_ID_INTEL_STD,
1087 .NumEraseRegions= 2,
1088 .regions = {
1089 ERASEINFO(0x10000, 127),
1090 ERASEINFO(0x02000, 8),
1091 }
1092 }, {
1093 .mfr_id = MANUFACTURER_INTEL,
1094 .dev_id = I82802AB,
1095 .name = "Intel 82802AB",
1096 .uaddr = {
1097 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1098 },
1099 .DevSize = SIZE_512KiB,
1100 .CmdSet = P_ID_INTEL_EXT,
1101 .NumEraseRegions= 1,
1102 .regions = {
1103 ERASEINFO(0x10000,8),
1104 }
1105 }, {
1106 .mfr_id = MANUFACTURER_INTEL,
1107 .dev_id = I82802AC,
1108 .name = "Intel 82802AC",
1109 .uaddr = {
1110 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1111 },
1112 .DevSize = SIZE_1MiB,
1113 .CmdSet = P_ID_INTEL_EXT,
1114 .NumEraseRegions= 1,
1115 .regions = {
1116 ERASEINFO(0x10000,16),
1117 }
1118 }, {
1119 .mfr_id = MANUFACTURER_MACRONIX,
1120 .dev_id = MX29LV160T,
1121 .name = "MXIC MX29LV160T",
1122 .uaddr = {
1123 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1124 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1125 },
1126 .DevSize = SIZE_2MiB,
1127 .CmdSet = P_ID_AMD_STD,
1128 .NumEraseRegions= 4,
1129 .regions = {
1130 ERASEINFO(0x10000,31),
1131 ERASEINFO(0x08000,1),
1132 ERASEINFO(0x02000,2),
1133 ERASEINFO(0x04000,1)
1134 }
1135 }, {
1136 .mfr_id = MANUFACTURER_MACRONIX,
1137 .dev_id = MX29LV160B,
1138 .name = "MXIC MX29LV160B",
1139 .uaddr = {
1140 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1141 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1142 },
1143 .DevSize = SIZE_2MiB,
1144 .CmdSet = P_ID_AMD_STD,
1145 .NumEraseRegions= 4,
1146 .regions = {
1147 ERASEINFO(0x04000,1),
1148 ERASEINFO(0x02000,2),
1149 ERASEINFO(0x08000,1),
1150 ERASEINFO(0x10000,31)
1151 }
1152 }, {
1153 .mfr_id = MANUFACTURER_MACRONIX,
1154 .dev_id = MX29F016,
1155 .name = "Macronix MX29F016",
1156 .uaddr = {
1157 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
1158 },
1159 .DevSize = SIZE_2MiB,
1160 .CmdSet = P_ID_AMD_STD,
1161 .NumEraseRegions= 1,
1162 .regions = {
1163 ERASEINFO(0x10000,32),
1164 }
1165 }, {
1166 .mfr_id = MANUFACTURER_MACRONIX,
1167 .dev_id = MX29F004T,
1168 .name = "Macronix MX29F004T",
1169 .uaddr = {
1170 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
1171 },
1172 .DevSize = SIZE_512KiB,
1173 .CmdSet = P_ID_AMD_STD,
1174 .NumEraseRegions= 4,
1175 .regions = {
1176 ERASEINFO(0x10000,7),
1177 ERASEINFO(0x08000,1),
1178 ERASEINFO(0x02000,2),
1179 ERASEINFO(0x04000,1),
1180 }
1181 }, {
1182 .mfr_id = MANUFACTURER_MACRONIX,
1183 .dev_id = MX29F004B,
1184 .name = "Macronix MX29F004B",
1185 .uaddr = {
1186 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
1187 },
1188 .DevSize = SIZE_512KiB,
1189 .CmdSet = P_ID_AMD_STD,
1190 .NumEraseRegions= 4,
1191 .regions = {
1192 ERASEINFO(0x04000,1),
1193 ERASEINFO(0x02000,2),
1194 ERASEINFO(0x08000,1),
1195 ERASEINFO(0x10000,7),
1196 }
1197 }, {
1198 .mfr_id = MANUFACTURER_MACRONIX,
1199 .dev_id = MX29F002T,
1200 .name = "Macronix MX29F002T",
1201 .DevSize = SIZE_256KiB,
1202 .NumEraseRegions = 4,
1203 .regions = {ERASEINFO(0x10000,3),
1204 ERASEINFO(0x08000,1),
1205 ERASEINFO(0x02000,2),
1206 ERASEINFO(0x04000,1)
1207 }
1208 }, {
1209 .mfr_id = MANUFACTURER_PMC,
1210 .dev_id = PM49FL002,
1211 .name = "PMC Pm49FL002",
1212 .uaddr = {
1213 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1214 },
1215 .DevSize = SIZE_256KiB,
1216 .CmdSet = P_ID_AMD_STD,
1217 .NumEraseRegions= 1,
1218 .regions = {
1219 ERASEINFO( 0x01000, 64 )
1220 }
1221 }, {
1222 .mfr_id = MANUFACTURER_PMC,
1223 .dev_id = PM49FL004,
1224 .name = "PMC Pm49FL004",
1225 .uaddr = {
1226 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1227 },
1228 .DevSize = SIZE_512KiB,
1229 .CmdSet = P_ID_AMD_STD,
1230 .NumEraseRegions= 1,
1231 .regions = {
1232 ERASEINFO( 0x01000, 128 )
1233 }
1234 }, {
1235 .mfr_id = MANUFACTURER_PMC,
1236 .dev_id = PM49FL008,
1237 .name = "PMC Pm49FL008",
1238 .uaddr = {
1239 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1240 },
1241 .DevSize = SIZE_1MiB,
1242 .CmdSet = P_ID_AMD_STD,
1243 .NumEraseRegions= 1,
1244 .regions = {
1245 ERASEINFO( 0x01000, 256 )
1246 }
1247 }, {
1248 .mfr_id = MANUFACTURER_SST,
1249 .dev_id = SST39LF512,
1250 .name = "SST 39LF512",
1251 .uaddr = {
1252 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1253 },
1254 .DevSize = SIZE_64KiB,
1255 .CmdSet = P_ID_AMD_STD,
1256 .NumEraseRegions= 1,
1257 .regions = {
1258 ERASEINFO(0x01000,16),
1259 }
1260 }, {
1261 .mfr_id = MANUFACTURER_SST,
1262 .dev_id = SST39LF010,
1263 .name = "SST 39LF010",
1264 .uaddr = {
1265 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1266 },
1267 .DevSize = SIZE_128KiB,
1268 .CmdSet = P_ID_AMD_STD,
1269 .NumEraseRegions= 1,
1270 .regions = {
1271 ERASEINFO(0x01000,32),
1272 }
1273 }, {
1274 .mfr_id = MANUFACTURER_SST,
1275 .dev_id = SST29EE020,
1276 .name = "SST 29EE020",
1277 .uaddr = {
1278 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1279 },
1280 .DevSize = SIZE_256KiB,
1281 .CmdSet = P_ID_SST_PAGE,
1282 .NumEraseRegions= 1,
1283 .regions = {ERASEINFO(0x01000,64),
1284 }
1285 }, {
1286 .mfr_id = MANUFACTURER_SST,
1287 .dev_id = SST29LE020,
1288 .name = "SST 29LE020",
1289 .uaddr = {
1290 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1291 },
1292 .DevSize = SIZE_256KiB,
1293 .CmdSet = P_ID_SST_PAGE,
1294 .NumEraseRegions= 1,
1295 .regions = {ERASEINFO(0x01000,64),
1296 }
1297 }, {
1298 .mfr_id = MANUFACTURER_SST,
1299 .dev_id = SST39LF020,
1300 .name = "SST 39LF020",
1301 .uaddr = {
1302 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1303 },
1304 .DevSize = SIZE_256KiB,
1305 .CmdSet = P_ID_AMD_STD,
1306 .NumEraseRegions= 1,
1307 .regions = {
1308 ERASEINFO(0x01000,64),
1309 }
1310 }, {
1311 .mfr_id = MANUFACTURER_SST,
1312 .dev_id = SST39LF040,
1313 .name = "SST 39LF040",
1314 .uaddr = {
1315 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1316 },
1317 .DevSize = SIZE_512KiB,
1318 .CmdSet = P_ID_AMD_STD,
1319 .NumEraseRegions= 1,
1320 .regions = {
1321 ERASEINFO(0x01000,128),
1322 }
1323 }, {
1324 .mfr_id = MANUFACTURER_SST,
1325 .dev_id = SST39SF010A,
1326 .name = "SST 39SF010A",
1327 .uaddr = {
1328 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1329 },
1330 .DevSize = SIZE_128KiB,
1331 .CmdSet = P_ID_AMD_STD,
1332 .NumEraseRegions= 1,
1333 .regions = {
1334 ERASEINFO(0x01000,32),
1335 }
1336 }, {
1337 .mfr_id = MANUFACTURER_SST,
1338 .dev_id = SST39SF020A,
1339 .name = "SST 39SF020A",
1340 .uaddr = {
1341 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1342 },
1343 .DevSize = SIZE_256KiB,
1344 .CmdSet = P_ID_AMD_STD,
1345 .NumEraseRegions= 1,
1346 .regions = {
1347 ERASEINFO(0x01000,64),
1348 }
1349 }, {
1350 .mfr_id = MANUFACTURER_SST,
1351 .dev_id = SST49LF004B,
1352 .name = "SST 49LF004B",
1353 .uaddr = {
1354 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1355 },
1356 .DevSize = SIZE_512KiB,
1357 .CmdSet = P_ID_AMD_STD,
1358 .NumEraseRegions= 1,
1359 .regions = {
1360 ERASEINFO(0x01000,128),
1361 }
1362 }, {
1363 .mfr_id = MANUFACTURER_SST,
1364 .dev_id = SST49LF008A,
1365 .name = "SST 49LF008A",
1366 .uaddr = {
1367 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1368 },
1369 .DevSize = SIZE_1MiB,
1370 .CmdSet = P_ID_AMD_STD,
1371 .NumEraseRegions= 1,
1372 .regions = {
1373 ERASEINFO(0x01000,256),
1374 }
1375 }, {
1376 .mfr_id = MANUFACTURER_SST,
1377 .dev_id = SST49LF030A,
1378 .name = "SST 49LF030A",
1379 .uaddr = {
1380 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1381 },
1382 .DevSize = SIZE_512KiB,
1383 .CmdSet = P_ID_AMD_STD,
1384 .NumEraseRegions= 1,
1385 .regions = {
1386 ERASEINFO(0x01000,96),
1387 }
1388 }, {
1389 .mfr_id = MANUFACTURER_SST,
1390 .dev_id = SST49LF040A,
1391 .name = "SST 49LF040A",
1392 .uaddr = {
1393 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1394 },
1395 .DevSize = SIZE_512KiB,
1396 .CmdSet = P_ID_AMD_STD,
1397 .NumEraseRegions= 1,
1398 .regions = {
1399 ERASEINFO(0x01000,128),
1400 }
1401 }, {
1402 .mfr_id = MANUFACTURER_SST,
1403 .dev_id = SST49LF080A,
1404 .name = "SST 49LF080A",
1405 .uaddr = {
1406 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1407 },
1408 .DevSize = SIZE_1MiB,
1409 .CmdSet = P_ID_AMD_STD,
1410 .NumEraseRegions= 1,
1411 .regions = {
1412 ERASEINFO(0x01000,256),
1413 }
1414 }, {
1415 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1416 .dev_id = M29W800DT,
1417 .name = "ST M29W800DT",
1418 .uaddr = {
1419 [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */
1420 [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */
1421 },
1422 .DevSize = SIZE_1MiB,
1423 .CmdSet = P_ID_AMD_STD,
1424 .NumEraseRegions= 4,
1425 .regions = {
1426 ERASEINFO(0x10000,15),
1427 ERASEINFO(0x08000,1),
1428 ERASEINFO(0x02000,2),
1429 ERASEINFO(0x04000,1)
1430 }
1431 }, {
1432 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1433 .dev_id = M29W800DB,
1434 .name = "ST M29W800DB",
1435 .uaddr = {
1436 [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */
1437 [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */
1438 },
1439 .DevSize = SIZE_1MiB,
1440 .CmdSet = P_ID_AMD_STD,
1441 .NumEraseRegions= 4,
1442 .regions = {
1443 ERASEINFO(0x04000,1),
1444 ERASEINFO(0x02000,2),
1445 ERASEINFO(0x08000,1),
1446 ERASEINFO(0x10000,15)
1447 }
1448 }, {
1449 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1450 .dev_id = M29W160DT,
1451 .name = "ST M29W160DT",
1452 .uaddr = {
1453 [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */
1454 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1455 },
1456 .DevSize = SIZE_2MiB,
1457 .CmdSet = P_ID_AMD_STD,
1458 .NumEraseRegions= 4,
1459 .regions = {
1460 ERASEINFO(0x10000,31),
1461 ERASEINFO(0x08000,1),
1462 ERASEINFO(0x02000,2),
1463 ERASEINFO(0x04000,1)
1464 }
1465 }, {
1466 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1467 .dev_id = M29W160DB,
1468 .name = "ST M29W160DB",
1469 .uaddr = {
1470 [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */
1471 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1472 },
1473 .DevSize = SIZE_2MiB,
1474 .CmdSet = P_ID_AMD_STD,
1475 .NumEraseRegions= 4,
1476 .regions = {
1477 ERASEINFO(0x04000,1),
1478 ERASEINFO(0x02000,2),
1479 ERASEINFO(0x08000,1),
1480 ERASEINFO(0x10000,31)
1481 }
1482 }, {
1483 .mfr_id = MANUFACTURER_ST,
1484 .dev_id = M29W040B,
1485 .name = "ST M29W040B",
1486 .uaddr = {
1487 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
1488 },
1489 .DevSize = SIZE_512KiB,
1490 .CmdSet = P_ID_AMD_STD,
1491 .NumEraseRegions= 1,
1492 .regions = {
1493 ERASEINFO(0x10000,8),
1494 }
1495 }, {
1496 .mfr_id = MANUFACTURER_ST,
1497 .dev_id = M50FW040,
1498 .name = "ST M50FW040",
1499 .uaddr = {
1500 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1501 },
1502 .DevSize = SIZE_512KiB,
1503 .CmdSet = P_ID_INTEL_EXT,
1504 .NumEraseRegions= 1,
1505 .regions = {
1506 ERASEINFO(0x10000,8),
1507 }
1508 }, {
1509 .mfr_id = MANUFACTURER_ST,
1510 .dev_id = M50FW080,
1511 .name = "ST M50FW080",
1512 .uaddr = {
1513 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1514 },
1515 .DevSize = SIZE_1MiB,
1516 .CmdSet = P_ID_INTEL_EXT,
1517 .NumEraseRegions= 1,
1518 .regions = {
1519 ERASEINFO(0x10000,16),
1520 }
1521 }, {
1522 .mfr_id = MANUFACTURER_ST,
1523 .dev_id = M50FW016,
1524 .name = "ST M50FW016",
1525 .uaddr = {
1526 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1527 },
1528 .DevSize = SIZE_2MiB,
1529 .CmdSet = P_ID_INTEL_EXT,
1530 .NumEraseRegions= 1,
1531 .regions = {
1532 ERASEINFO(0x10000,32),
1533 }
1534 }, {
1535 .mfr_id = MANUFACTURER_TOSHIBA,
1536 .dev_id = TC58FVT160,
1537 .name = "Toshiba TC58FVT160",
1538 .uaddr = {
1539 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1540 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
1541 },
1542 .DevSize = SIZE_2MiB,
1543 .CmdSet = P_ID_AMD_STD,
1544 .NumEraseRegions= 4,
1545 .regions = {
1546 ERASEINFO(0x10000,31),
1547 ERASEINFO(0x08000,1),
1548 ERASEINFO(0x02000,2),
1549 ERASEINFO(0x04000,1)
1550 }
1551 }, {
1552 .mfr_id = MANUFACTURER_TOSHIBA,
1553 .dev_id = TC58FVB160,
1554 .name = "Toshiba TC58FVB160",
1555 .uaddr = {
1556 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1557 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
1558 },
1559 .DevSize = SIZE_2MiB,
1560 .CmdSet = P_ID_AMD_STD,
1561 .NumEraseRegions= 4,
1562 .regions = {
1563 ERASEINFO(0x04000,1),
1564 ERASEINFO(0x02000,2),
1565 ERASEINFO(0x08000,1),
1566 ERASEINFO(0x10000,31)
1567 }
1568 }, {
1569 .mfr_id = MANUFACTURER_TOSHIBA,
1570 .dev_id = TC58FVB321,
1571 .name = "Toshiba TC58FVB321",
1572 .uaddr = {
1573 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1574 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
1575 },
1576 .DevSize = SIZE_4MiB,
1577 .CmdSet = P_ID_AMD_STD,
1578 .NumEraseRegions= 2,
1579 .regions = {
1580 ERASEINFO(0x02000,8),
1581 ERASEINFO(0x10000,63)
1582 }
1583 }, {
1584 .mfr_id = MANUFACTURER_TOSHIBA,
1585 .dev_id = TC58FVT321,
1586 .name = "Toshiba TC58FVT321",
1587 .uaddr = {
1588 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1589 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
1590 },
1591 .DevSize = SIZE_4MiB,
1592 .CmdSet = P_ID_AMD_STD,
1593 .NumEraseRegions= 2,
1594 .regions = {
1595 ERASEINFO(0x10000,63),
1596 ERASEINFO(0x02000,8)
1597 }
1598 }, {
1599 .mfr_id = MANUFACTURER_TOSHIBA,
1600 .dev_id = TC58FVB641,
1601 .name = "Toshiba TC58FVB641",
1602 .uaddr = {
1603 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1604 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1605 },
1606 .DevSize = SIZE_8MiB,
1607 .CmdSet = P_ID_AMD_STD,
1608 .NumEraseRegions= 2,
1609 .regions = {
1610 ERASEINFO(0x02000,8),
1611 ERASEINFO(0x10000,127)
1612 }
1613 }, {
1614 .mfr_id = MANUFACTURER_TOSHIBA,
1615 .dev_id = TC58FVT641,
1616 .name = "Toshiba TC58FVT641",
1617 .uaddr = {
1618 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1619 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1620 },
1621 .DevSize = SIZE_8MiB,
1622 .CmdSet = P_ID_AMD_STD,
1623 .NumEraseRegions= 2,
1624 .regions = {
1625 ERASEINFO(0x10000,127),
1626 ERASEINFO(0x02000,8)
1627 }
1628 }, {
1629 .mfr_id = MANUFACTURER_WINBOND,
1630 .dev_id = W49V002A,
1631 .name = "Winbond W49V002A",
1632 .uaddr = {
1633 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1634 },
1635 .DevSize = SIZE_256KiB,
1636 .CmdSet = P_ID_AMD_STD,
1637 .NumEraseRegions= 4,
1638 .regions = {
1639 ERASEINFO(0x10000, 3),
1640 ERASEINFO(0x08000, 1),
1641 ERASEINFO(0x02000, 2),
1642 ERASEINFO(0x04000, 1),
1643 }
1644 }
1645 };
1646
1647
1648 static int cfi_jedec_setup(struct cfi_private *p_cfi, int index);
1649
1650 static int jedec_probe_chip(struct map_info *map, __u32 base,
1651 unsigned long *chip_map, struct cfi_private *cfi);
1652
1653 struct mtd_info *jedec_probe(struct map_info *map);
1654
1655 static inline u32 jedec_read_mfr(struct map_info *map, __u32 base,
1656 struct cfi_private *cfi)
1657 {
1658 map_word result;
1659 unsigned long mask;
1660 mask = (1 << (cfi->device_type * 8)) -1;
1661 result = map_read(map, base);
1662 return result.x[0] & mask;
1663 }
1664
1665 static inline u32 jedec_read_id(struct map_info *map, __u32 base,
1666 struct cfi_private *cfi)
1667 {
1668 int osf;
1669 map_word result;
1670 unsigned long mask;
1671 osf = cfi->interleave *cfi->device_type;
1672 mask = (1 << (cfi->device_type * 8)) -1;
1673 result = map_read(map, base + osf);
1674 return result.x[0] & mask;
1675 }
1676
1677 static inline void jedec_reset(u32 base, struct map_info *map,
1678 struct cfi_private *cfi)
1679 {
1680 /* Reset */
1681
1682 /* after checking the datasheets for SST, MACRONIX and ATMEL
1683 * (oh and incidentaly the jedec spec - 3.5.3.3) the reset
1684 * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at
1685 * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips
1686 * as they will ignore the writes and dont care what address
1687 * the F0 is written to */
1688 if(cfi->addr_unlock1) {
1689 /*printk("reset unlock called %x %x \n",cfi->addr_unlock1,cfi->addr_unlock2);*/
1690 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1691 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1692 }
1693
1694 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
1695 /* Some misdesigned intel chips do not respond for 0xF0 for a reset,
1696 * so ensure we're in read mode. Send both the Intel and the AMD command
1697 * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so
1698 * this should be safe.
1699 */
1700 cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL);
1701 /* FIXME - should have reset delay before continuing */
1702 }
1703
1704
1705 static inline __u8 finfo_uaddr(const struct amd_flash_info *finfo, int device_type)
1706 {
1707 int uaddr_idx;
1708 __u8 uaddr = MTD_UADDR_NOT_SUPPORTED;
1709
1710 switch ( device_type ) {
1711 case CFI_DEVICETYPE_X8: uaddr_idx = 0; break;
1712 case CFI_DEVICETYPE_X16: uaddr_idx = 1; break;
1713 case CFI_DEVICETYPE_X32: uaddr_idx = 2; break;
1714 default:
1715 printk(KERN_NOTICE "MTD: %s(): unknown device_type %d\n",
1716 __func__, device_type);
1717 goto uaddr_done;
1718 }
1719
1720 uaddr = finfo->uaddr[uaddr_idx];
1721
1722 if (uaddr != MTD_UADDR_NOT_SUPPORTED ) {
1723 /* ASSERT("The unlock addresses for non-8-bit mode
1724 are bollocks. We don't really need an array."); */
1725 uaddr = finfo->uaddr[0];
1726 }
1727
1728 uaddr_done:
1729 return uaddr;
1730 }
1731
1732
1733 static int cfi_jedec_setup(struct cfi_private *p_cfi, int index)
1734 {
1735 int i,num_erase_regions;
1736 unsigned long mask;
1737 __u8 uaddr;
1738
1739 printk("Found: %s\n",jedec_table[index].name);
1740
1741 num_erase_regions = jedec_table[index].NumEraseRegions;
1742
1743 p_cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL);
1744 if (!p_cfi->cfiq) {
1745 //xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name);
1746 return 0;
1747 }
1748
1749 memset(p_cfi->cfiq,0,sizeof(struct cfi_ident));
1750
1751 p_cfi->cfiq->P_ID = jedec_table[index].CmdSet;
1752 p_cfi->cfiq->NumEraseRegions = jedec_table[index].NumEraseRegions;
1753 p_cfi->cfiq->DevSize = jedec_table[index].DevSize;
1754 p_cfi->cfi_mode = CFI_MODE_JEDEC;
1755
1756 for (i=0; i<num_erase_regions; i++){
1757 p_cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i];
1758 }
1759 p_cfi->cmdset_priv = NULL;
1760
1761 /* This may be redundant for some cases, but it doesn't hurt */
1762 p_cfi->mfr = jedec_table[index].mfr_id;
1763 p_cfi->id = jedec_table[index].dev_id;
1764
1765 uaddr = finfo_uaddr(&jedec_table[index], p_cfi->device_type);
1766 if ( uaddr == MTD_UADDR_NOT_SUPPORTED ) {
1767 kfree( p_cfi->cfiq );
1768 return 0;
1769 }
1770
1771 /* Mask out address bits which are smaller than the device type */
1772 mask = ~(p_cfi->device_type-1);
1773 p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 & mask;
1774 p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 & mask;
1775
1776 return 1; /* ok */
1777 }
1778
1779
1780 /*
1781 * There is a BIG problem properly ID'ing the JEDEC devic and guaranteeing
1782 * the mapped address, unlock addresses, and proper chip ID. This function
1783 * attempts to minimize errors. It is doubtfull that this probe will ever
1784 * be perfect - consequently there should be some module parameters that
1785 * could be manually specified to force the chip info.
1786 */
1787 static inline int jedec_match( __u32 base,
1788 struct map_info *map,
1789 struct cfi_private *cfi,
1790 const struct amd_flash_info *finfo )
1791 {
1792 int rc = 0; /* failure until all tests pass */
1793 u32 mfr, id;
1794 __u8 uaddr;
1795 unsigned long mask;
1796
1797 /*
1798 * The IDs must match. For X16 and X32 devices operating in
1799 * a lower width ( X8 or X16 ), the device ID's are usually just
1800 * the lower byte(s) of the larger device ID for wider mode. If
1801 * a part is found that doesn't fit this assumption (device id for
1802 * smaller width mode is completely unrealated to full-width mode)
1803 * then the jedec_table[] will have to be augmented with the IDs
1804 * for different widths.
1805 */
1806 switch (cfi->device_type) {
1807 case CFI_DEVICETYPE_X8:
1808 mfr = (__u8)finfo->mfr_id;
1809 id = (__u8)finfo->dev_id;
1810 break;
1811 case CFI_DEVICETYPE_X16:
1812 mfr = (__u16)finfo->mfr_id;
1813 id = (__u16)finfo->dev_id;
1814 break;
1815 case CFI_DEVICETYPE_X32:
1816 mfr = (__u16)finfo->mfr_id;
1817 id = (__u32)finfo->dev_id;
1818 break;
1819 default:
1820 printk(KERN_WARNING
1821 "MTD %s(): Unsupported device type %d\n",
1822 __func__, cfi->device_type);
1823 goto match_done;
1824 }
1825 if ( cfi->mfr != mfr || cfi->id != id ) {
1826 goto match_done;
1827 }
1828
1829 /* the part size must fit in the memory window */
1830 DEBUG( MTD_DEBUG_LEVEL3,
1831 "MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n",
1832 __func__, base, 1 << finfo->DevSize, base + (1 << finfo->DevSize) );
1833 if ( base + cfi->interleave * ( 1 << finfo->DevSize ) > map->size ) {
1834 DEBUG( MTD_DEBUG_LEVEL3,
1835 "MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n",
1836 __func__, finfo->mfr_id, finfo->dev_id,
1837 1 << finfo->DevSize );
1838 goto match_done;
1839 }
1840
1841 uaddr = finfo_uaddr(finfo, cfi->device_type);
1842 if ( uaddr == MTD_UADDR_NOT_SUPPORTED ) {
1843 goto match_done;
1844 }
1845
1846 mask = ~(cfi->device_type-1);
1847
1848 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n",
1849 __func__, cfi->addr_unlock1, cfi->addr_unlock2 );
1850 if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr
1851 && ( (unlock_addrs[uaddr].addr1 & mask) != cfi->addr_unlock1 ||
1852 (unlock_addrs[uaddr].addr2 & mask) != cfi->addr_unlock2 ) ) {
1853 DEBUG( MTD_DEBUG_LEVEL3,
1854 "MTD %s(): 0x%.4lx 0x%.4lx did not match\n",
1855 __func__,
1856 unlock_addrs[uaddr].addr1 & mask,
1857 unlock_addrs[uaddr].addr2 & mask);
1858 goto match_done;
1859 }
1860
1861 /*
1862 * Make sure the ID's dissappear when the device is taken out of
1863 * ID mode. The only time this should fail when it should succeed
1864 * is when the ID's are written as data to the same
1865 * addresses. For this rare and unfortunate case the chip
1866 * cannot be probed correctly.
1867 * FIXME - write a driver that takes all of the chip info as
1868 * module parameters, doesn't probe but forces a load.
1869 */
1870 DEBUG( MTD_DEBUG_LEVEL3,
1871 "MTD %s(): check ID's disappear when not in ID mode\n",
1872 __func__ );
1873 jedec_reset( base, map, cfi );
1874 mfr = jedec_read_mfr( map, base, cfi );
1875 id = jedec_read_id( map, base, cfi );
1876 if ( mfr == cfi->mfr && id == cfi->id ) {
1877 DEBUG( MTD_DEBUG_LEVEL3,
1878 "MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n"
1879 "You might need to manually specify JEDEC parameters.\n",
1880 __func__, cfi->mfr, cfi->id );
1881 goto match_done;
1882 }
1883
1884 /* all tests passed - mark as success */
1885 rc = 1;
1886
1887 /*
1888 * Put the device back in ID mode - only need to do this if we
1889 * were truly frobbing a real device.
1890 */
1891 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): return to ID mode\n", __func__ );
1892 if(cfi->addr_unlock1) {
1893 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1894 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1895 }
1896 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1897 /* FIXME - should have a delay before continuing */
1898
1899 match_done:
1900 return rc;
1901 }
1902
1903
1904 static int jedec_probe_chip(struct map_info *map, __u32 base,
1905 unsigned long *chip_map, struct cfi_private *cfi)
1906 {
1907 int i;
1908 enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
1909
1910 retry:
1911 if (!cfi->numchips) {
1912 unsigned long mask = ~(cfi->device_type-1);
1913
1914 uaddr_idx++;
1915
1916 if (MTD_UADDR_UNNECESSARY == uaddr_idx)
1917 return 0;
1918
1919 /* Mask out address bits which are smaller than the device type */
1920 cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 & mask;
1921 cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 & mask;
1922 }
1923
1924 /* Make certain we aren't probing past the end of map */
1925 if (base >= map->size) {
1926 printk(KERN_NOTICE
1927 "Probe at base(0x%08x) past the end of the map(0x%08lx)\n",
1928 base, map->size -1);
1929 return 0;
1930
1931 }
1932 if ((base + cfi->addr_unlock1) >= map->size) {
1933 printk(KERN_NOTICE
1934 "Probe at addr_unlock1(0x%08x + 0x%08x) past the end of the map(0x%08lx)\n",
1935 base, cfi->addr_unlock1, map->size -1);
1936
1937 return 0;
1938 }
1939 if ((base + cfi->addr_unlock2) >= map->size) {
1940 printk(KERN_NOTICE
1941 "Probe at addr_unlock2(0x%08x + 0x%08x) past the end of the map(0x%08lx)\n",
1942 base, cfi->addr_unlock2, map->size -1);
1943 return 0;
1944
1945 }
1946
1947 /* Reset */
1948 jedec_reset(base, map, cfi);
1949
1950 /* Autoselect Mode */
1951 if(cfi->addr_unlock1) {
1952 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1953 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1954 }
1955 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, CFI_DEVICETYPE_X8, NULL);
1956 /* FIXME - should have a delay before continuing */
1957
1958 if (!cfi->numchips) {
1959 /* This is the first time we're called. Set up the CFI
1960 stuff accordingly and return */
1961
1962 cfi->mfr = jedec_read_mfr(map, base, cfi);
1963 cfi->id = jedec_read_id(map, base, cfi);
1964 DEBUG(MTD_DEBUG_LEVEL3,
1965 "Search for id:(%02x %02x) interleave(%d) type(%d)\n",
1966 cfi->mfr, cfi->id, cfi->interleave, cfi->device_type);
1967 for (i=0; i<sizeof(jedec_table)/sizeof(jedec_table[0]); i++) {
1968 if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) {
1969 DEBUG( MTD_DEBUG_LEVEL3,
1970 "MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n",
1971 __func__, cfi->mfr, cfi->id,
1972 cfi->addr_unlock1, cfi->addr_unlock2 );
1973 if (!cfi_jedec_setup(cfi, i))
1974 return 0;
1975 goto ok_out;
1976 }
1977 }
1978 goto retry;
1979 } else {
1980 __u16 mfr;
1981 __u16 id;
1982
1983 /* Make sure it is a chip of the same manufacturer and id */
1984 mfr = jedec_read_mfr(map, base, cfi);
1985 id = jedec_read_id(map, base, cfi);
1986
1987 if ((mfr != cfi->mfr) || (id != cfi->id)) {
1988 printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n",
1989 map->name, mfr, id, base);
1990 jedec_reset(base, map, cfi);
1991 return 0;
1992 }
1993 }
1994
1995 /* Check each previous chip locations to see if it's an alias */
1996 for (i=0; i < (base >> cfi->chipshift); i++) {
1997 unsigned long start;
1998 if(!test_bit(i, chip_map)) {
1999 continue; /* Skip location; no valid chip at this address */
2000 }
2001 start = i << cfi->chipshift;
2002 if (jedec_read_mfr(map, start, cfi) == cfi->mfr &&
2003 jedec_read_id(map, start, cfi) == cfi->id) {
2004 /* Eep. This chip also looks like it's in autoselect mode.
2005 Is it an alias for the new one? */
2006 jedec_reset(start, map, cfi);
2007
2008 /* If the device IDs go away, it's an alias */
2009 if (jedec_read_mfr(map, base, cfi) != cfi->mfr ||
2010 jedec_read_id(map, base, cfi) != cfi->id) {
2011 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
2012 map->name, base, start);
2013 return 0;
2014 }
2015
2016 /* Yes, it's actually got the device IDs as data. Most
2017 * unfortunate. Stick the new chip in read mode
2018 * too and if it's the same, assume it's an alias. */
2019 /* FIXME: Use other modes to do a proper check */
2020 jedec_reset(base, map, cfi);
2021 if (jedec_read_mfr(map, base, cfi) == cfi->mfr &&
2022 jedec_read_id(map, base, cfi) == cfi->id) {
2023 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
2024 map->name, base, start);
2025 return 0;
2026 }
2027 }
2028 }
2029
2030 /* OK, if we got to here, then none of the previous chips appear to
2031 be aliases for the current one. */
2032 set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */
2033 cfi->numchips++;
2034
2035 ok_out:
2036 /* Put it back into Read Mode */
2037 jedec_reset(base, map, cfi);
2038
2039 printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n",
2040 map->name, cfi->interleave, cfi->device_type*8, base,
2041 map->bankwidth*8);
2042
2043 return 1;
2044 }
2045
2046 static struct chip_probe jedec_chip_probe = {
2047 .name = "JEDEC",
2048 .probe_chip = jedec_probe_chip
2049 };
2050
2051 struct mtd_info *jedec_probe(struct map_info *map)
2052 {
2053 /*
2054 * Just use the generic probe stuff to call our CFI-specific
2055 * chip_probe routine in all the possible permutations, etc.
2056 */
2057 return mtd_do_chip_probe(map, &jedec_chip_probe);
2058 }
2059
2060 static struct mtd_chip_driver jedec_chipdrv = {
2061 .probe = jedec_probe,
2062 .name = "jedec_probe",
2063 .module = THIS_MODULE
2064 };
2065
2066 int __init jedec_probe_init(void)
2067 {
2068 register_mtd_chip_driver(&jedec_chipdrv);
2069 return 0;
2070 }
2071
2072 static void __exit jedec_probe_exit(void)
2073 {
2074 unregister_mtd_chip_driver(&jedec_chipdrv);
2075 }
2076
2077 module_init(jedec_probe_init);
2078 module_exit(jedec_probe_exit);
2079
2080 MODULE_LICENSE("GPL");
2081 MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al.");
2082 MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips");
MOXA 2.6.9 from sdlinux-moxaart.tgz