drivers/mmc/mmci.c

   1 /*
   2  *  linux/drivers/mmc/mmci.c - ARM PrimeCell MMCI PL180/1 driver
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/config.h>
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/init.h>
  14 #include <linux/ioport.h>
  15 #include <linux/device.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/mmc/protocol.h>
  22
  23 #include <asm/io.h>
  24 #include <asm/irq.h>
  25 #include <asm/hardware/amba.h>
  26 #include <asm/hardware/clock.h>
  27 #include <asm/mach/mmc.h>
  28
  29 #include "mmci.h"
  30
  31 #define DRIVER_NAME "mmci-pl18x"
  32
  33 #ifdef CONFIG_MMC_DEBUG
  34 #define DBG(host,fmt,args...)   \
  35         pr_debug("%s: %s: " fmt, host->mmc->host_name, __func__ , args)
  36 #else
  37 #define DBG(host,fmt,args...)   do { } while (0)
  38 #endif
  39
  40 static unsigned int fmax = 515633;
  41
  42 static void
  43 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
  44 {
  45         writel(0, host->base + MMCICOMMAND);
  46
  47         host->mrq = NULL;
  48         host->cmd = NULL;
  49
  50         if (mrq->data)
  51                 mrq->data->bytes_xfered = host->data_xfered;
  52
  53         /*
  54          * Need to drop the host lock here; mmc_request_done may call
  55          * back into the driver...
  56          */
  57         spin_unlock(&host->lock);
  58         mmc_request_done(host->mmc, mrq);
  59         spin_lock(&host->lock);
  60 }
  61
  62 static void mmci_stop_data(struct mmci_host *host)
  63 {
  64         writel(0, host->base + MMCIDATACTRL);
  65         writel(0, host->base + MMCIMASK1);
  66         host->data = NULL;
  67 }
  68
  69 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
  70 {
  71         unsigned int datactrl, timeout, irqmask;
  72         void *base;
  73
  74         DBG(host, "blksz %04x blks %04x flags %08x\n",
  75             1 << data->blksz_bits, data->blocks, data->flags);
  76
  77         host->data = data;
  78         host->size = data->blocks << data->blksz_bits;
  79         host->data_xfered = 0;
  80
  81         mmci_init_sg(host, data);
  82
  83         timeout = data->timeout_clks +
  84                   ((unsigned long long)data->timeout_ns * host->cclk) /
  85                    1000000000ULL;
  86
  87         base = host->base;
  88         writel(timeout, base + MMCIDATATIMER);
  89         writel(host->size, base + MMCIDATALENGTH);
  90
  91         datactrl = MCI_DPSM_ENABLE | data->blksz_bits << 4;
  92         if (data->flags & MMC_DATA_READ) {
  93                 datactrl |= MCI_DPSM_DIRECTION;
  94                 irqmask = MCI_RXFIFOHALFFULLMASK;
  95         } else {
  96                 /*
  97                  * We don't actually need to include "FIFO empty" here
  98                  * since its implicit in "FIFO half empty".
  99                  */
 100                 irqmask = MCI_TXFIFOHALFEMPTYMASK;
 101         }
 102
 103         writel(datactrl, base + MMCIDATACTRL);
 104         writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
 105         writel(irqmask, base + MMCIMASK1);
 106 }
 107
 108 static void
 109 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
 110 {
 111         void *base = host->base;
 112
 113         DBG(host, "op %02x arg %08x flags %08x\n",
 114             cmd->opcode, cmd->arg, cmd->flags);
 115
 116         if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
 117                 writel(0, base + MMCICOMMAND);
 118                 udelay(1);
 119         }
 120
 121         c |= cmd->opcode | MCI_CPSM_ENABLE;
 122         switch (cmd->flags & MMC_RSP_MASK) {
 123         case MMC_RSP_NONE:
 124         default:
 125                 break;
 126         case MMC_RSP_LONG:
 127                 c |= MCI_CPSM_LONGRSP;
 128         case MMC_RSP_SHORT:
 129                 c |= MCI_CPSM_RESPONSE;
 130                 break;
 131         }
 132         if (/*interrupt*/0)
 133                 c |= MCI_CPSM_INTERRUPT;
 134
 135         host->cmd = cmd;
 136
 137         writel(cmd->arg, base + MMCIARGUMENT);
 138         writel(c, base + MMCICOMMAND);
 139 }
 140
 141 static void
 142 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
 143               unsigned int status)
 144 {
 145         if (status & MCI_DATABLOCKEND) {
 146                 host->data_xfered += 1 << data->blksz_bits;
 147         }
 148         if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
 149                 if (status & MCI_DATACRCFAIL)
 150                         data->error = MMC_ERR_BADCRC;
 151                 else if (status & MCI_DATATIMEOUT)
 152                         data->error = MMC_ERR_TIMEOUT;
 153                 else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
 154                         data->error = MMC_ERR_FIFO;
 155                 status |= MCI_DATAEND;
 156         }
 157         if (status & MCI_DATAEND) {
 158                 mmci_stop_data(host);
 159
 160                 if (!data->stop) {
 161                         mmci_request_end(host, data->mrq);
 162                 } else {
 163                         mmci_start_command(host, data->stop, 0);
 164                 }
 165         }
 166 }
 167
 168 static void
 169 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
 170              unsigned int status)
 171 {
 172         void *base = host->base;
 173
 174         host->cmd = NULL;
 175
 176         cmd->resp[0] = readl(base + MMCIRESPONSE0);
 177         cmd->resp[1] = readl(base + MMCIRESPONSE1);
 178         cmd->resp[2] = readl(base + MMCIRESPONSE2);
 179         cmd->resp[3] = readl(base + MMCIRESPONSE3);
 180
 181         if (status & MCI_CMDTIMEOUT) {
 182                 cmd->error = MMC_ERR_TIMEOUT;
 183         } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
 184                 cmd->error = MMC_ERR_BADCRC;
 185         }
 186
 187         if (!cmd->data || cmd->error != MMC_ERR_NONE) {
 188                 mmci_request_end(host, cmd->mrq);
 189         } else if (!(cmd->data->flags & MMC_DATA_READ)) {
 190                 mmci_start_data(host, cmd->data);
 191         }
 192 }
 193
 194 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
 195 {
 196         void *base = host->base;
 197         char *ptr = buffer;
 198         u32 status;
 199
 200         do {
 201                 int count = host->size - (readl(base + MMCIFIFOCNT) << 2);
 202
 203                 if (count > remain)
 204                         count = remain;
 205
 206                 if (count <= 0)
 207                         break;
 208
 209                 readsl(base + MMCIFIFO, ptr, count >> 2);
 210
 211                 ptr += count;
 212                 remain -= count;
 213
 214                 if (remain == 0)
 215                         break;
 216
 217                 status = readl(base + MMCISTATUS);
 218         } while (status & MCI_RXDATAAVLBL);
 219
 220         return ptr - buffer;
 221 }
 222
 223 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
 224 {
 225         void *base = host->base;
 226         char *ptr = buffer;
 227
 228         do {
 229                 unsigned int count, maxcnt;
 230
 231                 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
 232                 count = min(remain, maxcnt);
 233
 234                 writesl(base + MMCIFIFO, ptr, count >> 2);
 235
 236                 ptr += count;
 237                 remain -= count;
 238
 239                 if (remain == 0)
 240                         break;
 241
 242                 status = readl(base + MMCISTATUS);
 243         } while (status & MCI_TXFIFOHALFEMPTY);
 244
 245         return ptr - buffer;
 246 }
 247
 248 /*
 249  * PIO data transfer IRQ handler.
 250  */
 251 static irqreturn_t mmci_pio_irq(int irq, void *dev_id, struct pt_regs *regs)
 252 {
 253         struct mmci_host *host = dev_id;
 254         void *base = host->base;
 255         u32 status;
 256
 257         status = readl(base + MMCISTATUS);
 258
 259         DBG(host, "irq1 %08x\n", status);
 260
 261         do {
 262                 unsigned long flags;
 263                 unsigned int remain, len;
 264                 char *buffer;
 265
 266                 /*
 267                  * For write, we only need to test the half-empty flag
 268                  * here - if the FIFO is completely empty, then by
 269                  * definition it is more than half empty.
 270                  *
 271                  * For read, check for data available.
 272                  */
 273                 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
 274                         break;
 275
 276                 /*
 277                  * Map the current scatter buffer.
 278                  */
 279                 buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
 280                 remain = host->sg_ptr->length - host->sg_off;
 281
 282                 len = 0;
 283                 if (status & MCI_RXACTIVE)
 284                         len = mmci_pio_read(host, buffer, remain);
 285                 if (status & MCI_TXACTIVE)
 286                         len = mmci_pio_write(host, buffer, remain, status);
 287
 288                 /*
 289                  * Unmap the buffer.
 290                  */
 291                 mmci_kunmap_atomic(host, &flags);
 292
 293                 host->sg_off += len;
 294                 host->size -= len;
 295                 remain -= len;
 296
 297                 if (remain)
 298                         break;
 299
 300                 if (!mmci_next_sg(host))
 301                         break;
 302
 303                 status = readl(base + MMCISTATUS);
 304         } while (1);
 305
 306         /*
 307          * If we're nearing the end of the read, switch to
 308          * "any data available" mode.
 309          */
 310         if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
 311                 writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
 312
 313         /*
 314          * If we run out of data, disable the data IRQs; this
 315          * prevents a race where the FIFO becomes empty before
 316          * the chip itself has disabled the data path, and
 317          * stops us racing with our data end IRQ.
 318          */
 319         if (host->size == 0) {
 320                 writel(0, base + MMCIMASK1);
 321                 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
 322         }
 323
 324         return IRQ_HANDLED;
 325 }
 326
 327 /*
 328  * Handle completion of command and data transfers.
 329  */
 330 static irqreturn_t mmci_irq(int irq, void *dev_id, struct pt_regs *regs)
 331 {
 332         struct mmci_host *host = dev_id;
 333         u32 status;
 334         int ret = 0;
 335
 336         spin_lock(&host->lock);
 337
 338         do {
 339                 struct mmc_command *cmd;
 340                 struct mmc_data *data;
 341
 342                 status = readl(host->base + MMCISTATUS);
 343                 status &= readl(host->base + MMCIMASK0);
 344                 writel(status, host->base + MMCICLEAR);
 345
 346                 DBG(host, "irq0 %08x\n", status);
 347
 348                 data = host->data;
 349                 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
 350                               MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
 351                         mmci_data_irq(host, data, status);
 352
 353                 cmd = host->cmd;
 354                 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
 355                         mmci_cmd_irq(host, cmd, status);
 356
 357                 ret = 1;
 358         } while (status);
 359
 360         spin_unlock(&host->lock);
 361
 362         return IRQ_RETVAL(ret);
 363 }
 364
 365 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 366 {
 367         struct mmci_host *host = mmc_priv(mmc);
 368
 369         WARN_ON(host->mrq != NULL);
 370
 371         spin_lock_irq(&host->lock);
 372
 373         host->mrq = mrq;
 374
 375         if (mrq->data && mrq->data->flags & MMC_DATA_READ)
 376                 mmci_start_data(host, mrq->data);
 377
 378         mmci_start_command(host, mrq->cmd, 0);
 379
 380         spin_unlock_irq(&host->lock);
 381 }
 382
 383 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 384 {
 385         struct mmci_host *host = mmc_priv(mmc);
 386         u32 clk = 0, pwr = 0;
 387
 388         DBG(host, "clock %uHz busmode %u powermode %u Vdd %u\n",
 389             ios->clock, ios->bus_mode, ios->power_mode, ios->vdd);
 390
 391         if (ios->clock) {
 392                 if (ios->clock >= host->mclk) {
 393                         clk = MCI_CLK_BYPASS;
 394                         host->cclk = host->mclk;
 395                 } else {
 396                         clk = host->mclk / (2 * ios->clock) - 1;
 397                         if (clk > 256)
 398                                 clk = 255;
 399                         host->cclk = host->mclk / (2 * (clk + 1));
 400                 }
 401                 clk |= MCI_CLK_ENABLE;
 402         }
 403
 404         if (host->plat->translate_vdd)
 405                 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
 406
 407         switch (ios->power_mode) {
 408         case MMC_POWER_OFF:
 409                 break;
 410         case MMC_POWER_UP:
 411                 pwr |= MCI_PWR_UP;
 412                 break;
 413         case MMC_POWER_ON:
 414                 pwr |= MCI_PWR_ON;
 415                 break;
 416         }
 417
 418         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 419                 pwr |= MCI_ROD;
 420
 421         writel(clk, host->base + MMCICLOCK);
 422
 423         if (host->pwr != pwr) {
 424                 host->pwr = pwr;
 425                 writel(pwr, host->base + MMCIPOWER);
 426         }
 427 }
 428
 429 static struct mmc_host_ops mmci_ops = {
 430         .request        = mmci_request,
 431         .set_ios        = mmci_set_ios,
 432 };
 433
 434 static void mmci_check_status(unsigned long data)
 435 {
 436         struct mmci_host *host = (struct mmci_host *)data;
 437         unsigned int status;
 438
 439         status = host->plat->status(mmc_dev(host->mmc));
 440         if (status ^ host->oldstat)
 441                 mmc_detect_change(host->mmc);
 442
 443         host->oldstat = status;
 444         mod_timer(&host->timer, jiffies + HZ);
 445 }
 446
 447 static int mmci_probe(struct amba_device *dev, void *id)
 448 {
 449         struct mmc_platform_data *plat = dev->dev.platform_data;
 450         struct mmci_host *host;
 451         struct mmc_host *mmc;
 452         int ret;
 453
 454         /* must have platform data */
 455         if (!plat) {
 456                 ret = -EINVAL;
 457                 goto out;
 458         }
 459
 460         ret = amba_request_regions(dev, DRIVER_NAME);
 461         if (ret)
 462                 goto out;
 463
 464         mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
 465         if (!mmc) {
 466                 ret = -ENOMEM;
 467                 goto rel_regions;
 468         }
 469
 470         host = mmc_priv(mmc);
 471         host->clk = clk_get(&dev->dev, "MCLK");
 472         if (IS_ERR(host->clk)) {
 473                 ret = PTR_ERR(host->clk);
 474                 host->clk = NULL;
 475                 goto host_free;
 476         }
 477
 478         ret = clk_use(host->clk);
 479         if (ret)
 480                 goto clk_free;
 481
 482         ret = clk_enable(host->clk);
 483         if (ret)
 484                 goto clk_unuse;
 485
 486         host->plat = plat;
 487         host->mclk = clk_get_rate(host->clk);
 488         host->mmc = mmc;
 489         host->base = ioremap(dev->res.start, SZ_4K);
 490         if (!host->base) {
 491                 ret = -ENOMEM;
 492                 goto clk_disable;
 493         }
 494
 495         mmc->ops = &mmci_ops;
 496         mmc->f_min = (host->mclk + 511) / 512;
 497         mmc->f_max = min(host->mclk, fmax);
 498         mmc->ocr_avail = plat->ocr_mask;
 499
 500         /*
 501          * We can do SGIO
 502          */
 503         mmc->max_hw_segs = 16;
 504         mmc->max_phys_segs = 16;
 505
 506         /*
 507          * Since we only have a 16-bit data length register, we must
 508          * ensure that we don't exceed 2^16-1 bytes in a single request.
 509          * Choose 64 (512-byte) sectors as the limit.
 510          */
 511         mmc->max_sectors = 64;
 512
 513         /*
 514          * Set the maximum segment size.  Since we aren't doing DMA
 515          * (yet) we are only limited by the data length register.
 516          */
 517         mmc->max_seg_size = mmc->max_sectors << 9;
 518
 519         spin_lock_init(&host->lock);
 520
 521         writel(0, host->base + MMCIMASK0);
 522         writel(0, host->base + MMCIMASK1);
 523         writel(0xfff, host->base + MMCICLEAR);
 524
 525         ret = request_irq(dev->irq[0], mmci_irq, SA_SHIRQ, DRIVER_NAME " (cmd)", host);
 526         if (ret)
 527                 goto unmap;
 528
 529         ret = request_irq(dev->irq[1], mmci_pio_irq, SA_SHIRQ, DRIVER_NAME " (pio)", host);
 530         if (ret)
 531                 goto irq0_free;
 532
 533         writel(MCI_IRQENABLE, host->base + MMCIMASK0);
 534
 535         amba_set_drvdata(dev, mmc);
 536
 537         mmc_add_host(mmc);
 538
 539         printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%08lx irq %d,%d\n",
 540                 mmc->host_name, amba_rev(dev), amba_config(dev),
 541                 dev->res.start, dev->irq[0], dev->irq[1]);
 542
 543         init_timer(&host->timer);
 544         host->timer.data = (unsigned long)host;
 545         host->timer.function = mmci_check_status;
 546         host->timer.expires = jiffies + HZ;
 547         add_timer(&host->timer);
 548
 549         return 0;
 550
 551  irq0_free:
 552         free_irq(dev->irq[0], host);
 553  unmap:
 554         iounmap(host->base);
 555  clk_disable:
 556         clk_disable(host->clk);
 557  clk_unuse:
 558         clk_unuse(host->clk);
 559  clk_free:
 560         clk_put(host->clk);
 561  host_free:
 562         mmc_free_host(mmc);
 563  rel_regions:
 564         amba_release_regions(dev);
 565  out:
 566         return ret;
 567 }
 568
 569 static int mmci_remove(struct amba_device *dev)
 570 {
 571         struct mmc_host *mmc = amba_get_drvdata(dev);
 572
 573         amba_set_drvdata(dev, NULL);
 574
 575         if (mmc) {
 576                 struct mmci_host *host = mmc_priv(mmc);
 577
 578                 del_timer_sync(&host->timer);
 579
 580                 mmc_remove_host(mmc);
 581
 582                 writel(0, host->base + MMCIMASK0);
 583                 writel(0, host->base + MMCIMASK1);
 584
 585                 writel(0, host->base + MMCICOMMAND);
 586                 writel(0, host->base + MMCIDATACTRL);
 587
 588                 free_irq(dev->irq[0], host);
 589                 free_irq(dev->irq[1], host);
 590
 591                 iounmap(host->base);
 592                 clk_disable(host->clk);
 593                 clk_unuse(host->clk);
 594                 clk_put(host->clk);
 595
 596                 mmc_free_host(mmc);
 597
 598                 amba_release_regions(dev);
 599         }
 600
 601         return 0;
 602 }
 603
 604 #ifdef CONFIG_PM
 605 static int mmci_suspend(struct amba_device *dev, u32 state)
 606 {
 607         struct mmc_host *mmc = amba_get_drvdata(dev);
 608         int ret = 0;
 609
 610         if (mmc) {
 611                 struct mmci_host *host = mmc_priv(mmc);
 612
 613                 ret = mmc_suspend_host(mmc, state);
 614                 if (ret == 0)
 615                         writel(0, host->base + MMCIMASK0);
 616         }
 617
 618         return ret;
 619 }
 620
 621 static int mmci_resume(struct amba_device *dev)
 622 {
 623         struct mmc_host *mmc = amba_get_drvdata(dev);
 624         int ret = 0;
 625
 626         if (mmc) {
 627                 struct mmci_host *host = mmc_priv(mmc);
 628
 629                 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
 630
 631                 ret = mmc_resume_host(mmc);
 632         }
 633
 634         return ret;
 635 }
 636 #else
 637 #define mmci_suspend    NULL
 638 #define mmci_resume     NULL
 639 #endif
 640
 641 static struct amba_id mmci_ids[] = {
 642         {
 643                 .id     = 0x00041180,
 644                 .mask   = 0x000fffff,
 645         },
 646         {
 647                 .id     = 0x00041181,
 648                 .mask   = 0x000fffff,
 649         },
 650         { 0, 0 },
 651 };
 652
 653 static struct amba_driver mmci_driver = {
 654         .drv            = {
 655                 .name   = DRIVER_NAME,
 656         },
 657         .probe          = mmci_probe,
 658         .remove         = mmci_remove,
 659         .suspend        = mmci_suspend,
 660         .resume         = mmci_resume,
 661         .id_table       = mmci_ids,
 662 };
 663
 664 static int __init mmci_init(void)
 665 {
 666         return amba_driver_register(&mmci_driver);
 667 }
 668
 669 static void __exit mmci_exit(void)
 670 {
 671         amba_driver_unregister(&mmci_driver);
 672 }
 673
 674 module_init(mmci_init);
 675 module_exit(mmci_exit);
 676 module_param(fmax, uint, 0444);
 677
 678 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
 679 MODULE_LICENSE("GPL");