drivers/char/serial_cpe.h

   1 #ifndef _SERIAL_CPE_H_
   2 #define _SERIAL_CPE_H_
   3 /* -------------------------------------------------------------------------------
   4  *  UART definitions
   5  * -------------------------------------------------------------------------------
   6  */
   7 #define SERIAL_THR                      0x00                    /*  Transmitter Holding Register(Write).*/
   8 #define SERIAL_RBR                      0x00                    /*  Receive Buffer register (Read).*/
   9 #define SERIAL_IER                      0x04                    /*  Interrupt Enable register.*/
  10 #define SERIAL_IIR                      0x08                    /*  Interrupt Identification register(Read).*/
  11 #define SERIAL_FCR                      0x08                    /*  FIFO control register(Write).*/
  12 #define SERIAL_EFR                                              0x08                    //  ?????????????????????
  13 #define SERIAL_LCR                      0x0C                    /*  Line Control register.*/
  14 #define SERIAL_MCR                      0x10                    /*  Modem Control Register.*/
  15 #define SERIAL_LSR                      0x14                    /*  Line status register(Read) .*/
  16 #define SERIAL_MSR                      0x18                    /*  Modem Status register (Read).*/
  17 #define SERIAL_SPR                      0x1C                    /*  Scratch pad register */
  18 #define SERIAL_DLL                      0x0                     /*  Divisor Register LSB */
  19 #define SERIAL_DLM                      0x4                     /*  Divisor Register MSB */
  20 #define SERIAL_PSR                      0x8                     /* Prescale Divison Factor */
  21
  22 #define SERIAL_MDR                                              0x20
  23 #define SERIAL_ACR                                              0x24
  24 #define SERIAL_TXLENL                                   0x28
  25 #define SERIAL_TXLENH                                   0x2C
  26 #define SERIAL_MRXLENL                                  0x30
  27 #define SERIAL_MRXLENH                                  0x34
  28 #define SERIAL_PLR                                              0x38
  29 #define SERIAL_FMIIR_PIO                                0x3C
  30
  31 /* IER Register */
  32 #define SERIAL_IER_DR                   0x1             /* Data ready Enable */
  33 #define SERIAL_IER_TE                   0x2             /* THR Empty Enable */
  34 #define SERIAL_IER_RLS                  0x4             /* Receive Line Status Enable */
  35 #define SERIAL_IER_MS                   0x8             /* Modem Staus Enable */
  36
  37 /* IIR Register */
  38 #define SERIAL_IIR_NONE                 0x1                     /* No interrupt pending */
  39 #define SERIAL_IIR_RLS                  0x6                     /* Receive Line Status */
  40 #define SERIAL_IIR_DR                   0x4                     /* Receive Data Ready */
  41 #define SERIAL_IIR_TIMEOUT              0xc                     /* Receive Time Out */
  42 #define SERIAL_IIR_TE                   0x2                     /* THR Empty */
  43 #define SERIAL_IIR_MODEM                0x0                     /* Modem Status */
  44
  45 /* FCR Register */
  46 #define SERIAL_FCR_FE                   0x1                     /* FIFO Enable */
  47 #define SERIAL_FCR_RXFR                 0x2                     /* Rx FIFO Reset */
  48 #define SERIAL_FCR_TXFR                 0x4                     /* Tx FIFO Reset */
  49
  50 #define SERIAL_FCR_TRIGGER_MASK                 0xC0            /* Mask for the FIFO trigger range */
  51 #define SERIAL_FCR_DMA_SELECT                   0x08            /* For DMA applications */
  52 #define SERIAL_FCR_TRIGGER_1                    0x00            /* Mask for trigger set at 1 */
  53 #define SERIAL_FCR_TRIGGER_4                    0x40            /* Mask for trigger set at 4 */
  54 #define SERIAL_FCR_TRIGGER_8                    0x80            /* Mask for trigger set at 8 */
  55 #define SERIAL_FCR_TRIGGER_14                   0xC0            /* Mask for trigger set at 14 */
  56
  57
  58
  59 /* LCR Register */
  60 #define SERIAL_LCR_LEN5                0x0
  61 #define SERIAL_LCR_LEN6                0x1
  62 #define SERIAL_LCR_LEN7                0x2
  63 #define SERIAL_LCR_LEN8                0x3
  64
  65 #define SERIAL_LCR_STOP                0x4
  66 //#define SERIAL_LCR_EVEN                0x18           /* Even Parity */
  67 #define SERIAL_LCR_EVEN                0x10             /* Even Parity */
  68 #define SERIAL_LCR_ODD                 0x8              /* Odd Parity */
  69 #define SERIAL_LCR_PE                  0x8                      /* Parity Enable */
  70 #define SERIAL_LCR_SETBREAK            0x40                     /* Set Break condition */
  71 #define SERIAL_LCR_STICKPARITY         0x20                     /* Stick Parity Enable */
  72 #define SERIAL_LCR_DLAB                0x80             /* Divisor Latch Access Bit */
  73
  74 /* LSR Register */
  75 #define SERIAL_LSR_DR                  0x1              /* Data Ready */
  76 #define SERIAL_LSR_OE                  0x2              /* Overrun Error */
  77 #define SERIAL_LSR_PE                  0x4              /* Parity Error */
  78 #define SERIAL_LSR_FE                  0x8              /* Framing Error */
  79 #define SERIAL_LSR_BI                  0x10             /* Break Interrupt */
  80 #define SERIAL_LSR_THRE                0x20             /* THR Empty */
  81 #define SERIAL_LSR_TE                  0x40             /* Transmitte Empty */
  82 #define SERIAL_LSR_DE                  0x80             /* FIFO Data Error */
  83
  84 /* MCR Register */
  85 #define SERIAL_MCR_DTR                 0x1              /* Data Terminal Ready */
  86 #define SERIAL_MCR_RTS                 0x2              /* Request to Send */
  87 #define SERIAL_MCR_OUT1                0x4              /* output       1 */
  88 #define SERIAL_MCR_OUT2                0x8              /* output2 or global interrupt enable */
  89 #define SERIAL_MCR_LPBK                0x10             /* loopback mode */
  90
  91
  92 /* MSR Register */
  93 #define SERIAL_MSR_DELTACTS            0x1              /* Delta CTS */
  94 #define SERIAL_MSR_DELTADSR            0x2              /* Delta DSR */
  95 #define SERIAL_MSR_TERI                0x4              /* Trailing Edge RI */
  96 #define SERIAL_MSR_DELTACD             0x8              /* Delta CD */
  97 #define SERIAL_MSR_CTS                 0x10             /* Clear To Send */
  98 #define SERIAL_MSR_DSR                 0x20             /* Data Set Ready */
  99 #define SERIAL_MSR_RI                  0x40             /* Ring Indicator */
 100 #define SERIAL_MSR_DCD                 0x80             /* Data Carrier Detect */
 101 #define SERIAL_MSR_ANY_DELTA               0x0f
 102
 103
 104 /* MDR register */
 105 #define SERIAL_MDR_MODE_SEL                             0x03
 106 #define SERIAL_MDR_UART                                 0x0
 107 #define SERIAL_MDR_SIR                                  0x1
 108 #define SERIAL_MDR_FIR                                  0x2
 109
 110 /* ACR register */
 111 #define SERIAL_ACR_TXENABLE                             0x1
 112 #define SERIAL_ACR_RXENABLE                             0x2
 113 #define SERIAL_ACR_SET_EOT                              0x4
 114
 115 #endif