| blob | f41eb0010eb9a970ed60cc3dedffed9870f81f6d |
1 /*
2 * linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
3 *
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2001 Altera Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm922.
25 *
26 * CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
27 */
28 #include <linux/linkage.h>
29 #include <linux/config.h>
30 #include <linux/init.h>
31 #include <asm/assembler.h>
32 #include <asm/pgtable.h>
33 #include <asm/procinfo.h>
34 #include <asm/hardware.h>
35 #include <asm/page.h>
36 #include <asm/ptrace.h>
37 #include "proc-macros.S"
39 /*
40 * The size of one data cache line.
41 */
42 #if 0 /* mask by Victor Yu. 05-30-2005 */
43 #define CACHE_DLINESIZE 32
44 #else /* add by Victor Yu. 05-30-2005 */
45 #define CACHE_DLINESIZE 16
46 #define CACHE_DSIZE 16384
47 #define CACHE_ISIZE 16384
48 #define CACHE_ILINESIZE 16
49 #endif
51 /*
52 * The number of data cache segments.
53 */
54 #define CACHE_DSEGMENTS 4
56 /*
57 * The number of lines in a cache segment.
58 */
59 #define CACHE_DENTRIES 64
61 /*
62 * This is the size at which it becomes more efficient to
63 * clean the whole cache, rather than using the individual
64 * cache line maintainence instructions. (I think this should
65 * be 32768).
66 */
67 #define CACHE_DLIMIT 8192
70 .text
71 /*
72 * cpu_arm922_proc_init()
73 */
74 ENTRY(cpu_arm922_proc_init)
75 mov pc, lr
77 /*
78 * cpu_arm922_proc_fin()
79 */
80 ENTRY(cpu_arm922_proc_fin)
81 stmfd sp!, {lr}
82 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
83 msr cpsr_c, ip
84 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
85 bl arm922_flush_kern_cache_all
86 #else
87 bl v4wt_flush_kern_cache_all
88 #endif
89 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
90 bic r0, r0, #0x1000 @ ...i............
91 bic r0, r0, #0x000e @ ............wca.
92 mcr p15, 0, r0, c1, c0, 0 @ disable caches
93 ldmfd sp!, {pc}
95 /*
96 * cpu_arm922_reset(loc)
97 *
98 * Perform a soft reset of the system. Put the CPU into the
99 * same state as it would be if it had been reset, and branch
100 * to what would be the reset vector.
101 *
102 * loc: location to jump to for soft reset
103 */
104 .align 5
105 ENTRY(cpu_arm922_reset)
106 mov ip, #0
107 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
108 mcr p15, 0, ip, c7, c10, 4 @ drain WB
109 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
110 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
111 bic ip, ip, #0x000f @ ............wcam
112 bic ip, ip, #0x1100 @ ...i...s........
113 #if 1 /* add by Victor Yu. 06-09-2005 */
114 #ifdef CONFIG_ARCH_MOXACPU
115 bic ip, ip, #0x0800 @ off BTB
116 #endif
117 #endif
118 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
119 #if 1 /* add by Victor Yu. 06-09-2005 */
120 #ifdef CONFIG_ARCH_MOXACPU
121 nop
122 nop
123 #endif
124 #endif
125 mov pc, r0
127 /*
128 * cpu_arm922_do_idle()
129 */
130 .align 5
131 ENTRY(cpu_arm922_do_idle)
132 #if 1 /* add by Victor Yu. 06-09-2005 */
133 #ifdef CONFIG_ARCH_MOXACPU
134 #ifdef CONFIG_CPU_FA_IDLE
135 nop
136 nop
137 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
138 #endif /* CONFIG_CPU_FA_IDLE */
139 #endif /* CONFIG_ARCH_MOXACPU */
140 #endif
141 mov pc, lr
144 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
146 /*
147 * flush_user_cache_all()
148 *
149 * Clean and invalidate all cache entries in a particular
150 * address space.
151 */
152 ENTRY(arm922_flush_user_cache_all)
153 /* FALLTHROUGH */
155 /*
156 * flush_kern_cache_all()
157 *
158 * Clean and invalidate the entire cache.
159 */
160 ENTRY(arm922_flush_kern_cache_all)
161 #if 0 /* mask by Victor Yu. 05-30-2005 */
162 mov r2, #VM_EXEC
163 mov ip, #0
164 __flush_whole_cache:
165 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
166 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
167 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
168 subs r3, r3, #1 << 26
169 bcs 2b @ entries 63 to 0
170 subs r1, r1, #1 << 5
171 bcs 1b @ segments 7 to 0
172 tst r2, #VM_EXEC
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
174 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
175 mov pc, lr
176 #else /* add by Victor Yu. 05-30-2005 */
177 mov ip, #0
179 #ifndef CONFIG_CPU_ICACHE_DISABLE
180 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
181 #endif
183 __flush_whole_cache:
185 #ifndef CONFIG_CPU_DCACHE_DISABLE
186 mov ip, #0
187 # ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
188 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
189 # else
190 mcr p15, 0, ip, c7,c14, 0 @ clean/invalidate D cache
191 # endif
192 #endif /*CONFIG_CPU_DCACHE_DISABLE*/
194 #ifndef CONFIG_CPU_FA_WB_DISABLE
195 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
196 #endif
198 #ifdef CONFIG_CPU_FA_BTB
199 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB
200 nop
201 nop
202 #endif
203 mov pc, lr
204 #endif
206 /*
207 * flush_user_cache_range(start, end, flags)
208 *
209 * Clean and invalidate a range of cache entries in the
210 * specified address range.
211 *
212 * - start - start address (inclusive)
213 * - end - end address (exclusive)
214 * - flags - vm_flags describing address space
215 */
216 ENTRY(arm922_flush_user_cache_range)
217 #if 0 /* mask by Victor Yu. 05-30-2005 */
218 mov ip, #0
219 sub r3, r1, r0 @ calculate total size
220 cmp r3, #CACHE_DLIMIT
221 bhs __flush_whole_cache
223 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
224 tst r2, #VM_EXEC
225 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
226 add r0, r0, #CACHE_DLINESIZE
227 cmp r0, r1
228 blo 1b
229 tst r2, #VM_EXEC
230 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
231 mov pc, lr
232 #else /* add by Victor Yu. 05-30-2005 */
233 mov ip, #0
234 sub r3, r1, r0 @ calculate total size
235 #ifndef CONFIG_CPU_ICACHE_DISABLE
236 tst r2, #VM_EXEC @ executable region?
237 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
238 #endif
240 #ifndef CONFIG_CPU_DCACHE_DISABLE
241 cmp r3, #CACHE_DSIZE @ total size >= limit?
242 bhs __flush_whole_cache @ flush whole D cache
244 1:
246 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
247 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
248 #else
249 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
250 #endif
251 add r0, r0, #CACHE_DLINESIZE
252 cmp r0, r1
253 bls 1b
254 #endif /* CONFIG_CPU_DCACHE_DISABLE */
256 #ifndef CONFIG_CPU_FA_WB_DISABLE
257 tst r2, #VM_EXEC
258 mcreq p15, 0, r4, c7, c10, 4 @ drain write buffer
259 #endif
261 #ifdef CONFIG_CPU_FA_BTB
262 tst r2, #VM_EXEC
263 mov ip, #0
264 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
265 nop
266 nop
267 #endif
268 mov pc, lr
269 #endif
271 /*
272 * flush_kern_dcache_page(void *page)
273 *
274 * Ensure no D cache aliasing occurs, either with itself or
275 * the I cache
276 *
277 * - addr - page aligned address
278 */
279 ENTRY(arm922_flush_kern_dcache_page)
280 #if 0 /* mask by Victor Yu. 05-30-2005 */
281 add r1, r0, #PAGE_SZ
282 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
283 add r0, r0, #CACHE_DLINESIZE
284 cmp r0, r1
285 blo 1b
286 mov r0, #0
287 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
288 mcr p15, 0, r0, c7, c10, 4 @ drain WB
289 mov pc, lr
290 #else /* add by Victor Yu. 05-30-2005 */
291 add r1, r0, #PAGE_SZ
292 /* fall through */
293 #endif
295 /*
296 * coherent_kern_range(start, end)
297 *
298 * Ensure coherency between the Icache and the Dcache in the
299 * region described by start, end. If you have non-snooping
300 * Harvard caches, you need to implement this function.
301 *
302 * - start - virtual start address
303 * - end - virtual end address
304 */
305 ENTRY(arm922_coherent_kern_range)
306 /* FALLTHROUGH */
308 /*
309 * coherent_user_range(start, end)
310 *
311 * Ensure coherency between the Icache and the Dcache in the
312 * region described by start, end. If you have non-snooping
313 * Harvard caches, you need to implement this function.
314 *
315 * - start - virtual start address
316 * - end - virtual end address
317 */
318 ENTRY(arm922_coherent_user_range)
319 #if 0 /* mask by Victor Yu. 06-09-2005 */
320 bic r0, r0, #CACHE_DLINESIZE - 1
321 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
322 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
323 add r0, r0, #CACHE_DLINESIZE
324 cmp r0, r1
325 blo 1b
326 mcr p15, 0, r0, c7, c10, 4 @ drain WB
327 mov pc, lr
328 #else /* add by Victor Yu. 06-09-2005 */
329 bic r0, r0, #CACHE_DLINESIZE-1
331 #if !(defined(CONFIG_CPU_DCACHE_DISABLE) && defined(CONFIG_CPU_ICACHE_DISABLE))
332 1:
333 #ifndef CONFIG_CPU_DCACHE_DISABLE
334 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
335 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
336 #else
337 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
338 #endif
339 #endif /* CONFIG_CPU_DCACHE_DISABLE */
341 #ifndef CONFIG_CPU_ICACHE_DISABLE
342 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
343 #endif
344 add r0, r0, #CACHE_DLINESIZE
345 cmp r0, r1
346 bls 1b @ Luke Lee 05/19/2005 blo->bls
347 #endif /* !(defined(CONFIG_CPU_DCACHE_DISABLE) && defined(CONFIG_CPU_ICACHE_DISABLE)) */
349 mov ip, #0
350 #ifdef CONFIG_CPU_FA_BTB
351 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB
352 nop
353 nop
354 #endif
356 #ifndef CONFIG_CPU_FA_WB_DISABLE
357 mcr p15, 0, ip, c7, c10, 4 @ drain WB
358 #endif
360 mov pc, lr
361 #endif
363 /*
364 * dma_inv_range(start, end)
365 *
366 * Invalidate (discard) the specified virtual address range.
367 * May not write back any entries. If 'start' or 'end'
368 * are not cache line aligned, those lines must be written
369 * back.
370 *
371 * - start - virtual start address
372 * - end - virtual end address
373 *
374 * (same as v4wb)
375 */
376 ENTRY(arm922_dma_inv_range)
377 #if 1 /* mask by Victor Yu. 05-30-2005 */
378 tst r0, #CACHE_DLINESIZE - 1
379 bic r0, r0, #CACHE_DLINESIZE - 1
380 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
381 tst r1, #CACHE_DLINESIZE - 1
382 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
383 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
384 add r0, r0, #CACHE_DLINESIZE
385 cmp r0, r1
386 blo 1b
387 mcr p15, 0, r0, c7, c10, 4 @ drain WB
388 mov pc, lr
389 #else /* add by Victor Yu. 05-30-2005 */
390 #ifndef CONFIG_CPU_DCACHE_DISABLE
392 # ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
393 tst r0, #CACHE_DLINESIZE -1
394 bic r0, r0, #CACHE_DLINESIZE -1
395 mcrne p15, 0, r0, c7, c10, 1 @ clean boundary D entry
396 mcr p15, 0, r1, c7, c10, 1 @ clean boundary D entry
397 # else
398 bic r0, r0, #CACHE_DLINESIZE -1
399 # endif /* CONFIG_CPU_DCACHE_WRITETHROUGH */
401 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
402 add r0, r0, #CACHE_DLINESIZE
403 cmp r0, r1
404 bls 1b @ Luke Lee 05/19/2005 blo->bls
405 #endif /* CONFIG_CPU_DCACHE_DISABLE */
407 #ifndef CONFIG_CPU_FA_WB_DISABLE
408 mov r0, #0
409 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
410 #endif
411 mov pc, lr
412 #endif
414 /*
415 * dma_clean_range(start, end)
416 *
417 * Clean the specified virtual address range.
418 *
419 * - start - virtual start address
420 * - end - virtual end address
421 *
422 * (same as v4wb)
423 */
424 ENTRY(arm922_dma_clean_range)
425 #if 0 /* mask by Victor Yu. 05-30-2005 */
426 bic r0, r0, #CACHE_DLINESIZE - 1
427 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
428 add r0, r0, #CACHE_DLINESIZE
429 cmp r0, r1
430 blo 1b
431 mcr p15, 0, r0, c7, c10, 4 @ drain WB
432 mov pc, lr
433 #else /* add by Victor Yu. 05-30-2005 */
434 #ifndef CONFIG_CPU_DCACHE_DISABLE
435 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
436 bic r0, r0, #CACHE_DLINESIZE - 1
437 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
438 add r0, r0, #CACHE_DLINESIZE
439 cmp r0, r1
440 bls 1b @ Luke Lee 05/19/2005 blo->bls
442 #endif /* CONFIG_CPU_DCACHE_WRITETHROUGH */
443 #endif /* CONFIG_CPU_DCACHE_DISABLE */
445 #ifndef CONFIG_CPU_FA_WB_DISABLE
446 mov r0, #0
447 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
448 #endif
449 mov pc, lr
450 #endif
452 /*
453 * dma_flush_range(start, end)
454 *
455 * Clean and invalidate the specified virtual address range.
456 *
457 * - start - virtual start address
458 * - end - virtual end address
459 */
460 ENTRY(arm922_dma_flush_range)
461 #if 0 /* mask by Victor Yu. 06-09-2005 */
462 bic r0, r0, #CACHE_DLINESIZE - 1
463 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
464 add r0, r0, #CACHE_DLINESIZE
465 cmp r0, r1
466 blo 1b
467 mcr p15, 0, r0, c7, c10, 4 @ drain WB
468 mov pc, lr
469 #else /* add by Victor Yu. 06-09-2005 */
470 .globl arm922_dma_flush_range
471 .set arm922_dma_flush_range, arm922_coherent_kern_range
472 #endif
474 ENTRY(arm922_cache_fns)
475 .long arm922_flush_kern_cache_all
476 .long arm922_flush_user_cache_all
477 .long arm922_flush_user_cache_range
478 .long arm922_coherent_kern_range
479 .long arm922_coherent_user_range
480 .long arm922_flush_kern_dcache_page
481 .long arm922_dma_inv_range
482 .long arm922_dma_clean_range
483 .long arm922_dma_flush_range
484 #if 1 /* add by Victor Yu. 06-09-2005 */
485 .size arm922_cache_fns, . - arm922_cache_fns
486 #endif
487 #endif
490 ENTRY(cpu_arm922_dcache_clean_area)
491 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
492 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
493 add r0, r0, #CACHE_DLINESIZE
494 subs r1, r1, #CACHE_DLINESIZE
495 bhi 1b
496 #endif
497 mov pc, lr
499 /* =============================== PageTable ============================== */
501 /*
502 * cpu_arm922_switch_mm(pgd)
503 *
504 * Set the translation base pointer to be as described by pgd.
505 *
506 * pgd: new page tables
507 */
508 .align 5
509 ENTRY(cpu_arm922_switch_mm)
510 mov ip, #0
511 #if 0 /* mask by Victor Yu. 06-09-2005 */
512 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
513 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
514 #else
515 @ && 'Clean & Invalidate whole DCache'
516 @ && Re-written to use Index Ops.
517 @ && Uses registers r1, r3 and ip
519 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 4 segments
520 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
521 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
522 subs r3, r3, #1 << 26
523 bcs 2b @ entries 63 to 0
524 subs r1, r1, #1 << 5
525 bcs 1b @ segments 7 to 0
526 #endif /* CONFIG_CPU_DCACHE_WRITETHROUGH */
527 #else /* add by Victor Yu. 06-09-2005 */
528 #ifndef CONFIG_CPU_DCACHE_DISABLE
529 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
530 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
531 #else
532 mcr p15, 0, ip, c7, c14, 0 @ Clean and invalidate whole DCache
533 #endif /* CONFIG_CPU_DCACHE_WRITETHROUGH */
534 #endif /*CONFIG_CPU_DCACHE_DISABLE*/
535 #endif
536 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
537 mcr p15, 0, ip, c7, c10, 4 @ drain WB
538 #if 1 /* add by Victor Yu. 06-09-2005 */
539 #ifdef CONFIG_ARCH_MOXACPU
540 bic r0, r0, #0xff @ clear bits [7:0]
541 bic r0, r0, #0x3f00 @ clear bits [13:8]
542 #endif
543 #endif
544 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
545 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
546 #if 1 /* add by Victor Yu. 06-09-2005 */
547 #ifdef CONFIG_ARCH_MOXACPU
548 nop
549 nop
550 #endif
551 #endif
552 mov pc, lr
554 /*
555 * cpu_arm922_set_pte(ptep, pte)
556 *
557 * Set a PTE and flush it out
558 */
559 .align 5
560 ENTRY(cpu_arm922_set_pte)
561 str r1, [r0], #-2048 @ linux version
563 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
565 bic r2, r1, #PTE_SMALL_AP_MASK
566 bic r2, r2, #PTE_TYPE_MASK
567 orr r2, r2, #PTE_TYPE_SMALL
569 tst r1, #L_PTE_USER @ User?
570 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
572 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
573 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
575 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
576 movne r2, #0
578 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
579 eor r3, r2, #0x0a @ C & small page?
580 tst r3, #0x0b
581 biceq r2, r2, #4
582 #endif
583 str r2, [r0] @ hardware version
584 #if 0 /* mask by Victor Yu. 06-09-2005 */
585 mov r0, r0
586 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
587 mcr p15, 0, r0, c7, c10, 4 @ drain WB
588 #else // add by Victor Yu. 06-09-2005 */
589 mov r2, #0
590 mcr p15, 0, r2, c7, c10, 0 @ clean D cache all
591 #endif
592 mov pc, lr
594 __INIT
596 .type __arm922_setup, #function
597 __arm922_setup:
598 mov r0, #0
599 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
600 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
601 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
602 #if 1 /* add by Victor Yu. 06-09-2005 */
603 #ifdef CONFIG_ARCH_MOXACPU
604 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
605 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB all
607 mov r0, #1
608 mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
610 mrc p15, 0, r0, c9, c1, 0 @ DScratchpad
611 bic r0, r0, #1
612 mcr p15, 0, r0, c9, c1, 0 @ disable it
613 mrc p15, 0, r0, c9, c1, 1 @ IScratchpad
614 bic r0, r0, #1
615 mcr p15, 0, r0, c9, c1, 1 @ disable it
617 mrc p15, 0, r0, c1, c0, 0 @ get control register v4
618 bic r0, r0, #0x0800
619 mcr p15, 0, r0, c1, c0, 0 @ disable it
621 mov r0, #0
622 mcr p15, 0, r0, c1, c1, 0 @ turn-off ECR
623 #endif /* CONFIG_ARCH_MOXACPU */
624 #endif
625 mcr p15, 0, r4, c2, c0 @ load page table pointer
626 mov r0, #0x1f @ Domains 0, 1 = client
627 mcr p15, 0, r0, c3, c0 @ load domain access register
628 mrc p15, 0, r0, c1, c0 @ get control register v4
629 /*
630 * Clear out 'unwanted' bits (then put them in if we need them)
631 */
632 @ VI ZFRS BLDP WCAM
633 bic r0, r0, #0x0e00
634 bic r0, r0, #0x0002
635 bic r0, r0, #0x000c
636 bic r0, r0, #0x1000 @ ...0 000. .... 000.
637 /*
638 * Turn on what we want
639 */
640 orr r0, r0, #0x0031
641 orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
643 #ifndef CONFIG_CPU_DCACHE_DISABLE
644 orr r0, r0, #0x0004 @ .... .... .... .1..
645 #endif
646 #ifndef CONFIG_CPU_ICACHE_DISABLE
647 orr r0, r0, #0x1000 @ ...1 .... .... ....
648 #endif
649 mov pc, lr
650 .size __arm922_setup, . - __arm922_setup
652 __INITDATA
654 /*
655 * Purpose : Function pointers used to access above functions - all calls
656 * come through these
657 */
658 .type arm922_processor_functions, #object
659 arm922_processor_functions:
660 #if 0 /* mask by Victor Yu. 06-08-2005 */
661 .word v4t_early_abort
662 #else /* add by Victor YU. 06-08-2005 */
663 .word v4_early_abort
664 #endif
665 .word cpu_arm922_proc_init
666 .word cpu_arm922_proc_fin
667 .word cpu_arm922_reset
668 .word cpu_arm922_do_idle
669 .word cpu_arm922_dcache_clean_area
670 .word cpu_arm922_switch_mm
671 .word cpu_arm922_set_pte
672 .size arm922_processor_functions, . - arm922_processor_functions
674 .section ".rodata"
676 .type cpu_arch_name, #object
677 cpu_arch_name:
678 .asciz "armv4t"
679 .size cpu_arch_name, . - cpu_arch_name
681 .type cpu_elf_name, #object
682 cpu_elf_name:
683 .asciz "v4"
684 .size cpu_elf_name, . - cpu_elf_name
686 .type cpu_arm922_name, #object
687 cpu_arm922_name:
688 .ascii "ARM922T"
689 #ifndef CONFIG_CPU_ICACHE_DISABLE
690 .ascii "i"
691 #endif
692 #ifndef CONFIG_CPU_DCACHE_DISABLE
693 .ascii "d"
694 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
695 .ascii "(wt)"
696 #else
697 .ascii "(wb)"
698 #endif
699 #endif
700 .ascii "\0"
701 .size cpu_arm922_name, . - cpu_arm922_name
703 .align
705 .section ".proc.info", #alloc, #execinstr
707 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
708 #define __PMD_SECT_BUFFERABLE 0
709 #else
710 #define __PMD_SECT_BUFFERABLE PMD_SECT_BUFFERABLE
711 #endif
712 .type __arm922_proc_info,#object
713 __arm922_proc_info:
714 #ifdef CONFIG_ARCH_MOXACPU /* add by Victor Yu. 05-23-2005 */
715 .long 0x66015261
716 .long 0xff01fff1
717 #if 1
718 .long PMD_TYPE_SECT | \
719 __PMD_SECT_BUFFERABLE | \
720 PMD_SECT_CACHEABLE | \
721 PMD_BIT4 | \
722 PMD_SECT_AP_WRITE | \
723 PMD_SECT_AP_READ
724 #else
725 .long 0x00000812
726 #endif
727 #else /* mask by Victor Yu. 05-23-2005 */
728 .long 0x41009220
729 .long 0xff00fff0
730 .long 0x00000c1e @ mmuflags
731 #endif /* CONFIG_ARCH_MOXACPU */
732 b __arm922_setup
733 .long cpu_arch_name
734 .long cpu_elf_name
735 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
736 .long cpu_arm922_name
737 .long arm922_processor_functions
738 .long v4wbi_tlb_fns
739 .long v4wb_user_fns
740 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
741 .long arm922_cache_fns
742 #else
743 .long v4wt_cache_fns
744 #endif
745 .size __arm922_proc_info, . - __arm922_proc_info