arch/arm/mach-moxacpu/cpe_setup.c

   1 /*
   2  * History:
   3  * Date         Author                  Comment
   4  * 05-12-2005   Victor Yu.              Create it.
   5  */
   6 #include <linux/init.h>
   7 #include <linux/device.h>
   8 #include <linux/serial.h>
   9 #include <linux/tty.h>
  10 #include <linux/serial_core.h>
  11 #include <linux/delay.h>
  12 #include <linux/pm.h>
  13 #include <linux/interrupt.h>
  14
  15 #include <asm/elf.h>
  16 #include <asm/setup.h>
  17 #include <asm/mach-types.h>
  18 #include <asm/mach/arch.h>
  19 #include <asm/arch/cpe/cpe.h>
  20 #include <asm/arch/irq.h>
  21 #include <asm/arch/hardware.h>
  22 #include <asm/sizes.h>
  23 #include <asm/mach/map.h>
  24
  25 /*
  26  * Following is used Faraday demo board
  27  * Physical     Logical
  28  * 98100000     f9810000    Power Management
  29  * 98200000     f9820000    UART 1
  30  * 98300000     f9830000    UART 2
  31  * 98400000     f9840000    Timer 1/2
  32  * 98800000     f9880000    INTC
  33  * 96700000     f9670000    MAC
  34  * 98700000     f9870000    GPIO
  35  * 98b00000     f98b0000    SSP1
  36  * 90400000     f9040000    AHB
  37  * 90100000     f9010000    AHB
  38  * 80400000     f0400000    Flash
  39  * 90c00000     90c00000    PCI base/IO
  40  * b0000000     b0000000    PCI memory resource
  41  * fb080000     b0800000    A321 Interrupt Controller
  42  *
  43  * Following is used Moxa CPU demo board
  44  * Physical     Logical
  45  * 90100000     f9010000        AHB controller
  46  * 90200000     f9020000        SMC
  47  * 90300000     f9030000        SDRAM controller
  48  * 90400000     f9040000        DMA
  49  * 90500000     f9050000        APB bridge
  50  * 90900000     f9090000        MAC #1
  51  * 90a00000     f90a0000        USB 2.0 host
  52  * 90b00000     f90b0000        USB 2.0 device
  53  * 90c00000     f90c0000        PCI bridge
  54  * 90f00000     f90f0000        DES/3DES/AES encryptor
  55  * 92000000     f9200000        MAC #2
  56  * 92300000     f9230000        EBI
  57  * 98100000     f9810000        PMU (power management)
  58  * 98200000     f9820000        UART (port 1 - 6), embedded on CPU
  59  * 98400000     f9840000        timer #1 & #2
  60  * 98500000     f9850000        watchdog timer
  61  * 98600000     f9860000        RTC, embedded on CPU
  62  * 98700000     f9870000        GPIO
  63  * 98800000     f9880000        INTC (interrupt controller)
  64  * 98b00000     f98b0000        SPI
  65  * 98e00000     f98e0000        SD controller
  66  * 99400000     f9940000        AC97
  67  * a0000000     a0000000        PCI memory
  68  */
  69
  70 static struct map_desc cpe_io_desc[] __initdata = {
  71 #ifdef CONFIG_ARCH_CPE
  72  { CPE_PMU_VA_BASE,     CPE_PMU_BASE,       SZ_4K, MT_DEVICE},
  73  { CPE_UART1_VA_BASE,   CPE_UART1_BASE,     SZ_4K, MT_DEVICE},
  74  { CPE_UART2_VA_BASE,   CPE_UART2_BASE,     SZ_4K, MT_DEVICE},
  75  { CPE_TIMER1_VA_BASE,  CPE_TIMER1_BASE,    SZ_4K, MT_DEVICE},
  76  { CPE_IC_VA_BASE,      CPE_IC_BASE,        SZ_4K, MT_DEVICE},
  77  { CPE_FTMAC_VA_BASE,   CPE_FTMAC_BASE,     SZ_4K, MT_DEVICE},
  78  { CPE_GPIO_VA_BASE,    CPE_GPIO_BASE,      SZ_4K, MT_DEVICE},
  79  { CPE_SSP1_VA_BASE,    CPE_SSP1_BASE,      SZ_4K, MT_DEVICE},
  80  { CPE_AHBDMA_VA_BASE,  CPE_AHBDMA_BASE,    SZ_4K, MT_DEVICE},
  81  { CPE_AHB_VA_BASE,     CPE_AHB_BASE,       SZ_4K, MT_DEVICE},
  82  { CPE_FLASH_VA_BASE,   CPE_FLASH_BASE,     CPE_FLASH_SZ,  MT_DEVICE},
  83  { CPE_PCI_VA_MEM,      CPE_PCI_MEM,        PCI_MEM_SIZE,  MT_DEVICE},
  84  { CPE_PCI_VA_BASE,     CPE_PCI_BASE,       PCI_MEM_SIZE,  MT_DEVICE},
  85  { CPE_A321_IC_VA_BASE, CPE_A321_IC_BASE,   SZ_4K, MT_DEVICE},
  86  { CPE_HOST20_VA_BASE,  CPE_HOST20_BASE,    SZ_4K, MT_DEVICE},
  87  { CPE_USBDEV_VA_BASE,  CPE_USBDEV_BASE,    SZ_4K, MT_DEVICE},
  88  { IO_ADDRESS(0x90E00000),    0x90E00000, SZ_4K, MT_DEVICE},// for HW crypto engine
  89  { IO_ADDRESS(0xB0900000),    0xB0900000, SZ_4K, MT_DEVICE},// for embedded UART
  90  { CPE_SD_VA_BASE,      CPE_SD_BASE,        SZ_4K, MT_DEVICE},   //SD
  91 #endif  // CONFIG_ARCH_CPE
  92
  93 #ifdef CONFIG_ARCH_MOXACPU
  94         {CPE_AHB_VA_BASE,       CPE_AHB_BASE,           SZ_4K, MT_DEVICE},
  95         {CPE_AHBDMA_VA_BASE,    CPE_AHBDMA_BASE,        SZ_4K, MT_DEVICE},
  96         {CPE_APBDMA_VA_BASE,    CPE_APBDMA_BASE,        SZ_4K, MT_DEVICE},
  97         {CPE_PMU_VA_BASE,       CPE_PMU_BASE,           SZ_4K, MT_DEVICE},
  98         {CPE_TIMER_VA_BASE,     CPE_TIMER_BASE,         SZ_4K, MT_DEVICE},
  99         {CPE_GPIO_VA_BASE,      CPE_GPIO_BASE,          SZ_4K, MT_DEVICE},
 100         {CPE_IC_VA_BASE,        CPE_IC_BASE,            SZ_4K, MT_DEVICE},
 101         {CPE_SD_VA_BASE,        CPE_SD_BASE,            SZ_4K, MT_DEVICE},
 102         {CPE_PCI_VA_BASE,       CPE_PCI_BASE,           SZ_64K, MT_DEVICE},
 103         {PCI_MEM_VA_BASE,       CPE_PCI_MEM,            PCI_MEM_SIZE, MT_DEVICE},
 104         {CPE_FTMAC_VA_BASE,     CPE_FTMAC_BASE,         SZ_4K, MT_DEVICE},
 105         {CPE_FTMAC2_VA_BASE,    CPE_FTMAC2_BASE,        SZ_4K, MT_DEVICE},
 106         {CPE_USBDEV_VA_BASE,    CPE_USBDEV_BASE,        SZ_4K, MT_DEVICE},
 107         {CPE_UART_VA_BASE,      CPE_UART_BASE,          SZ_4K, MT_DEVICE},
 108         {CPE_SPI_VA_BASE,       CPE_SPI_BASE,           SZ_4K, MT_DEVICE},
 109         {CPE_USBHOST_VA_BASE,   CPE_USBHOST_BASE,       SZ_4K, MT_DEVICE},
 110         {CPE_AES_DES_VA_BASE,   CPE_AES_DES_BASE,       SZ_4K, MT_DEVICE},
 111         {CPE_AC97_VA_BASE,      CPE_AC97_BASE,          SZ_4K, MT_DEVICE},
 112         {CPE_EBI_VA_BASE,       CPE_EBI_BASE,           SZ_4K, MT_DEVICE},
 113         {CPE_WATCHDOG_VA_BASE,  CPE_WATCHDOG_BASE,      SZ_4K, MT_DEVICE},
 114         {CPE_RTC_VA_BASE,       CPE_RTC_BASE,           SZ_4K, MT_DEVICE},
 115         {CPE_FLASH_VA_BASE,     CPE_FLASH_BASE,         CPE_FLASH_SZ, MT_DEVICE},
 116 /*
 117 #if defined CONFIG_ARCH_W311
 118         {CPE_WLAN_LED_REG_VA_BASE, CPE_WLAN_LED_REG_BASE, SZ_4K, MT_DEVICE},
 119
 120 #endif
 121 */
 122 #if defined(CONFIG_ARCH_IA241_32128)
 123         {CPE_FLASH_VA_BASE2,    CPE_FLASH_BASE2,        CPE_FLASH_SZ, MT_DEVICE},
 124 #endif  // CONFIG_ARCH_IA241_32128
 125 #endif  // CONFIG_ARCH_MOXACPU
 126 };
 127
 128 #if 1   // add by Victor Yu. 06-02-2005
 129 static struct uart_port cpe_serial_ports[] = {
 130         {
 131                 .iobase         = CPE_UART1_VA_BASE,
 132                 .mapbase        = CPE_UART1_BASE,
 133 #ifdef CONFIG_ARCH_CPE
 134                 .irq            = IRQ_UART1,
 135                 .flags          = UPF_SKIP_TEST,
 136 #endif  // CONFIG_ARCH_CPE
 137 #ifdef CONFIG_ARCH_MOXACPU
 138                 .irq            = IRQ_UART,
 139                 .flags          = UPF_SKIP_TEST | UPF_SHARE_IRQ,
 140 #endif  // CONFIG_ARCH_MOXACPU
 141                 .iotype         = UPIO_PORT,
 142                 .regshift       = 2,
 143                 .uartclk        = CONFIG_UART_CLK,
 144                 .line           = 0,
 145                 .type           = PORT_16550A,
 146                 .fifosize       = 16
 147 #if !(defined CONFIG_ARCH_W311)
 148         }, {
 149                 .iobase         = CPE_UART2_VA_BASE,
 150                 .mapbase        = CPE_UART2_BASE,
 151 #ifdef CONFIG_ARCH_CPE
 152                 .irq            = IRQ_UART2,
 153                 .flags          = UPF_SKIP_TEST,
 154 #endif  // CONFIG_ARCH_CPE
 155 #ifdef CONFIG_ARCH_MOXACPU
 156                 .irq            = IRQ_UART,
 157                 .flags          = UPF_SKIP_TEST | UPF_SHARE_IRQ,
 158 #endif  // CONFIG_ARCH_MOXACPU
 159                 .iotype         = UPIO_PORT,
 160                 .regshift       = 2,
 161                 .uartclk        = CONFIG_UART_CLK,
 162                 .line           = 1,
 163                 .type           = PORT_16550A,
 164                 .fifosize       = 16
 165         }
 166 #else   // add by Victor Yu. 06-13-2005
 167         }
 168 #endif
 169 };
 170 #endif
 171
 172 void __init cpe_map_io(void)
 173 {
 174         early_serial_setup(&cpe_serial_ports[0]);
 175 #if !(defined CONFIG_ARCH_W311)
 176         early_serial_setup(&cpe_serial_ports[1]);
 177 #endif
 178         iotable_init(cpe_io_desc, ARRAY_SIZE(cpe_io_desc));
 179 }
 180
 181 static void __init fixup_cpe(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi)
 182 {
 183         mi->nr_banks      = 1;
 184         mi->bank[0].start = 0;
 185 #if defined(CONFIG_ARCH_UC_7112_LX_PLUS) || defined(CONFIG_ARCH_W311) || defined(CONFIG_ARCH_W321) || defined(CONFIG_ARCH_W325) || defined(CONFIG_ARCH_W315)
 186         mi->bank[0].size  = SZ_32M;
 187 #elif defined(CONFIG_ARCH_IA241_32128) || defined(CONFIG_ARCH_W345_IMP1) || defined(CONFIG_ARCH_IA241_16128)
 188         mi->bank[0].size  = SZ_128M;
 189 #else
 190         mi->bank[0].size  = SZ_64M;
 191 #endif
 192         mi->bank[0].node  = 0;
 193 }
 194
 195 #if 1   // add by Victor Yu. 05-25-2005
 196 extern void     cpe_timer_init(void);
 197 #endif
 198 MACHINE_START(MOXACPU, "Moxa CPU development platform")
 199         MAINTAINER("Victor")
 200         BOOT_MEM(0x00000000, 0x98200000, 0xf9820000)
 201         BOOT_PARAMS(0x00000100)
 202         FIXUP(fixup_cpe)
 203         MAPIO(cpe_map_io)
 204         INITIRQ(irq_init_irq)
 205         INITTIME(cpe_timer_init)
 206 MACHINE_END