drivers/net/arm/moxart_ether.h

   1 /* MOXART Ethernet (RTL8201CP) Device Driver (based on MOXA sources)
   2  * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com>
   3  * This program is free software; you can redistribute it and/or modify it
   4  * under the terms of the GNU General Public License as published by the
   5  * Free Software Foundation; either version 2 of the License,
   6  * or (at your option) any later version.
   7  */
   8
   9 #ifndef _MOXART_ETHERNET_H
  10 #define _MOXART_ETHERNET_H
  11
  12 #define TX_DESC_NUM         64
  13 #define TX_DESC_NUM_MASK    (TX_DESC_NUM-1)
  14 #define RX_DESC_NUM         64
  15 #define RX_DESC_NUM_MASK    (RX_DESC_NUM-1)
  16 #define TX_BUF_SIZE         1600
  17 #define RX_BUF_SIZE         1600
  18
  19 struct tx_desc_t {
  20         union {
  21                 unsigned int ui;
  22 #define TXDMA_OWN           (1<<31)
  23 #define TXPKT_EXSCOL        (1<<1)
  24 #define TXPKT_LATECOL       (1<<0)
  25                 struct {
  26                         /* is aborted due to late collision */
  27                         unsigned int tx_pkt_late_col:1;
  28
  29                         /* is aborted after 16 collisions */
  30                         unsigned int rx_pkt_exs_col:1;
  31
  32                         unsigned int reserved1:29;
  33
  34                         /* is owned by the MAC controller */
  35                         unsigned int tx_dma_own:1;
  36                 } ubit;
  37         } txdes0;
  38         union {
  39                 unsigned int ui;
  40 #define EDOTR               (1<<31)
  41 #define TXIC                (1<<30)
  42 #define TX2FIC              (1<<29)
  43 #define FTS                 (1<<28)
  44 #define LTS                 (1<<27)
  45 #define TXBUF_SIZE_MASK     0x7ff
  46 #define TXBUF_SIZE_MAX      (TXBUF_SIZE_MASK+1)
  47                 struct {
  48                         /* transmit buffer size in byte */
  49                         unsigned int tx_buf_size:11;
  50
  51                         unsigned int reserved2:16;
  52
  53                         /* is the last descriptor of a Tx packet */
  54                         unsigned int lts:1;
  55
  56                         /* is the first descriptor of a Tx packet */
  57                         unsigned int fts:1;
  58
  59                         /* transmit to FIFO interrupt on completion */
  60                         unsigned int tx2_fic:1;
  61
  62                         /* transmit interrupt on completion */
  63                         unsigned int tx_ic:1;
  64
  65                         /* end descriptor of transmit ring */
  66                         unsigned int edotr:1;
  67                 } ubit;
  68         } txdes1;
  69         struct {
  70                 /* transmit buffer physical base address */
  71                 unsigned int phy_tx_buf_baseaddr;
  72
  73                 /* transmit buffer virtual base address */
  74                 unsigned char *virt_tx_buf_baseaddr;
  75         } txdes2;
  76 };
  77
  78 struct rx_desc_t {
  79         union {
  80                 unsigned int ui;
  81 #define RXDMA_OWN           (1<<31)
  82 #define FRS                 (1<<29)
  83 #define LRS                 (1<<28)
  84 #define RX_ODD_NB           (1<<22)
  85 #define RUNT                (1<<21)
  86 #define FTL                 (1<<20)
  87 #define CRC_ERR             (1<<19)
  88 #define RX_ERR              (1<<18)
  89 #define BROADCAST_RXDES0    (1<<17)
  90 #define MULTICAST_RXDES0    (1<<16)
  91 #define RFL_MASK        0x7ff
  92 #define RFL_MAX             (RFL_MASK+1)
  93                 struct {
  94                         /* receive frame length */
  95                         unsigned int recv_frame_len:11;
  96                         unsigned int reserved1:5;
  97
  98                         /* multicast frame */
  99                         unsigned int multicast:1;
 100
 101                         /* broadcast frame */
 102                         unsigned int broadcast:1;
 103                         unsigned int rx_err:1;         /* receive error */
 104                         unsigned int crc_err:1;        /* CRC error */
 105                         unsigned int ftl:1;           /* frame too long */
 106
 107                         /* runt packet, less than 64 bytes */
 108                         unsigned int runt:1;
 109
 110                         /* receive odd nibbles */
 111                         unsigned int rx_odd_nb:1;
 112                         unsigned int reserved2:5;
 113
 114                         /* last receive segment descriptor */
 115                         unsigned int lrs:1;
 116
 117                         /* first receive segment descriptor */
 118                         unsigned int frs:1;
 119
 120                         unsigned int reserved3:1;
 121                         unsigned int rx_dma_own:1;      /* RXDMA onwership */
 122                 } ubit;
 123         } rxdes0;
 124         union {
 125                 unsigned int ui;
 126 #define EDORR               (1<<31)
 127 #define RXBUF_SIZE_MASK     0x7ff
 128 #define RXBUF_SIZE_MAX      (RXBUF_SIZE_MASK+1)
 129                 struct {
 130                         /* receive buffer size */
 131                         unsigned int rx_buf_size:11;
 132
 133                         unsigned int reserved4:20;
 134
 135                         /* end descriptor of receive ring */
 136                         unsigned int edorr:1;
 137                 } ubit;
 138         } rxdes1;
 139         struct {
 140                 /* receive buffer physical base address */
 141                 unsigned int phy_rx_buf_baseaddr;
 142
 143                 /* receive buffer virtual base address */
 144                 unsigned char *virt_rx_buf_baseaddr;
 145         } rxdes2;
 146 };
 147
 148 struct mac_control_reg_t {
 149         unsigned int isr;       /* interrupt status, 0x0 */
 150
 151 /* RXDMA has received packets into RX buffer successfully */
 152 #define RPKT_FINISH         (1<<0)
 153
 154 /* receive buffer unavailable */
 155 #define NORXBUF             (1<<1)
 156
 157 /* TXDMA has moved data into the TX FIFO */
 158 #define XPKT_FINISH         (1<<2)
 159
 160 /* transmit buffer unavailable */
 161 #define NOTXBUF             (1<<3)
 162
 163 /* packets transmitted to ethernet successfully */
 164 #define XPKT_OK_INT_STS     (1<<4)
 165
 166 /* packets transmitted to ethernet lost due to late
 167  * collision or excessive collision
 168  */
 169 #define XPKT_LOST_INT_STS   (1<<5)
 170
 171 /* packets received into RX FIFO successfully */
 172 #define RPKT_SAV            (1<<6)
 173
 174 /* received packet lost due to RX FIFO full */
 175 #define RPKT_LOST_INT_STS   (1<<7)
 176
 177 #define AHB_ERR             (1<<8)         /* AHB error */
 178 #define PHYSTS_CHG          (1<<9)         /* PHY link status change */
 179         unsigned int imr;                      /* interrupt mask, 0x4 */
 180 #define RPKT_FINISH_M       (1<<0)         /* interrupt mask of ISR[0] */
 181 #define NORXBUF_M           (1<<1)         /* interrupt mask of ISR[1] */
 182 #define XPKT_FINISH_M       (1<<2)         /* interrupt mask of ISR[2] */
 183 #define NOTXBUF_M           (1<<3)         /* interrupt mask of ISR[3] */
 184 #define XPKT_OK_M           (1<<4)         /* interrupt mask of ISR[4] */
 185 #define XPKT_LOST_M         (1<<5)         /* interrupt mask of ISR[5] */
 186 #define RPKT_SAV_M          (1<<6)         /* interrupt mask of ISR[6] */
 187 #define RPKT_LOST_M         (1<<7)         /* interrupt mask of ISR[7] */
 188 #define AHB_ERR_M           (1<<8)         /* interrupt mask of ISR[8] */
 189 #define PHYSTS_CHG_M        (1<<9)         /* interrupt mask of ISR[9] */
 190
 191         /* MAC most significant address, 0x8 */
 192         unsigned int mac_madr;
 193
 194 /* the most significant 2 bytes of MAC address */
 195 #define MAC_MADR_MASK       0xffff
 196
 197         /* MAC least significant address, 0xc */
 198         unsigned int mac_ldar;
 199
 200         /* multicast address hash table 0, 0x10 */
 201         unsigned int matht0;
 202
 203         /* multicast address hash table 1, 0x14 */
 204         unsigned int matht1;
 205
 206         /* transmit poll demand, 0x18 */
 207         unsigned int txpd;
 208
 209         /* receive poll demand, 0x1c */
 210         unsigned int rxpd;
 211
 212         /* transmit ring base address, 0x20 */
 213         unsigned int txr_badr;
 214
 215         /* receive ring base address, 0x24 */
 216         unsigned int rxr_badr;
 217
 218         /* interrupt timer control, 0x28 */
 219         unsigned int itc;
 220
 221 /* defines the period of TX cycle time */
 222 #define TXINT_TIME_SEL      (1<<15)
 223
 224 #define TXINT_THR_MASK      (1<<14 | 1 < 13 | 1 < 12)
 225 #define TXINT_CNT_MASK      (1<<11 | 1<<10 | 1<<9 | 1<<8)
 226
 227 /* defines the period of RX cycle time */
 228 #define RXINT_TIME_SEL      (1<<7)
 229
 230 #define RXINT_THR_MASK      (1<<6 | 1<<5 | 1<<4)
 231 #define RXINT_CNT_MASK      (1<<3 | 1<<2 | 1<<1 | 1<<0)
 232
 233         /* automatic polling timer control, 0x2c */
 234         unsigned int aptc;
 235
 236 /* defines the period of TX poll time */
 237 #define TXPOLL_TIME_SEL     (1<<12)
 238
 239 #define TXPOLL_CNT_MASK     (1<<11 | 1<<10 | 1<<9 | 1<<8)
 240 #define TXPOLL_CNT_SHIFT_BIT    8
 241
 242 /* defines the period of RX poll time */
 243 #define RXPOLL_TIME_SEL     (1<<4)
 244
 245 #define RXPOLL_CNT_MASK     (1<<3 | 1<<2 | 1<<1 | 1<<0)
 246 #define RXPOLL_CNT_SHIFT_BIT    0
 247
 248         /* DMA burst length and arbitration control, 0x30 */
 249         unsigned int dblac;
 250
 251 /* enable RX FIFO threshold arbitration */
 252 #define RX_THR_EN           (1<<9)
 253
 254 #define RXFIFO_HTHR_MASK    (1<<8 | 1<<7 | 1<<6)
 255 #define RXFIFO_LTHR_MASK    (1<<5 | 1<<4 | 1<<3)
 256
 257 /* use INCR16 burst command in AHB bus */
 258 #define INCR16_EN           (1<<2)
 259
 260 /* use INCR8 burst command in AHB bus */
 261 #define INCR8_EN            (1<<1)
 262
 263 /* use INCR4 burst command in AHB bus */
 264 #define INCR4_EN            (1<<0)
 265
 266         unsigned int reserved1[21];            /* 0x34 - 0x84 */
 267         unsigned int maccr;                    /* MAC control, 0x88 */
 268 #define RX_BROADPKT         (1<<17)        /* receive boradcast packet */
 269
 270 /* receive all multicast packet */
 271 #define RX_MULTIPKT         (1<<16)
 272
 273 #define FULLDUP             (1<<15)        /* full duplex */
 274
 275 /* append CRC to transmitted packet */
 276 #define CRC_APD             (1<<14)
 277
 278 /* not check incoming packet's dest. address */
 279 #define RCV_ALL             (1<<12)
 280
 281 /* store incoming packet even if its length is great than 1518 bytes */
 282 #define RX_FTL              (1<<11)
 283
 284 /* store incoming packet even if its length is less than 64 bytes */
 285 #define RX_RUNT             (1<<10)
 286
 287 /* enable storing incoming packet if the packet passes hash table
 288  * address filtering and is a multicast packet
 289  */
 290 #define HT_MULTI_EN         (1<<9)
 291
 292 #define RCV_EN              (1<<8)         /* receiver enable */
 293
 294 /* enable packet reception when transmitting packet in half duplex mode */
 295 #define ENRX_IN_HALFTX      (1<<6)
 296
 297 #define XMT_EN              (1<<5)         /* transmitter enable */
 298
 299 /* disable CRC check when receiving packets */
 300 #define CRC_DIS             (1<<4)
 301
 302 #define LOOP_EN             (1<<3)         /* internal loop-back */
 303
 304 /* software reset, last 64 AHB bus clocks */
 305 #define SW_RST              (1<<2)
 306
 307 #define RDMA_EN             (1<<1)         /* enable receive DMA channel */
 308 #define XDMA_EN             (1<<0)         /* enable transmit DMA channel */
 309         unsigned int macsr;                    /* MAC status, 0x8c */
 310 #define COL_EXCEED          (1<<11)        /* collision amount exceeds 16 */
 311
 312 /* transmitter detects late collision */
 313 #define LATE_COL            (1<<10)
 314
 315 /* packet transmitted to ethernet lost due to late collision
 316  * or excessive collision
 317  */
 318 #define XPKT_LOST           (1<<9)
 319
 320 /* packets transmitted to ethernet successfully */
 321 #define XPKT_OK             (1<<8)
 322
 323 /* receiver detects a runt packet */
 324 #define RUNT_MAC_STS        (1<<7)
 325
 326 /* receiver detects a frame that is too long */
 327 #define FTL_MAC_STS         (1<<6)
 328
 329 #define CRC_ERR_MAC_STS     (1<<5)
 330
 331 /* received packets list due to RX FIFO full */
 332 #define RPKT_LOST           (1<<4)
 333
 334 /* packets received into RX FIFO successfully */
 335 #define RPKT_SAVE           (1<<3)
 336
 337 /* incoming packet dropped due to collision */
 338 #define COL                 (1<<2)
 339
 340 #define MCPU_BROADCAST      (1<<1)
 341 #define MCPU_MULTICAST      (1<<0)
 342         unsigned int phycr;                    /* PHY control, 0x90 */
 343
 344 /* initialize a write sequence to PHY by setting this bit to 1.
 345  * This bit would be auto cleared after the write operation is finished.
 346  */
 347 #define MIIWR               (1<<27)
 348
 349 #define MIIRD               (1<<26)
 350 #define REGAD_MASK          (1<<25 | 1<<24 | 1<<23 | 1<<22 | 1<<21)
 351 #define PHYAD_MASK          (1<<20 | 1<<19 | 1<<18 | 1<<17 | 1<<16)
 352 #define MIIRDATA_MASK       0xffff
 353         unsigned int phywdata;                 /* PHY write data, 0x94 */
 354 #define MIIWDATA_MASK       0xffff
 355         unsigned int fcr;                      /* flow control, 0x98 */
 356 #define PAUSE_TIME_MASK     0xffff0000
 357 #define FC_HIGH_MASK        (1<<15 | 1<<14 | 1<<13 | 1<<12)
 358 #define FC_LOW_MASK         (1<<11 | 1<<10 | 1<<9 | 1<<8)
 359 #define RX_PAUSE            (1<<4)         /* receive pause frame */
 360
 361 /* packet transmission is paused due to receive */
 362 #define TXPAUSED            (1<<3)
 363
 364         /* pause frame */
 365
 366 /* enable flow control threshold mode. */
 367 #define FCTHR_EN            (1<<2)
 368
 369 #define TX_PAUSE            (1<<1)         /* transmit pause frame */
 370 #define FC_EN               (1<<0)         /* flow control mode enable */
 371         unsigned int bpr;                      /* back pressure, 0x9c */
 372 #define BK_LOW_MASK         (1<<11 | 1<<10 | 1<<9 | 1<<8)
 373 #define BKJAM_LEN_MASK      (1<<7 | 1<<6 | 1<<5 | 1<<4)
 374 #define BK_MODE             (1<<1)         /* back pressure address mode */
 375 #define BK_EN               (1<<0)         /* back pressure mode enable */
 376         unsigned int reserved2[9];             /* 0xa0 - 0xc0 */
 377         unsigned int ts;                       /* test seed, 0xc4 */
 378 #define TEST_SEED_MASK      0x3fff
 379         unsigned int dmafifos;                 /* DMA/FIFO state, 0xc8 */
 380 #define TXD_REQ             (1<<31)        /* TXDMA request */
 381 #define RXD_REQ             (1<<30)        /* RXDMA request */
 382 #define DARB_TXGNT          (1<<29)        /* TXDMA grant */
 383 #define DARB_RXGNT          (1<<28)        /* RXDMA grant */
 384 #define TXFIFO_EMPTY        (1<<27)        /* TX FIFO is empty */
 385 #define RXFIFO_EMPTY        (1<<26)        /* RX FIFO is empty */
 386 #define TXDMA2_SM_MASK      (1<<14 | 1<<13 | 1<<12)
 387 #define TXDMA1_SM_MASK      (1<<11 | 1<<10 | 1<<9 | 1<<8)
 388 #define RXDMA2_SM_MASK      (1<<6 | 1<<5 | 1<<4)
 389 #define RXDMA1_SM_MASK      (1<<3 | 1<<2 | 1<<1 | 1<<0)
 390         unsigned int tm;                       /* test mode, 0xcc */
 391 #define SINGLE_PKT          (1<<26)        /* single packet mode */
 392
 393 /* automatic polling timer test mode */
 394 #define PTIMER_TEST         (1<<25)
 395
 396 #define ITIMER_TEST         (1<<24)        /* interrupt timer test mode */
 397 #define TEST_SEED_SEL       (1<<22)        /* test seed select */
 398 #define SEED_SEL            (1<<21)        /* seed select */
 399 #define TEST_MODE           (1<<20)        /* transmission test mode */
 400 #define TEST_TIME_MASK      (1<<19 | 1<<18 | 1<<17 | 1<<16 | 1<<15 \
 401         | 1<<14 | 1<<13 | 1<<12 | 1<<11 | 1<<10)
 402 #define TEST_EXCEL_MASK     (1<<9 | 1<<8 | 1<<7 | 1<<6 | 1<<5)
 403         unsigned int reserved3;                /* 0xd0 */
 404
 405         /* TX_MCOL and TX_SCOL counter, 0xd4 */
 406         unsigned int txmcol_xscol;
 407
 408 #define TX_MCOL_MASK        0xffff0000
 409 #define TX_MCOL_SHIFT_BIT   16
 410 #define TX_SCOL_MASK        0xffff
 411 #define TX_SCOL_SHIFT_BIT   0
 412         unsigned int rpf_aep;                  /* RPF and AEP counter, 0xd8 */
 413 #define RPF_MASK        0xffff0000
 414 #define RPF_SHIFT_BIT       16
 415 #define AEP_MASK        0xffff
 416 #define AEP_SHIFT_BIT       0
 417         unsigned int xm_pg;                    /* XM and PG counter, 0xdc */
 418 #define XM_MASK         0xffff0000
 419 #define XM_SHIFT_BIT        16
 420 #define PG_MASK         0xffff
 421 #define PG_SHIFT_BIT        0
 422
 423         /* RUNT_CNT and TLCC counter, 0xe0 */
 424         unsigned int runtcnt_tlcc;
 425
 426 #define RUNT_CNT_MASK       0xffff0000
 427 #define RUNT_CNT_SHIFT_BIT  16
 428 #define TLCC_MASK       0xffff
 429 #define TLCC_SHIFT_BIT      0
 430
 431         /* CRCER_CNT and FTL_CNT counter, 0xe4 */
 432         unsigned int crcercnt_ftlcnt;
 433
 434 #define CRCER_CNT_MASK      0xffff0000
 435 #define CRCER_CNT_SHIFT_BIT 16
 436 #define FTL_CNT_MASK        0xffff
 437 #define FTL_CNT_SHIFT_BIT   0
 438         unsigned int rlc_rcc;                  /* RLC and RCC counter, 0xe8 */
 439 #define RLC_MASK        0xffff0000
 440 #define RLC_SHIFT_BIT       16
 441 #define RCC_MASK        0xffff
 442 #define RCC_SHIFT_BIT       0
 443         unsigned int broc;                     /* BROC counter, 0xec */
 444         unsigned int mulca;                    /* MULCA counter, 0xf0 */
 445         unsigned int rp;                       /* RP counter, 0xf4 */
 446         unsigned int xp;                       /* XP counter, 0xf8 */
 447 };
 448
 449 #define ISR_REG_OFFSET                             0x00
 450 #define IMR_REG_OFFSET                             0x04
 451 #define MAC_MADR_REG_OFFSET                        0x08
 452 #define MAC_LADR_REG_OFFSET                        0x0C
 453 #define MATH0_REG_OFFSET                           0x10
 454 #define MATH1_REG_OFFSET                           0x14
 455 #define TXPD_REG_OFFSET                            0x18
 456 #define RXPD_REG_OFFSET                            0x1C
 457 #define TXR_BADR_REG_OFFSET                        0x20
 458 #define RXR_BADR_REG_OFFSET                        0x24
 459 #define ITC_REG_OFFSET                             0x28
 460 #define APTC_REG_OFFSET                            0x2C
 461 #define DBLAC_REG_OFFSET                           0x30
 462 #define MACCR_REG_OFFSET                           0x88
 463 #define MACSR_REG_OFFSET                           0x8C
 464 #define PHYCR_REG_OFFSET                           0x90
 465 #define PHYWDATA_REG_OFFSET                        0x94
 466 #define FCR_REG_OFFSET                             0x98
 467 #define BPR_REG_OFFSET                             0x9C
 468 #define TS_REG_OFFSET                              0xC4
 469 #define DMAFIFOS_REG_OFFSET                        0xC8
 470 #define TM_REG_OFFSET                              0xCC
 471 #define TX_MCOL_TX_SCOL_REG_OFFSET                 0xD4
 472 #define RPF_AEP_REG_OFFSET                         0xD8
 473 #define XM_PG_REG_OFFSET                           0xDC
 474 #define RUNT_CNT_TLCC_REG_OFFSET                   0xE0
 475 #define CRCER_CNT_FTL_CNT_REG_OFFSET               0xE4
 476 #define RLC_RCC_REG_OFFSET                         0xE8
 477 #define BROC_REG_OFFSET                            0xEC
 478 #define MULCA_REG_OFFSET                           0xF0
 479 #define RP_REG_OFFSET                              0xF4
 480 #define XP_REG_OFFSET                              0xF8
 481 #define PHY_CNTL_REG                               0x00
 482 #define PHY_STATUS_REG                             0x01
 483 #define PHY_ID_REG1                                0x02
 484 #define PHY_ID_REG2                                0x03
 485 #define PHY_ANA_REG                                0x04
 486 #define PHY_ANLPAR_REG                             0x05
 487 #define PHY_ANE_REG                                0x06
 488 #define PHY_ECNTL_REG1                             0x10
 489 #define PHY_QPDS_REG                               0x11
 490 #define PHY_10BOP_REG                              0x12
 491 #define PHY_ECNTL_REG2                             0x13
 492 #define FTMAC100_REG_PHY_WRITE                     0x08000000
 493 #define FTMAC100_REG_PHY_READ                      0x04000000
 494
 495 /* PHY Status register */
 496 #define AN_COMPLETE                                0x0020
 497
 498 #define LINK_STATUS                                0x0004
 499
 500 struct moxart_mac_priv_t {
 501         /* Tx descriptor physical base address */
 502         unsigned int phy_tx_desc_baseaddr;
 503
 504         /* Tx descriptor virtual base address */
 505         struct tx_desc_t *virt_tx_desc_baseaddr;
 506
 507         /* Rx descriptor physical base address */
 508         unsigned int phy_rx_desc_baseaddr;
 509
 510         /* Rx descriptor virtual base address */
 511         struct rx_desc_t *virt_rx_desc_baseaddr;
 512
 513         /* Tx buffer physical base address */
 514         unsigned int phy_tx_buf_baseaddr;
 515
 516         /* Tx buffer virtual base address */
 517         unsigned char *virt_tx_buf_baseaddr;
 518
 519         /* Rx buffer physical base address */
 520         unsigned int phy_rx_buf_baseaddr;
 521
 522         /* Rx buffer virtual base address */
 523         unsigned char *virt_rx_buf_baseaddr;
 524
 525         /* Tx descriptor now first used index */
 526         int tx_desc_now;
 527
 528         /* Rx descriptor now first used index */
 529         int rx_desc_now;
 530
 531         /* OS about the ethernet statistics */
 532         struct net_device_stats stats;
 533
 534         spinlock_t txlock;
 535         spinlock_t rxlock;
 536
 537         /* store the maccr control register value */
 538         unsigned int maccr;
 539
 540         struct work_struct rqueue;
 541 };
 542
 543 #if TX_BUF_SIZE >= TXBUF_SIZE_MAX
 544 #error Moxa CPU ethernet device driver Tx buffer size too large !
 545 #endif
 546 #if RX_BUF_SIZE >= RXBUF_SIZE_MAX
 547 #error Moxa CPU ethernet device driver Rx buffer size too large !
 548 #endif
 549
 550 #endif /* MOXACPU_MAC_H */