include/asm-arm/arch-moxart/moxa.h

   1 /*
   2  *      History:
   3  *      Date            Author                  Comment
   4  *      11-17-2005      Victor Yu.              Create it.
   5  */
   6
   7 #ifndef     _MOXACPU_H
   8 #define     _MOXACPU_H
   9
  10 /*****************************************************************
  11     IO Mapping
  12 *****************************************************************/
  13 #define MEM_ADDRESS(x)                  (x)
  14 #define IO_ADDRESS(x)                   (x)
  15 #define PHY_ADDRESS(x)                  (x)
  16
  17 /*****************************************************************
  18     Clock Setting
  19 *****************************************************************/
  20 #define AHB_CLK                         48000000
  21 #define APB_CLK                         48000000
  22
  23 /******************************************************************
  24     AHB/APB device register mapping
  25  *****************************************************************/
  26 #define CPE_AHB_BASE                    0x90100000
  27 #define CPE_SRAMC_BASE                  0x90200000
  28 #define CPE_SDRAMC_BASE                 0x90300000
  29 #define CPE_AHBDMA_BASE                 0x90400000
  30 #define CPE_APBDMA_BASE                 0x90500000
  31 #define CPE_PMU_BASE                    0x98100000
  32 #define CPE_TIMER_BASE                  0x98400000
  33 #define CPE_TIMER1_BASE                 0x98400000
  34 #define CPE_TIMER2_BASE                 0x98400010
  35 #define CPE_GPIO_BASE                   0x98700000
  36 #define CPE_IC_BASE                     0x98800000
  37 #define CPE_SD_BASE                     0x98e00000
  38 #define CPE_PCI_BASE                    0x90c00000
  39 #define CPE_PCI_MEM                     0xa0000000
  40 #define CPE_FTMAC_BASE                  0x90900000
  41 #define CPE_FTMAC2_BASE                 0x92000000   //2nd MAC
  42 #define CPE_USBDEV_BASE                 0x90b00000   //USB device
  43 #define CPE_UART_BASE                   0x98200000
  44 #define CPE_UART1_BASE                  0x98200000
  45 #define CPE_UART2_BASE                  0x98200020
  46 #define CPE_UART3_BASE                  0x98200040
  47 #define CPE_UART4_BASE                  0x98200060
  48 #define CPE_UART5_BASE                  0x98200080
  49 #define CPE_UART6_BASE                  0x982000a0
  50 #define CPE_UART_INT_VEC_BASE           0x982000c0
  51 #define CPE_UART_MODE_BASE              0x982000e4
  52 #define CPE_SPI_BASE                    0x98b00000
  53 #define CPE_USBHOST_BASE                0x90a00000
  54 #define CPE_AES_DES_BASE                0x90f00000
  55 #define CPE_AC97_BASE                   0x99400000
  56 #define CPE_RTC_BASE                    0x98600000
  57 #define CPE_WATCHDOG_BASE               0x98500000
  58 #define CPE_EBI_BASE                    0x92300000
  59
  60 //virtual address
  61 #define CPE_AHB_VA_BASE                 IO_ADDRESS(CPE_AHB_BASE)
  62 #define CPE_SRAMC_VA_BASEi              IO_ADDRESS(CPE_SRAMC_BASE)
  63 #define CPE_SDRAMC_VA_BASE              IO_ADDRESS(CPE_SDRAMC_BASE)
  64 #define CPE_AHBDMA_VA_BASE              IO_ADDRESS(CPE_AHBDMA_BASE)
  65 #define CPE_APBDMA_VA_BASE              IO_ADDRESS(CPE_APBDMA_BASE)
  66 #define CPE_PMU_VA_BASE                 IO_ADDRESS(CPE_PMU_BASE)
  67 #define CPE_TIMER_VA_BASE               IO_ADDRESS(CPE_TIMER_BASE)
  68 #define CPE_TIMER1_VA_BASE              IO_ADDRESS(CPE_TIMER1_BASE)
  69 #define CPE_TIMER2_VA_BASE              IO_ADDRESS(CPE_TIMER2_BASE)
  70 #define CPE_GPIO_VA_BASE                IO_ADDRESS(CPE_GPIO_BASE)
  71 #define CPE_IC_VA_BASE                  IO_ADDRESS(CPE_IC_BASE)
  72 #define CPE_SD_VA_BASE                  IO_ADDRESS(CPE_SD_BASE)
  73 #define CPE_PCI_VA_BASE                 IO_ADDRESS(CPE_PCI_BASE)
  74 #define CPE_PCI_VA_MEM                  IO_ADDRESS(CPE_PCI_MEM)
  75 #define CPE_FTMAC_VA_BASE               IO_ADDRESS(CPE_FTMAC_BASE)
  76 #define CPE_FTMAC2_VA_BASE              IO_ADDRESS(CPE_FTMAC2_BASE)     //2nd MAC
  77 #define CPE_USBDEV_VA_BASE              IO_ADDRESS(CPE_USBDEV_BASE)     //USB device
  78 #define CPE_UART_VA_BASE                IO_ADDRESS(CPE_UART_BASE)
  79 #define CPE_UART1_VA_BASE               IO_ADDRESS(CPE_UART1_BASE)
  80 #define CPE_UART2_VA_BASE               IO_ADDRESS(CPE_UART2_BASE)
  81 #define CPE_UART3_VA_BASE               IO_ADDRESS(CPE_UART3_BASE)
  82 #define CPE_UART4_VA_BASE               IO_ADDRESS(CPE_UART4_BASE)
  83 #define CPE_UART5_VA_BASE               IO_ADDRESS(CPE_UART5_BASE)
  84 #define CPE_UART6_VA_BASE               IO_ADDRESS(CPE_UART6_BASE)
  85 #define CPE_UART_INT_VEC_VA_BASE        IO_ADDRESS(CPE_UART_INT_VEC_BASE)
  86 #define CPE_UART_MODE_VA_BASE           IO_ADDRESS(CPE_UART_MODE_BASE)
  87 #define CPE_SPI_VA_BASE                 IO_ADDRESS(CPE_SPI_BASE)
  88 #define CPE_USBHOST_VA_BASE             IO_ADDRESS(CPE_USBHOST_BASE)
  89 #define CPE_AES_DES_VA_BASE             IO_ADDRESS(CPE_AES_DES_BASE)
  90 #define CPE_AC97_VA_BASE                IO_ADDRESS(CPE_AC97_BASE)
  91 #define CPE_RTC_VA_BASE                 IO_ADDRESS(CPE_RTC_BASE)
  92 #define CPE_WATCHDOG_VA_BASE            IO_ADDRESS(CPE_WATCHDOG_BASE)
  93 #define CPE_EBI_VA_BASE                 IO_ADDRESS(CPE_EBI_BASE)
  94
  95 /*****************************************************************
  96     IRQ
  97 *****************************************************************/
  98 /*
  99 interrupt:
 100  0-31       irq
 101  32-63      fiq
 102  64 - 67    Virtual IRQ (PCI)
 103  68 - 99    Virtual IRQ (reserved)
 104  */
 105 #if 0   // mask by Victor Yu. 11-21-2005, to use default value 128
 106 #define NR_IRQS                         100
 107 #endif
 108 #define CPE_VIRQ_START                  64
 109 #define CPE_NR_IRQS                     32
 110 #define CPE_NR_FIQS                     32
 111
 112 #define VIRQ_PCI_A                      (0+CPE_VIRQ_START)
 113 #define VIRQ_PCI_B                      (1+CPE_VIRQ_START)
 114 #define VIRQ_PCI_C                      (2+CPE_VIRQ_START)
 115 #define VIRQ_PCI_D                      (3+CPE_VIRQ_START)
 116
 117 //irq number
 118 #define IRQ_GPIO                        13
 119 #define IRQ_MAC                         25
 120 #define IRQ_TIMER1                      19
 121 #define IRQ_TIMER2                      14
 122 #define IRQ_TIMER3                      15
 123 #define IRQ_UART                        31
 124 #define IRQ_AES_DES                     29
 125 #define IRQ_USBHOST                     28
 126 #define IRQ_MAC2                        27
 127 #define IRQ_PCI                         26
 128 #define IRQ_APBDMA                      24
 129 #define IRQ_DMAC_ERR                    23
 130 #define IRQ_DMAC_TC                     22
 131 #define IRQ_DMAC                        21
 132 #define IRQ_RTC_SECOND                  18
 133 #define IRQ_RTC_ALARM                   17
 134 #define IRQ_WATCHDOG                    16
 135 #define IRQ_USBDEV_RESUME               12
 136 #define IRQ_USBDEV                      11
 137 #define IRQ_PMU                         8
 138 #define IRQ_AC97                        6
 139 #define IRQ_SD                          5
 140 #define IRQ_SPI                         2
 141
 142 #define LEVEL                           0
 143 #define EDGE                            1
 144 #define H_ACTIVE                        0
 145 #define L_ACTIVE                        1
 146
 147 #define IRQ_SOURCE_REG                  0
 148 #define IRQ_MASK_REG                    0x04
 149 #define IRQ_CLEAR_REG                   0x08
 150 #define IRQ_MODE_REG                    0x0c
 151 #define IRQ_LEVEL_REG                   0x10
 152 #define IRQ_STATUS_REG                  0x14
 153
 154 #define FIQ_SOURCE_REG                  0x20
 155 #define FIQ_MASK_REG                    0x24
 156 #define FIQ_CLEAR_REG                   0x28
 157 #define FIQ_MODE_REG                    0x2c
 158 #define FIQ_LEVEL_REG                   0x30
 159 #define FIQ_STATUS_REG                  0x34
 160
 161 /*****************************************************************
 162     Flash
 163 *****************************************************************/
 164 #if 0   // mask by Victor Yu. 11-17-2005
 165 #define CPE_FLASH_BASE                  0x80400000
 166 #define CPE_FLASH_SZ                    0x02000000
 167 #define CPE_FLASH_VA_BASE               MEM_ADDRESS(CPE_FLASH_BASE)
 168 #endif
 169
 170 /*****************************************************************
 171     PCI
 172 *****************************************************************/
 173 #define PCI_IO_VA_BASE                  (CPE_PCI_VA_BASE+SZ_4K)
 174 #define PCI_IO_VA_SIZE                  (SZ_1M-SZ_4K)
 175 #define PCI_IO_VA_END                   (CPE_PCI_VA_BASE+SZ_1M)
 176 #define PCI_MEM_BASE                    CPE_PCI_MEM
 177 #define PCI_MEM_SIZE                    SZ_1M
 178 #define PCI_MEM_END                     (CPE_PCI_MEM+SZ_1M)
 179
 180 #define PCI_BRIDGE_DEVID                0x4321
 181 #define PCI_BRIDGE_VENID                0x159b
 182
 183 /*****************************************************************
 184     PMU
 185 *****************************************************************/
 186 #define PMU_SSP_DMA_CHANNEL             0x2
 187
 188 #endif  // _MOXACPU_H