drivers/net/ks8695/ks8695_chipdef.h

   1 /*
   2  *  ks8695_chipdef.h
   3  *      This file defines the driver-independent constants, macro and
   4  *      structures used in the Linux driver.
   5  *
   6  *  Copyright (c) 1998-2002 by Micrel-Kendin Operations. All rights reserved.
   7  *
   8  *  Modification History
   9  *
  10  *  Name        Date        Ver     Brief
  11  *  ----------- ----------- ------- ------------------------------------------
  12  *      RLQ     05/13/2000  1.0.0.0 Modified based on KS8695 Linux driver
  13  *
  14  */
  15 #ifndef __KS8695_CHIPDEF_H
  16 #define __KS8695_CHIPDEF_H
  17
  18 #include <linux/module.h>
  19 #include <linux/types.h>
  20 #include <linux/kernel.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/skbuff.h>
  24
  25 /* should change to system wise platform.h instead of local copy */
  26 //#include <asm/arch/platform.h>
  27 //#include "platform.h"
  28
  29 #ifndef BIT
  30 #define BIT(x) (1 << (x))
  31 #endif
  32
  33 #ifndef REG_MISC_CONTROL
  34
  35 #define REG_MISC_CONTROL                0xEA08
  36 #define REG_LAN12_POWERMAGR             0xE84C
  37 #define REG_LAN34_POWERMAGR             0xE850
  38
  39 #endif
  40
  41 /* DMA related register offset */
  42 #define REG_TXCTRL                              0x0000
  43 #define REG_RXCTRL                              0x0004
  44 #define REG_TXSTART                             0x0008
  45 #define REG_RXSTART                             0x000c
  46 #define REG_TXBASE                              0x0010
  47 #define REG_RXBASE                              0x0014
  48 #define REG_STATION_LOW                 0x0018
  49 #define REG_STATION_HIGH                0x001c
  50
  51 #define REG_MAC0_LOW                    0x0080
  52 #define REG_MAC0_HIGH                   0x0084
  53 #define REG_MAC1_LOW                    0x0088
  54 #define REG_MAC1_HIGH                   0x008c
  55 #define REG_MAC2_LOW                    0x0090
  56 #define REG_MAC2_HIGH                   0x0094
  57 #define REG_MAC3_LOW                    0x0098
  58 #define REG_MAC3_HIGH                   0x009c
  59 #define REG_MAC4_LOW                    0x00a0
  60 #define REG_MAC4_HIGH                   0x00a4
  61 #define REG_MAC5_LOW                    0x00a8
  62 #define REG_MAC5_HIGH                   0x00ac
  63 #define REG_MAC6_LOW                    0x00b0
  64 #define REG_MAC6_HIGH                   0x00b4
  65 #define REG_MAC7_LOW                    0x00b8
  66 #define REG_MAC7_HIGH                   0x00bc
  67 #define REG_MAC8_LOW                    0x00c0
  68 #define REG_MAC8_HIGH                   0x00c4
  69 #define REG_MAC9_LOW                    0x00c8
  70 #define REG_MAC9_HIGH                   0x00cc
  71 #define REG_MAC10_LOW                   0x00d0
  72 #define REG_MAC10_HIGH                  0x00d4
  73 #define REG_MAC11_LOW                   0x00d8
  74 #define REG_MAC11_HIGH                  0x00dc
  75 #define REG_MAC12_LOW                   0x00e0
  76 #define REG_MAC12_HIGH                  0x00e4
  77 #define REG_MAC13_LOW                   0x00e8
  78 #define REG_MAC13_HIGH                  0x00ec
  79 #define REG_MAC14_LOW                   0x00f0
  80 #define REG_MAC14_HIGH                  0x00f4
  81 #define REG_MAC15_LOW                   0x00f8
  82 #define REG_MAC15_HIGH                  0x00fc
  83
  84 /* register Bit field defines for Tx Ctrl and (some are shared with RX) */
  85 #define DMA_SOFTRESET                   0x80000000              /* DMA soft reset (shared with RX) */
  86 #define DMA_UDPCHECKSUM                 0x00040000              /* bit 18 (shared with RX) */
  87 #define DMA_TCPCHECKSUM                 0x00020000              /* bit 17 (shared with RX) */
  88 #define DMA_IPCHECKSUM                  0x00010000              /* bit 16 (shared with RX) */
  89 #define DMA_FLOWCTRL                    0x00000200              /* bit 9 (shared with RX) */
  90 #define DMA_LOOPBACK                    0x00000100              /* bit 8 */
  91 #define DMA_ERRORFRAME                  0x00000008              /* bit 3 */
  92 #define DMA_PADDING                             0x00000004              /* bit 2 */
  93 #define DMA_CRC                                 0x00000002              /* bit 1 */
  94 #define DMA_START                               0x00000001              /* bit 0 (shared with RX) */
  95
  96 #define DMA_PBLTMASK                    0x3f000000              /* DMA Burst Size bit mask (shared with RX) */
  97 #define DMA_PBLTSHIFT                   24                              /* DMA Burst Size bit shift */
  98
  99 /* some bits for RX Ctrl register */
 100 #define DMA_BROADCAST                   0x00000040              /* bit 6 */
 101 #define DMA_MULTICAST                   0x00000020              /* bit 5 */
 102 #define DMA_UNICAST                             0x00000010              /* bit 4 */
 103 #define DMA_PROMISCUOUS                 0x00000004              /* bit 2 */
 104
 105 /* Addition station registers */
 106 #define DMA_MACENABLE                   0x80000000              /* enable/disable additional MAC station address */
 107
 108 enum DMAID {
 109         DMA_WAN = 0x6000,                       /* WAN DMA */
 110         DMA_LAN = 0x8000,                       /* LAN DMA */
 111 #ifndef CONFIG_ARCH_KS8695P
 112         DMA_HPNA= 0xA000                        /* HPNA DMA */
 113 #endif
 114 };
 115
 116 /* DESC and Data buffer */
 117 #define DESC_ALIGNMENT                  16      /* two dwords */
 118
 119 /* Receive Descriptor */
 120 typedef struct
 121 {
 122     volatile uint32_t RxFrameControl;
 123     volatile uint32_t RxDMAFragLen;
 124     volatile uint32_t RxDMAFragAddr;
 125     volatile uint32_t RxDMANextPtr;
 126 } RXDESC, *PRXDESC;
 127
 128 #define DESC_OWN_BIT                    0x80000000              /* shared with Tx descriptor */
 129
 130 /* In Linux, we use all 32 bits definitions! */
 131 /* Bits related to RxFrameControl */
 132 #define RFC_FS                                  0x40000000              /* First Descriptor of the received frame */
 133 #define RFC_LS                                  0x20000000              /* Last Descriptor of the received frame */
 134 #define RFC_IPE                                 0x10000000              /* IP checksum generation */
 135 #define RFC_TCPE                                0x08000000              /* TCP checksum generation */
 136 #define RFC_UDPE                                0x04000000              /* UDP checksum generation */
 137 #define RFC_ES                                  0x02000000              /* Error Summary */
 138 #define RFC_MF                                  0x01000000              /* Multicast Frame */
 139
 140 #define RFC_RE                                  0x00080000              /* Report on MII/GMII error */
 141 #define RFC_TL                                  0x00040000              /* Frame Too Long */
 142 #define RFC_RF                                  0x00020000              /* Runt Frame */
 143 #define RFC_CRC                                 0x00010000              /* CRC error */
 144 #define RFC_FT                                  0x00008000              /* Frame Type */
 145
 146 #define RFC_SPN_MASK                    0x00f00000              /* Switch engine destination port map, 20:23 */
 147 #define RFC_FL_MASK                             0x000007ff              /* Frame Length bit mask, 0:10 */
 148 #define RFC_FRAMECTRL_MASK              (RFC_FS | RFC_LS | RFC_ES | RFC_MF | RFC_RE | RFC_TL | RFC_CRC | RFC_FT | RFC_FL_MASK)
 149
 150 /* Bits related to RxDMAFragLen */
 151 #define RFC_RER                                 0x02000000              /* Receive End of Ring */
 152 #define RFC_RBS_MASK                    0x000007ff              /* Receive buffer Size bit mask, 0:10 */
 153
 154 /* Transmit descriptor */
 155 typedef struct
 156 {
 157     volatile uint32_t TxOwnBit;
 158     volatile uint32_t TxFrameControl;
 159     volatile uint32_t TxDMAFragAddr;
 160     volatile uint32_t TxDMANextPtr;
 161 } TXDESC, *PTXDESC;
 162
 163 /* Bits related to TxFrameControl */
 164 #define TFC_IC                                  0x80000000              /* Interrupt on completion */
 165 #define TFC_FS                                  0x40000000              /* first segment */
 166 #define TFC_LS                                  0x20000000              /* last segment */
 167 #define TFC_IPCKG                               0x10000000              /* IP checksum generation */
 168 #define TFC_TCPCKG                              0x08000000              /* TCP checksum generation */
 169 #define TFC_UDPCKG                              0x04000000              /* UDP checksum generation */
 170 #define TFC_TER                                 0x02000000              /* Transmit End of Ring */
 171
 172 #define TFC_SPN_MASK                    0x00f00000              /* Switch engine destination port map, 20:23 */
 173 #define TFC_TBS_MASK                    0x000007ff              /* Transmit Buffer Size Mask (0:10) */
 174 #define TFC_FRAMECTRL_MASK              (TFC_IC | TFC_FS | TFC_LS | TFC_SPN_MASK | TFC_TBS_MASK)
 175
 176 /* Interrupt related (shared among IMR, IER, ISR, IPR, and IQR) */
 177 #define INT_WAN_LINK                    0x80000000              /* WAN link change interrupt */
 178 #define INT_WAN_TX                              0x40000000              /* WAN Tx complete interrupt */
 179 #define INT_WAN_RX                              0x20000000              /* WAN Rx complete interrupt */
 180 #define INT_WAN_TX_UNAVIAL              0x10000000              /* WAN Tx desc unavailable interrupt */
 181 #define INT_WAN_RX_UNAVIAL              0x08000000              /* WAN Rx desc unavailable interrupt */
 182 #define INT_WAN_TX_STOPPED              0x04000000              /* WAN Tx stopped interrupt */
 183 #define INT_WAN_RX_STOPPED              0x02000000              /* WAN Rx stopped interrupt */
 184
 185 #define INT_WAN_MASK                    0x7e000000              /* not include LINK interrupt bit */
 186
 187 #define INT_AMBA_BUS_ERROR              0x01000000              /* AMBA bus error interrupt */
 188
 189 #define INT_HPNA_TX                             0x00800000              /* HPNA Tx complete interrupt */
 190 #define INT_HPNA_RX                             0x00400000              /* HPNA Rx complete interrupt */
 191 #define INT_HPNA_TX_UNAVIAL             0x00200000              /* HPNA Tx desc unavailable interrupt */
 192 #define INT_HPNA_RX_UNAVIAL             0x00100000              /* HPNA Rx desc unavailable interrupt */
 193 #define INT_HPNA_TX_STOPPED             0x00080000              /* HPNA Tx stopped interrupt */
 194 #define INT_HPNA_RX_STOPPED             0x00040000              /* HPNA Rx stopped interrupt */
 195
 196 #define INT_HPNA_MASK                   0x00fc0000
 197
 198 #define INT_LAN_TX                              0x00020000              /* LAN Tx complete interrupt */
 199 #define INT_LAN_RX                              0x00010000              /* LAN Rx complete interrupt */
 200 #define INT_LAN_TX_UNAVIAL              0x00008000              /* LAN Tx desc unavailable interrupt */
 201 #define INT_LAN_RX_UNAVIAL              0x00004000              /* LAN Rx desc unavailable interrupt */
 202 #define INT_LAN_TX_STOPPED              0x00002000              /* LAN Tx stopped interrupt */
 203 #define INT_LAN_RX_STOPPED              0x00001000              /* LAN Rx stopped interrupt */
 204
 205 #define INT_LAN_MASK                    0x0003f000
 206
 207 #define INT_DMA_MASK                    0xfefff000              /* interrupt bit mask for DMA (WAN, HPNA and LAN) */
 208
 209 #define INT_DMA_STOP_MASK               (INT_WAN_TX_STOPPED | INT_WAN_RX_STOPPED | INT_HPNA_TX_STOPPED | INT_HPNA_RX_STOPPED | INT_LAN_TX_STOPPED | INT_LAN_RX_STOPPED)
 210 #define INT_TX_BIT                              BIT(5)
 211 #define INT_RX_BIT                              BIT(4)
 212 #define INT_TX_UNAVAIL_BIT              BIT(3)
 213 #define INT_RX_UNAVAIL_BIT              BIT(2)
 214 #define INT_TX_STOPPED_BIT              BIT(1)
 215 #define INT_RX_STOPPED_BIT              BIT(0)
 216
 217 /* MAC address */
 218 #define MAC_ADDRESS_LEN                 6
 219 #define MAC_MAX_EXTRA                   16
 220
 221 typedef enum {
 222         LED_SPEED,                      /* 0 */
 223         LED_LINK,
 224         LED_FD,                         /* full duplex */
 225         LED_COLLISION,
 226         LED_ACTIVITY,
 227         LED_FD_COLLISION,       /* full duplex/collision */
 228         LED_LINK_ACTIVITY,      /* link/activities */
 229 } LED_SELECTOR;
 230
 231 /* register Bit field for Switch control 0 */
 232 #define SW_CTRL0_AUTO_FAST_AGING        0x00100000      /* automic fast aging when link changed detected */
 233 #define SW_CTRL0_ERROR_PKT              0x00080000              /* pass all error packets */
 234 #define SW_CTRL0_ENABLE_PORT5   0x00040000              /* enable port 5 flow control */
 235 #define SW_CTRL0_ENABLE_PORTS   0x00020000              /* enable flow control for port 1 - 4 */
 236 #define SW_CTRL0_BUFFER_SHARE   0x00010000              /* buffer share mode */
 237 #define SW_CTRL0_AGING_ENABLE   0x00008000              /* aging enable */
 238 #define SW_CTRL0_FAST_AGING             0x00004000              /* fast aging enable */
 239 #define SW_CTRL0_FAST_BACKOFF   0x00002000              /* fast back off */
 240 #define SW_CTRL0_MISMATCH_DISCARD       0x00001000      /* VLAN mismatch discard */
 241 #define SW_CTRL0_NO_BCAST_STORM_PROT    0x00000800              /* no broadcast storm proection tp ,cast pkts */
 242 #define SW_CTRL0_PREAMBLE_MODE  0x00000400              /* back pressure mode */
 243 #define SW_CTRL0_FLOWCTRL_FAIR  0x00000200              /* flow control fair mode */
 244 #define SW_CTRL0_COLLISION_DROP 0x00000100              /* no excessive collision drop */
 245 #define SW_CTRL0_LEN_CHECKING   0x00000080              /* enforced max length checking */
 246 #define SW_CTRL0_6K_BUFFER              0x00000040              /* 6K byte buffer per port reserved for high priority pkts */
 247 #define SW_CTRL0_BACK_PRESSURE  0x00000020              /* back pressure enable */
 248 #define SW_CTRL0_SWITCH_ENABLE  0x00000001              /* enable switch bit */
 249
 250 /* register Bit field for Auto Regotiation */
 251 #define SW_AUTONEGO_COMPLETE    0x00004000              /* auto nego completed */
 252 #define SW_AUTONEGO_RESTART             0x00002000              /* auto nego restart */
 253 #define SW_AUTONEGO_ADV_PUASE   0x00001000              /* auto nego advertise PAUSE */
 254 #define SW_AUTONEGO_ADV_100FD   0x00000800              /* auto nego advertise 100 FD */
 255 #define SW_AUTONEGO_ADV_100HD   0x00000400              /* auto nego advertise 100 HD */
 256 #define SW_AUTONEGO_ADV_10FD    0x00000200              /* auto nego advertise 10 FD */
 257 #define SW_AUTONEGO_ADV_10HD    0x00000100              /* auto nego advertise 10 HD */
 258 #define SW_AUTONEGO_STAT_LINK   0x00000080              /* auto nego link status */
 259 #define SW_AUTONEGO_STAT_DUPLEX 0x00000040              /* auto nego duplex status (solved) */
 260 #define SW_AUTONEGO_STAT_SPEED  0x00000020              /* auto nego speed status (solved) */
 261 #define SW_AUTONEGO_PART_PAUSE  0x00000010              /* auto nego parterner pause */
 262 #define SW_AUTONEGO_PART_100FD  0x00000008              /* auto nego parterner 100 FD */
 263 #define SW_AUTONEGO_PART_100HD  0x00000004              /* auto nego parterner 100 HD */
 264 #define SW_AUTONEGO_PART_10FD   0x00000002              /* auto nego parterner 10 FD */
 265 #define SW_AUTONEGO_PART_10HD   0x00000001              /* auto nego parterner 10 HD */
 266
 267 #define SW_AUTONEGO_ADV_MASK    0x00001f00
 268
 269 #define SW_MAX_LAN_PORTS                4                               /* max LAN ports */
 270
 271 /* bits for SNMP data register (SEMCD) */
 272 #ifndef CONFIG_ARCH_KS8695P
 273 #define SW_SNMP_DATA_VALID      0x80000000              /* counter value is valid */
 274 #define SW_SNMP_DATA_OVERFLOW   0x40000000              /* counter is overflow */
 275 #else
 276 #define SW_SNMP_DATA_OVERFLOW   0x80000000              /* counter is overflow */
 277 #define SW_SNMP_DATA_VALID      0x40000000              /* counter value is valid */
 278 #endif
 279
 280 enum PORTS {
 281         SW_PORT_1 = 0,
 282         SW_PORT_2,
 283         SW_PORT_3,
 284         SW_PORT_4
 285 };
 286
 287 /* bits related to power management */
 288 #define POWER_POWERDOWN                 0x00000010              /* port power down */
 289 #define POWER_DMDX_DISABLE              0x00000008              /* disable auto MDI/MDIX */
 290 #define POWER_FORCE_MDIX                0x00000004              /* if auto MDI/MDIX is disabled, force PHY into MDIX mode */
 291 #define POWER_LOOPBACK                  0x00000002              /* PHY loopback */
 292
 293 #define SW_PHY_AUTO                             0   /* autosense */
 294 #define SW_PHY_10BASE_T                 1   /* 10Base-T */
 295 #define SW_PHY_10BASE_T_FD              2   /* 10Base-T Full Duplex */
 296 #define SW_PHY_100BASE_TX               3   /* 100Base-TX */
 297 #define SW_PHY_100BASE_TX_FD    4   /* 100Base-TX Full Duplex */
 298
 299 #define SW_PHY_DEFAULT                  SW_PHY_AUTO
 300
 301 enum SPANNINGTREE {
 302         SW_SPANNINGTREE_NONE,           /* no spanning tree */
 303         SW_SPANNINGTREE_RX,                     /* spanning tree, RX only */
 304         SW_SPANNINGTREE_TX,                     /* spanning tree, TX only */
 305         SW_SPANNINGTREE_ALL,            /* spanning tree, both TX/RX */
 306 };
 307
 308 /* bits related to port configuration register */
 309 #define SW_PORT_DISABLE_AUTONEG 0x00008000              /* port disable auto nego */
 310 #define SW_PORT_100BASE                 0x00004000              /* force 100 when auto nego disabled */
 311 #define SW_PORT_FULLDUPLEX              0x00002000              /* force full duplex when auto nego disabled */
 312 #define SW_PORT_TX_SPANNINGTREE 0x00000080              /* spanning tree transmit enable */
 313 #define SW_PORT_RX_SPANNINGTREE 0x00000040              /* spanning tree receive enable */
 314 #define SW_PORT_NO_SPANNINGTREE 0x00000020              /* spanning tree disable */
 315 #define SW_PORT_STORM_PROCTION  0x00000010              /* broadcast storm protection (ingress) */
 316 #define SW_PORT_HI_PRIORITY             0x00000008              /* high priority (ingress) */
 317 #define SW_PORT_TOS_ENABLE              0x00000004              /* Enable TOS based priotiry classification (ingress) */
 318 #define SW_PORT_8021Q_ENABLE    0x00000002              /* Enable 802.1Q based priotiry classification (ingress) */
 319 #define SW_PORT_PRIOTIRY_ENABLE 0x00000001              /* Enable priotiry function on the port (egress) */
 320
 321 /* port 5 only */
 322 #define SW_PORT_RX_DIRECT_MODE  0x00004000              /* receive direct mode for port 5 */
 323 #define SW_PORT_TX_PRETAG_MODE  0x00002000              /* transmit pre-tag mode for port 5 */
 324
 325 typedef struct _PORT_INFO {
 326     uint16_t usTag;                                     /* tag value for the port (ingress) */
 327         uint8_t byCrossTalkMask;                /* specify ports that this port can talk to */
 328         uint8_t byStormProtection;              /* broadcast storm protection */
 329         uint8_t bySpanningTree;                 /* spanning tree */
 330         uint8_t byDisableSpanningTreeLearn;     /* disable spanning tree learn for the port */
 331         uint8_t byIngressPriority;              /* ingress priority */
 332         uint8_t byIngressPriorityTOS;   /* TOS based ingress priority */
 333         uint8_t byIngressPriority802_1P;/* 802.1p based ingress priority */
 334         uint8_t byEgressPriority;               /* egress priority */
 335 } PORT_INFO, *PPORT_INFO;
 336
 337 typedef struct _DMA_INFO {
 338         unsigned short  usDMAId;        /* DMAID */
 339         int32_t nBaseAddr;              /* base address */
 340         int32_t nOffset;                /* DMA register offset */
 341         uint8_t bUseFIQ;                /* use FIQ or not */
 342         uint32_t *pbaseVa;
 343         uint32_t nResetCount;           /* DMA reset counter */
 344
 345         /* interrupt related */
 346         uint32_t uIntMask;              /* interrupt mask checked within ISR */
 347         uint32_t uLinkIntMask;          /* WAN link interrupt mask checked within ISR */
 348         uint32_t uIntShift;             /* interrupt bit shift */
 349
 350         /* mac */
 351         uint8_t stMacStation[MAC_ADDRESS_LEN];
 352         uint8_t stMacCurrent[MAC_ADDRESS_LEN];
 353         uint8_t stSwitchMac[MAC_ADDRESS_LEN];
 354
 355         /* spinlock */
 356         spinlock_t      lock;           /* spin lock */
 357         spinlock_t      lock_refill;    /* spin lock */
 358
 359         /* Tx related */
 360         uint8_t bTxStarted;             /* Tx DMA started or stopped! */
 361         uint8_t bTxFlowCtrl;            /* flow control for Tx DMA */
 362         uint8_t bTxOffLoad;             /* enable/disable Task offload for Tx DMA */
 363         uint8_t byTxPBL;                /* Tx PBL */
 364         uint8_t bTxChecksum;            /* checksum enable/disable indicator */
 365         uint8_t bTxNoResource;          /* flag indicates out of Tx resource */
 366         uint32_t uDebugDumpTxPkt;       /* flag to dump tx packet for debugging */
 367
 368         /* Tx desc related */
 369         int32_t nTxDesc;                /* number of Tx descriptors */
 370         int32_t nTxDescNextAvail;       /* next available Tx descriptor */
 371         int32_t nTxDescUsed;            /* used Tx descriptor */
 372         volatile int32_t nTransmitCount;        /* number of packets to transmit */
 373         int32_t nTxProcessedCount;      /* number of packets to transmitted */
 374         int32_t nTxDescTotal;           /* total number fo Tx descriptors */
 375         int32_t nTransmitCoalescing;    /* Tx packets coalescing count */
 376
 377         TXDESC *pTxDescriptors;
 378         dma_addr_t TxDescDMA;
 379         struct ks8695_buffer *pTxSkb;
 380         atomic_t nTxDescAvail;
 381
 382         /* Rx related */
 383         uint8_t bRxStarted;             /* Rx DMA started or stopped! */
 384         uint8_t bRxFlowCtrl;            /* flow control for Rx DMA */
 385         uint8_t bPort5FlowCtrl;         /* flow control for LAN port 5 */
 386         uint8_t bPortsFlowCtrl;         /* flow control for LAN port 1 - 4 */
 387         uint8_t byRxPBL;                /* Rx PBL */
 388         uint8_t bRxChecksum;            /* checksum enable/disable indicator */
 389         uint32_t uRxBufferLen;          /* rx buffer length */
 390         uint32_t uDebugDumpRxPkt;       /* flag to dump rx packet for debugging */
 391         uint32_t uRx1518plus;           /* rx packet counter for 1518 plus for debugging */
 392         uint32_t uRxUnderSize;          /* rx packet counter for under size packets (< 64) */
 393         uint32_t nMaxFilledCount;       /* max refilled count */
 394         uint32_t nMaxProcessedCount;    /* max rx pkt count in one process cycle */
 395
 396         int32_t nRxDesc;                /* number of Rx descriptors */
 397         int32_t nRxDescNextAvail;       /* next available Rx descriptor */
 398         int32_t nRxDescNextToFill;      /* next Rx desc to fill new buffer to */
 399         RXDESC *pRxDescriptors;
 400         dma_addr_t RxDescDMA;
 401         struct ks8695_buffer *pRxSkb;
 402         atomic_t RxDescEmpty;           /* atomic flag for empty Rx descriptor  */
 403         struct tasklet_struct rx_fill_tasklet;
 404         int32_t nRxDescTotal;           /* total number fo Rx descriptors */
 405         int32_t rx_fill_scheduled;      /* flag for rx fill schedule routine */
 406
 407 #ifdef  RX_TASK
 408         struct tasklet_struct rx_tasklet;
 409         int32_t rx_scheduled;           /* flag for rx receive task schedule routine */
 410 #endif
 411
 412 #ifdef  TX_TASK
 413         struct tasklet_struct tx_tasklet;
 414         int32_t tx_scheduled;           /* flag for tx receive task schedule routine */
 415 #endif
 416
 417         /* PHY related */
 418         uint8_t bAutoNegoInProgress[SW_MAX_LAN_PORTS];/* if set, means that auto nego is in progress!!! */
 419         uint8_t bLinkActive[SW_MAX_LAN_PORTS];          /* flag indicates whether link is active or not */
 420         uint8_t bLinkChanged[SW_MAX_LAN_PORTS];         /* link changed indicator */
 421         uint8_t bHalfDuplex[SW_MAX_LAN_PORTS];          /* HD/FD */
 422         uint16_t usCType[SW_MAX_LAN_PORTS];             /* Convert type */
 423         uint16_t usLinkSpeed[SW_MAX_LAN_PORTS];         /* link speed */
 424         PORT_INFO       port[SW_MAX_LAN_PORTS + 1];     /* port related */
 425         int32_t nLinkChangeCount;                       /* trace link change count */
 426         uint8_t byDisableAutoNego[SW_MAX_LAN_PORTS];    /* auto nego/disable auto nego/partial auto nego */
 427         uint8_t bHalfDuplexDetected[SW_MAX_LAN_PORTS];  /* HD/FD detected based on partner's settings */
 428
 429         uint8_t bRxDirectMode;                          /* for port 5 only */
 430         uint8_t bTxRreTagMode;                          /* for port 5 only */
 431
 432         uint8_t bPowerDownReset;        /* perform powerdown reset instead of soft reset */
 433 } DMA_INFO, *PDMA_INFO;
 434
 435 typedef struct _INTCFG {
 436         uint8_t bFIQ;           /* use FIQ */
 437         uint8_t byPriority;     /* priority level for IRQ */
 438 } INTCFG, *PINTCFG;
 439
 440 #endif  /*__KS8695_CHIPDEF_H*/