1 #ifndef __ASM_SH_FAST_TIMER_H
2 #define __ASM_SH_FAST_TIMER_H
4 #include <linux/sched.h>
5 #include <linux/interrupt.h>
11 #define FASTTIMER_IRQ 17
12 #define FASTTIMER_IPR_ADDR INTC_IPRA
13 #define FASTTIMER_IPR_POS 2
14 #define FASTTIMER_PRIORITY 3
17 #define TMU1_TCR_INIT 0x0020
19 #define TMU1_TCR_INIT 0
21 #define TMU_TSTR_INIT 1
22 #define TMU1_TCR_CALIB 0x0000
23 #define TMU_TOCR 0xffd80000 /* Byte access */
24 #define TMU_TSTR 0xffd80004 /* Byte access */
25 #define TMU1_TCOR 0xffd80014 /* Long access */
26 #define TMU1_TCNT 0xffd80018 /* Long access */
27 #define TMU1_TCR 0xffd8001c /* Word access */
30 fast_timer_interrupt(int irq
, void *dev_id
)
32 unsigned long timer_status
;
34 timer_status
= ctrl_inw(TMU1_TCR
);
35 timer_status
&= ~0x100;
36 ctrl_outw(timer_status
, TMU1_TCR
);
42 static void fast_timer_set(void)
44 unsigned long interval
;
45 struct clk
*clk
= clk_get("module_clk");
49 interval
= (clk_get_rate(clk
)/4 + fast_timer_rate
/2) / fast_timer_rate
;
52 interval
= 0xffffffff;
54 ctrl_outb(ctrl_inb(TMU_TSTR
) & ~0x2, TMU_TSTR
); /* disable timer 1 */
55 ctrl_outw(TMU1_TCR_INIT
, TMU1_TCR
);
56 ctrl_outl(interval
, TMU1_TCOR
);
57 ctrl_outl(interval
, TMU1_TCNT
);
58 ctrl_outb(ctrl_inb(TMU_TSTR
) | 0x2, TMU_TSTR
); /* enable timer 1 */
61 static int __init
fast_timer_setup(void)
64 static struct ipr_data fast_timer_ipr_map
[] = {
65 { FASTTIMER_IRQ
, FASTTIMER_IPR_ADDR
, FASTTIMER_IPR_POS
, FASTTIMER_PRIORITY
},
68 make_ipr_irq(fast_timer_ipr_map
, ARRAY_SIZE(fast_timer_ipr_map
));
70 if (request_irq(FASTTIMER_IRQ
, fast_timer_interrupt
, SA_INTERRUPT
,
75 fast_timer_rate
= cpu_data
->type
== CPU_SH7751R
? 2000 : 1000;
79 printk("fast timer: %d Hz, IRQ %d\n", fast_timer_rate
,
82 printk("fast timer: %d Hz\n", fast_timer_rate
);
87 static void __exit
fast_timer_cleanup(void)
89 ctrl_outb(ctrl_inb(TMU_TSTR
) & ~0x2, TMU_TSTR
); /* disable timer 1 */
90 free_irq(FASTTIMER_IRQ
, NULL
);
95 * return the current ticks on the fast timer
98 unsigned long fast_timer_count(void)
100 return(ctrl_inl(TMU1_TCNT
));