include/asm-arm/arch-s5c7375/dma.h

   1 /*
   2  * linux/include/asm-arm/arch-s5c7375/dma-s5c7375.h
   3  * Generic S5C7375  DMA support
   4  * Copyright (C) 2002 SW.LEE <hitchcar@sec.samsung.com>
   5  * Copyright (C) 2003 Hyok S. Choi <hyok.choi@samsung.com>
   6  */
   7
   8 #include <asm/hardware.h>
   9 #include <linux/wait.h>
  10
  11 #ifndef __ASM_S5C7375_ARCH_DMA_H
  12 #define __ASM_S5C7375_ARCH_DMA_H
  13
  14 /*
  15  * This is the maximum DMA address(physical address) that can be DMAd to.
  16  *
  17  */
  18 #define MAX_DMA_ADDRESS         0x20000000
  19 #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
  20
  21 /*
  22  * The regular generic DMA interface is inappropriate for the
  23  * S5C7375 DMA model.  None of the S5C7375 specific drivers using
  24  * DMA are portable anyway so it's pointless to try to twist the
  25  * regular DMA API to accommodate them.
  26  */
  27
  28 /***************************************************************************/
  29 /* this means that We will use arch/arm/mach/dma.h i.e generic dma module  */
  30 #define MAX_DMA_CHANNELS        0
  31 /****************************************************************************/
  32
  33 /*
  34  * The S5C7375 has four internal DMA channels.
  35  */
  36 #define S5C7375_DMA_CHANNELS     6
  37
  38 #define MAX_S5C7375_DMA_CHANNELS S5C7375_DMA_CHANNELS
  39
  40
  41 /*
  42  * All possible S5C7375 devices the specific DMA channel can be attached to.
  43  * I'm sorry for only DMA Device Address
  44  * DMA request sources would be controlled by H/W DMA mode selected by DCON register
  45  */
  46
  47 typedef enum {
  48       DMA0_SOURCE0 ,            /* EXT device 0 */
  49       DMA0_SOURCE1 ,            /* UART1  */
  50       DMA0_SOURCE2 ,            /* USB  */
  51       DMA0_SOURCE3 ,            /* PPIC  */
  52       DMA0_SOURCE4 ,            /* UART0 */
  53       DMA0_SOURCE5 ,            /* EXT device 1 */
  54 } dma_device_t;
  55
  56
  57 /*
  58  * DMA buffer structure
  59  */
  60
  61 typedef struct dma_buf_s {
  62         int size;               /* buffer size */
  63         dma_addr_t dma_start;   /* starting DMA address */
  64         dma_addr_t dma_ptr;     /* next DMA pointer to use */
  65         int ref;                /* number of DMA references */
  66         void *id;               /* to identify buffer from outside */
  67         struct dma_buf_s *next; /* next buffer to process */
  68 } dma_buf_t;
  69
  70
  71 /*
  72  * DMA channel structure.
  73  */
  74
  75 /*
  76  * DMA control register structure
  77  * one channel S5C7375 DMA control register is 0x40 byte
  78  *
  79  */
  80
  81 typedef void (*dma_callback_t)( void *buf_id, int size);
  82
  83 typedef struct {
  84         volatile u_long DISRC;
  85         volatile u_long DISRCC;
  86         volatile u_long DIDST;
  87         volatile u_long DIDSTC;
  88         volatile u_long DCON;
  89         volatile u_long DSTAT;
  90         volatile u_long DCSRC;
  91         volatile u_long DCDST;
  92         volatile u_long DMASKTRIG;
  93 } dma_regs_t;
  94
  95 #define DOUBLE_BUFFER_COUNT 3
  96 typedef struct {
  97         unsigned int in_use;    /* Device is allocated */
  98         const char *device_id;  /* Device name */
  99         dma_device_t device;    /* ... to which this channel is attached */
 100         dma_buf_t *head;        /* where to insert buffers */
 101         dma_buf_t *tail;        /* where to remove buffers */
 102         dma_buf_t *curr;        /* buffer currently DMA'ed */
 103         int stopped;            /* 1 if DMA is stalled */
 104         dma_regs_t *regs;       /* points to appropriate DMA registers */
 105         int irq;                /* IRQ used by the channel */
 106         dma_callback_t callback; /* ... to call when buffers are done */
 107
 108         unsigned int queueCnt;
 109         unsigned int usedQueueCnt;
 110         int     isSleeping;
 111         int spin_size;          /* > 0 when DMA should spin when no more buffer */
 112         dma_addr_t spin_addr;   /* DMA address to spin onto */
 113         int spin_ref;           /* number of spinning references */
 114
 115         unsigned char already_init;     /* S5C7375 specific  */
 116 } s5c7375_dma_t;
 117
 118 /* S5C7375 DMA API */
 119 extern int s5c7375_request_dma( dmach_t channel, const char *device_id,
 120                                dma_device_t device );
 121 extern int s5c7375_dma_set_callback( dmach_t channel, dma_callback_t cb );
 122 extern int s5c7375_dma_set_spin( dmach_t channel, dma_addr_t addr, int size );
 123 extern int s5c7375_dma_queue_buffer( dmach_t channel, void *buf_id,
 124                                     dma_addr_t data, int size );
 125 extern int s5c7375_dma_get_current( dmach_t channel, void **buf_id, dma_addr_t *addr );
 126 extern int s5c7375_dma_stop( dmach_t channel );
 127 extern int s5c7375_dma_resume( dmach_t channel );
 128 extern int s5c7375_dma_flush_all( dmach_t channel );
 129 extern void s5c7375_free_dma( dmach_t channel );
 130 extern int s5c7375_dma_sleep( dmach_t channel );
 131 extern int s5c7375_dma_wakeup( dmach_t channel );
 132 extern void s5c7375_dma_done (s5c7375_dma_t *dma);
 133
 134 #endif /* _ASM_S5C7375_ARCH_DMA_H */
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