| blob | a6343087baede77636b1c32bf1169fc341219ae5 |
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15 */
16 #ifndef __ASM_ARCH_KS8695_REGS_H
17 #define __ASM_ARCH_KS8695_REGS_H 1
19 /* Physical IO address space of KS8695 internal peripheral registers */
20 #define KS8695_IO_BASE 0x03FF0000
21 #define KS8695_IO_SIZE 0x00010000
23 #define KS8695_SYSTEN_CONFIG 0x00
24 #define KS8695_SYSTEN_BUS_CLOCK 0x04
26 /* bus clock definitions*/
27 #define KS8695_BUS_CLOCK_125MHZ 0x0
28 #define KS8695_BUS_CLOCK_100MHZ 0x1
29 #define KS8695_BUS_CLOCK_62MHZ 0x2
30 #define KS8695_BUS_CLOCK_50MHZ 0x3
31 #define KS8695_BUS_CLOCK_41MHZ 0x4
32 #define KS8695_BUS_CLOCK_33MHZ 0x5
33 #define KS8695_BUS_CLOCK_31MHZ 0x6
34 #define KS8695_BUS_CLOCK_25MHZ 0x7
36 /* i/o control registers offset difinitions */
37 #define KS8695_IO_CTRL0 0x4000
38 #define KS8695_IO_CTRL1 0x4004
39 #define KS8695_IO_CTRL2 0x4008
40 #define KS8695_IO_CTRL3 0x400C
42 /* memory control registers offset difinitions */
43 #define KS8695_MEM_CTRL0 0x4010
44 #define KS8695_MEM_CTRL1 0x4014
45 #define KS8695_MEM_CTRL2 0x4018
46 #define KS8695_MEM_CTRL3 0x401C
47 #define KS8695_MEM_GENERAL 0x4020
48 #define KS8695_SDRAM_CTRL0 0x4030
49 #define KS8695_SDRAM_CTRL1 0x4034
50 #define KS8695_SDRAM_GENERAL 0x4038
51 #define KS8695_SDRAM_BUFFER 0x403C
52 #define KS8695_SDRAM_REFRESH 0x4040
54 /* WAN control registers offset difinitions */
55 #define KS8695_WAN_DMA_TX 0x6000
56 #define KS8695_WAN_DMA_RX 0x6004
57 #define KS8695_WAN_DMA_TX_START 0x6008
58 #define KS8695_WAN_DMA_RX_START 0x600C
59 #define KS8695_WAN_TX_LIST 0x6010
60 #define KS8695_WAN_RX_LIST 0x6014
61 #define KS8695_WAN_MAC_LOW 0x6018
62 #define KS8695_WAN_MAC_HIGH 0x601C
63 #define KS8695_WAN_MAC_ELOW 0x6080
64 #define KS8695_WAN_MAC_EHIGH 0x6084
66 /* LAN control registers offset difinitions */
67 #define KS8695_LAN_DMA_TX 0x8000
68 #define KS8695_LAN_DMA_RX 0x8004
69 #define KS8695_LAN_DMA_TX_START 0x8008
70 #define KS8695_LAN_DMA_RX_START 0x800C
71 #define KS8695_LAN_TX_LIST 0x8010
72 #define KS8695_LAN_RX_LIST 0x8014
73 #define KS8695_LAN_MAC_LOW 0x8018
74 #define KS8695_LAN_MAC_HIGH 0x801C
75 #define KS8695_LAN_MAC_ELOW 0X8080
76 #define KS8695_LAN_MAC_EHIGH 0X8084
78 /* HPNA control registers offset difinitions */
79 #define KS8695_HPNA_DMA_TX 0xA000
80 #define KS8695_HPNA_DMA_RX 0xA004
81 #define KS8695_HPNA_DMA_TX_START 0xA008
82 #define KS8695_HPNA_DMA_RX_START 0xA00C
83 #define KS8695_HPNA_TX_LIST 0xA010
84 #define KS8695_HPNA_RX_LIST 0xA014
85 #define KS8695_HPNA_MAC_LOW 0xA018
86 #define KS8695_HPNA_MAC_HIGH 0xA01C
87 #define KS8695_HPNA_MAC_ELOW 0xA080
88 #define KS8695_HPNA_MAC_EHIGH 0xA084
90 /* UART control registers offset difinitions */
91 #define KS8695_UART_RX_BUFFER 0xE000
92 #define KS8695_UART_TX_HOLDING 0xE004
94 #define KS8695_UART_FIFO_CTRL 0xE008
95 #define KS8695_UART_FIFO_TRIG01 0x00
96 #define KS8695_UART_FIFO_TRIG04 0x80
97 #define KS8695_UART_FIFO_TXRST 0x03
98 #define KS8695_UART_FIFO_RXRST 0x02
99 #define KS8695_UART_FIFO_FEN 0x01
101 #define KS8695_UART_LINE_CTRL 0xE00C
102 #define KS8695_UART_LINEC_BRK 0x40
103 #define KS8695_UART_LINEC_EPS 0x10
104 #define KS8695_UART_LINEC_PEN 0x08
105 #define KS8695_UART_LINEC_STP2 0x04
106 #define KS8695_UART_LINEC_WLEN8 0x03
107 #define KS8695_UART_LINEC_WLEN7 0x02
108 #define KS8695_UART_LINEC_WLEN6 0x01
109 #define KS8695_UART_LINEC_WLEN5 0x00
111 #define KS8695_UART_MODEM_CTRL 0xE010
112 #define KS8695_UART_MODEMC_RTS 0x02
113 #define KS8695_UART_MODEMC_DTR 0x01
115 #define KS8695_UART_LINE_STATUS 0xE014
116 #define KS8695_UART_LINES_TXFE 0x20
117 #define KS8695_UART_LINES_BE 0x10
118 #define KS8695_UART_LINES_FE 0x08
119 #define KS8695_UART_LINES_PE 0x04
120 #define KS8695_UART_LINES_OE 0x02
121 #define KS8695_UART_LINES_RXFE 0x01
122 #define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE | \
123 KS8695_UART_LINES_BE | \
124 KS8695_UART_LINES_PE | \
125 KS8695_UART_LINES_FE)
127 #define KS8695_UART_MODEM_STATUS 0xE018
128 #define KS8695_UART_MODEM_DCD 0x80
129 #define KS8695_UART_MODEM_DSR 0x20
130 #define KS8695_UART_MODEM_CTS 0x10
131 #define KS8695_UART_MODEM_DDCD 0x08
132 #define KS8695_UART_MODEM_DDSR 0x02
133 #define KS8695_UART_MODEM_DCTS 0x01
134 #define KS8695_UART_MODEM_ANY 0xFF
136 #define KS8695_UART_DIVISOR 0xE01C
137 #define KS8695_UART_STATUS 0xE020
139 /* Interrupt controlller registers offset difinitions */
140 #define KS8695_INT_CONTL 0xE200
141 #define KS8695_INT_ENABLE 0xE204
142 #define KS8695_INT_ENABLE_MODEM 0x0800
143 #define KS8695_INT_ENABLE_ERR 0x0400
144 #define KS8695_INT_ENABLE_RX 0x0200
145 #define KS8695_INT_ENABLE_TX 0x0100
146 #define KS8695_INT_UART_MASK 0x0f00
148 #define KS8695_INT_STATUS 0xE208
149 #define KS8695_INT_WAN_PRIORITY 0xE20C
150 #define KS8695_INT_HPNA_PRIORITY 0xE210
151 #define KS8695_INT_LAN_PRIORITY 0xE214
152 #define KS8695_INT_TIMER_PRIORITY 0xE218
153 #define KS8695_INT_UART_PRIORITY 0xE21C
154 #define KS8695_INT_EXT_PRIORITY 0xE220
155 #define KS8695_INT_CHAN_PRIORITY 0xE224
156 #define KS8695_INT_BUSERROR_PRO 0xE228
157 #define KS8695_INT_MASK_STATUS 0xE22C
158 #define KS8695_FIQ_PEND_PRIORITY 0xE230
159 #define KS8695_IRQ_PEND_PRIORITY 0xE234
161 /* timer registers offset difinitions */
162 #define KS8695_TIMER_CTRL 0xE400
163 #define KS8695_TIMER1 0xE404
164 #define KS8695_TIMER0 0xE408
165 #define KS8695_TIMER1_PCOUNT 0xE40C
166 #define KS8695_TIMER0_PCOUNT 0xE410
168 /* GPIO registers offset difinitions */
169 #define KS8695_GPIO_MODE 0xE600
170 #define KS8695_GPIO_CTRL 0xE604
171 #define KS8695_GPIO_DATA 0xE608
173 /* SWITCH registers offset difinitions */
174 #define KS8695_SWITCH_CTRL0 0xE800
175 #define KS8695_SWITCH_CTRL1 0xE804
176 #define KS8695_SWITCH_PORT1 0xE808
177 #define KS8695_SWITCH_PORT2 0xE80C
178 #define KS8695_SWITCH_PORT3 0xE810
179 #define KS8695_SWITCH_PORT4 0xE814
180 #define KS8695_SWITCH_PORT5 0xE818
181 #define KS8695_SWITCH_LUE_CTRL 0xE824
182 #define KS8695_SWITCH_LUE_HIGH 0xE828
183 #define KS8695_SWITCH_LUE_LOW 0xE82C
185 /* some differences between the KS8695(X) and KS8695P */
186 #ifdef CONFIG_PCI
187 #define KS8695_SWITCH_AUTO0 0xE848
188 #define KS8695_SWITCH_AUTO1 0xE84C
189 #define KS8695_SWITCH_ADVANCED 0xE860
190 #define KS8695_DSCP_HIGH 0xE864
191 #define KS8695_DSCP_LOW 0xE868
192 #define KS8695_SWITCH_MAC_HIGH 0xE86C
193 #define KS8695_SWITCH_MAC_LOW 0xE870
194 #define KS8695_LAN12_POWERMAGR 0xE874
195 #define KS8695_LAN34_POWERMAGR 0xE878
196 #else
197 #define KS8695_SWITCH_AUTO0 0xE81C
198 #define KS8695_SWITCH_AUTO1 0xE820
199 #define KS8695_SWITCH_ADVANCED 0xE830
200 #define KS8695_DSCP_HIGH 0xE834
201 #define KS8695_DSCP_LOW 0xE838
202 #define KS8695_SWITCH_MAC_HIGH 0xE83C
203 #define KS8695_SWITCH_MAC_LOW 0xE840
204 #define KS8695_LAN12_POWERMAGR 0xE84C
205 #define KS8695_LAN34_POWERMAGR 0xE850
206 #endif
208 /* miscellaneours registers difinitions */
209 #define KS8695_MANAGE_COUNTER 0xE844
210 #define KS8695_MANAGE_DATA 0xE848
212 #define KS8695_DEVICE_ID 0xEA00
213 #define KS8695_REVISION_ID 0xEA04
215 #define KS8695_MISC_CONTROL 0xEA08
216 #define KS8695_WAN_CONTROL 0xEA0C
217 #define KS8695_WAN_POWERMAGR 0xEA10
218 #define KS8695_WAN_PHY_CONTROL 0xEA14
219 #define KS8695_WAN_PHY_STATUS 0xEA18
222 /*
223 * The following are all new in the KS8695P.
224 */
225 #ifdef CONFIG_PCI
227 /* most bit definition are same as KS8695, except few new bits */
228 #define KS8695_SEC0 0xE800
229 #define KS8695_SEC1 0xE804
231 /* new bits */
232 #define KS8695_SEC0_BACKOFF_EN 0x80000000
233 #define KS8695_SEC0_FRAME_LEN_CHECK 0x00020000
234 #define KS8695_SEC0_DMA_HALF_DUPLEX 0x00000010
236 /* new bits */
237 #define KS8695_SEC1_NO_IEEE_AN 0x00000800
238 #define KS8695_SEC1_TPID_MODE 0x00000400
239 #define KS8695_SEC1_NO_TX_8021X_FLOW_CTRL 0x00000080
240 #define KS8695_SEC1_NO_RX_8021X_FLOW_CTRL 0x00000040
241 #define KS8695_SEC1_HUGE_PACKET 0x00000020
242 #define KS8695_SEC1_8021Q_VLAN_EN 0x00000010
243 #define KS8695_SEC1_MII_10BT 0x00000002
244 #define KS8695_SEC1_NULL_VID 0x00000001
246 /* Port 1-4 and 5 Configuration Register Set 1 */
247 #define KS8695_SEP1C1 0xE80C
248 #define KS8695_SEP2C1 0xE818
249 #define KS8695_SEP3C1 0xE824
250 #define KS8695_SEP4C1 0xE830
251 #define KS8695_SEP5C1 0xE83C
253 /* Port 1-4 and 5 Configuration Register Set 2 */
254 #define KS8695_SEP1C2 0xE810
255 #define KS8695_SEP2C2 0xE81C
256 #define KS8695_SEP3C2 0xE828
257 #define KS8695_SEP4C2 0xE834
258 #define KS8695_SEP5C2 0xE840
260 #define KS8695_SEPC2_VLAN_FILTER 0x10000000
261 #define KS8695_SEPC2_DISCARD_NON_PVID 0x08000000
262 #define KS8695_SEPC2_FORCE_FLOW_CTRL 0x04000000
263 #define KS8695_SEPC2_BACK_PRESSURE_EN 0x02000000
265 #define KS8695_SEPC2_TX_H_RATECTRL_MASK 0x00FFF000
266 #define KS8695_SEPC2_TX_L_RATECTRL_MASK 0x00000FFF
268 /* Port 1-4 and 5 Configuration Register Set 3 */
269 #define KS8695_SEP1C3 0xE814
270 #define KS8695_SEP2C3 0xE820
271 #define KS8695_SEP3C3 0xE82C
272 #define KS8695_SEP4C3 0xE838
273 #define KS8695_SEP5C3 0xE844
275 #define KS8695_SEPC3_RX_H_RATECTRL_MASK 0xFFF00000
276 #define KS8695_SEPC3_RX_L_RATECTRL_MASK 0x000FFF00
277 #define KS8695_SEPC3_RX_DIF_RATECTRL_EN 0x00000080
278 #define KS8695_SEPC3_RX_L_RATECTRL_EN 0x00000040
279 #define KS8695_SEPC3_RX_H_RATECTRL_EN 0x00000020
280 #define KS8695_SEPC3_RX_L_RATEFLOW_EN 0x00000010
281 #define KS8695_SEPC3_RX_H_RATEFLOW_EN 0x00000008
282 #define KS8695_SEPC3_TX_DIF_RATECTRL_EN 0x00000004
283 #define KS8695_SEPC3_TX_L_RATECTRL_EN 0x00000002
284 #define KS8695_SEPC3_TX_H_RATECTRL_EN 0x00000001
286 /* Port auto negotiation related registers */
287 #define KS8695_SEP12AN 0xE848
288 #define KS8695_SEP34AN 0xE84C
290 /* Indirect Access Control register */
291 #define KS8695_SEIAC 0xE850
292 #define KS8695_SEIADH2 0xE854
293 #define KS8695_SEIADH1 0xE858
294 #define KS8695_SEIADL 0xE85C
296 #define KS8695_SEIAC_READ 0x00001000
297 #define KS8695_SEIAC_WRITE 0x00000000
298 #define KS8695_SEIAC_TAB_STATIC 0x00000000
299 #define KS8695_SEIAC_TAB_VLAN 0x00000400
300 #define KS8695_SEIAC_TAB_DYNAMIC 0x00000800
301 #define KS8695_SEIAC_TAB_MIB 0x00000C00
302 #define KS8695_SEIAC_INDEX_MASK 0x000003FF
304 /* Advanced Feature Control register */
305 #define KS8695_SEAFC 0xE860
306 #define KS8695_SEDSCPH 0xE864
307 #define KS8695_SEDSCPL 0xE868
308 #define KS8695_SEMAH 0xE86C
309 #define KS8695_SEMAL 0xE870
311 /* LAN PHY power management related registers */
312 #define KS8695_LPPM12 0xE874
313 #define KS8695_LPPM34 0xE878
315 /* new bits */
316 #define KS8695_LPPM_PHY_LOOPBACK 0x4000
317 #define KS8695_LPPM_RMT_LOOPBACK 0x2000
318 #define KS8695_LPPM_PHY_ISOLATE 0x1000
319 #define KS8695_LPPM_SOFT_RESET 0x0800
320 #define KS8695_LPPM_FORCE_LINK 0x0400
322 /* new bits */
323 #define KS8695_LPPM_PHY_LOOPBACK 0x4000
324 #define KS8695_LPPM_RMT_LOOPBACK 0x2000
325 #define KS8695_LPPM_PHY_ISOLATE 0x1000
326 #define KS8695_LPPM_SOFT_RESET 0x0800
327 #define KS8695_LPPM_FORCE_LINK 0x0400
329 /* Digital Testing Status and Control Registers */
330 #define KS8695_SEDTS 0xE87C
331 #define KS8695_SEATCS 0xE880
333 /* new bits for WAN PHY Power mangement register */
334 #define KS8695_WPPM_PHY_LOOPBACK 0x00004000
335 #define KS8695_WPPM_RMT_LOOPBACK 0x00002000
336 #define KS8695_WPPM_PHY_ISOLATION 0x00001000
337 #define KS8695_WPPM_FORCE_LINK 0x00000400