include/asm-arm/arch-espd_4510b/s3c4510b.h

   1 #ifndef __HW_S3C4510_H
   2 #define __HW_S3C4510_H
   3
   4 /*
   5  * linux/include/asm-armnommu/arch-espd_4510b/s3c4510b.h
   6  *
   7  * Copyright (c) 2004   Cucy Systems (http://www.cucy.com)
   8  * Curt Brune <curt@cucy.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  *
  28  * MODULE:        $Id: s3c4510b.h,v 1.2 2005/11/28 03:55:11 gerg Exp $
  29  * Description:   Samsung S3C4510B register layout
  30  * Runtime Env:   ARM7TDMI
  31  * Change History:
  32  *     03-02-04    Create (Curt Brune) curt@cucy.com
  33  */
  34
  35 /*------------------------------------------------------------------------
  36  *        ASIC Address Definition
  37  *----------------------------------------------------------------------*/
  38
  39
  40 #define S3C4510B_MEM_SIZE     (CONFIG_DRAM_SIZE)
  41 #define MEM_SIZE              S3C4510B_MEM_SIZE
  42 #define PA_SDRAM_BASE         CONFIG_DRAM_BASE
  43
  44 /* L1 8KB on chip SRAM base address */
  45 #define SRAM_BASE       (0x03fe0000)
  46
  47 /* Special Register Start Address After System Reset */
  48 #define REG_BASE        (0x03ff0000)
  49 #define SPSTR           (REG_BASE)
  50
  51 /* *********************** */
  52 /* System Manager Register */
  53 /* *********************** */
  54 #define REG_SYSCFG      (REG_BASE+0x0000)
  55
  56 #define REG_CLKCON      (REG_BASE+0x3000)
  57 #define REG_EXTACON0    (REG_BASE+0x3008)
  58 #define REG_EXTACON1    (REG_BASE+0x300c)
  59 #define REG_EXTDBWTH    (REG_BASE+0x3010)
  60 #define REG_ROMCON0     (REG_BASE+0x3014)
  61 #define REG_ROMCON1     (REG_BASE+0x3018)
  62 #define REG_ROMCON2     (REG_BASE+0x301c)
  63 #define REG_ROMCON3     (REG_BASE+0x3020)
  64 #define REG_ROMCON4     (REG_BASE+0x3024)
  65 #define REG_ROMCON5     (REG_BASE+0x3028)
  66 #define REG_DRAMCON0    (REG_BASE+0x302c)
  67 #define REG_DRAMCON1    (REG_BASE+0x3030)
  68 #define REG_DRAMCON2    (REG_BASE+0x3034)
  69 #define REG_DRAMCON3    (REG_BASE+0x3038)
  70 #define REG_REFEXTCON   (REG_BASE+0x303c)
  71
  72 /* *********************** */
  73 /* Ethernet BDMA Register  */
  74 /* *********************** */
  75 #define REG_BDMATXCON   (REG_BASE+0x9000)
  76 #define REG_BDMARXCON   (REG_BASE+0x9004)
  77 #define REG_BDMATXPTR   (REG_BASE+0x9008)
  78 #define REG_BDMARXPTR   (REG_BASE+0x900c)
  79 #define REG_BDMARXLSZ   (REG_BASE+0x9010)
  80 #define REG_BDMASTAT    (REG_BASE+0x9014)
  81
  82 /* Content Address Memory */
  83 #define REG_CAM_BASE    (REG_BASE+0x9100)
  84
  85 #define REG_BDMATXBUF   (REG_BASE+0x9200)
  86 #define REG_BDMARXBUF   (REG_BASE+0x9800)
  87
  88 /* *********************** */
  89 /* Ethernet MAC Register   */
  90 /* *********************** */
  91 #define REG_MACCON      (REG_BASE+0xa000)
  92 #define REG_CAMCON      (REG_BASE+0xa004)
  93 #define REG_MACTXCON    (REG_BASE+0xa008)
  94 #define REG_MACTXSTAT   (REG_BASE+0xa00c)
  95 #define REG_MACRXCON    (REG_BASE+0xa010)
  96 #define REG_MACRXSTAT   (REG_BASE+0xa014)
  97 #define REG_STADATA     (REG_BASE+0xa018)
  98 #define REG_STACON      (REG_BASE+0xa01c)
  99 #define REG_CAMEN       (REG_BASE+0xa028)
 100 #define REG_EMISSCNT    (REG_BASE+0xa03c)
 101 #define REG_EPZCNT      (REG_BASE+0xa040)
 102 #define REG_ERMPZCNT    (REG_BASE+0xa044)
 103 #define REG_ETXSTAT     (REG_BASE+0x9040)
 104 #define REG_MACRXDESTR  (REG_BASE+0xa064)
 105 #define REG_MACRXSTATEM (REG_BASE+0xa090)
 106 #define REG_MACRXFIFO   (REG_BASE+0xa200)
 107
 108 /********************/
 109 /* I2C Bus Register */
 110 /********************/
 111 #define REG_I2C_CON     (REG_BASE+0xf000)
 112 #define REG_I2C_BUF     (REG_BASE+0xf004)
 113 #define REG_I2C_PS      (REG_BASE+0xf008)
 114 #define REG_I2C_COUNT   (REG_BASE+0xf00c)
 115
 116 /********************/
 117 /*    GDMA 0        */
 118 /********************/
 119 #define REG_GDMACON0    (REG_BASE+0xb000)
 120 #define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020)
 121 #define REG_GDMASRC0    (REG_BASE+0xb004)
 122 #define REG_GDMADST0    (REG_BASE+0xb008)
 123 #define REG_GDMACNT0    (REG_BASE+0xb00c)
 124
 125 /********************/
 126 /*    GDMA 1        */
 127 /********************/
 128 #define REG_GDMACON1    (REG_BASE+0xc000)
 129 #define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020)
 130 #define REG_GDMASRC1    (REG_BASE+0xc004)
 131 #define REG_GDMADST1    (REG_BASE+0xc008)
 132 #define REG_GDMACNT1    (REG_BASE+0xc00c)
 133
 134 #define UART_CNT        (2)
 135 /********************/
 136 /*      UART 0      */
 137 /********************/
 138 #define UART0_BASE       (REG_BASE+0xd000)
 139 #define REG_UART0_LCON   (REG_BASE+0xd000)
 140 #define REG_UART0_CTRL   (REG_BASE+0xd004)
 141 #define REG_UART0_STAT   (REG_BASE+0xd008)
 142 #define REG_UART0_TXB    (REG_BASE+0xd00c)
 143 #define REG_UART0_RXB    (REG_BASE+0xd010)
 144 #define REG_UART0_BAUD_DIV    (REG_BASE+0xd014)
 145 #define REG_UART0_BAUD_CNT    (REG_BASE+0xd018)
 146 #define REG_UART0_BAUD_CLK    (REG_BASE+0xd01C)
 147
 148 /********************/
 149 /*     UART 1       */
 150 /********************/
 151 #define UART1_BASE       (REG_BASE+0xe000)
 152 #define REG_UART1_LCON   (REG_BASE+0xe000)
 153 #define REG_UART1_CTRL   (REG_BASE+0xe004)
 154 #define REG_UART1_STAT   (REG_BASE+0xe008)
 155 #define REG_UART1_TXB    (REG_BASE+0xe00c)
 156 #define REG_UART1_RXB    (REG_BASE+0xe010)
 157 #define REG_UART1_BAUD_DIV    (REG_BASE+0xe014)
 158 #define REG_UART1_BAUD_CNT    (REG_BASE+0xe018)
 159 #define REG_UART1_BAUD_CLK    (REG_BASE+0xe01C)
 160
 161 /********************/
 162 /*  Timer Register  */
 163 /********************/
 164 #define REG_TMOD        (REG_BASE+0x6000)
 165 #define REG_TDATA0      (REG_BASE+0x6004)
 166 #define REG_TDATA1      (REG_BASE+0x6008)
 167 #define REG_TCNT0       (REG_BASE+0x600c)
 168 #define REG_TCNT1       (REG_BASE+0x6010)
 169
 170 /**********************/
 171 /* I/O Port Interface */
 172 /**********************/
 173 #define REG_IOPMODE     (REG_BASE+0x5000)
 174 #define REG_IOPCON      (REG_BASE+0x5004)
 175 #define REG_IOPDATA     (REG_BASE+0x5008)
 176
 177 /*********************************/
 178 /* Interrupt Controller Register */
 179 /*********************************/
 180 #define REG_INTMODE     (REG_BASE+0x4000)
 181 #define REG_INTPEND     (REG_BASE+0x4004)
 182 #define REG_INTMASK     (REG_BASE+0x4008)
 183
 184 #define REG_INTPRI0     (REG_BASE+0x400c)
 185 #define REG_INTPRI1     (REG_BASE+0x4010)
 186 #define REG_INTPRI2     (REG_BASE+0x4014)
 187 #define REG_INTPRI3     (REG_BASE+0x4018)
 188 #define REG_INTPRI4     (REG_BASE+0x401c)
 189 #define REG_INTPRI5     (REG_BASE+0x4020)
 190 #define REG_INTOFFSET   (REG_BASE+0x4024)
 191 #define REG_INTPNDPRI   (REG_BASE+0x4028)
 192 #define REG_INTPNDTST   (REG_BASE+0x402C)
 193 #define REG_INTOSET_FIQ (REG_BASE+0x4030)
 194 #define REG_INTOSET_IRQ (REG_BASE+0x4034)
 195
 196 #define INT_MODE_IRQ    0x000000
 197 #define INT_MODE_FIQ    0x1FFFFF
 198 #define INT_MASK_DIS    0x1FFFFF
 199 #define INT_MASK_ENA    0x000000
 200
 201 /*********************************/
 202 /* CACHE CONTROL MASKS           */
 203 /*********************************/
 204 #define CACHE_STALL      (0x00000001)
 205 #define CACHE_ENABLE     (0x00000002)
 206 #define CACHE_WRITE_BUFF (0x00000004)
 207 #define CACHE_MODE       (0x00000030)
 208 #define CACHE_MODE_00    (0x00000000)
 209 #define CACHE_MODE_01    (0x00000010)
 210 #define CACHE_MODE_10    (0x00000020)
 211
 212 /*********************************/
 213 /* CACHE RAM BASE ADDRESSES      */
 214 /*********************************/
 215 #define CACHE_SET0_RAM   (0x10000000)
 216 #define CACHE_SET1_RAM   (0x10800000)
 217 #define CACHE_TAG_RAM    (0x11000000)
 218
 219 /*********************************/
 220 /* CACHE_DISABLE MASK            */
 221 /*********************************/
 222 #define CACHE_DISABLE_MASK (0x04000000)
 223
 224 /*********************************************************/
 225 /*             TIMER MODE REGISTER                       */
 226 /*********************************************************/
 227 #define  TM0_RUN      0x01  /* Timer 0 enable */
 228 #define  TM0_TOGGLE   0x02  /* 0, interval mode */
 229 #define  TM0_OUT_1    0x04  /* Timer 0 Initial TOUT0 value */
 230 #define  TM1_RUN      0x08  /* Timer 1 enable */
 231 #define  TM1_TOGGLE   0x10  /* 0, interval mode */
 232 #define  TM1_OUT_1    0x20  /* Timer 0 Initial TOUT0 value */
 233
 234 /*********************************************************
 235  *             INTERRUPT CONTROL
 236  *
 237  * An interrupt is enabled when mask bit is clear.
 238  * An interrupt is disabled when mask bit is set.
 239  *********************************************************/
 240 #define INT_ENABLE(n)           outl( inl(REG_INTMASK) & ~( 1 << (n)), REG_INTMASK)
 241 #define INT_DISABLE(n)          outl( inl(REG_INTMASK) | ( 1 << (n)), REG_INTMASK)
 242 #define CLEAR_PEND_INT(n)       outl( (1 << (n)), REG_INTPEND)
 243 #define SET_PEND_INT(n)         outl( inl(REG_INTPNDTST) | ( 1 << (n)), REG_INTPNDMASK)
 244
 245 #ifdef CONFIG_ARCH_ESPD_4510B
 246 #define LED_SET(n)              outl( inl(REG_IOPDATA) & ~(1<<(n)), REG_IOPDATA)
 247 #define LED_CLR(n)              outl( inl(REG_IOPDATA) |  (1<<(n)), REG_IOPDATA)
 248 #define LED_TOGGLE(n)           outl( inl(REG_IOPDATA) ^  (1<<(n)), REG_IOPDATA)
 249 #else
 250 #define LED_SET(n)
 251 #define LED_CLR(n)
 252 #define LED_TOGGLE(n)
 253 #endif
 254
 255 #endif /* __S3C4510_h */