drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /* statistics can be kept for for tuning/monitoring */
  25 struct ehci_stats {
  26         /* irq usage */
  27         unsigned long           normal;
  28         unsigned long           error;
  29         unsigned long           reclaim;
  30         unsigned long           lost_iaa;
  31
  32         /* termination of urbs from core */
  33         unsigned long           complete;
  34         unsigned long           unlink;
  35 };
  36
  37 /* ehci_hcd->lock guards shared data against other CPUs:
  38  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
  39  *   usb_host_endpoint: hcpriv
  40  *   ehci_qh:   qh_next, qtd_list
  41  *   ehci_qtd:  qtd_list
  42  *
  43  * Also, hold this lock when talking to HC registers or
  44  * when updating hw_* fields in shared qh/qtd/... structures.
  45  */
  46
  47 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  48
  49 struct ehci_hcd {                       /* one per controller */
  50         /* glue to PCI and HCD framework */
  51         struct ehci_caps __iomem *caps;
  52         struct ehci_regs __iomem *regs;
  53         struct ehci_dbg_port __iomem *debug;
  54
  55         __u32                   hcs_params;     /* cached register copy */
  56         spinlock_t              lock;
  57
  58         /* async schedule support */
  59         struct ehci_qh          *async;
  60         struct ehci_qh          *reclaim;
  61         unsigned                reclaim_ready : 1;
  62         unsigned                scanning : 1;
  63
  64         /* periodic schedule support */
  65 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
  66         unsigned                periodic_size;
  67         __le32                  *periodic;      /* hw periodic table */
  68         dma_addr_t              periodic_dma;
  69         unsigned                i_thresh;       /* uframes HC might cache */
  70
  71         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
  72         int                     next_uframe;    /* scan periodic, start here */
  73         unsigned                periodic_sched; /* periodic activity count */
  74
  75         /* per root hub port */
  76         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
  77
  78         /* per-HC memory pools (could be per-bus, but ...) */
  79         struct dma_pool         *qh_pool;       /* qh per active urb */
  80         struct dma_pool         *qtd_pool;      /* one or more per qh */
  81         struct dma_pool         *itd_pool;      /* itd per iso urb */
  82         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
  83
  84         struct timer_list       watchdog;
  85         unsigned long           actions;
  86         unsigned                stamp;
  87         unsigned long           next_statechange;
  88         u32                     command;
  89
  90         /* SILICON QUIRKS */
  91         unsigned                is_tdi_rh_tt:1; /* TDI roothub with TT */
  92         unsigned                no_selective_suspend:1;
  93         unsigned                has_fsl_port_bug:1; /* FreeScale */
  94
  95         u8                      sbrn;           /* packed release number */
  96
  97         /* irq statistics */
  98 #ifdef EHCI_STATS
  99         struct ehci_stats       stats;
 100 #       define COUNT(x) do { (x)++; } while (0)
 101 #else
 102 #       define COUNT(x) do {} while (0)
 103 #endif
 104 };
 105
 106 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 107 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 108 {
 109         return (struct ehci_hcd *) (hcd->hcd_priv);
 110 }
 111 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 112 {
 113         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 114 }
 115
 116
 117 enum ehci_timer_action {
 118         TIMER_IO_WATCHDOG,
 119         TIMER_IAA_WATCHDOG,
 120         TIMER_ASYNC_SHRINK,
 121         TIMER_ASYNC_OFF,
 122 };
 123
 124 static inline void
 125 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 126 {
 127         clear_bit (action, &ehci->actions);
 128 }
 129
 130 static inline void
 131 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
 132 {
 133         if (!test_and_set_bit (action, &ehci->actions)) {
 134                 unsigned long t;
 135
 136                 switch (action) {
 137                 case TIMER_IAA_WATCHDOG:
 138                         t = EHCI_IAA_JIFFIES;
 139                         break;
 140                 case TIMER_IO_WATCHDOG:
 141                         t = EHCI_IO_JIFFIES;
 142                         break;
 143                 case TIMER_ASYNC_OFF:
 144                         t = EHCI_ASYNC_JIFFIES;
 145                         break;
 146                 // case TIMER_ASYNC_SHRINK:
 147                 default:
 148                         t = EHCI_SHRINK_JIFFIES;
 149                         break;
 150                 }
 151                 t += jiffies;
 152                 // all timings except IAA watchdog can be overridden.
 153                 // async queue SHRINK often precedes IAA.  while it's ready
 154                 // to go OFF neither can matter, and afterwards the IO
 155                 // watchdog stops unless there's still periodic traffic.
 156                 if (action != TIMER_IAA_WATCHDOG
 157                                 && t > ehci->watchdog.expires
 158                                 && timer_pending (&ehci->watchdog))
 159                         return;
 160                 mod_timer (&ehci->watchdog, t);
 161         }
 162 }
 163
 164 /*-------------------------------------------------------------------------*/
 165
 166 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 167
 168 /* Section 2.2 Host Controller Capability Registers */
 169 struct ehci_caps {
 170         /* these fields are specified as 8 and 16 bit registers,
 171          * but some hosts can't perform 8 or 16 bit PCI accesses.
 172          */
 173         u32             hc_capbase;
 174 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
 175 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
 176         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
 177 #define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
 178 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
 179 #define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
 180 #define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
 181 #define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */
 182 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
 183 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
 184
 185         u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
 186 #define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
 187 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
 188 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
 189 #define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
 190 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
 191 #define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
 192         u8              portroute [8];   /* nibbles for routing - offset 0xC */
 193 } __attribute__ ((packed));
 194
 195
 196 /* Section 2.3 Host Controller Operational Registers */
 197 struct ehci_regs {
 198
 199         /* USBCMD: offset 0x00 */
 200         u32             command;
 201 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
 202 #define CMD_PARK        (1<<11)         /* enable "park" on async qh */
 203 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
 204 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
 205 #define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
 206 #define CMD_ASE         (1<<5)          /* async schedule enable */
 207 #define CMD_PSE         (1<<4)          /* periodic schedule enable */
 208 /* 3:2 is periodic frame list size */
 209 #define CMD_RESET       (1<<1)          /* reset HC not bus */
 210 #define CMD_RUN         (1<<0)          /* start/stop HC */
 211
 212         /* USBSTS: offset 0x04 */
 213         u32             status;
 214 #define STS_ASS         (1<<15)         /* Async Schedule Status */
 215 #define STS_PSS         (1<<14)         /* Periodic Schedule Status */
 216 #define STS_RECL        (1<<13)         /* Reclamation */
 217 #define STS_HALT        (1<<12)         /* Not running (any reason) */
 218 /* some bits reserved */
 219         /* these STS_* flags are also intr_enable bits (USBINTR) */
 220 #define STS_IAA         (1<<5)          /* Interrupted on async advance */
 221 #define STS_FATAL       (1<<4)          /* such as some PCI access errors */
 222 #define STS_FLR         (1<<3)          /* frame list rolled over */
 223 #define STS_PCD         (1<<2)          /* port change detect */
 224 #define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
 225 #define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
 226
 227         /* USBINTR: offset 0x08 */
 228         u32             intr_enable;
 229
 230         /* FRINDEX: offset 0x0C */
 231         u32             frame_index;    /* current microframe number */
 232         /* CTRLDSSEGMENT: offset 0x10 */
 233         u32             segment;        /* address bits 63:32 if needed */
 234         /* PERIODICLISTBASE: offset 0x14 */
 235         u32             frame_list;     /* points to periodic list */
 236         /* ASYNCLISTADDR: offset 0x18 */
 237         u32             async_next;     /* address of next async queue head */
 238
 239 #ifdef CONFIG_ARCH_MOXART       // add by Victor Yu. 07-24-2007
 240         /* not used: offset 0x1C */
 241         u32             reserved;
 242
 243         /* PORTSC: offset 0x20 */
 244         u32             port_status [1];        /* just one port */
 245 /* 31:23 reserved */
 246 #define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
 247 #define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
 248 #define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
 249 /* 19:16 for port testing */
 250 #define PORT_LED_OFF    (0<<14)
 251 #define PORT_LED_AMBER  (1<<14)
 252 #define PORT_LED_GREEN  (2<<14)
 253 #define PORT_LED_MASK   (3<<14)
 254 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
 255 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
 256 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
 257 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
 258 /* 9 reserved */
 259 #define PORT_RESET      (1<<8)          /* reset port */
 260 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 261 #define PORT_RESUME     (1<<6)          /* resume it */
 262 #define PORT_OCC        (1<<5)          /* over current change */
 263 #define PORT_OC         (1<<4)          /* over current active */
 264 #define PORT_PEC        (1<<3)          /* port enable change */
 265 #define PORT_PE         (1<<2)          /* port enable */
 266 #define PORT_CSC        (1<<1)          /* connect status change */
 267 #define PORT_CONNECT    (1<<0)          /* device connected */
 268
 269         /* EOF time & asynchronous schedule sleep timer register: offset 0x24 */
 270         u32             eof_time;
 271 #define U_SUSP_N        (1<<6)          /* transceiver suspend mode */
 272
 273 #define EOF2_TIME_MASK  (3<<4)
 274 #define EOF2_TIME_2     (0<<4)          /* high-speed E0F2 time 2 clocks */
 275 #define EOF2_TIME_4     (1<<4)          /* high-speed EOF2 time 4 clocks */
 276 #define EOF2_TIME_8     (2<<4)          /* high-speed EOF2 time 8 clocks */
 277 #define EOF2_TIME_16    (3<<4)          /* high-speed EOF2 time 16 clocks */
 278 #define EOF2_TIME_20    (0<<4)          /* full-speed EOF2 time 20 clocks */
 279 #define EOF2_TIME_40    (1<<4)          /* full-speed EOF2 time 40 clocks */
 280 #define EOF2_TIME_80    (2<<4)          /* full-speed EOF2 time 80 clocks */
 281 #define EOF2_TIME_160   (3<<4)          /* full-speed EOF2 time 160 clocks */
 282 #define EOF2_TIME_40L   (0<<4)          /* low-speed EOF2 time 40 clocks */
 283 #define EOF2_TIME_80L   (1<<4)          /* low-speed EOF2 time 80 clocks */
 284 #define EOF2_TIME_160L  (2<<4)          /* low-speed EOF2 time 160 clocks */
 285 #define EOF2_TIME_320L  (3<<4)          /* low-speed EOF2 time 320 clocks */
 286
 287         /* 0x28 - 0x2C : reserved */
 288         u32             reserved2[2];
 289
 290         /* bus monitor control/status: offset 0x30 */
 291         u32             bus_mon;
 292 #define HOST_SPEED_MASK (3<<9)
 293 #define HOST_SPEED_HS   (2<<9)          /* High speed */
 294 #define HOST_SPEED_FS   (0<<9)          /* full speed */
 295 #define HOST_SPEED_LS   (1<<9)          /* low speed */
 296 #define VBUS_VLD        (0<<8)          /* VBUS valid */
 297 #define VBUS_INVLD      (1<<8)          /* VBUS invalid */
 298 #define FORCE_HIGH_SPEED        (1<<6)
 299 #define FORCE_FULL_SPEED        (1<<7)
 300 #define VBUS_ON         (0<<4)          /* VBUS on */
 301 #define VBUS_OFF        (1<<4)          /* VBUS off */
 302 #define INT_ACT_LOW     (0<<3)          /* interrupt active low */
 303 #define INT_ACT_HIGH    (1<<3)          /* interrupt active high */
 304
 305         /* bus monitor interrupt status: offset 0x34 */
 306         u32             bus_mon_int;
 307
 308         /* bus monitor interrrupt enable: offset 0x38 */
 309         u32             bus_mon_int_enable;
 310
 311         /* 0x3C reserved */
 312         u32             reserved3;
 313
 314         /* test register: offset 0x40 */
 315         u32             test;
 316
 317         /* vendor specific IO control: offset 0x44 */
 318         u32             vendor_io;
 319
 320         /* vendor specific status: offset 0x48 */
 321         u32             vendor_status;
 322
 323         /* 0x4c - 0x5c reserved */
 324         u32             reserved4[5];
 325
 326         /* DMA controller parameter setting 1: offset 0x60 */
 327         u32             dma_cntl1;
 328
 329         /* DMA controller parameter setting 2: offset 0x64 */
 330         u32             dma_cntl2;
 331
 332         /* 0x68 - 0x6c reserved */
 333         u32             reserved5[2];
 334
 335         /* PHY control register */
 336         u32             phy_ctrl;
 337 #define PHY_RESET       (1<<15)
 338 #else   // CONFIG_ARCH_MOXACPU
 339         u32             reserved [9];
 340
 341         /* CONFIGFLAG: offset 0x40 */
 342         u32             configured_flag;
 343 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
 344
 345         /* PORTSC: offset 0x44 */
 346         u32             port_status [0];        /* up to N_PORTS */
 347 /* 31:23 reserved */
 348 #define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
 349 #define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
 350 #define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
 351 /* 19:16 for port testing */
 352 #define PORT_LED_OFF    (0<<14)
 353 #define PORT_LED_AMBER  (1<<14)
 354 #define PORT_LED_GREEN  (2<<14)
 355 #define PORT_LED_MASK   (3<<14)
 356 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
 357 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
 358 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
 359 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
 360 /* 9 reserved */
 361 #define PORT_RESET      (1<<8)          /* reset port */
 362 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 363 #define PORT_RESUME     (1<<6)          /* resume it */
 364 #define PORT_OCC        (1<<5)          /* over current change */
 365 #define PORT_OC         (1<<4)          /* over current active */
 366 #define PORT_PEC        (1<<3)          /* port enable change */
 367 #define PORT_PE         (1<<2)          /* port enable */
 368 #define PORT_CSC        (1<<1)          /* connect status change */
 369 #define PORT_CONNECT    (1<<0)          /* device connected */
 370 #endif  // CONFIG_ARCH_MOXART
 371 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
 372 } __attribute__ ((packed));
 373
 374 /* Appendix C, Debug port ... intended for use with special "debug devices"
 375  * that can help if there's no serial console.  (nonstandard enumeration.)
 376  */
 377 struct ehci_dbg_port {
 378         u32     control;
 379 #define DBGP_OWNER      (1<<30)
 380 #define DBGP_ENABLED    (1<<28)
 381 #define DBGP_DONE       (1<<16)
 382 #define DBGP_INUSE      (1<<10)
 383 #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
 384 #       define DBGP_ERR_BAD     1
 385 #       define DBGP_ERR_SIGNAL  2
 386 #define DBGP_ERROR      (1<<6)
 387 #define DBGP_GO         (1<<5)
 388 #define DBGP_OUT        (1<<4)
 389 #define DBGP_LEN(x)     (((x)>>0)&0x0f)
 390         u32     pids;
 391 #define DBGP_PID_GET(x)         (((x)>>16)&0xff)
 392 #define DBGP_PID_SET(data,tok)  (((data)<<8)|(tok))
 393         u32     data03;
 394         u32     data47;
 395         u32     address;
 396 #define DBGP_EPADDR(dev,ep)     (((dev)<<8)|(ep))
 397 } __attribute__ ((packed));
 398
 399 /*-------------------------------------------------------------------------*/
 400
 401 #define QTD_NEXT(dma)   cpu_to_le32((u32)dma)
 402
 403 /*
 404  * EHCI Specification 0.95 Section 3.5
 405  * QTD: describe data transfer components (buffer, direction, ...)
 406  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 407  *
 408  * These are associated only with "QH" (Queue Head) structures,
 409  * used with control, bulk, and interrupt transfers.
 410  */
 411 struct ehci_qtd {
 412         /* first part defined by EHCI spec */
 413         __le32                  hw_next;          /* see EHCI 3.5.1 */
 414         __le32                  hw_alt_next;      /* see EHCI 3.5.2 */
 415         __le32                  hw_token;         /* see EHCI 3.5.3 */
 416 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 417 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 418 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 419 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 420 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 421 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 422 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 423 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 424 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 425 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 426 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 427 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 428 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 429         __le32                  hw_buf [5];        /* see EHCI 3.5.4 */
 430         __le32                  hw_buf_hi [5];        /* Appendix B */
 431
 432         /* the rest is HCD-private */
 433         dma_addr_t              qtd_dma;                /* qtd address */
 434         struct list_head        qtd_list;               /* sw qtd list */
 435         struct urb              *urb;                   /* qtd's urb */
 436         size_t                  length;                 /* length of buffer */
 437 } __attribute__ ((aligned (32)));
 438
 439 /* mask NakCnt+T in qh->hw_alt_next */
 440 #define QTD_MASK __constant_cpu_to_le32 (~0x1f)
 441
 442 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 443
 444 /*-------------------------------------------------------------------------*/
 445
 446 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 447 #define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1))
 448
 449 /* values for that type tag */
 450 #define Q_TYPE_ITD      __constant_cpu_to_le32 (0 << 1)
 451 #define Q_TYPE_QH       __constant_cpu_to_le32 (1 << 1)
 452 #define Q_TYPE_SITD     __constant_cpu_to_le32 (2 << 1)
 453 #define Q_TYPE_FSTN     __constant_cpu_to_le32 (3 << 1)
 454
 455 /* next async queue entry, or pointer to interrupt/periodic QH */
 456 #define QH_NEXT(dma)    (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
 457
 458 /* for periodic/async schedules and qtd lists, mark end of list */
 459 #define EHCI_LIST_END   __constant_cpu_to_le32(1) /* "null pointer" to hw */
 460
 461 /*
 462  * Entries in periodic shadow table are pointers to one of four kinds
 463  * of data structure.  That's dictated by the hardware; a type tag is
 464  * encoded in the low bits of the hardware's periodic schedule.  Use
 465  * Q_NEXT_TYPE to get the tag.
 466  *
 467  * For entries in the async schedule, the type tag always says "qh".
 468  */
 469 union ehci_shadow {
 470         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 471         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 472         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 473         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 474         __le32                  *hw_next;       /* (all types) */
 475         void                    *ptr;
 476 };
 477
 478 /*-------------------------------------------------------------------------*/
 479
 480 /*
 481  * EHCI Specification 0.95 Section 3.6
 482  * QH: describes control/bulk/interrupt endpoints
 483  * See Fig 3-7 "Queue Head Structure Layout".
 484  *
 485  * These appear in both the async and (for interrupt) periodic schedules.
 486  */
 487
 488 struct ehci_qh {
 489         /* first part defined by EHCI spec */
 490         __le32                  hw_next;         /* see EHCI 3.6.1 */
 491         __le32                  hw_info1;        /* see EHCI 3.6.2 */
 492 #define QH_HEAD         0x00008000
 493         __le32                  hw_info2;        /* see EHCI 3.6.2 */
 494 #define QH_SMASK        0x000000ff
 495 #define QH_CMASK        0x0000ff00
 496 #define QH_HUBADDR      0x007f0000
 497 #define QH_HUBPORT      0x3f800000
 498 #define QH_MULT         0xc0000000
 499         __le32                  hw_current;      /* qtd list - see EHCI 3.6.4 */
 500
 501         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 502         __le32                  hw_qtd_next;
 503         __le32                  hw_alt_next;
 504         __le32                  hw_token;
 505         __le32                  hw_buf [5];
 506         __le32                  hw_buf_hi [5];
 507
 508         /* the rest is HCD-private */
 509         dma_addr_t              qh_dma;         /* address of qh */
 510         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 511         struct list_head        qtd_list;       /* sw qtd list */
 512         struct ehci_qtd         *dummy;
 513         struct ehci_qh          *reclaim;       /* next to reclaim */
 514
 515         struct ehci_hcd         *ehci;
 516         struct kref             kref;
 517         unsigned                stamp;
 518
 519         u8                      qh_state;
 520 #define QH_STATE_LINKED         1               /* HC sees this */
 521 #define QH_STATE_UNLINK         2               /* HC may still see this */
 522 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 523 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 524 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 525
 526         /* periodic schedule info */
 527         u8                      usecs;          /* intr bandwidth */
 528         u8                      gap_uf;         /* uframes split/csplit gap */
 529         u8                      c_usecs;        /* ... split completion bw */
 530         u16                     tt_usecs;       /* tt downstream bandwidth */
 531         unsigned short          period;         /* polling interval */
 532         unsigned short          start;          /* where polling starts */
 533 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 534         struct usb_device       *dev;           /* access to TT */
 535 } __attribute__ ((aligned (32)));
 536
 537 /*-------------------------------------------------------------------------*/
 538
 539 /* description of one iso transaction (up to 3 KB data if highspeed) */
 540 struct ehci_iso_packet {
 541         /* These will be copied to iTD when scheduling */
 542         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 543         __le32                  transaction;    /* itd->hw_transaction[i] |= */
 544         u8                      cross;          /* buf crosses pages */
 545         /* for full speed OUT splits */
 546         u32                     buf1;
 547 };
 548
 549 /* temporary schedule data for packets from iso urbs (both speeds)
 550  * each packet is one logical usb transaction to the device (not TT),
 551  * beginning at stream->next_uframe
 552  */
 553 struct ehci_iso_sched {
 554         struct list_head        td_list;
 555         unsigned                span;
 556         struct ehci_iso_packet  packet [0];
 557 };
 558
 559 /*
 560  * ehci_iso_stream - groups all (s)itds for this endpoint.
 561  * acts like a qh would, if EHCI had them for ISO.
 562  */
 563 struct ehci_iso_stream {
 564         /* first two fields match QH, but info1 == 0 */
 565         __le32                  hw_next;
 566         __le32                  hw_info1;
 567
 568         u32                     refcount;
 569         u8                      bEndpointAddress;
 570         u8                      highspeed;
 571         u16                     depth;          /* depth in uframes */
 572         struct list_head        td_list;        /* queued itds/sitds */
 573         struct list_head        free_list;      /* list of unused itds/sitds */
 574         struct usb_device       *udev;
 575         struct usb_host_endpoint *ep;
 576
 577         /* output of (re)scheduling */
 578         unsigned long           start;          /* jiffies */
 579         unsigned long           rescheduled;
 580         int                     next_uframe;
 581         __le32                  splits;
 582
 583         /* the rest is derived from the endpoint descriptor,
 584          * trusting urb->interval == f(epdesc->bInterval) and
 585          * including the extra info for hw_bufp[0..2]
 586          */
 587         u8                      interval;
 588         u8                      usecs, c_usecs;
 589         u16                     tt_usecs;
 590         u16                     maxp;
 591         u16                     raw_mask;
 592         unsigned                bandwidth;
 593
 594         /* This is used to initialize iTD's hw_bufp fields */
 595         __le32                  buf0;
 596         __le32                  buf1;
 597         __le32                  buf2;
 598
 599         /* this is used to initialize sITD's tt info */
 600         __le32                  address;
 601 };
 602
 603 /*-------------------------------------------------------------------------*/
 604
 605 /*
 606  * EHCI Specification 0.95 Section 3.3
 607  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 608  *
 609  * Schedule records for high speed iso xfers
 610  */
 611 struct ehci_itd {
 612         /* first part defined by EHCI spec */
 613         __le32                  hw_next;           /* see EHCI 3.3.1 */
 614         __le32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 615 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 616 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 617 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 618 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 619 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 620 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 621
 622 #define ITD_ACTIVE      __constant_cpu_to_le32(EHCI_ISOC_ACTIVE)
 623
 624         __le32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 625         __le32                  hw_bufp_hi [7]; /* Appendix B */
 626
 627         /* the rest is HCD-private */
 628         dma_addr_t              itd_dma;        /* for this itd */
 629         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 630
 631         struct urb              *urb;
 632         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 633         struct list_head        itd_list;       /* list of stream's itds */
 634
 635         /* any/all hw_transactions here may be used by that urb */
 636         unsigned                frame;          /* where scheduled */
 637         unsigned                pg;
 638         unsigned                index[8];       /* in urb->iso_frame_desc */
 639         u8                      usecs[8];
 640 } __attribute__ ((aligned (32)));
 641
 642 /*-------------------------------------------------------------------------*/
 643
 644 /*
 645  * EHCI Specification 0.95 Section 3.4
 646  * siTD, aka split-transaction isochronous Transfer Descriptor
 647  *       ... describe full speed iso xfers through TT in hubs
 648  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 649  */
 650 struct ehci_sitd {
 651         /* first part defined by EHCI spec */
 652         __le32                  hw_next;
 653 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 654         __le32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 655         __le32                  hw_uframe;              /* EHCI table 3-10 */
 656         __le32                  hw_results;             /* EHCI table 3-11 */
 657 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 658 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 659 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 660 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 661 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 662 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 663 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 664 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 665 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 666 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 667
 668 #define SITD_ACTIVE     __constant_cpu_to_le32(SITD_STS_ACTIVE)
 669
 670         __le32                  hw_buf [2];             /* EHCI table 3-12 */
 671         __le32                  hw_backpointer;         /* EHCI table 3-13 */
 672         __le32                  hw_buf_hi [2];          /* Appendix B */
 673
 674         /* the rest is HCD-private */
 675         dma_addr_t              sitd_dma;
 676         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 677
 678         struct urb              *urb;
 679         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 680         struct list_head        sitd_list;      /* list of stream's sitds */
 681         unsigned                frame;
 682         unsigned                index;
 683 } __attribute__ ((aligned (32)));
 684
 685 /*-------------------------------------------------------------------------*/
 686
 687 /*
 688  * EHCI Specification 0.96 Section 3.7
 689  * Periodic Frame Span Traversal Node (FSTN)
 690  *
 691  * Manages split interrupt transactions (using TT) that span frame boundaries
 692  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 693  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 694  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 695  */
 696 struct ehci_fstn {
 697         __le32                  hw_next;        /* any periodic q entry */
 698         __le32                  hw_prev;        /* qh or EHCI_LIST_END */
 699
 700         /* the rest is HCD-private */
 701         dma_addr_t              fstn_dma;
 702         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 703 } __attribute__ ((aligned (32)));
 704
 705 /*-------------------------------------------------------------------------*/
 706
 707 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 708
 709 /*
 710  * Some EHCI controllers have a Transaction Translator built into the
 711  * root hub. This is a non-standard feature.  Each controller will need
 712  * to add code to the following inline functions, and call them as
 713  * needed (mostly in root hub code).
 714  */
 715
 716 #define ehci_is_TDI(e)                  ((e)->is_tdi_rh_tt)
 717
 718 /* Returns the speed of a device attached to a port on the root hub. */
 719 static inline unsigned int
 720 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 721 {
 722 #ifdef CONFIG_ARCH_MOXART       // add by Victor Yu. 07-24-2007
 723         switch ( readl(&ehci->regs->bus_mon) & HOST_SPEED_MASK ) {
 724         case HOST_SPEED_FS :
 725                 return 0;
 726         case HOST_SPEED_LS :
 727                 return (1 << USB_PORT_FEAT_LOWSPEED);
 728         case HOST_SPEED_HS :
 729         default :
 730                 return (1 << USB_PORT_FEAT_HIGHSPEED);
 731         }
 732 #else
 733         if (ehci_is_TDI(ehci)) {
 734                 switch ((portsc>>26)&3) {
 735                 case 0:
 736                         return 0;
 737                 case 1:
 738                         return (1<<USB_PORT_FEAT_LOWSPEED);
 739                 case 2:
 740                 default:
 741                         return (1<<USB_PORT_FEAT_HIGHSPEED);
 742                 }
 743         }
 744 #endif
 745         return (1<<USB_PORT_FEAT_HIGHSPEED);
 746 }
 747
 748 #else
 749
 750 #define ehci_is_TDI(e)                  (0)
 751
 752 #define ehci_port_speed(ehci, portsc)   (1<<USB_PORT_FEAT_HIGHSPEED)
 753 #endif
 754
 755 /*-------------------------------------------------------------------------*/
 756
 757 #ifdef CONFIG_PPC_83xx
 758 /* Some Freescale processors have an erratum in which the TT
 759  * port number in the queue head was 0..N-1 instead of 1..N.
 760  */
 761 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 762 #else
 763 #define ehci_has_fsl_portno_bug(e)              (0)
 764 #endif
 765
 766
 767 /*-------------------------------------------------------------------------*/
 768
 769 #ifndef DEBUG
 770 #define STUB_DEBUG_FILES
 771 #endif  /* DEBUG */
 772
 773 /*-------------------------------------------------------------------------*/
 774
 775 #endif /* __LINUX_EHCI_HCD_H */