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MOXA linux-2.6.x / linux-2.6.19-uc1 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz
[linux-2.6.19-moxart.git] / drivers / serial / mcf.c
blob2d169ae04a18b218d2efce7670ada43af73f25bf
1 /****************************************************************************/
2
3 /*
4 * mcf.c -- Freescale ColdFire UART driver
5 *
6 * (C) Copyright 2003-2006, Greg Ungerer <gerg@snapgear.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 /****************************************************************************/
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/console.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/serial.h>
24 #include <linux/serial_core.h>
25
26 #include <asm/coldfire.h>
27 #include <asm/mcfsim.h>
28 #include <asm/mcfuart.h>
29 #include <asm/nettel.h>
30 #include <asm/io.h>
31
32 /****************************************************************************/
33
34 #ifdef DEBUG
35 #define dprintk(x...) printk(x)
36 #else
37 #define dprintk(...) do { } while (0)
38 #endif
39
40 /****************************************************************************/
41
42 /*
43 * On some ColdFire parts the IRQs for serial use are completely
44 * software programmable. On others they are pretty much fixed.
45 * On the programmed CPU's we arbitarily choose 73 (known not to
46 * interfere with anything else programed).
47 */
48 #if defined(MCFINT_VECBASE) && defined(MCFINT_UART0)
49 #define IRQBASE (MCFINT_VECBASE + MCFINT_UART0)
50 #else
51 #define IRQBASE 73
52 #endif
53
54 /*
55 * Some boards implement the DTR/DCD lines using GPIO lines, most
56 * don't. Dummy out the access macros for those that don't. Those
57 * that do should define these macros somewhere in there board
58 * specific inlude files.
59 */
60 #if !defined(mcf_getppdcd)
61 #define mcf_getppdcd(p) (1)
62 #endif
63 #if !defined(mcf_getppdtr)
64 #define mcf_getppdtr(p) (1)
65 #endif
66 #if !defined(mcf_setppdtr)
67 #define mcf_setppdtr(p,v) do { } while (0)
68 #endif
69
70 /****************************************************************************/
71
72 /*
73 * Local per-uart structure.
74 */
75 struct mcf_uart {
76 struct uart_port port;
77 unsigned int sigs; /* Local copy of line sigs */
78 unsigned char imr; /* Local IMR mirror */
79 };
80
81 /****************************************************************************/
82
83 static inline unsigned int mcf_getreg(struct uart_port *port, unsigned int reg)
84 {
85 return readb(port->membase + reg);
86 }
87
88 static inline void mcf_setreg(struct uart_port *port, unsigned int reg, unsigned int val)
89 {
90 writeb(val, port->membase + reg);
91 }
92
93 /****************************************************************************/
94
95 unsigned int mcf_tx_empty(struct uart_port *port)
96 {
97 dprintk("mcf_tx_empty(port=%x)\n", (int)port);
98
99 return (mcf_getreg(port, MCFUART_USR) & MCFUART_USR_TXEMPTY) ? TIOCSER_TEMT : 0;
100 }
101
102 /****************************************************************************/
103
104 unsigned int mcf_get_mctrl(struct uart_port *port)
105 {
106 struct mcf_uart *pp = (struct mcf_uart *) port;
107 unsigned long flags;
108 unsigned int sigs;
109
110 dprintk(" mcf_get_mctrl(port=%x)\n", (int)port);
111
112 spin_lock_irqsave(&port->lock, flags);
113 sigs = (mcf_getreg(port, MCFUART_UIPR) & MCFUART_UIPR_CTS) ? 0 : TIOCM_CTS;
114 sigs |= (pp->sigs & TIOCM_RTS);
115 sigs |= (mcf_getppdcd(port->line) ? TIOCM_CD : 0);
116 sigs |= (mcf_getppdtr(port->line) ? TIOCM_DTR : 0);
117 spin_unlock_irqrestore(&port->lock, flags);
118 return sigs;
119 }
120
121 /****************************************************************************/
122
123 void mcf_set_mctrl(struct uart_port *port, unsigned int sigs)
124 {
125 struct mcf_uart *pp = (struct mcf_uart *) port;
126 unsigned long flags;
127
128 dprintk("mcf_set_mctrl(port=%x,sigs=%x)\n", (int)port, sigs);
129
130 spin_lock_irqsave(&port->lock, flags);
131 pp->sigs = sigs;
132 mcf_setppdtr(port->line, (sigs & TIOCM_DTR));
133 if (sigs & TIOCM_RTS)
134 mcf_setreg(port, MCFUART_UOP1, MCFUART_UOP_RTS);
135 else
136 mcf_setreg(port, MCFUART_UOP0, MCFUART_UOP_RTS);
137 spin_unlock_irqrestore(&port->lock, flags);
138 }
139
140 /****************************************************************************/
141
142 void mcf_start_tx(struct uart_port *port)
143 {
144 struct mcf_uart *pp = (struct mcf_uart *) port;
145 unsigned long flags;
146
147 dprintk("mcf_start_tx(port=%x)\n", (int)port);
148
149 spin_lock_irqsave(&port->lock, flags);
150 pp->imr |= MCFUART_UIR_TXREADY;
151 mcf_setreg(port, MCFUART_UIMR, pp->imr);
152 spin_unlock_irqrestore(&port->lock, flags);
153 }
154
155 /****************************************************************************/
156
157 void mcf_stop_tx(struct uart_port *port)
158 {
159 struct mcf_uart *pp = (struct mcf_uart *) port;
160 unsigned long flags;
161
162 dprintk("mcf_stop_tx(port=%x)\n", (int)port);
163
164 spin_lock_irqsave(&port->lock, flags);
165 pp->imr &= ~MCFUART_UIR_TXREADY;
166 mcf_setreg(port, MCFUART_UIMR, pp->imr);
167 spin_unlock_irqrestore(&port->lock, flags);
168 }
169
170 /****************************************************************************/
171
172 void mcf_start_rx(struct uart_port *port)
173 {
174 struct mcf_uart *pp = (struct mcf_uart *) port;
175 unsigned long flags;
176
177 dprintk("mcf_start_rx(port=%x)\n", (int)port);
178
179 spin_lock_irqsave(&port->lock, flags);
180 pp->imr |= MCFUART_UIR_RXREADY;
181 mcf_setreg(port, MCFUART_UIMR, pp->imr);
182 spin_unlock_irqrestore(&port->lock, flags);
183 }
184
185 /****************************************************************************/
186
187 void mcf_stop_rx(struct uart_port *port)
188 {
189 struct mcf_uart *pp = (struct mcf_uart *) port;
190 unsigned long flags;
191
192 dprintk("mcf_stop_rx(port=%x)\n", (int)port);
193
194 spin_lock_irqsave(&port->lock, flags);
195 pp->imr &= ~MCFUART_UIR_RXREADY;
196 mcf_setreg(port, MCFUART_UIMR, pp->imr);
197 spin_unlock_irqrestore(&port->lock, flags);
198 }
199
200 /****************************************************************************/
201
202 void mcf_break_ctl(struct uart_port *port, int break_state)
203 {
204 unsigned long flags;
205
206 dprintk("mcf_break_ctl(port=%x,break_state=%x)\n", (int)port, break_state);
207
208 spin_lock_irqsave(&port->lock, flags);
209 if (break_state == -1)
210 mcf_setreg(port, MCFUART_UCR, MCFUART_UCR_CMDBREAKSTART);
211 else
212 mcf_setreg(port, MCFUART_UCR, MCFUART_UCR_CMDBREAKSTOP);
213 spin_unlock_irqrestore(&port->lock, flags);
214 }
215
216 /****************************************************************************/
217
218 void mcf_enable_ms(struct uart_port *port)
219 {
220 dprintk("mcf_enable_ms(port=%x)\n", (int)port);
221 }
222
223 /****************************************************************************/
224
225 int mcf_startup(struct uart_port *port)
226 {
227 struct mcf_uart *pp = (struct mcf_uart *) port;
228 unsigned long flags;
229
230 dprintk("mcf_startup(port=%x)\n", (int)port);
231
232 spin_lock_irqsave(&port->lock, flags);
233
234 /* Reset UART, get it into known state... */
235 mcf_setreg(port, MCFUART_UCR, MCFUART_UCR_CMDRESETRX);
236 mcf_setreg(port, MCFUART_UCR, MCFUART_UCR_CMDRESETTX);
237
238 /* Enable the UART transmitter and receiver */
239 mcf_setreg(port, MCFUART_UCR, MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE);
240
241 /* Enable RX interrupts now */
242 pp->imr = MCFUART_UIR_RXREADY;
243 mcf_setreg(port, MCFUART_UIMR, pp->imr);
244
245 spin_unlock_irqrestore(&port->lock, flags);
246
247 return 0;
248 }
249
250 /****************************************************************************/
251
252 void mcf_shutdown(struct uart_port *port)
253 {
254 struct mcf_uart *pp = (struct mcf_uart *) port;
255 unsigned long flags;
256
257 dprintk("mcf_shutdown(port=%x)\n", (int)port);
258
259 spin_lock_irqsave(&port->lock, flags);
260
261 /* Disable all interrupts now */
262 pp->imr = 0;
263 mcf_setreg(port, MCFUART_UIMR, pp->imr);
264
265 /* Disable UART transmitter and receiver */
266 mcf_setreg(port, MCFUART_UCR, MCFUART_UCR_CMDRESETRX);
267 mcf_setreg(port, MCFUART_UCR, MCFUART_UCR_CMDRESETTX);
268
269 spin_unlock_irqrestore(&port->lock, flags);
270 }
271
272 /****************************************************************************/
273
274 void mcf_set_termios(struct uart_port *port, struct termios *termios,
275 struct termios *old)
276 {
277 unsigned long flags;
278 unsigned int baud, baudclk;
279 unsigned char mr1, mr2;
280
281 dprintk("mcf_set_termios(port=%x,termios=%x,old=%x)\n", (int)port, (int)termios, (int)old);
282
283 baud = uart_get_baud_rate(port, termios, old, 0, 230400);
284 baudclk = ((MCF_BUSCLK / baud) + 16) / 32;
285
286 mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR;
287 mr2 = 0;
288
289 switch (termios->c_cflag & CSIZE) {
290 case CS5: mr1 |= MCFUART_MR1_CS5; break;
291 case CS6: mr1 |= MCFUART_MR1_CS6; break;
292 case CS7: mr1 |= MCFUART_MR1_CS7; break;
293 case CS8:
294 default: mr1 |= MCFUART_MR1_CS8; break;
295 }
296
297 if (termios->c_cflag & PARENB) {
298 if (termios->c_cflag & CMSPAR) {
299 if (termios->c_cflag & PARODD)
300 mr1 |= MCFUART_MR1_PARITYMARK;
301 else
302 mr1 |= MCFUART_MR1_PARITYSPACE;
303 } else {
304 if (termios->c_cflag & PARODD)
305 mr1 |= MCFUART_MR1_PARITYODD;
306 else
307 mr1 |= MCFUART_MR1_PARITYEVEN;
308 }
309 } else {
310 mr1 |= MCFUART_MR1_PARITYNONE;
311 }
312
313 if (termios->c_cflag & CSTOPB)
314 mr2 |= MCFUART_MR2_STOP2;
315 else
316 mr2 |= MCFUART_MR2_STOP1;
317
318 if (termios->c_cflag & CRTSCTS) {
319 mr1 |= MCFUART_MR1_RXRTS;
320 mr2 |= MCFUART_MR2_TXCTS;
321 }
322
323 #if 0
324 printk("%s(%d): mr1=%x mr2=%x baudclk=%x\n", __FILE__, __LINE__,
325 mr1, mr2, baudclk);
326 #endif
327 spin_lock_irqsave(&port->lock, flags);
328 mcf_setreg(port, MCFUART_UCR, MCFUART_UCR_CMDRESETRX);
329 mcf_setreg(port, MCFUART_UCR, MCFUART_UCR_CMDRESETTX);
330 mcf_setreg(port, MCFUART_UCR, MCFUART_UCR_CMDRESETMRPTR);
331 mcf_setreg(port, MCFUART_UMR, mr1);
332 mcf_setreg(port, MCFUART_UMR, mr2);
333 mcf_setreg(port, MCFUART_UBG1, (baudclk & 0xff00) >> 8);
334 mcf_setreg(port, MCFUART_UBG2, (baudclk & 0xff));
335 mcf_setreg(port, MCFUART_UCSR, MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER);
336 mcf_setreg(port, MCFUART_UCR, MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE);
337 spin_unlock_irqrestore(&port->lock, flags);
338 }
339
340 /****************************************************************************/
341
342 static void mcf_rx_chars(struct mcf_uart *pp)
343 {
344 struct uart_port *port = (struct uart_port *) pp;
345 unsigned char status, ch, flag;
346
347 while ((status = mcf_getreg(port, MCFUART_USR)) & MCFUART_USR_RXREADY) {
348 ch = mcf_getreg(port, MCFUART_URB);
349 flag = TTY_NORMAL;
350 port->icount.rx++;
351
352 if (status & MCFUART_USR_RXERR) {
353 mcf_setreg(port, MCFUART_UCR, MCFUART_UCR_CMDRESETERR);
354 if (status & MCFUART_USR_RXBREAK) {
355 port->icount.brk++;
356 if (uart_handle_break(port))
357 continue;
358 } else if (status & MCFUART_USR_RXPARITY) {
359 port->icount.parity++;
360 } else if (status & MCFUART_USR_RXOVERRUN) {
361 port->icount.overrun++;
362 } else if (status & MCFUART_USR_RXFRAMING) {
363 port->icount.frame++;
364 }
365
366 status &= port->read_status_mask;
367
368 if (status & MCFUART_USR_RXBREAK)
369 flag = TTY_BREAK;
370 else if (status & MCFUART_USR_RXPARITY)
371 flag = TTY_PARITY;
372 else if (status & MCFUART_USR_RXFRAMING)
373 flag = TTY_FRAME;
374 }
375
376 if (uart_handle_sysrq_char(port, ch))
377 continue;
378 uart_insert_char(port, status, MCFUART_USR_RXOVERRUN, ch, flag);
379 }
380
381 tty_flip_buffer_push(port->info->tty);
382 }
383
384 /****************************************************************************/
385
386 static void mcf_tx_chars(struct mcf_uart *pp)
387 {
388 struct uart_port *port = (struct uart_port *) pp;
389 struct circ_buf *xmit = &port->info->xmit;
390
391 if (port->x_char) {
392 /* Send special char - probably flow control */
393 mcf_setreg(port, MCFUART_UTB, port->x_char);
394 port->x_char = 0;
395 port->icount.tx++;
396 return;
397 }
398
399 while (mcf_getreg(port, MCFUART_USR) & MCFUART_USR_TXREADY) {
400 if (xmit->head == xmit->tail)
401 break;
402 mcf_setreg(port, MCFUART_UTB, xmit->buf[xmit->tail]);
403 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
404 port->icount.tx++;
405 }
406
407 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
408 uart_write_wakeup(port);
409
410 if (xmit->head == xmit->tail) {
411 pp->imr &= ~MCFUART_UIR_TXREADY;
412 mcf_setreg(port, MCFUART_UIMR, pp->imr);
413 }
414 }
415
416 /****************************************************************************/
417
418 static irqreturn_t mcf_interrupt(int irq, void *data)
419 {
420 struct uart_port *port = data;
421 struct mcf_uart *pp = (struct mcf_uart *) port;
422 unsigned int isr;
423
424 isr = mcf_getreg(port, MCFUART_UISR) & pp->imr;
425 if (isr & MCFUART_UIR_RXREADY)
426 mcf_rx_chars(pp);
427 if (isr & MCFUART_UIR_TXREADY)
428 mcf_tx_chars(pp);
429 return IRQ_HANDLED;
430 }
431
432 /****************************************************************************/
433
434 void mcf_config_port(struct uart_port *port, int flags)
435 {
436 #if defined(CONFIG_M5272)
437 unsigned long iop;
438
439 switch (port->line) {
440 case 0:
441 writel(0xe0000000, (MCF_MBAR + MCFSIM_ICR2));
442 break;
443 case 1:
444 writel(0x0e000000, (MCF_MBAR + MCFSIM_ICR2));;
445 break;
446 default:
447 printk("MCF: don't know how to handle UART %d interrupt?\n",
448 port->line);
449 return;
450 }
451
452 /* Enable the output lines for the serial ports */
453 iop = readl(MCF_MBAR + MCFSIM_PBCNT);
454 iop = (iop & ~0x000000ff) | 0x00000055;
455 writel(iop, MCF_MBAR + MCFSIM_PBCNT);
456
457 iop = readl(MCF_MBAR + MCFSIM_PDCNT);
458 iop = (iop & ~0x000003fc) | 0x000002a8;
459 writel(iop, MCF_MBAR + MCFSIM_PBCNT);
460
461 #elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
462 unsigned long imr;
463
464 /* level 6, line based priority */
465 writeb(0x30 + port->line, MCF_MBAR + MCFICM_INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + port->line);
466
467 imr = readl(MCF_MBAR + MCFICM_INTC0 + MCFINTC_IMRL);
468 imr &= ~((1 << (port->irq - 64)) | 1);
469 writel(imr, MCF_MBAR + MCFICM_INTC0 + MCFINTC_IMRL);
470
471 #elif defined(CONFIG_M527x)
472 unsigned long imr;
473 unsigned short sem;
474
475 /* level 6, line based priority */
476 writeb(0x30 + port->line, MCF_MBAR + MCFICM_INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + port->line);
477
478 imr = readl(MCF_MBAR + MCFICM_INTC0 + MCFINTC_IMRL);
479 imr &= ~((1 << (port->irq - 64)) | 1);
480 writel(imr, MCF_MBAR + MCFICM_INTC0 + MCFINTC_IMRL);
481
482 sem = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
483 if (port->line == 0)
484 sem |= UART0_ENABLE_MASK;
485 else if (port->line == 1)
486 sem |= UART1_ENABLE_MASK;
487 else if (port->line == 2)
488 sem |= UART2_ENABLE_MASK;
489 writew(sem, MCF_IPSBAR + MCF_GPIO_PAR_UART);
490
491 #elif defined(CONFIG_M520x)
492 unsigned long imr;
493 unsigned short par;
494 unsigned char par2;
495
496 writeb(0x03, MCF_MBAR + MCFICM_INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + port->line);
497
498 imr = readl(MCF_MBAR + MCFICM_INTC0 + MCFINTC_IMRL);
499 imr &= ~((1 << (port->irq - MCFINT_VECBASE)) | 1);
500 writel(imr, MCF_MBAR + MCFICM_INTC0 + MCFINTC_IMRL);
501
502 switch (port->line) {
503 case 0:
504 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
505 par |= MCF_GPIO_PAR_UART_PAR_UTXD0 |
506 MCF_GPIO_PAR_UART_PAR_URXD0;
507 writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART);
508 break;
509 case 1:
510 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
511 par |= MCF_GPIO_PAR_UART_PAR_UTXD1 |
512 MCF_GPIO_PAR_UART_PAR_URXD1;
513 writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART);
514 break;
515 case 2:
516 par2 = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
517 par2 &= ~0x0F;
518 par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
519 MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
520 writeb(par2, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
521 break;
522 default:
523 printk("MCF: don't know how to handle UART %d interrupt?\n",
524 port->line);
525 break;
526 }
527
528 #elif defined(CONFIG_M532x)
529 switch (port->line) {
530 case 0:
531 MCF_INTC0_ICR26 = 0x3;
532 MCF_INTC0_CIMR = 26;
533 /* GPIO initialization */
534 MCF_GPIO_PAR_UART |= 0x000F;
535 break;
536 case 1:
537 MCF_INTC0_ICR27 = 0x3;
538 MCF_INTC0_CIMR = 27;
539 /* GPIO initialization */
540 MCF_GPIO_PAR_UART |= 0x0FF0;
541 break;
542 case 2:
543 MCF_INTC0_ICR28 = 0x3;
544 MCF_INTC0_CIMR = 28;
545 /* GPIOs also must be initalized, depends on board */
546 break;
547 }
548
549 #else
550 volatile unsigned char *icrp;
551
552 switch (port->line) {
553 case 0:
554 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
555 break;
556 case 1:
557 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
558 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
559 break;
560 default:
561 printk("MCF: don't know how to handle UART %d interrupt?\n",
562 info->line);
563 return;
564 }
565
566 mcfsetreg(port, MCFUART_UIVR, port->irq);
567 #endif
568
569 port->type = PORT_MCF;
570
571 /* Clear mask, so no surprise interrupts. */
572 mcf_setreg(port, MCFUART_UIMR, 0);
573
574 if (request_irq(port->irq, mcf_interrupt, SA_INTERRUPT,
575 "ColdFire UART", port)) {
576 printk("MCF: Unable to attach ColdFire UART %d interrupt "
577 "vector=%d\n", port->line, port->irq);
578 }
579
580 }
581
582 /****************************************************************************/
583
584 static const char *mcf_type(struct uart_port *port)
585 {
586 dprintk("mcf_type()\n");
587 return ((port->type == PORT_MCF) ? "ColdFire UART" : NULL);
588 }
589
590 /****************************************************************************/
591
592 int mcf_request_port(struct uart_port *port)
593 {
594 /* UARTs always present */
595 dprintk("mcf_request_port()\n");
596 return 0;
597 }
598
599 /****************************************************************************/
600
601 void mcf_release_port(struct uart_port *port)
602 {
603 /* Nothing to release... */
604 dprintk("mcf_release_port()\n");
605 }
606
607 /****************************************************************************/
608
609 int mcf_verify_port(struct uart_port *port, struct serial_struct *ser)
610 {
611 dprintk("mcf_verify_port()\n");
612 if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_MCF))
613 return -EINVAL;
614 return 0;
615 }
616
617 /****************************************************************************/
618
619 /*
620 * Define the basic serial functions we support.
621 */
622 static struct uart_ops mcf_uart_ops= {
623 .tx_empty = mcf_tx_empty,
624 .get_mctrl = mcf_get_mctrl,
625 .set_mctrl = mcf_set_mctrl,
626 .start_tx = mcf_start_tx,
627 .stop_tx = mcf_stop_tx,
628 .stop_rx = mcf_stop_rx,
629 .enable_ms = mcf_enable_ms,
630 .break_ctl = mcf_break_ctl,
631 .startup = mcf_startup,
632 .shutdown = mcf_shutdown,
633 .set_termios = mcf_set_termios,
634 .type = mcf_type,
635 .request_port = mcf_request_port,
636 .release_port = mcf_release_port,
637 .config_port = mcf_config_port,
638 .verify_port = mcf_verify_port,
639 };
640
641 /*
642 * Define the port structures, 1 per port/uart.
643 */
644 static struct mcf_uart mcf_ports[] = {
645 {
646 .port = {
647 .line = 0,
648 .type = PORT_MCF,
649 .membase = (void *) MCF_MBAR + MCFUART_BASE1,
650 .mapbase = MCF_MBAR + MCFUART_BASE1,
651 .iotype = SERIAL_IO_MEM,
652 .irq = IRQBASE,
653 .uartclk = MCF_BUSCLK,
654 .ops = &mcf_uart_ops,
655 .flags = ASYNC_BOOT_AUTOCONF,
656 },
657 },
658 #if defined(MCFUART_BASE2)
659 {
660 .port = {
661 .line = 1,
662 .type = PORT_MCF,
663 .membase = (void *) MCF_MBAR + MCFUART_BASE2,
664 .mapbase = MCF_MBAR + MCFUART_BASE2,
665 .iotype = SERIAL_IO_MEM,
666 .irq = IRQBASE + 1,
667 .uartclk = MCF_BUSCLK,
668 .ops = &mcf_uart_ops,
669 .flags = ASYNC_BOOT_AUTOCONF,
670 },
671 },
672 #endif
673 #if defined(MCFUART_BASE3)
674 {
675 .port = {
676 .line = 2,
677 .type = PORT_MCF,
678 .membase = (void *) MCF_MBAR + MCFUART_BASE3,
679 .mapbase = MCF_MBAR + MCFUART_BASE3,
680 .iotype = SERIAL_IO_MEM,
681 .irq = IRQBASE + 2,
682 .uartclk = MCF_BUSCLK,
683 .ops = &mcf_uart_ops,
684 .flags = ASYNC_BOOT_AUTOCONF,
685 },
686 }
687 #endif
688 };
689
690 #define MCF_MAXPORTS (sizeof(mcf_ports) / sizeof(struct mcf_uart))
691
692 /****************************************************************************/
693 #if defined(CONFIG_SERIAL_MCF_CONSOLE)
694 /****************************************************************************/
695
696 static void mcf_console_putc(struct console *co, const char c)
697 {
698 struct uart_port *port = &(mcf_ports + co->index)->port;
699 int i;
700
701 for (i = 0; (i < 0x10000); i++) {
702 if (mcf_getreg(port, MCFUART_USR) & MCFUART_USR_TXREADY)
703 break;
704 }
705 mcf_setreg(port, MCFUART_UTB, c);
706 for (i = 0; (i < 0x10000); i++) {
707 if (mcf_getreg(port, MCFUART_USR) & MCFUART_USR_TXREADY)
708 break;
709 }
710 }
711
712 /****************************************************************************/
713
714 static void mcf_console_write(struct console *co, const char *s, unsigned int count)
715 {
716 for ( ; (count); count--, s++) {
717 mcf_console_putc(co, *s);
718 if (*s == '\n')
719 mcf_console_putc(co, '\r');
720 }
721 }
722
723 /****************************************************************************/
724
725 static int __init mcf_console_setup(struct console *co, char *options)
726 {
727 struct uart_port *port;
728 int baud = CONFIG_SERIAL_MCF_BAUDRATE;
729 int bits = 8;
730 int parity = 'n';
731 int flow = 'n';
732
733 if ((co->index >= 0) && (co->index <= MCF_MAXPORTS))
734 co->index = 0;
735 port = &mcf_ports[co->index].port;
736
737 if (options)
738 uart_parse_options(options, &baud, &parity, &bits, &flow);
739
740 return uart_set_options(port, co, baud, parity, bits, flow);
741 }
742
743 /****************************************************************************/
744
745 static struct uart_driver mcf_driver;
746
747 static struct console mcf_console = {
748 .name = "ttyS",
749 .write = mcf_console_write,
750 .device = uart_console_device,
751 .setup = mcf_console_setup,
752 .flags = CON_PRINTBUFFER,
753 .index = -1,
754 .data = &mcf_driver,
755 };
756
757 static int __init mcf_console_init(void)
758 {
759 register_console(&mcf_console);
760 return 0;
761 }
762
763 console_initcall(mcf_console_init);
764
765 #define MCF_CONSOLE &mcf_console
766
767 /****************************************************************************/
768 #else
769 /****************************************************************************/
770
771 #define MCF_CONSOLE NULL
772
773 /****************************************************************************/
774 #endif /* CONFIG_MCF_CONSOLE */
775 /****************************************************************************/
776
777 /*
778 * Define the mcf UART driver structure.
779 */
780 static struct uart_driver mcf_driver = {
781 .owner = THIS_MODULE,
782 .driver_name = "mcf",
783 .dev_name = "ttyS",
784 .major = TTY_MAJOR,
785 .minor = 64,
786 .nr = MCF_MAXPORTS,
787 .cons = MCF_CONSOLE,
788 };
789
790 /****************************************************************************/
791
792 static int __init mcf_init(void)
793 {
794 int i, rc;
795
796 printk("ColdFire internal UART serial driver\n");
797
798 if ((rc = uart_register_driver(&mcf_driver)))
799 return rc;
800
801 for (i = 0; (i < MCF_MAXPORTS); i++) {
802 if ((rc = uart_add_one_port(&mcf_driver, &mcf_ports[i].port)) < 0)
803 printk("mcf: failed to add UART, %d\n", rc);
804 }
805 return 0;
806 }
807
808 /****************************************************************************/
809
810 static void __exit mcf_exit(void)
811 {
812 int i;
813
814 for (i = 0; (i < MCF_MAXPORTS); i++)
815 uart_remove_one_port(&mcf_driver, &mcf_ports[i].port);
816 uart_unregister_driver(&mcf_driver);
817 }
818
819 /****************************************************************************/
820
821 module_init(mcf_init);
822 module_exit(mcf_exit);
823
824 MODULE_AUTHOR("Greg Ungerer <gerg@snapgear.com>");
825 MODULE_DESCRIPTION("Freescale ColdFire UART driver");
826 MODULE_LICENSE("GPL");
827
828 /****************************************************************************/
MOXA 2.6.19 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz