2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
26 /* The Mellanox Tavor device gives false positive parity errors
27 * Mark this device with a broken_parity_status, to allow
28 * PCI scanning code to "skip" this now blacklisted device.
30 static void __devinit
quirk_mellanox_tavor(struct pci_dev
*dev
)
32 dev
->broken_parity_status
= 1; /* This device gives false positives */
34 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
,PCI_DEVICE_ID_MELLANOX_TAVOR
,quirk_mellanox_tavor
);
35 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE
,quirk_mellanox_tavor
);
37 /* Deal with broken BIOS'es that neglect to enable passive release,
38 which can cause problems in combination with the 82441FX/PPro MTRRs */
39 static void __devinit
quirk_passive_release(struct pci_dev
*dev
)
41 struct pci_dev
*d
= NULL
;
44 /* We have to make sure a particular bit is set in the PIIX3
45 ISA bridge, so we have to go out and find it. */
46 while ((d
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
47 pci_read_config_byte(d
, 0x82, &dlc
);
49 printk(KERN_ERR
"PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d
));
51 pci_write_config_byte(d
, 0x82, dlc
);
55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
57 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
58 but VIA don't answer queries. If you happen to have good contacts at VIA
59 ask them for me please -- Alan
61 This appears to be BIOS not version dependent. So presumably there is a
63 int isa_dma_bridge_buggy
; /* Exported */
65 static void __devinit
quirk_isa_dma_hangs(struct pci_dev
*dev
)
67 if (!isa_dma_bridge_buggy
) {
68 isa_dma_bridge_buggy
=1;
69 printk(KERN_INFO
"Activating ISA DMA hang workarounds.\n");
73 * Its not totally clear which chipsets are the problematic ones
74 * We know 82C586 and 82C596 variants are affected.
76 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
);
77 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C596
, quirk_isa_dma_hangs
);
78 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, quirk_isa_dma_hangs
);
79 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, quirk_isa_dma_hangs
);
80 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_1
, quirk_isa_dma_hangs
);
81 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_2
, quirk_isa_dma_hangs
);
82 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_3
, quirk_isa_dma_hangs
);
87 * Chipsets where PCI->PCI transfers vanish or hang
89 static void __devinit
quirk_nopcipci(struct pci_dev
*dev
)
91 if ((pci_pci_problems
& PCIPCI_FAIL
)==0) {
92 printk(KERN_INFO
"Disabling direct PCI/PCI transfers.\n");
93 pci_pci_problems
|= PCIPCI_FAIL
;
97 static void __devinit
quirk_nopciamd(struct pci_dev
*dev
)
100 pci_read_config_byte(dev
, 0x08, &rev
);
103 printk(KERN_INFO
"Chipset erratum: Disabling direct PCI/AGP transfers.\n");
104 pci_pci_problems
|= PCIAGP_FAIL
;
108 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, quirk_nopcipci
);
109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_496
, quirk_nopcipci
);
110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8151_0
, quirk_nopciamd
);
113 * Triton requires workarounds to be used by the drivers
115 static void __devinit
quirk_triton(struct pci_dev
*dev
)
117 if ((pci_pci_problems
&PCIPCI_TRITON
)==0) {
118 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
119 pci_pci_problems
|= PCIPCI_TRITON
;
122 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437
, quirk_triton
);
123 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
, quirk_triton
);
124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439
, quirk_triton
);
125 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439TX
, quirk_triton
);
128 * VIA Apollo KT133 needs PCI latency patch
129 * Made according to a windows driver based patch by George E. Breese
130 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
131 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
132 * the info on which Mr Breese based his work.
134 * Updated based on further information from the site and also on
135 * information provided by VIA
137 static void __devinit
quirk_vialatency(struct pci_dev
*dev
)
142 /* Ok we have a potential problem chipset here. Now see if we have
143 a buggy southbridge */
145 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, NULL
);
147 pci_read_config_byte(p
, PCI_CLASS_REVISION
, &rev
);
148 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
149 /* Check for buggy part revisions */
150 if (rev
< 0x40 || rev
> 0x42)
153 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
154 if (p
==NULL
) /* No problem parts */
156 pci_read_config_byte(p
, PCI_CLASS_REVISION
, &rev
);
157 /* Check for buggy part revisions */
158 if (rev
< 0x10 || rev
> 0x12)
163 * Ok we have the problem. Now set the PCI master grant to
164 * occur every master grant. The apparent bug is that under high
165 * PCI load (quite common in Linux of course) you can get data
166 * loss when the CPU is held off the bus for 3 bus master requests
167 * This happens to include the IDE controllers....
169 * VIA only apply this fix when an SB Live! is present but under
170 * both Linux and Windows this isnt enough, and we have seen
171 * corruption without SB Live! but with things like 3 UDMA IDE
172 * controllers. So we ignore that bit of the VIA recommendation..
175 pci_read_config_byte(dev
, 0x76, &busarb
);
176 /* Set bit 4 and bi 5 of byte 76 to 0x01
177 "Master priority rotation on every PCI master grant */
180 pci_write_config_byte(dev
, 0x76, busarb
);
181 printk(KERN_INFO
"Applying VIA southbridge workaround.\n");
185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
190 * VIA Apollo VP3 needs ETBF on BT848/878
192 static void __devinit
quirk_viaetbf(struct pci_dev
*dev
)
194 if ((pci_pci_problems
&PCIPCI_VIAETBF
)==0) {
195 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
196 pci_pci_problems
|= PCIPCI_VIAETBF
;
199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_viaetbf
);
201 static void __devinit
quirk_vsfx(struct pci_dev
*dev
)
203 if ((pci_pci_problems
&PCIPCI_VSFX
)==0) {
204 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
205 pci_pci_problems
|= PCIPCI_VSFX
;
208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C576
, quirk_vsfx
);
211 * Ali Magik requires workarounds to be used by the drivers
212 * that DMA to AGP space. Latency must be set to 0xA and triton
213 * workaround applied too
214 * [Info kindly provided by ALi]
216 static void __init
quirk_alimagik(struct pci_dev
*dev
)
218 if ((pci_pci_problems
&PCIPCI_ALIMAGIK
)==0) {
219 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
220 pci_pci_problems
|= PCIPCI_ALIMAGIK
|PCIPCI_TRITON
;
223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1647
, quirk_alimagik
);
224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1651
, quirk_alimagik
);
227 * Natoma has some interesting boundary conditions with Zoran stuff
230 static void __devinit
quirk_natoma(struct pci_dev
*dev
)
232 if ((pci_pci_problems
&PCIPCI_NATOMA
)==0) {
233 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
234 pci_pci_problems
|= PCIPCI_NATOMA
;
237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_natoma
);
238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_0
, quirk_natoma
);
239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_1
, quirk_natoma
);
240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
, quirk_natoma
);
241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_1
, quirk_natoma
);
242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
, quirk_natoma
);
245 * This chip can cause PCI parity errors if config register 0xA0 is read
246 * while DMAs are occurring.
248 static void __devinit
quirk_citrine(struct pci_dev
*dev
)
250 dev
->cfg_size
= 0xA0;
252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CITRINE
, quirk_citrine
);
255 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
256 * If it's needed, re-allocate the region.
258 static void __devinit
quirk_s3_64M(struct pci_dev
*dev
)
260 struct resource
*r
= &dev
->resource
[0];
262 if ((r
->start
& 0x3ffffff) || r
->end
!= r
->start
+ 0x3ffffff) {
267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_868
, quirk_s3_64M
);
268 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_968
, quirk_s3_64M
);
270 static void __devinit
quirk_io_region(struct pci_dev
*dev
, unsigned region
,
271 unsigned size
, int nr
, const char *name
)
275 struct pci_bus_region bus_region
;
276 struct resource
*res
= dev
->resource
+ nr
;
278 res
->name
= pci_name(dev
);
280 res
->end
= region
+ size
- 1;
281 res
->flags
= IORESOURCE_IO
;
283 /* Convert from PCI bus to resource space. */
284 bus_region
.start
= res
->start
;
285 bus_region
.end
= res
->end
;
286 pcibios_bus_to_resource(dev
, res
, &bus_region
);
288 pci_claim_resource(dev
, nr
);
289 printk("PCI quirk: region %04x-%04x claimed by %s\n", region
, region
+ size
- 1, name
);
294 * ATI Northbridge setups MCE the processor if you even
295 * read somewhere between 0x3b0->0x3bb or read 0x3d3
297 static void __devinit
quirk_ati_exploding_mce(struct pci_dev
*dev
)
299 printk(KERN_INFO
"ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
300 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
301 request_region(0x3b0, 0x0C, "RadeonIGP");
302 request_region(0x3d3, 0x01, "RadeonIGP");
304 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, quirk_ati_exploding_mce
);
307 * Let's make the southbridge information explicit instead
308 * of having to worry about people probing the ACPI areas,
309 * for example.. (Yes, it happens, and if you read the wrong
310 * ACPI register it will put the machine to sleep with no
311 * way of waking it up again. Bummer).
313 * ALI M7101: Two IO regions pointed to by words at
314 * 0xE0 (64 bytes of ACPI registers)
315 * 0xE2 (32 bytes of SMB registers)
317 static void __devinit
quirk_ali7101_acpi(struct pci_dev
*dev
)
321 pci_read_config_word(dev
, 0xE0, ®ion
);
322 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "ali7101 ACPI");
323 pci_read_config_word(dev
, 0xE2, ®ion
);
324 quirk_io_region(dev
, region
, 32, PCI_BRIDGE_RESOURCES
+1, "ali7101 SMB");
326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M7101
, quirk_ali7101_acpi
);
328 static void piix4_io_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
331 u32 mask
, size
, base
;
333 pci_read_config_dword(dev
, port
, &devres
);
334 if ((devres
& enable
) != enable
)
336 mask
= (devres
>> 16) & 15;
337 base
= devres
& 0xffff;
340 unsigned bit
= size
>> 1;
341 if ((bit
& mask
) == bit
)
346 * For now we only print it out. Eventually we'll want to
347 * reserve it (at least if it's in the 0x1000+ range), but
348 * let's get enough confirmation reports first.
351 printk("%s PIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
354 static void piix4_mem_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
357 u32 mask
, size
, base
;
359 pci_read_config_dword(dev
, port
, &devres
);
360 if ((devres
& enable
) != enable
)
362 base
= devres
& 0xffff0000;
363 mask
= (devres
& 0x3f) << 16;
366 unsigned bit
= size
>> 1;
367 if ((bit
& mask
) == bit
)
372 * For now we only print it out. Eventually we'll want to
373 * reserve it, but let's get enough confirmation reports first.
376 printk("%s MMIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
380 * PIIX4 ACPI: Two IO regions pointed to by longwords at
381 * 0x40 (64 bytes of ACPI registers)
382 * 0x90 (16 bytes of SMB registers)
383 * and a few strange programmable PIIX4 device resources.
385 static void __devinit
quirk_piix4_acpi(struct pci_dev
*dev
)
389 pci_read_config_dword(dev
, 0x40, ®ion
);
390 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "PIIX4 ACPI");
391 pci_read_config_dword(dev
, 0x90, ®ion
);
392 quirk_io_region(dev
, region
, 16, PCI_BRIDGE_RESOURCES
+1, "PIIX4 SMB");
394 /* Device resource A has enables for some of the other ones */
395 pci_read_config_dword(dev
, 0x5c, &res_a
);
397 piix4_io_quirk(dev
, "PIIX4 devres B", 0x60, 3 << 21);
398 piix4_io_quirk(dev
, "PIIX4 devres C", 0x64, 3 << 21);
400 /* Device resource D is just bitfields for static resources */
402 /* Device 12 enabled? */
403 if (res_a
& (1 << 29)) {
404 piix4_io_quirk(dev
, "PIIX4 devres E", 0x68, 1 << 20);
405 piix4_mem_quirk(dev
, "PIIX4 devres F", 0x6c, 1 << 7);
407 /* Device 13 enabled? */
408 if (res_a
& (1 << 30)) {
409 piix4_io_quirk(dev
, "PIIX4 devres G", 0x70, 1 << 20);
410 piix4_mem_quirk(dev
, "PIIX4 devres H", 0x74, 1 << 7);
412 piix4_io_quirk(dev
, "PIIX4 devres I", 0x78, 1 << 20);
413 piix4_io_quirk(dev
, "PIIX4 devres J", 0x7c, 1 << 20);
415 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, quirk_piix4_acpi
);
416 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_3
, quirk_piix4_acpi
);
419 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
420 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
421 * 0x58 (64 bytes of GPIO I/O space)
423 static void __devinit
quirk_ich4_lpc_acpi(struct pci_dev
*dev
)
427 pci_read_config_dword(dev
, 0x40, ®ion
);
428 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
, "ICH4 ACPI/GPIO/TCO");
430 pci_read_config_dword(dev
, 0x58, ®ion
);
431 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
+1, "ICH4 GPIO");
433 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, quirk_ich4_lpc_acpi
);
434 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_0
, quirk_ich4_lpc_acpi
);
435 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, quirk_ich4_lpc_acpi
);
436 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_10
, quirk_ich4_lpc_acpi
);
437 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, quirk_ich4_lpc_acpi
);
438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, quirk_ich4_lpc_acpi
);
439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, quirk_ich4_lpc_acpi
);
440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, quirk_ich4_lpc_acpi
);
441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, quirk_ich4_lpc_acpi
);
442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_1
, quirk_ich4_lpc_acpi
);
444 static void __devinit
quirk_ich6_lpc_acpi(struct pci_dev
*dev
)
448 pci_read_config_dword(dev
, 0x40, ®ion
);
449 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
, "ICH6 ACPI/GPIO/TCO");
451 pci_read_config_dword(dev
, 0x48, ®ion
);
452 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
+1, "ICH6 GPIO");
454 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_0
, quirk_ich6_lpc_acpi
);
455 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, quirk_ich6_lpc_acpi
);
456 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_0
, quirk_ich6_lpc_acpi
);
457 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_1
, quirk_ich6_lpc_acpi
);
458 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_31
, quirk_ich6_lpc_acpi
);
459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_0
, quirk_ich6_lpc_acpi
);
460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_2
, quirk_ich6_lpc_acpi
);
461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_3
, quirk_ich6_lpc_acpi
);
464 * VIA ACPI: One IO region pointed to by longword at
465 * 0x48 or 0x20 (256 bytes of ACPI registers)
467 static void __devinit
quirk_vt82c586_acpi(struct pci_dev
*dev
)
472 pci_read_config_byte(dev
, PCI_CLASS_REVISION
, &rev
);
474 pci_read_config_dword(dev
, 0x48, ®ion
);
475 region
&= PCI_BASE_ADDRESS_IO_MASK
;
476 quirk_io_region(dev
, region
, 256, PCI_BRIDGE_RESOURCES
, "vt82c586 ACPI");
479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_vt82c586_acpi
);
482 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
483 * 0x48 (256 bytes of ACPI registers)
484 * 0x70 (128 bytes of hardware monitoring register)
485 * 0x90 (16 bytes of SMB registers)
487 static void __devinit
quirk_vt82c686_acpi(struct pci_dev
*dev
)
492 quirk_vt82c586_acpi(dev
);
494 pci_read_config_word(dev
, 0x70, &hm
);
495 hm
&= PCI_BASE_ADDRESS_IO_MASK
;
496 quirk_io_region(dev
, hm
, 128, PCI_BRIDGE_RESOURCES
+ 1, "vt82c686 HW-mon");
498 pci_read_config_dword(dev
, 0x90, &smb
);
499 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
500 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 2, "vt82c686 SMB");
502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_vt82c686_acpi
);
505 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
506 * 0x88 (128 bytes of power management registers)
507 * 0xd0 (16 bytes of SMB registers)
509 static void __devinit
quirk_vt8235_acpi(struct pci_dev
*dev
)
513 pci_read_config_word(dev
, 0x88, &pm
);
514 pm
&= PCI_BASE_ADDRESS_IO_MASK
;
515 quirk_io_region(dev
, pm
, 128, PCI_BRIDGE_RESOURCES
, "vt8235 PM");
517 pci_read_config_word(dev
, 0xd0, &smb
);
518 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
519 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 1, "vt8235 SMB");
521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_vt8235_acpi
);
524 #ifdef CONFIG_X86_IO_APIC
526 #include <asm/io_apic.h>
529 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
530 * devices to the external APIC.
532 * TODO: When we have device-specific interrupt routers,
533 * this code will go away from quirks.
535 static void __devinit
quirk_via_ioapic(struct pci_dev
*dev
)
540 tmp
= 0; /* nothing routed to external APIC */
542 tmp
= 0x1f; /* all known bits (4-0) routed to external APIC */
544 printk(KERN_INFO
"PCI: %sbling Via external APIC routing\n",
545 tmp
== 0 ? "Disa" : "Ena");
547 /* Offset 0x58: External APIC IRQ output control */
548 pci_write_config_byte (dev
, 0x58, tmp
);
550 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
553 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
554 * This leads to doubled level interrupt rates.
555 * Set this bit to get rid of cycle wastage.
556 * Otherwise uncritical.
558 static void __devinit
quirk_via_vt8237_bypass_apic_deassert(struct pci_dev
*dev
)
561 #define BYPASS_APIC_DEASSERT 8
563 pci_read_config_byte(dev
, 0x5B, &misc_control2
);
564 if (!(misc_control2
& BYPASS_APIC_DEASSERT
)) {
565 printk(KERN_INFO
"PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
566 pci_write_config_byte(dev
, 0x5B, misc_control2
|BYPASS_APIC_DEASSERT
);
569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
572 * The AMD io apic can hang the box when an apic irq is masked.
573 * We check all revs >= B0 (yet not in the pre production!) as the bug
574 * is currently marked NoFix
576 * We have multiple reports of hangs with this chipset that went away with
577 * noapic specified. For the moment we assume it's the erratum. We may be wrong
578 * of course. However the advice is demonstrably good even if so..
580 static void __devinit
quirk_amd_ioapic(struct pci_dev
*dev
)
584 pci_read_config_byte(dev
, PCI_REVISION_ID
, &rev
);
586 printk(KERN_WARNING
"I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
587 printk(KERN_WARNING
" : booting with the \"noapic\" option.\n");
590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_VIPER_7410
, quirk_amd_ioapic
);
592 static void __init
quirk_ioapic_rmw(struct pci_dev
*dev
)
594 if (dev
->devfn
== 0 && dev
->bus
->number
== 0)
597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_ANY_ID
, quirk_ioapic_rmw
);
599 #define AMD8131_revA0 0x01
600 #define AMD8131_revB0 0x11
601 #define AMD8131_MISC 0x40
602 #define AMD8131_NIOAMODE_BIT 0
603 static void __init
quirk_amd_8131_ioapic(struct pci_dev
*dev
)
605 unsigned char revid
, tmp
;
610 pci_read_config_byte(dev
, PCI_REVISION_ID
, &revid
);
611 if (revid
== AMD8131_revA0
|| revid
== AMD8131_revB0
) {
612 printk(KERN_INFO
"Fixing up AMD8131 IOAPIC mode\n");
613 pci_read_config_byte( dev
, AMD8131_MISC
, &tmp
);
614 tmp
&= ~(1 << AMD8131_NIOAMODE_BIT
);
615 pci_write_config_byte( dev
, AMD8131_MISC
, tmp
);
618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_ioapic
);
619 #endif /* CONFIG_X86_IO_APIC */
623 * FIXME: it is questionable that quirk_via_acpi
624 * is needed. It shows up as an ISA bridge, and does not
625 * support the PCI_INTERRUPT_LINE register at all. Therefore
626 * it seems like setting the pci_dev's 'irq' to the
627 * value of the ACPI SCI interrupt is only done for convenience.
630 static void __devinit
quirk_via_acpi(struct pci_dev
*d
)
633 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
636 pci_read_config_byte(d
, 0x42, &irq
);
638 if (irq
&& (irq
!= 2))
641 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_acpi
);
642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_acpi
);
645 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
646 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
647 * when written, it makes an internal connection to the PIC.
648 * For these devices, this register is defined to be 4 bits wide.
649 * Normally this is fine. However for IO-APIC motherboards, or
650 * non-x86 architectures (yes Via exists on PPC among other places),
651 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
652 * interrupts delivered properly.
654 * Some of the on-chip devices are actually '586 devices' so they are
658 static int via_irq_fixup_needed
= -1;
661 * As some VIA hardware is available in PCI-card form, we need to restrict
662 * this quirk to VIA PCI hardware built onto VIA-based motherboards only.
663 * We try to locate a VIA southbridge before deciding whether the quirk
666 static const struct pci_device_id via_irq_fixup_tbl
[] = {
668 .vendor
= PCI_VENDOR_ID_VIA
,
669 .device
= PCI_ANY_ID
,
670 .subvendor
= PCI_ANY_ID
,
671 .subdevice
= PCI_ANY_ID
,
672 .class = PCI_CLASS_BRIDGE_ISA
<< 8,
673 .class_mask
= 0xffff00,
678 static void quirk_via_irq(struct pci_dev
*dev
)
682 if (via_irq_fixup_needed
== -1)
683 via_irq_fixup_needed
= pci_dev_present(via_irq_fixup_tbl
);
685 if (!via_irq_fixup_needed
)
690 /* Don't quirk interrupts outside the legacy IRQ range */
691 if (!new_irq
|| new_irq
> 15)
694 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
695 if (new_irq
!= irq
) {
696 printk(KERN_INFO
"PCI: VIA IRQ fixup for %s, from %d to %d\n",
697 pci_name(dev
), irq
, new_irq
);
698 udelay(15); /* unknown if delay really needed */
699 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, new_irq
);
702 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_via_irq
);
705 * VIA VT82C598 has its device ID settable and many BIOSes
706 * set it to the ID of VT82C597 for backward compatibility.
707 * We need to switch it off to be able to recognize the real
710 static void __devinit
quirk_vt82c598_id(struct pci_dev
*dev
)
712 pci_write_config_byte(dev
, 0xfc, 0);
713 pci_read_config_word(dev
, PCI_DEVICE_ID
, &dev
->device
);
715 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_vt82c598_id
);
718 * CardBus controllers have a legacy base address that enables them
719 * to respond as i82365 pcmcia controllers. We don't want them to
720 * do this even if the Linux CardBus driver is not loaded, because
721 * the Linux i82365 driver does not (and should not) handle CardBus.
723 static void __devinit
quirk_cardbus_legacy(struct pci_dev
*dev
)
725 if ((PCI_CLASS_BRIDGE_CARDBUS
<< 8) ^ dev
->class)
727 pci_write_config_dword(dev
, PCI_CB_LEGACY_MODE_BASE
, 0);
729 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, quirk_cardbus_legacy
);
732 * Following the PCI ordering rules is optional on the AMD762. I'm not
733 * sure what the designers were smoking but let's not inhale...
735 * To be fair to AMD, it follows the spec by default, its BIOS people
738 static void __devinit
quirk_amd_ordering(struct pci_dev
*dev
)
741 pci_read_config_dword(dev
, 0x4C, &pcic
);
744 printk(KERN_WARNING
"BIOS failed to enable PCI standards compliance, fixing this error.\n");
745 pci_write_config_dword(dev
, 0x4C, pcic
);
746 pci_read_config_dword(dev
, 0x84, &pcic
);
747 pcic
|= (1<<23); /* Required in this mode */
748 pci_write_config_dword(dev
, 0x84, pcic
);
751 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
754 * DreamWorks provided workaround for Dunord I-3000 problem
756 * This card decodes and responds to addresses not apparently
757 * assigned to it. We force a larger allocation to ensure that
758 * nothing gets put too close to it.
760 static void __devinit
quirk_dunord ( struct pci_dev
* dev
)
762 struct resource
*r
= &dev
->resource
[1];
766 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD
, PCI_DEVICE_ID_DUNORD_I3000
, quirk_dunord
);
769 * i82380FB mobile docking controller: its PCI-to-PCI bridge
770 * is subtractive decoding (transparent), and does indicate this
771 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
774 static void __devinit
quirk_transparent_bridge(struct pci_dev
*dev
)
776 dev
->transparent
= 1;
778 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82380FB
, quirk_transparent_bridge
);
779 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA
, 0x605, quirk_transparent_bridge
);
782 * Common misconfiguration of the MediaGX/Geode PCI master that will
783 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
784 * datasheets found at http://www.national.com/ds/GX for info on what
785 * these bits do. <christer@weinigel.se>
787 static void __init
quirk_mediagx_master(struct pci_dev
*dev
)
790 pci_read_config_byte(dev
, 0x41, ®
);
793 printk(KERN_INFO
"PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg
);
794 pci_write_config_byte(dev
, 0x41, reg
);
797 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
800 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
801 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
802 * secondary channels respectively). If the device reports Compatible mode
803 * but does use BAR0-3 for address decoding, we assume that firmware has
804 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
805 * Exceptions (if they exist) must be handled in chip/architecture specific
808 * Note: for non x86 people. You may need an arch specific quirk to handle
809 * moving IDE devices to native mode as well. Some plug in card devices power
810 * up in compatible mode and assume the BIOS will adjust them.
812 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
813 * we do now ? We don't want is pci_enable_device to come along
814 * and assign new resources. Both approaches work for that.
816 static void __devinit
quirk_ide_bases(struct pci_dev
*dev
)
818 struct resource
*res
;
819 int first_bar
= 2, last_bar
= 0;
821 if ((dev
->class >> 8) != PCI_CLASS_STORAGE_IDE
)
824 res
= &dev
->resource
[0];
826 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
827 if (!(dev
->class & 1) && (res
[0].flags
|| res
[1].flags
)) {
828 res
[0].start
= res
[0].end
= res
[0].flags
= 0;
829 res
[1].start
= res
[1].end
= res
[1].flags
= 0;
834 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
835 if (!(dev
->class & 4) && (res
[2].flags
|| res
[3].flags
)) {
836 res
[2].start
= res
[2].end
= res
[2].flags
= 0;
837 res
[3].start
= res
[3].end
= res
[3].flags
= 0;
844 printk(KERN_INFO
"PCI: Ignoring BAR%d-%d of IDE controller %s\n",
845 first_bar
, last_bar
, pci_name(dev
));
847 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, quirk_ide_bases
);
850 * Ensure C0 rev restreaming is off. This is normally done by
851 * the BIOS but in the odd case it is not the results are corruption
852 * hence the presence of a Linux check
854 static void __init
quirk_disable_pxb(struct pci_dev
*pdev
)
859 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev
);
860 if (rev
!= 0x04) /* Only C0 requires this */
862 pci_read_config_word(pdev
, 0x40, &config
);
863 if (config
& (1<<6)) {
865 pci_write_config_word(pdev
, 0x40, config
);
866 printk(KERN_INFO
"PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
873 * Serverworks CSB5 IDE does not fully support native mode
875 static void __devinit
quirk_svwks_csb5ide(struct pci_dev
*pdev
)
878 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
882 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
883 /* need to re-assign BARs for compat mode */
884 quirk_ide_bases(pdev
);
887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, quirk_svwks_csb5ide
);
890 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
892 static void __init
quirk_ide_samemode(struct pci_dev
*pdev
)
896 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
898 if (((prog
& 1) && !(prog
& 4)) || ((prog
& 4) && !(prog
& 1))) {
899 printk(KERN_INFO
"PCI: IDE mode mismatch; forcing legacy mode\n");
902 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
903 /* need to re-assign BARs for compat mode */
904 quirk_ide_bases(pdev
);
907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
, quirk_ide_samemode
);
909 /* This was originally an Alpha specific thing, but it really fits here.
910 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
912 static void __init
quirk_eisa_bridge(struct pci_dev
*dev
)
914 dev
->class = PCI_CLASS_BRIDGE_EISA
<< 8;
916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
, quirk_eisa_bridge
);
919 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled
920 * when a PCI-Soundcard is added. The BIOS only gives Options
921 * "Disabled" and "AUTO". This Quirk Sets the corresponding
922 * Register-Value to enable the Soundcard.
924 * FIXME: Presently this quirk will run on anything that has an 8237
925 * which isn't correct, we need to check DMI tables or something in
926 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it
927 * runs everywhere at present we suppress the printk output in most
930 static void __init
k8t_sound_hostbridge(struct pci_dev
*dev
)
934 pci_read_config_byte(dev
, 0x50, &val
);
935 if (val
== 0x88 || val
== 0xc8) {
936 /* Assume it's probably a MSI-K8T-Neo2Fir */
937 printk(KERN_INFO
"PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n");
938 pci_write_config_byte(dev
, 0x50, val
& (~0x40));
940 /* Verify the Change for Status output */
941 pci_read_config_byte(dev
, 0x50, &val
);
943 printk(KERN_INFO
"PCI: MSI-K8T-Neo2Fir, soundcard still off\n");
945 printk(KERN_INFO
"PCI: MSI-K8T-Neo2Fir, soundcard on\n");
948 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, k8t_sound_hostbridge
);
950 #ifndef CONFIG_ACPI_SLEEP
952 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
953 * is not activated. The myth is that Asus said that they do not want the
954 * users to be irritated by just another PCI Device in the Win98 device
955 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
956 * package 2.7.0 for details)
958 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
959 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
960 * becomes necessary to do this tweak in two steps -- I've chosen the Host
963 * Actually, leaving it unhidden and not redoing the quirk over suspend2ram
964 * will cause thermal management to break down, and causing machine to
967 static int __initdata asus_hides_smbus
;
969 static void __init
asus_hides_smbus_hostbridge(struct pci_dev
*dev
)
971 if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
972 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845_HB
)
973 switch(dev
->subsystem_device
) {
974 case 0x8025: /* P4B-LX */
975 case 0x8070: /* P4B */
976 case 0x8088: /* P4B533 */
977 case 0x1626: /* L3C notebook */
978 asus_hides_smbus
= 1;
980 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
)
981 switch(dev
->subsystem_device
) {
982 case 0x80b1: /* P4GE-V */
983 case 0x80b2: /* P4PE */
984 case 0x8093: /* P4B533-V */
985 asus_hides_smbus
= 1;
987 if (dev
->device
== PCI_DEVICE_ID_INTEL_82850_HB
)
988 switch(dev
->subsystem_device
) {
989 case 0x8030: /* P4T533 */
990 asus_hides_smbus
= 1;
992 if (dev
->device
== PCI_DEVICE_ID_INTEL_7205_0
)
993 switch (dev
->subsystem_device
) {
994 case 0x8070: /* P4G8X Deluxe */
995 asus_hides_smbus
= 1;
997 if (dev
->device
== PCI_DEVICE_ID_INTEL_E7501_MCH
)
998 switch (dev
->subsystem_device
) {
999 case 0x80c9: /* PU-DLS */
1000 asus_hides_smbus
= 1;
1002 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
1003 switch (dev
->subsystem_device
) {
1004 case 0x1751: /* M2N notebook */
1005 case 0x1821: /* M5N notebook */
1006 asus_hides_smbus
= 1;
1008 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1009 switch (dev
->subsystem_device
) {
1010 case 0x184b: /* W1N notebook */
1011 case 0x186a: /* M6Ne notebook */
1012 asus_hides_smbus
= 1;
1014 if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
) {
1015 switch (dev
->subsystem_device
) {
1016 case 0x1882: /* M6V notebook */
1017 case 0x1977: /* A6VA notebook */
1018 asus_hides_smbus
= 1;
1021 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_HP
)) {
1022 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1023 switch(dev
->subsystem_device
) {
1024 case 0x088C: /* HP Compaq nc8000 */
1025 case 0x0890: /* HP Compaq nc6000 */
1026 asus_hides_smbus
= 1;
1028 if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1029 switch (dev
->subsystem_device
) {
1030 case 0x12bc: /* HP D330L */
1031 case 0x12bd: /* HP D530 */
1032 asus_hides_smbus
= 1;
1034 if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
) {
1035 switch (dev
->subsystem_device
) {
1036 case 0x099c: /* HP Compaq nx6110 */
1037 asus_hides_smbus
= 1;
1040 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_TOSHIBA
)) {
1041 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
1042 switch(dev
->subsystem_device
) {
1043 case 0x0001: /* Toshiba Satellite A40 */
1044 asus_hides_smbus
= 1;
1046 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1047 switch(dev
->subsystem_device
) {
1048 case 0x0001: /* Toshiba Tecra M2 */
1049 asus_hides_smbus
= 1;
1051 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_SAMSUNG
)) {
1052 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1053 switch(dev
->subsystem_device
) {
1054 case 0xC00C: /* Samsung P35 notebook */
1055 asus_hides_smbus
= 1;
1057 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
)) {
1058 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1059 switch(dev
->subsystem_device
) {
1060 case 0x0058: /* Compaq Evo N620c */
1061 asus_hides_smbus
= 1;
1065 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845_HB
, asus_hides_smbus_hostbridge
);
1066 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_HB
, asus_hides_smbus_hostbridge
);
1067 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82850_HB
, asus_hides_smbus_hostbridge
);
1068 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
, asus_hides_smbus_hostbridge
);
1069 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_7205_0
, asus_hides_smbus_hostbridge
);
1070 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7501_MCH
, asus_hides_smbus_hostbridge
);
1071 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855PM_HB
, asus_hides_smbus_hostbridge
);
1072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855GM_HB
, asus_hides_smbus_hostbridge
);
1073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82915GM_HB
, asus_hides_smbus_hostbridge
);
1075 static void __init
asus_hides_smbus_lpc(struct pci_dev
*dev
)
1079 if (likely(!asus_hides_smbus
))
1082 pci_read_config_word(dev
, 0xF2, &val
);
1084 pci_write_config_word(dev
, 0xF2, val
& (~0x8));
1085 pci_read_config_word(dev
, 0xF2, &val
);
1087 printk(KERN_INFO
"PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val
);
1089 printk(KERN_INFO
"PCI: Enabled i801 SMBus device\n");
1092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1095 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1096 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1097 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1099 static void __init
asus_hides_smbus_lpc_ich6(struct pci_dev
*dev
)
1104 if (likely(!asus_hides_smbus
))
1106 pci_read_config_dword(dev
, 0xF0, &rcba
);
1107 base
= ioremap_nocache(rcba
& 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1108 if (base
== NULL
) return;
1109 val
=readl(base
+ 0x3418); /* read the Function Disable register, dword mode only */
1110 writel(val
& 0xFFFFFFF7, base
+ 0x3418); /* enable the SMBus device */
1112 printk(KERN_INFO
"PCI: Enabled ICH6/i801 SMBus device\n");
1114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6
);
1119 * SiS 96x south bridge: BIOS typically hides SMBus device...
1121 static void __init
quirk_sis_96x_smbus(struct pci_dev
*dev
)
1124 printk(KERN_INFO
"Enabling SiS 96x SMBus.\n");
1125 pci_read_config_byte(dev
, 0x77, &val
);
1126 pci_write_config_byte(dev
, 0x77, val
& ~0x10);
1127 pci_read_config_byte(dev
, 0x77, &val
);
1131 * ... This is further complicated by the fact that some SiS96x south
1132 * bridges pretend to be 85C503/5513 instead. In that case see if we
1133 * spotted a compatible north bridge to make sure.
1134 * (pci_find_device doesn't work yet)
1136 * We can also enable the sis96x bit in the discovery register..
1138 static int __devinitdata sis_96x_compatible
= 0;
1140 #define SIS_DETECT_REGISTER 0x40
1142 static void __init
quirk_sis_503(struct pci_dev
*dev
)
1147 pci_read_config_byte(dev
, SIS_DETECT_REGISTER
, ®
);
1148 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
| (1 << 6));
1149 pci_read_config_word(dev
, PCI_DEVICE_ID
, &devid
);
1150 if (((devid
& 0xfff0) != 0x0960) && (devid
!= 0x0018)) {
1151 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
);
1155 /* Make people aware that we changed the config.. */
1156 printk(KERN_WARNING
"Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid
, sis_96x_compatible
);
1159 * Ok, it now shows up as a 96x.. The 96x quirks are after
1160 * the 503 quirk in the quirk table, so they'll automatically
1161 * run and enable things like the SMBus device
1163 dev
->device
= devid
;
1166 static void __init
quirk_sis_96x_compatible(struct pci_dev
*dev
)
1168 sis_96x_compatible
= 1;
1170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_645
, quirk_sis_96x_compatible
);
1171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_646
, quirk_sis_96x_compatible
);
1172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_648
, quirk_sis_96x_compatible
);
1173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_650
, quirk_sis_96x_compatible
);
1174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_651
, quirk_sis_96x_compatible
);
1175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_735
, quirk_sis_96x_compatible
);
1177 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1179 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1180 * and MC97 modem controller are disabled when a second PCI soundcard is
1181 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1184 static void __init
asus_hides_ac97_lpc(struct pci_dev
*dev
)
1187 int asus_hides_ac97
= 0;
1189 if (likely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1190 if (dev
->device
== PCI_DEVICE_ID_VIA_8237
)
1191 asus_hides_ac97
= 1;
1194 if (!asus_hides_ac97
)
1197 pci_read_config_byte(dev
, 0x50, &val
);
1199 pci_write_config_byte(dev
, 0x50, val
& (~0xc0));
1200 pci_read_config_byte(dev
, 0x50, &val
);
1202 printk(KERN_INFO
"PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val
);
1204 printk(KERN_INFO
"PCI: enabled onboard AC97/MC97 devices\n");
1207 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1211 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1215 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1218 * If we are using libata we can drive this chip properly but must
1219 * do this early on to make the additional device appear during
1223 static void __devinit
quirk_jmicron_dualfn(struct pci_dev
*pdev
)
1228 /* Only poke fn 0 */
1229 if (PCI_FUNC(pdev
->devfn
))
1232 switch(pdev
->device
) {
1233 case PCI_DEVICE_ID_JMICRON_JMB365
:
1234 case PCI_DEVICE_ID_JMICRON_JMB366
:
1235 /* Redirect IDE second PATA port to the right spot */
1236 pci_read_config_dword(pdev
, 0x80, &conf
);
1239 pci_write_config_dword(pdev
, 0x80, conf
);
1240 case PCI_DEVICE_ID_JMICRON_JMB361
:
1241 case PCI_DEVICE_ID_JMICRON_JMB363
:
1242 pci_read_config_dword(pdev
, 0x40, &conf
);
1243 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1244 /* Set the class codes correctly and then direct IDE 0 */
1245 conf
&= ~0x000F0200; /* Clear bit 9 and 16-19 */
1246 conf
|= 0x00C20002; /* Set bit 1, 17, 22, 23 */
1247 pci_write_config_dword(pdev
, 0x40, conf
);
1249 /* Reconfigure so that the PCI scanner discovers the
1250 device is now multifunction */
1252 pci_read_config_byte(pdev
, PCI_HEADER_TYPE
, &hdr
);
1253 pdev
->hdr_type
= hdr
& 0x7f;
1254 pdev
->multifunction
= !!(hdr
& 0x80);
1260 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, quirk_jmicron_dualfn
);
1264 #ifdef CONFIG_X86_IO_APIC
1265 static void __init
quirk_alder_ioapic(struct pci_dev
*pdev
)
1269 if ((pdev
->class >> 8) != 0xff00)
1272 /* the first BAR is the location of the IO APIC...we must
1273 * not touch this (and it's already covered by the fixmap), so
1274 * forcibly insert it into the resource tree */
1275 if (pci_resource_start(pdev
, 0) && pci_resource_len(pdev
, 0))
1276 insert_resource(&iomem_resource
, &pdev
->resource
[0]);
1278 /* The next five BARs all seem to be rubbish, so just clean
1280 for (i
=1; i
< 6; i
++) {
1281 memset(&pdev
->resource
[i
], 0, sizeof(pdev
->resource
[i
]));
1285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EESSC
, quirk_alder_ioapic
);
1288 enum ide_combined_type
{ COMBINED
= 0, IDE
= 1, LIBATA
= 2 };
1289 /* Defaults to combined */
1290 static enum ide_combined_type combined_mode
;
1292 static int __init
combined_setup(char *str
)
1294 if (!strncmp(str
, "ide", 3))
1295 combined_mode
= IDE
;
1296 else if (!strncmp(str
, "libata", 6))
1297 combined_mode
= LIBATA
;
1298 else /* "combined" or anything else defaults to old behavior */
1299 combined_mode
= COMBINED
;
1303 __setup("combined_mode=", combined_setup
);
1305 #ifdef CONFIG_SATA_INTEL_COMBINED
1306 static void __devinit
quirk_intel_ide_combined(struct pci_dev
*pdev
)
1312 * Narrow down to Intel SATA PCI devices.
1314 switch (pdev
->device
) {
1315 /* PCI ids taken from drivers/scsi/ata_piix.c */
1325 case 0x2680: /* ESB2 */
1332 case 0x2828: /* ICH8M */
1336 /* we do not handle this PCI device */
1341 * Read combined mode register.
1343 pci_read_config_byte(pdev
, 0x90, &tmp
); /* combined mode reg */
1346 tmp
&= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1347 if (tmp
== 0x4) /* bits 10x */
1348 comb
= (1 << 0); /* SATA port 0, PATA port 1 */
1349 else if (tmp
== 0x6) /* bits 11x */
1350 comb
= (1 << 2); /* PATA port 0, SATA port 1 */
1352 return; /* not in combined mode */
1354 WARN_ON((ich
!= 6) && (ich
!= 7) && (ich
!= 8));
1355 tmp
&= 0x3; /* interesting bits 1:0 */
1357 comb
= (1 << 2); /* PATA port 0, SATA port 1 */
1358 else if (tmp
& (1 << 1))
1359 comb
= (1 << 0); /* SATA port 0, PATA port 1 */
1361 return; /* not in combined mode */
1365 * Read programming interface register.
1366 * (Tells us if it's legacy or native mode)
1368 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1370 /* if SATA port is in native mode, we're ok. */
1374 /* Don't reserve any so the IDE driver can get them (but only if
1375 * combined_mode=ide).
1377 if (combined_mode
== IDE
)
1380 /* Grab them both for libata if combined_mode=libata. */
1381 if (combined_mode
== LIBATA
) {
1382 request_region(0x1f0, 8, "libata"); /* port 0 */
1383 request_region(0x170, 8, "libata"); /* port 1 */
1387 /* SATA port is in legacy mode. Reserve port so that
1388 * IDE driver does not attempt to use it. If request_region
1389 * fails, it will be obvious at boot time, so we don't bother
1390 * checking return values.
1392 if (comb
== (1 << 0))
1393 request_region(0x1f0, 8, "libata"); /* port 0 */
1395 request_region(0x170, 8, "libata"); /* port 1 */
1397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, quirk_intel_ide_combined
);
1398 #endif /* CONFIG_SATA_INTEL_COMBINED */
1403 static void __devinit
quirk_pcie_mch(struct pci_dev
*pdev
)
1407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
, quirk_pcie_mch
);
1408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
, quirk_pcie_mch
);
1409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
, quirk_pcie_mch
);
1413 * It's possible for the MSI to get corrupted if shpc and acpi
1414 * are used together on certain PXH-based systems.
1416 static void __devinit
quirk_pcie_pxh(struct pci_dev
*dev
)
1418 disable_msi_mode(dev
, pci_find_capability(dev
, PCI_CAP_ID_MSI
),
1422 printk(KERN_WARNING
"PCI: PXH quirk detected, "
1423 "disabling MSI for SHPC device\n");
1425 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_0
, quirk_pcie_pxh
);
1426 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_1
, quirk_pcie_pxh
);
1427 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_pcie_pxh
);
1428 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_pcie_pxh
);
1429 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_pcie_pxh
);
1432 * Some Intel PCI Express chipsets have trouble with downstream
1433 * device power management.
1435 static void quirk_intel_pcie_pm(struct pci_dev
* dev
)
1437 pci_pm_d3_delay
= 120;
1441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_pcie_pm
);
1442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_pcie_pm
);
1443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_pcie_pm
);
1444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_pcie_pm
);
1445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_pcie_pm
);
1446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_pcie_pm
);
1447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_pcie_pm
);
1448 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_pcie_pm
);
1449 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_pcie_pm
);
1450 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_pcie_pm
);
1451 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2601, quirk_intel_pcie_pm
);
1452 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2602, quirk_intel_pcie_pm
);
1453 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2603, quirk_intel_pcie_pm
);
1454 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2604, quirk_intel_pcie_pm
);
1455 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2605, quirk_intel_pcie_pm
);
1456 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2606, quirk_intel_pcie_pm
);
1457 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2607, quirk_intel_pcie_pm
);
1458 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2608, quirk_intel_pcie_pm
);
1459 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2609, quirk_intel_pcie_pm
);
1460 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260a, quirk_intel_pcie_pm
);
1461 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260b, quirk_intel_pcie_pm
);
1463 static void __devinit
quirk_netmos(struct pci_dev
*dev
)
1465 unsigned int num_parallel
= (dev
->subsystem_device
& 0xf0) >> 4;
1466 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
1469 * These Netmos parts are multiport serial devices with optional
1470 * parallel ports. Even when parallel ports are present, they
1471 * are identified as class SERIAL, which means the serial driver
1472 * will claim them. To prevent this, mark them as class OTHER.
1473 * These combo devices should be claimed by parport_serial.
1475 * The subdevice ID is of the form 0x00PS, where <P> is the number
1476 * of parallel ports and <S> is the number of serial ports.
1478 switch (dev
->device
) {
1479 case PCI_DEVICE_ID_NETMOS_9735
:
1480 case PCI_DEVICE_ID_NETMOS_9745
:
1481 case PCI_DEVICE_ID_NETMOS_9835
:
1482 case PCI_DEVICE_ID_NETMOS_9845
:
1483 case PCI_DEVICE_ID_NETMOS_9855
:
1484 if ((dev
->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL
&&
1486 printk(KERN_INFO
"PCI: Netmos %04x (%u parallel, "
1487 "%u serial); changing class SERIAL to OTHER "
1488 "(use parport_serial)\n",
1489 dev
->device
, num_parallel
, num_serial
);
1490 dev
->class = (PCI_CLASS_COMMUNICATION_OTHER
<< 8) |
1491 (dev
->class & 0xff);
1495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS
, PCI_ANY_ID
, quirk_netmos
);
1497 static void __devinit
quirk_e100_interrupt(struct pci_dev
*dev
)
1504 switch (dev
->device
) {
1505 /* PCI IDs taken from drivers/net/e100.c */
1507 case 0x1030 ... 0x1034:
1508 case 0x1038 ... 0x103E:
1509 case 0x1050 ... 0x1057:
1511 case 0x1064 ... 0x106B:
1512 case 0x1091 ... 0x1095:
1525 * Some firmware hands off the e100 with interrupts enabled,
1526 * which can cause a flood of interrupts if packets are
1527 * received before the driver attaches to the device. So
1528 * disable all e100 interrupts here. The driver will
1529 * re-enable them when it's ready.
1531 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1532 pci_read_config_dword(dev
, PCI_BASE_ADDRESS_0
, &bar
);
1534 if (!(command
& PCI_COMMAND_MEMORY
) || !bar
)
1537 csr
= ioremap(bar
, 8);
1539 printk(KERN_WARNING
"PCI: Can't map %s e100 registers\n",
1544 cmd_hi
= readb(csr
+ 3);
1546 printk(KERN_WARNING
"PCI: Firmware left %s e100 interrupts "
1547 "enabled, disabling\n", pci_name(dev
));
1553 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, quirk_e100_interrupt
);
1555 static void __devinit
fixup_rev1_53c810(struct pci_dev
* dev
)
1557 /* rev 1 ncr53c810 chips don't set the class at all which means
1558 * they don't get their resources remapped. Fix that here.
1561 if (dev
->class == PCI_CLASS_NOT_DEFINED
) {
1562 printk(KERN_INFO
"NCR 53c810 rev 1 detected, setting PCI class.\n");
1563 dev
->class = PCI_CLASS_STORAGE_SCSI
;
1566 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR
, PCI_DEVICE_ID_NCR_53C810
, fixup_rev1_53c810
);
1568 static void pci_do_fixups(struct pci_dev
*dev
, struct pci_fixup
*f
, struct pci_fixup
*end
)
1571 if ((f
->vendor
== dev
->vendor
|| f
->vendor
== (u16
) PCI_ANY_ID
) &&
1572 (f
->device
== dev
->device
|| f
->device
== (u16
) PCI_ANY_ID
)) {
1573 pr_debug("PCI: Calling quirk %p for %s\n", f
->hook
, pci_name(dev
));
1580 extern struct pci_fixup __start_pci_fixups_early
[];
1581 extern struct pci_fixup __end_pci_fixups_early
[];
1582 extern struct pci_fixup __start_pci_fixups_header
[];
1583 extern struct pci_fixup __end_pci_fixups_header
[];
1584 extern struct pci_fixup __start_pci_fixups_final
[];
1585 extern struct pci_fixup __end_pci_fixups_final
[];
1586 extern struct pci_fixup __start_pci_fixups_enable
[];
1587 extern struct pci_fixup __end_pci_fixups_enable
[];
1590 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
)
1592 struct pci_fixup
*start
, *end
;
1595 case pci_fixup_early
:
1596 start
= __start_pci_fixups_early
;
1597 end
= __end_pci_fixups_early
;
1600 case pci_fixup_header
:
1601 start
= __start_pci_fixups_header
;
1602 end
= __end_pci_fixups_header
;
1605 case pci_fixup_final
:
1606 start
= __start_pci_fixups_final
;
1607 end
= __end_pci_fixups_final
;
1610 case pci_fixup_enable
:
1611 start
= __start_pci_fixups_enable
;
1612 end
= __end_pci_fixups_enable
;
1616 /* stupid compiler warning, you would think with an enum... */
1619 pci_do_fixups(dev
, start
, end
);
1622 /* Enable 1k I/O space granularity on the Intel P64H2 */
1623 static void __devinit
quirk_p64h2_1k_io(struct pci_dev
*dev
)
1626 u8 io_base_lo
, io_limit_lo
;
1627 unsigned long base
, limit
;
1628 struct resource
*res
= dev
->resource
+ PCI_BRIDGE_RESOURCES
;
1630 pci_read_config_word(dev
, 0x40, &en1k
);
1633 printk(KERN_INFO
"PCI: Enable I/O Space to 1 KB Granularity\n");
1635 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
1636 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
1637 base
= (io_base_lo
& (PCI_IO_RANGE_MASK
| 0x0c)) << 8;
1638 limit
= (io_limit_lo
& (PCI_IO_RANGE_MASK
| 0x0c)) << 8;
1640 if (base
<= limit
) {
1642 res
->end
= limit
+ 0x3ff;
1646 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io
);
1648 /* Under some circumstances, AER is not linked with extended capabilities.
1649 * Force it to be linked by setting the corresponding control bit in the
1652 static void __devinit
quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev
*dev
)
1655 if (pci_read_config_byte(dev
, 0xf41, &b
) == 0) {
1657 pci_write_config_byte(dev
, 0xf41, b
| 0x20);
1659 "PCI: Linking AER extended capability on %s\n",
1664 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
1665 quirk_nvidia_ck804_pcie_aer_ext_cap
);
1667 #ifdef CONFIG_PCI_MSI
1668 /* To disable MSI globally */
1671 /* The Serverworks PCI-X chipset does not support MSI. We cannot easily rely
1672 * on setting PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1673 * some other busses controlled by the chipset even if Linux is not aware of it.
1674 * Instead of setting the flag on all busses in the machine, simply disable MSI
1677 static void __init
quirk_svw_msi(struct pci_dev
*dev
)
1680 printk(KERN_WARNING
"PCI: MSI quirk detected. pci_msi_quirk set.\n");
1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE
, quirk_svw_msi
);
1684 /* Disable MSI on chipsets that are known to not support it */
1685 static void __devinit
quirk_disable_msi(struct pci_dev
*dev
)
1687 if (dev
->subordinate
) {
1688 printk(KERN_WARNING
"PCI: MSI quirk detected. "
1689 "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n",
1691 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
1694 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_msi
);
1696 /* Go through the list of Hypertransport capabilities and
1697 * return 1 if a HT MSI capability is found and enabled */
1698 static int __devinit
msi_ht_cap_enabled(struct pci_dev
*dev
)
1702 for (pos
= pci_find_capability(dev
, PCI_CAP_ID_HT
), ttl
= 48;
1704 pos
= pci_find_next_capability(dev
, pos
, PCI_CAP_ID_HT
), ttl
--) {
1706 /* MSI mapping section according to Hypertransport spec */
1707 if (pci_read_config_dword(dev
, pos
, &cap_hdr
) == 0
1708 && (cap_hdr
& 0xf8000000) == 0xa8000000 /* MSI mapping */) {
1709 printk(KERN_INFO
"PCI: Found HT MSI mapping on %s with capability %s\n",
1710 pci_name(dev
), cap_hdr
& 0x10000 ? "enabled" : "disabled");
1711 return (cap_hdr
& 0x10000) != 0; /* MSI mapping cap enabled */
1717 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1718 static void __devinit
quirk_msi_ht_cap(struct pci_dev
*dev
)
1720 if (dev
->subordinate
&& !msi_ht_cap_enabled(dev
)) {
1721 printk(KERN_WARNING
"PCI: MSI quirk detected. "
1722 "MSI disabled on chipset %s.\n",
1724 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
1727 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE
,
1730 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
1731 * MSI are supported if the MSI capability set in any of these mappings.
1733 static void __devinit
quirk_nvidia_ck804_msi_ht_cap(struct pci_dev
*dev
)
1735 struct pci_dev
*pdev
;
1737 if (!dev
->subordinate
)
1740 /* check HT MSI cap on this chipset and the root one.
1741 * a single one having MSI is enough to be sure that MSI are supported.
1743 pdev
= pci_get_slot(dev
->bus
, 0);
1744 if (dev
->subordinate
&& !msi_ht_cap_enabled(dev
)
1745 && !msi_ht_cap_enabled(pdev
)) {
1746 printk(KERN_WARNING
"PCI: MSI quirk detected. "
1747 "MSI disabled on chipset %s.\n",
1749 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
1753 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
1754 quirk_nvidia_ck804_msi_ht_cap
);
1755 #endif /* CONFIG_PCI_MSI */
1757 EXPORT_SYMBOL(pcie_mch_quirk
);
1758 #ifdef CONFIG_HOTPLUG
1759 EXPORT_SYMBOL(pci_fixup_device
);