drivers/net/stdphy.h

   1 /*--------------------------------------------------------------------
   2  * stdphy.h
   3  *
   4  * 802.3 standard ethernet transceiver phy registers (0-8)
   5  *
   6  * Derived from various works, Alpha, ix86, M68K, Sparc, ...et al
   7  *
   8  * Copyright (C) 2004   Microtronix Datacom Ltd
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * Apr2004      DGT Microtronix Datacom
  21  *
  22  ---------------------------------------------------------------------*/
  23
  24 #ifndef _STDPHY_H_
  25     #define _STDPHY_H_
  26
  27 // PHY Control Register
  28 #define PHY_CTL_REG             0x00    // Std Phy Reg0
  29
  30 #define PHY_CTL_RST_MASK        0x8000  // PHY Reset
  31 #define PHY_CTL_LPBK_MASK       0x4000  // PHY Loopback
  32 #define PHY_CTL_SPEED_MASK      0x2000  // 100Mbps, 0=10Mpbs
  33 #define PHY_CTL_ANEG_EN_MASK    0x1000  // Enable Auto negotiation
  34 #define PHY_CTL_PDN_MASK        0x0800  // PHY Power Down mode
  35 #define PHY_CTL_MII_DIS_MASK    0x0400  // MII 4 bit interface disabled
  36 #define PHY_CTL_ANEG_RST_MASK   0x0200  // Restart Auto negotiation
  37 #define PHY_CTL_DPLX_MASK       0x0100  // Full Duplex (Else Half)
  38 #define PHY_CTL_COLTST_MASK     0x0080  // MII Colision Test
  39
  40 // PHY Status Register
  41 #define PHY_STS_REG             0x01    // Std Phy Reg1
  42
  43 #define PHY_STS_CAP_T4_MASK     0x8000  // 100Base-T4            capable
  44 #define PHY_STS_CAP_TXF_MASK    0x4000  // 100Base-X full duplex capable
  45 #define PHY_STS_CAP_TXH_MASK    0x2000  // 100Base-X half duplex capable
  46 #define PHY_STS_CAP_TF_MASK     0x1000  // 10Mbps full duplex    capable
  47 #define PHY_STS_CAP_TH_MASK     0x0800  // 10Mbps half duplex    capable
  48 #define PHY_STS_ANEGDONE_MASK   0x0020  // ANEG has completed
  49 #define PHY_STS_REM_FLT_MASK    0x0010  // Remote Fault detected
  50 #define PHY_STS_CAP_ANEG_MASK   0x0008  // Auto negotiate        capable
  51 #define PHY_STS_LNKSTS_MASK     0x0004  // Valid link
  52 #define PHY_STS_JAB_MASK        0x0002  // 10Mbps jabber condition
  53 #define PHY_STS_EXREG_MASK      0x0001  // Extended regs implemented
  54
  55 // PHY Identifier Registers
  56 #define PHY_ID1_REG             0x02    // Std Phy Reg2
  57 #define PHY_ID2_REG             0x03    // Std Phy Reg3
  58
  59 // PHY Auto-Negotiation Advertisement Register
  60 #define PHY_ADV_REG             0x04    // Std Phy Reg4
  61
  62 #define PHY_ADV_T4              0x0200  // 100Base-T4       capable
  63 #define PHY_ADV_TX_FDX          0x0100  // 100Base-TX FDPLX capable
  64 #define PHY_ADV_TX_HDX          0x0080  // 100Base-TX HDPLX capable
  65 #define PHY_ADV_10_FDX          0x0040  // 10Base-T FDPLX   capable
  66 #define PHY_ADV_10_HDX          0x0020  // 10Base-T HDPLX   capable
  67 #define PHY_ADV_CSMA            0x0001  // 802.3 CMSA       capable
  68
  69 // PHY Auto-negotiation Remote End Capability Register
  70 #define PHY_REMCAP_REG          0x05    // Std Phy Reg5
  71
  72 #define PHY_REMCAP_T4           PHY_ADV_T4
  73 #define PHY_REMCAP_TX_FDX       PHY_ADV_TX_FDX
  74 #define PHY_REMCAP_TX_HDX       PHY_ADV_TX_HDX
  75 #define PHY_REMCAP_10_FDX       PHY_ADV_10_FDX
  76 #define PHY_REMCAP_10_HDX       PHY_ADV_10_HDX
  77 #define PHY_REMCAP_CSMA         PHY_ADV_CSMA
  78
  79 #endif  /* _STDPHY_H_ */